LXR linux-bk/include/asm-ppc64/system.h

   1#ifndef __PPC64_SYSTEM_H
   2#define __PPC64_SYSTEM_H
   3
   4/*
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License
   7 * as published by the Free Software Foundation; either version
   8 * 2 of the License, or (at your option) any later version.
   9 */
  10
  11#include <linux/config.h>
  12#include <linux/compiler.h>
  13#include <asm/page.h>
  14#include <asm/processor.h>
  15#include <asm/hw_irq.h>
  16#include <asm/memory.h>
  17
  18/*
  19 * Memory barrier.
  20 * The sync instruction guarantees that all memory accesses initiated
  21 * by this processor have been performed (with respect to all other
  22 * mechanisms that access memory).  The eieio instruction is a barrier
  23 * providing an ordering (separately) for (a) cacheable stores and (b)
  24 * loads and stores to non-cacheable memory (e.g. I/O devices).
  25 *
  26 * mb() prevents loads and stores being reordered across this point.
  27 * rmb() prevents loads being reordered across this point.
  28 * wmb() prevents stores being reordered across this point.
  29 * read_barrier_depends() prevents data-dependent loads being reordered
  30 *      across this point (nop on PPC).
  31 *
  32 * We have to use the sync instructions for mb(), since lwsync doesn't
  33 * order loads with respect to previous stores.  Lwsync is fine for
  34 * rmb(), though.
  35 * For wmb(), we use sync since wmb is used in drivers to order
  36 * stores to system memory with respect to writes to the device.
  37 * However, smp_wmb() can be a lighter-weight eieio barrier on
  38 * SMP since it is only used to order updates to system memory.
  39 */
  40#define mb()   __asm__ __volatile__ ("sync" : : : "memory")
  41#define rmb()  __asm__ __volatile__ ("lwsync" : : : "memory")
  42#define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
  43#define read_barrier_depends()  do { } while(0)
  44
  45#define set_mb(var, value)      do { var = value; smp_mb(); } while (0)
  46#define set_wmb(var, value)     do { var = value; smp_wmb(); } while (0)
  47
  48#ifdef CONFIG_SMP
  49#define smp_mb()        mb()
  50#define smp_rmb()       rmb()
  51#define smp_wmb()       __asm__ __volatile__ ("eieio" : : : "memory")
  52#define smp_read_barrier_depends()  read_barrier_depends()
  53#else
  54#define smp_mb()        __asm__ __volatile__("": : :"memory")
  55#define smp_rmb()       __asm__ __volatile__("": : :"memory")
  56#define smp_wmb()       __asm__ __volatile__("": : :"memory")
  57#define smp_read_barrier_depends()  do { } while(0)
  58#endif /* CONFIG_SMP */
  59
  60#ifdef __KERNEL__
  61struct task_struct;
  62struct pt_regs;
  63
  64#ifdef CONFIG_DEBUGGER
  65
  66extern int (*__debugger)(struct pt_regs *regs);
  67extern int (*__debugger_ipi)(struct pt_regs *regs);
  68extern int (*__debugger_bpt)(struct pt_regs *regs);
  69extern int (*__debugger_sstep)(struct pt_regs *regs);
  70extern int (*__debugger_iabr_match)(struct pt_regs *regs);
  71extern int (*__debugger_dabr_match)(struct pt_regs *regs);
  72extern int (*__debugger_fault_handler)(struct pt_regs *regs);
  73
  74#define DEBUGGER_BOILERPLATE(__NAME) \
  75static inline int __NAME(struct pt_regs *regs) \
  76{ \
  77        if (unlikely(__ ## __NAME)) \
  78                return __ ## __NAME(regs); \
  79        return 0; \
  80}
  81
  82DEBUGGER_BOILERPLATE(debugger)
  83DEBUGGER_BOILERPLATE(debugger_ipi)
  84DEBUGGER_BOILERPLATE(debugger_bpt)
  85DEBUGGER_BOILERPLATE(debugger_sstep)
  86DEBUGGER_BOILERPLATE(debugger_iabr_match)
  87DEBUGGER_BOILERPLATE(debugger_dabr_match)
  88DEBUGGER_BOILERPLATE(debugger_fault_handler)
  89
  90#ifdef CONFIG_XMON
  91extern void xmon_init(void);
  92#endif
  93
  94#else
  95static inline int debugger(struct pt_regs *regs) { return 0; }
  96static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
  97static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
  98static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
  99static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
 100static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
 101static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 102#endif
 103
 104extern int fix_alignment(struct pt_regs *regs);
 105extern void bad_page_fault(struct pt_regs *regs, unsigned long address,
 106                           int sig);
 107extern void show_regs(struct pt_regs * regs);
 108extern int die(const char *str, struct pt_regs *regs, long err);
 109
 110extern void flush_instruction_cache(void);
 111extern int _get_PVR(void);
 112extern void giveup_fpu(struct task_struct *);
 113extern void disable_kernel_fp(void);
 114extern void flush_fp_to_thread(struct task_struct *);
 115extern void enable_kernel_fp(void);
 116extern void giveup_altivec(struct task_struct *);
 117extern void disable_kernel_altivec(void);
 118extern void enable_kernel_altivec(void);
 119extern int emulate_altivec(struct pt_regs *);
 120extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
 121extern void cvt_df(double *from, float *to, unsigned long *fpscr);
 122
 123#ifdef CONFIG_ALTIVEC
 124extern void flush_altivec_to_thread(struct task_struct *);
 125#else
 126static inline void flush_altivec_to_thread(struct task_struct *t)
 127{
 128}
 129#endif
 130
 131/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
 132extern unsigned char e2a(unsigned char);
 133
 134extern struct task_struct *__switch_to(struct task_struct *,
 135                                       struct task_struct *);
 136#define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 137
 138struct thread_struct;
 139extern struct task_struct * _switch(struct thread_struct *prev,
 140                                    struct thread_struct *next);
 141
 142static inline int __is_processor(unsigned long pv)
 143{
 144        unsigned long pvr;
 145        asm("mfspr %0, 0x11F" : "=r" (pvr)); 
 146        return(PVR_VER(pvr) == pv);
 147}
 148
 149/*
 150 * Atomic exchange
 151 *
 152 * Changes the memory location '*ptr' to be val and returns
 153 * the previous value stored there.
 154 *
 155 * Inline asm pulled from arch/ppc/kernel/misc.S so ppc64
 156 * is more like most of the other architectures.
 157 */
 158static __inline__ unsigned long
 159__xchg_u32(volatile int *m, unsigned long val)
 160{
 161        unsigned long dummy;
 162
 163        __asm__ __volatile__(
 164        EIEIO_ON_SMP
 165"1:     lwarx %0,0,%3           # __xchg_u32\n\
 166        stwcx. %2,0,%3\n\
 1672:      bne- 1b"
 168        ISYNC_ON_SMP
 169        : "=&r" (dummy), "=m" (*m)
 170        : "r" (val), "r" (m)
 171        : "cc", "memory");
 172
 173        return (dummy);
 174}
 175
 176static __inline__ unsigned long
 177__xchg_u64(volatile long *m, unsigned long val)
 178{
 179        unsigned long dummy;
 180
 181        __asm__ __volatile__(
 182        EIEIO_ON_SMP
 183"1:     ldarx %0,0,%3           # __xchg_u64\n\
 184        stdcx. %2,0,%3\n\
 1852:      bne- 1b"
 186        ISYNC_ON_SMP
 187        : "=&r" (dummy), "=m" (*m)
 188        : "r" (val), "r" (m)
 189        : "cc", "memory");
 190
 191        return (dummy);
 192}
 193
 194/*
 195 * This function doesn't exist, so you'll get a linker error
 196 * if something tries to do an invalid xchg().
 197 */
 198extern void __xchg_called_with_bad_pointer(void);
 199
 200static __inline__ unsigned long
 201__xchg(volatile void *ptr, unsigned long x, int size)
 202{
 203        switch (size) {
 204        case 4:
 205                return __xchg_u32(ptr, x);
 206        case 8:
 207                return __xchg_u64(ptr, x);
 208        }
 209        __xchg_called_with_bad_pointer();
 210        return x;
 211}
 212
 213#define xchg(ptr,x)                                                          \
 214  ({                                                                         \
 215     __typeof__(*(ptr)) _x_ = (x);                                           \
 216     (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
 217  })
 218
 219#define tas(ptr) (xchg((ptr),1))
 220
 221#define __HAVE_ARCH_CMPXCHG     1
 222
 223static __inline__ unsigned long
 224__cmpxchg_u32(volatile int *p, int old, int new)
 225{
 226        unsigned int prev;
 227
 228        __asm__ __volatile__ (
 229        EIEIO_ON_SMP
 230"1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 231        cmpw    0,%0,%3\n\
 232        bne-    2f\n\
 233        stwcx.  %4,0,%2\n\
 234        bne-    1b"
 235        ISYNC_ON_SMP
 236        "\n\
 2372:"
 238        : "=&r" (prev), "=m" (*p)
 239        : "r" (p), "r" (old), "r" (new), "m" (*p)
 240        : "cc", "memory");
 241
 242        return prev;
 243}
 244
 245static __inline__ unsigned long
 246__cmpxchg_u64(volatile long *p, unsigned long old, unsigned long new)
 247{
 248        unsigned long prev;
 249
 250        __asm__ __volatile__ (
 251        EIEIO_ON_SMP
 252"1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 253        cmpd    0,%0,%3\n\
 254        bne-    2f\n\
 255        stdcx.  %4,0,%2\n\
 256        bne-    1b"
 257        ISYNC_ON_SMP
 258        "\n\
 2592:"
 260        : "=&r" (prev), "=m" (*p)
 261        : "r" (p), "r" (old), "r" (new), "m" (*p)
 262        : "cc", "memory");
 263
 264        return prev;
 265}
 266
 267/* This function doesn't exist, so you'll get a linker error
 268   if something tries to do an invalid cmpxchg().  */
 269extern void __cmpxchg_called_with_bad_pointer(void);
 270
 271static __inline__ unsigned long
 272__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 273{
 274        switch (size) {
 275        case 4:
 276                return __cmpxchg_u32(ptr, old, new);
 277        case 8:
 278                return __cmpxchg_u64(ptr, old, new);
 279        }
 280        __cmpxchg_called_with_bad_pointer();
 281        return old;
 282}
 283
 284#define cmpxchg(ptr,o,n)                                                 \
 285  ({                                                                     \
 286     __typeof__(*(ptr)) _o_ = (o);                                       \
 287     __typeof__(*(ptr)) _n_ = (n);                                       \
 288     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 289                                    (unsigned long)_n_, sizeof(*(ptr))); \
 290  })
 291
 292/*
 293 * We handle most unaligned accesses in hardware. On the other hand 
 294 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 295 * powers of 2 writes until it reaches sufficient alignment).
 296 *
 297 * Based on this we disable the IP header alignment in network drivers.
 298 */
 299#define NET_IP_ALIGN   0
 300
 301#endif /* __KERNEL__ */
 302#endif
 303