LXR linux-bk/include/asm-ppc64/processor.h

   1#ifndef __ASM_PPC64_PROCESSOR_H
   2#define __ASM_PPC64_PROCESSOR_H
   3
   4/*
   5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License
   9 * as published by the Free Software Foundation; either version
  10 * 2 of the License, or (at your option) any later version.
  11 */
  12
  13#include <linux/stringify.h>
  14#ifndef __ASSEMBLY__
  15#include <linux/config.h>
  16#include <asm/atomic.h>
  17#include <asm/ppcdebug.h>
  18#include <asm/a.out.h>
  19#endif
  20#include <asm/ptrace.h>
  21#include <asm/types.h>
  22
  23/*
  24 * Default implementation of macro that returns current
  25 * instruction pointer ("program counter").
  26 */
  27#define current_text_addr() ({ __label__ _l; _l: &&_l;})
  28
  29/* Machine State Register (MSR) Fields */
  30#define MSR_SF_LG       63              /* Enable 64 bit mode */
  31#define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
  32#define MSR_HV_LG       60              /* Hypervisor state */
  33#define MSR_VEC_LG      25              /* Enable AltiVec */
  34#define MSR_POW_LG      18              /* Enable Power Management */
  35#define MSR_WE_LG       18              /* Wait State Enable */
  36#define MSR_TGPR_LG     17              /* TLB Update registers in use */
  37#define MSR_CE_LG       17              /* Critical Interrupt Enable */
  38#define MSR_ILE_LG      16              /* Interrupt Little Endian */
  39#define MSR_EE_LG       15              /* External Interrupt Enable */
  40#define MSR_PR_LG       14              /* Problem State / Privilege Level */
  41#define MSR_FP_LG       13              /* Floating Point enable */
  42#define MSR_ME_LG       12              /* Machine Check Enable */
  43#define MSR_FE0_LG      11              /* Floating Exception mode 0 */
  44#define MSR_SE_LG       10              /* Single Step */
  45#define MSR_BE_LG       9               /* Branch Trace */
  46#define MSR_DE_LG       9               /* Debug Exception Enable */
  47#define MSR_FE1_LG      8               /* Floating Exception mode 1 */
  48#define MSR_IP_LG       6               /* Exception prefix 0x000/0xFFF */
  49#define MSR_IR_LG       5               /* Instruction Relocate */
  50#define MSR_DR_LG       4               /* Data Relocate */
  51#define MSR_PE_LG       3               /* Protection Enable */
  52#define MSR_PX_LG       2               /* Protection Exclusive Mode */
  53#define MSR_RI_LG       1               /* Recoverable Exception */
  54#define MSR_LE_LG       0               /* Little Endian */
  55
  56#ifdef __ASSEMBLY__
  57#define __MASK(X)       (1<<(X))
  58#else
  59#define __MASK(X)       (1UL<<(X))
  60#endif
  61
  62#define MSR_SF          __MASK(MSR_SF_LG)       /* Enable 64 bit mode */
  63#define MSR_ISF         __MASK(MSR_ISF_LG)      /* Interrupt 64b mode valid on 630 */
  64#define MSR_HV          __MASK(MSR_HV_LG)       /* Hypervisor state */
  65#define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
  66#define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
  67#define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
  68#define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */
  69#define MSR_CE          __MASK(MSR_CE_LG)       /* Critical Interrupt Enable */
  70#define MSR_ILE         __MASK(MSR_ILE_LG)      /* Interrupt Little Endian */
  71#define MSR_EE          __MASK(MSR_EE_LG)       /* External Interrupt Enable */
  72#define MSR_PR          __MASK(MSR_PR_LG)       /* Problem State / Privilege Level */
  73#define MSR_FP          __MASK(MSR_FP_LG)       /* Floating Point enable */
  74#define MSR_ME          __MASK(MSR_ME_LG)       /* Machine Check Enable */
  75#define MSR_FE0         __MASK(MSR_FE0_LG)      /* Floating Exception mode 0 */
  76#define MSR_SE          __MASK(MSR_SE_LG)       /* Single Step */
  77#define MSR_BE          __MASK(MSR_BE_LG)       /* Branch Trace */
  78#define MSR_DE          __MASK(MSR_DE_LG)       /* Debug Exception Enable */
  79#define MSR_FE1         __MASK(MSR_FE1_LG)      /* Floating Exception mode 1 */
  80#define MSR_IP          __MASK(MSR_IP_LG)       /* Exception prefix 0x000/0xFFF */
  81#define MSR_IR          __MASK(MSR_IR_LG)       /* Instruction Relocate */
  82#define MSR_DR          __MASK(MSR_DR_LG)       /* Data Relocate */
  83#define MSR_PE          __MASK(MSR_PE_LG)       /* Protection Enable */
  84#define MSR_PX          __MASK(MSR_PX_LG)       /* Protection Exclusive Mode */
  85#define MSR_RI          __MASK(MSR_RI_LG)       /* Recoverable Exception */
  86#define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
  87
  88#define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
  89#define MSR_KERNEL      MSR_ | MSR_SF | MSR_HV
  90
  91#define MSR_USER32      MSR_ | MSR_PR | MSR_EE
  92#define MSR_USER64      MSR_USER32 | MSR_SF
  93
  94/* Floating Point Status and Control Register (FPSCR) Fields */
  95
  96#define FPSCR_FX        0x80000000      /* FPU exception summary */
  97#define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
  98#define FPSCR_VX        0x20000000      /* Invalid operation summary */
  99#define FPSCR_OX        0x10000000      /* Overflow exception summary */
 100#define FPSCR_UX        0x08000000      /* Underflow exception summary */
 101#define FPSCR_ZX        0x04000000      /* Zero-divide exception summary */
 102#define FPSCR_XX        0x02000000      /* Inexact exception summary */
 103#define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
 104#define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
 105#define FPSCR_VXIDI     0x00400000      /* Invalid op for Inv / Inv */
 106#define FPSCR_VXZDZ     0x00200000      /* Invalid op for Zero / Zero */
 107#define FPSCR_VXIMZ     0x00100000      /* Invalid op for Inv * Zero */
 108#define FPSCR_VXVC      0x00080000      /* Invalid op for Compare */
 109#define FPSCR_FR        0x00040000      /* Fraction rounded */
 110#define FPSCR_FI        0x00020000      /* Fraction inexact */
 111#define FPSCR_FPRF      0x0001f000      /* FPU Result Flags */
 112#define FPSCR_FPCC      0x0000f000      /* FPU Condition Codes */
 113#define FPSCR_VXSOFT    0x00000400      /* Invalid op for software request */
 114#define FPSCR_VXSQRT    0x00000200      /* Invalid op for square root */
 115#define FPSCR_VXCVI     0x00000100      /* Invalid op for integer convert */
 116#define FPSCR_VE        0x00000080      /* Invalid op exception enable */
 117#define FPSCR_OE        0x00000040      /* IEEE overflow exception enable */
 118#define FPSCR_UE        0x00000020      /* IEEE underflow exception enable */
 119#define FPSCR_ZE        0x00000010      /* IEEE zero divide exception enable */
 120#define FPSCR_XE        0x00000008      /* FP inexact exception enable */
 121#define FPSCR_NI        0x00000004      /* FPU non IEEE-Mode */
 122#define FPSCR_RN        0x00000003      /* FPU rounding control */
 123
 124/* Special Purpose Registers (SPRNs)*/
 125
 126#define SPRN_CDBCR      0x3D7   /* Cache Debug Control Register */
 127#define SPRN_CTR        0x009   /* Count Register */
 128#define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
 129#define SPRN_DAC1       0x3F6   /* Data Address Compare 1 */
 130#define SPRN_DAC2       0x3F7   /* Data Address Compare 2 */
 131#define SPRN_DAR        0x013   /* Data Address Register */
 132#define SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
 133#define   DBCR_EDM      0x80000000
 134#define   DBCR_IDM      0x40000000
 135#define   DBCR_RST(x)   (((x) & 0x3) << 28)
 136#define     DBCR_RST_NONE               0
 137#define     DBCR_RST_CORE               1
 138#define     DBCR_RST_CHIP               2
 139#define     DBCR_RST_SYSTEM             3
 140#define   DBCR_IC       0x08000000      /* Instruction Completion Debug Evnt */
 141#define   DBCR_BT       0x04000000      /* Branch Taken Debug Event */
 142#define   DBCR_EDE      0x02000000      /* Exception Debug Event */
 143#define   DBCR_TDE      0x01000000      /* TRAP Debug Event */
 144#define   DBCR_FER      0x00F80000      /* First Events Remaining Mask */
 145#define   DBCR_FT       0x00040000      /* Freeze Timers on Debug Event */
 146#define   DBCR_IA1      0x00020000      /* Instr. Addr. Compare 1 Enable */
 147#define   DBCR_IA2      0x00010000      /* Instr. Addr. Compare 2 Enable */
 148#define   DBCR_D1R      0x00008000      /* Data Addr. Compare 1 Read Enable */
 149#define   DBCR_D1W      0x00004000      /* Data Addr. Compare 1 Write Enable */
 150#define   DBCR_D1S(x)   (((x) & 0x3) << 12)     /* Data Adrr. Compare 1 Size */
 151#define     DAC_BYTE    0
 152#define     DAC_HALF    1
 153#define     DAC_WORD    2
 154#define     DAC_QUAD    3
 155#define   DBCR_D2R      0x00000800      /* Data Addr. Compare 2 Read Enable */
 156#define   DBCR_D2W      0x00000400      /* Data Addr. Compare 2 Write Enable */
 157#define   DBCR_D2S(x)   (((x) & 0x3) << 8)      /* Data Addr. Compare 2 Size */
 158#define   DBCR_SBT      0x00000040      /* Second Branch Taken Debug Event */
 159#define   DBCR_SED      0x00000020      /* Second Exception Debug Event */
 160#define   DBCR_STD      0x00000010      /* Second Trap Debug Event */
 161#define   DBCR_SIA      0x00000008      /* Second IAC Enable */
 162#define   DBCR_SDA      0x00000004      /* Second DAC Enable */
 163#define   DBCR_JOI      0x00000002      /* JTAG Serial Outbound Int. Enable */
 164#define   DBCR_JII      0x00000001      /* JTAG Serial Inbound Int. Enable */
 165#define SPRN_DBCR0      0x3F2   /* Debug Control Register 0 */
 166#define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */
 167#define SPRN_DBSR       0x3F0   /* Debug Status Register */
 168#define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
 169#define   DCCR_NOCACHE          0       /* Noncacheable */
 170#define   DCCR_CACHE            1       /* Cacheable */
 171#define SPRN_DCMP       0x3D1   /* Data TLB Compare Register */
 172#define SPRN_DCWR       0x3BA   /* Data Cache Write-thru Register */
 173#define   DCWR_COPY             0       /* Copy-back */
 174#define   DCWR_WRITE            1       /* Write-through */
 175#define SPRN_DEAR       0x3D5   /* Data Error Address Register */
 176#define SPRN_DEC        0x016   /* Decrement Register */
 177#define SPRN_DMISS      0x3D0   /* Data TLB Miss Register */
 178#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
 179#define SPRN_EAR        0x11A   /* External Address Register */
 180#define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
 181#define   ESR_IMCP      0x80000000      /* Instr. Machine Check - Protection */
 182#define   ESR_IMCN      0x40000000      /* Instr. Machine Check - Non-config */
 183#define   ESR_IMCB      0x20000000      /* Instr. Machine Check - Bus error */
 184#define   ESR_IMCT      0x10000000      /* Instr. Machine Check - Timeout */
 185#define   ESR_PIL       0x08000000      /* Program Exception - Illegal */
 186#define   ESR_PPR       0x04000000      /* Program Exception - Priveleged */
 187#define   ESR_PTR       0x02000000      /* Program Exception - Trap */
 188#define   ESR_DST       0x00800000      /* Storage Exception - Data miss */
 189#define   ESR_DIZ       0x00400000      /* Storage Exception - Zone fault */
 190#define SPRN_EVPR       0x3D6   /* Exception Vector Prefix Register */
 191#define SPRN_HASH1      0x3D2   /* Primary Hash Address Register */
 192#define SPRN_HASH2      0x3D3   /* Secondary Hash Address Resgister */
 193#define SPRN_HID0       0x3F0   /* Hardware Implementation Register 0 */
 194#define   HID0_EMCP     (1<<31)         /* Enable Machine Check pin */
 195#define   HID0_EBA      (1<<29)         /* Enable Bus Address Parity */
 196#define   HID0_EBD      (1<<28)         /* Enable Bus Data Parity */
 197#define   HID0_SBCLK    (1<<27)
 198#define   HID0_EICE     (1<<26)
 199#define   HID0_ECLK     (1<<25)
 200#define   HID0_PAR      (1<<24)
 201#define   HID0_DOZE     (1<<23)
 202#define   HID0_NAP      (1<<22)
 203#define   HID0_SLEEP    (1<<21)
 204#define   HID0_DPM      (1<<20)
 205#define   HID0_ICE      (1<<15)         /* Instruction Cache Enable */
 206#define   HID0_DCE      (1<<14)         /* Data Cache Enable */
 207#define   HID0_ILOCK    (1<<13)         /* Instruction Cache Lock */
 208#define   HID0_DLOCK    (1<<12)         /* Data Cache Lock */
 209#define   HID0_ICFI     (1<<11)         /* Instr. Cache Flash Invalidate */
 210#define   HID0_DCI      (1<<10)         /* Data Cache Invalidate */
 211#define   HID0_SPD      (1<<9)          /* Speculative disable */
 212#define   HID0_SGE      (1<<7)          /* Store Gathering Enable */
 213#define   HID0_SIED     (1<<7)          /* Serial Instr. Execution [Disable] */
 214#define   HID0_BTIC     (1<<5)          /* Branch Target Instruction Cache Enable */
 215#define   HID0_ABE      (1<<3)          /* Address Broadcast Enable */
 216#define   HID0_BHTE     (1<<2)          /* Branch History Table Enable */
 217#define   HID0_BTCD     (1<<1)          /* Branch target cache disable */
 218#define SPRN_MSRDORM    0x3F1   /* Hardware Implementation Register 1 */
 219#define SPRN_HID1       0x3F1   /* Hardware Implementation Register 1 */
 220#define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
 221#define SPRN_NIADORM    0x3F3   /* Hardware Implementation Register 2 */
 222#define SPRN_HID4       0x3F4   /* 970 HID4 */
 223#define SPRN_HID5       0x3F6   /* 970 HID5 */
 224#define SPRN_TSC        0x3FD   /* Thread switch control */
 225#define SPRN_TST        0x3FC   /* Thread switch timeout */
 226#define SPRN_IAC1       0x3F4   /* Instruction Address Compare 1 */
 227#define SPRN_IAC2       0x3F5   /* Instruction Address Compare 2 */
 228#define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
 229#define   ICCR_NOCACHE          0       /* Noncacheable */
 230#define   ICCR_CACHE            1       /* Cacheable */
 231#define SPRN_ICDBDR     0x3D3   /* Instruction Cache Debug Data Register */
 232#define SPRN_ICMP       0x3D5   /* Instruction TLB Compare Register */
 233#define SPRN_ICTC       0x3FB   /* Instruction Cache Throttling Control Reg */
 234#define SPRN_IMISS      0x3D4   /* Instruction TLB Miss Register */
 235#define SPRN_IMMR       0x27E   /* Internal Memory Map Register */
 236#define SPRN_L2CR       0x3F9   /* Level 2 Cache Control Regsiter */
 237#define SPRN_LR         0x008   /* Link Register */
 238#define SPRN_PBL1       0x3FC   /* Protection Bound Lower 1 */
 239#define SPRN_PBL2       0x3FE   /* Protection Bound Lower 2 */
 240#define SPRN_PBU1       0x3FD   /* Protection Bound Upper 1 */
 241#define SPRN_PBU2       0x3FF   /* Protection Bound Upper 2 */
 242#define SPRN_PID        0x3B1   /* Process ID */
 243#define SPRN_PIR        0x3FF   /* Processor Identification Register */
 244#define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
 245#define SPRN_PURR       0x135   /* Processor Utilization of Resources Register */
 246#define SPRN_PVR        0x11F   /* Processor Version Register */
 247#define SPRN_RPA        0x3D6   /* Required Physical Address Register */
 248#define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
 249#define SPRN_SDR1       0x019   /* MMU Hash Base Register */
 250#define SPRN_SGR        0x3B9   /* Storage Guarded Register */
 251#define   SGR_NORMAL            0
 252#define   SGR_GUARDED           1
 253#define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
 254#define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
 255#define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
 256#define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
 257#define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
 258#define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
 259#define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
 260#define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
 261#define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
 262#define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, W/O) */
 263#define SPRN_TBWU       0x11D   /* Time Base Write Upper Register (super, W/O) */
 264#define SPRN_HIOR       0x137   /* 970 Hypervisor interrupt offset */
 265#define SPRN_TCR        0x3DA   /* Timer Control Register */
 266#define   TCR_WP(x)             (((x)&0x3)<<30) /* WDT Period */
 267#define     WP_2_17             0               /* 2^17 clocks */
 268#define     WP_2_21             1               /* 2^21 clocks */
 269#define     WP_2_25             2               /* 2^25 clocks */
 270#define     WP_2_29             3               /* 2^29 clocks */
 271#define   TCR_WRC(x)            (((x)&0x3)<<28) /* WDT Reset Control */
 272#define     WRC_NONE            0               /* No reset will occur */
 273#define     WRC_CORE            1               /* Core reset will occur */
 274#define     WRC_CHIP            2               /* Chip reset will occur */
 275#define     WRC_SYSTEM          3               /* System reset will occur */
 276#define   TCR_WIE               0x08000000      /* WDT Interrupt Enable */
 277#define   TCR_PIE               0x04000000      /* PIT Interrupt Enable */
 278#define   TCR_FP(x)             (((x)&0x3)<<24) /* FIT Period */
 279#define     FP_2_9              0               /* 2^9 clocks */
 280#define     FP_2_13             1               /* 2^13 clocks */
 281#define     FP_2_17             2               /* 2^17 clocks */
 282#define     FP_2_21             3               /* 2^21 clocks */
 283#define   TCR_FIE               0x00800000      /* FIT Interrupt Enable */
 284#define   TCR_ARE               0x00400000      /* Auto Reload Enable */
 285#define SPRN_THRM1      0x3FC   /* Thermal Management Register 1 */
 286#define   THRM1_TIN             (1<<0)
 287#define   THRM1_TIV             (1<<1)
 288#define   THRM1_THRES           (0x7f<<2)
 289#define   THRM1_TID             (1<<29)
 290#define   THRM1_TIE             (1<<30)
 291#define   THRM1_V               (1<<31)
 292#define SPRN_THRM2      0x3FD   /* Thermal Management Register 2 */
 293#define SPRN_THRM3      0x3FE   /* Thermal Management Register 3 */
 294#define   THRM3_E               (1<<31)
 295#define SPRN_TSR        0x3D8   /* Timer Status Register */
 296#define   TSR_ENW               0x80000000      /* Enable Next Watchdog */
 297#define   TSR_WIS               0x40000000      /* WDT Interrupt Status */
 298#define   TSR_WRS(x)            (((x)&0x3)<<28) /* WDT Reset Status */
 299#define     WRS_NONE            0               /* No WDT reset occurred */
 300#define     WRS_CORE            1               /* WDT forced core reset */
 301#define     WRS_CHIP            2               /* WDT forced chip reset */
 302#define     WRS_SYSTEM          3               /* WDT forced system reset */
 303#define   TSR_PIS               0x08000000      /* PIT Interrupt Status */
 304#define   TSR_FIS               0x04000000      /* FIT Interrupt Status */
 305#define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
 306#define SPRN_XER        0x001   /* Fixed Point Exception Register */
 307#define SPRN_ZPR        0x3B0   /* Zone Protection Register */
 308#define SPRN_VRSAVE     0x100   /* Vector save */
 309
 310/* Performance monitor SPRs */
 311#define SPRN_SIAR       780
 312#define SPRN_SDAR       781
 313#define SPRN_MMCRA      786
 314#define SPRN_PMC1       787
 315#define SPRN_PMC2       788
 316#define SPRN_PMC3       789
 317#define SPRN_PMC4       790
 318#define SPRN_PMC5       791
 319#define SPRN_PMC6       792
 320#define SPRN_PMC7       793
 321#define SPRN_PMC8       794
 322#define SPRN_MMCR0      795
 323#define SPRN_MMCR1      798
 324
 325/* Short-hand versions for a number of the above SPRNs */
 326
 327#define CTR     SPRN_CTR        /* Counter Register */
 328#define DAR     SPRN_DAR        /* Data Address Register */
 329#define DABR    SPRN_DABR       /* Data Address Breakpoint Register */
 330#define DCMP    SPRN_DCMP       /* Data TLB Compare Register */
 331#define DEC     SPRN_DEC        /* Decrement Register */
 332#define DMISS   SPRN_DMISS      /* Data TLB Miss Register */
 333#define DSISR   SPRN_DSISR      /* Data Storage Interrupt Status Register */
 334#define EAR     SPRN_EAR        /* External Address Register */
 335#define HASH1   SPRN_HASH1      /* Primary Hash Address Register */
 336#define HASH2   SPRN_HASH2      /* Secondary Hash Address Register */
 337#define HID0    SPRN_HID0       /* Hardware Implementation Register 0 */
 338#define MSRDORM SPRN_MSRDORM    /* MSR Dormant Register */
 339#define NIADORM SPRN_NIADORM    /* NIA Dormant Register */
 340#define TSC     SPRN_TSC        /* Thread switch control */
 341#define TST     SPRN_TST        /* Thread switch timeout */
 342#define IABR    SPRN_IABR       /* Instruction Address Breakpoint Register */
 343#define ICMP    SPRN_ICMP       /* Instruction TLB Compare Register */
 344#define IMISS   SPRN_IMISS      /* Instruction TLB Miss Register */
 345#define IMMR    SPRN_IMMR       /* PPC 860/821 Internal Memory Map Register */
 346#define L2CR    SPRN_L2CR       /* PPC 750 L2 control register */
 347#define __LR    SPRN_LR
 348#define PVR     SPRN_PVR        /* Processor Version */
 349#define PIR     SPRN_PIR        /* Processor ID */
 350#define PURR    SPRN_PURR       /* Processor Utilization of Resource Register */
 351//#define       RPA     SPRN_RPA        /* Required Physical Address Register */
 352#define SDR1    SPRN_SDR1       /* MMU hash base register */
 353#define SPR0    SPRN_SPRG0      /* Supervisor Private Registers */
 354#define SPR1    SPRN_SPRG1
 355#define SPR2    SPRN_SPRG2
 356#define SPR3    SPRN_SPRG3
 357#define SPRG0   SPRN_SPRG0
 358#define SPRG1   SPRN_SPRG1
 359#define SPRG2   SPRN_SPRG2
 360#define SPRG3   SPRN_SPRG3
 361#define SRR0    SPRN_SRR0       /* Save and Restore Register 0 */
 362#define SRR1    SPRN_SRR1       /* Save and Restore Register 1 */
 363#define TBRL    SPRN_TBRL       /* Time Base Read Lower Register */
 364#define TBRU    SPRN_TBRU       /* Time Base Read Upper Register */
 365#define TBWL    SPRN_TBWL       /* Time Base Write Lower Register */
 366#define TBWU    SPRN_TBWU       /* Time Base Write Upper Register */
 367#define ICTC    1019
 368#define THRM1   SPRN_THRM1      /* Thermal Management Register 1 */
 369#define THRM2   SPRN_THRM2      /* Thermal Management Register 2 */
 370#define THRM3   SPRN_THRM3      /* Thermal Management Register 3 */
 371#define XER     SPRN_XER
 372
 373/* Processor Version Register (PVR) field extraction */
 374
 375#define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF) /* Version field */
 376#define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF) /* Revison field */
 377
 378/* Processor Version Numbers */
 379#define PV_NORTHSTAR    0x0033
 380#define PV_PULSAR       0x0034
 381#define PV_POWER4       0x0035
 382#define PV_ICESTAR      0x0036
 383#define PV_SSTAR        0x0037
 384#define PV_POWER4p      0x0038
 385#define PV_970          0x0039
 386#define PV_POWER5       0x003A
 387#define PV_POWER5p      0x003B
 388#define PV_970FX        0x003C
 389#define PV_630          0x0040
 390#define PV_630p         0x0041
 391
 392/* Platforms supported by PPC64 */
 393#define PLATFORM_PSERIES      0x0100
 394#define PLATFORM_PSERIES_LPAR 0x0101
 395#define PLATFORM_ISERIES_LPAR 0x0201
 396#define PLATFORM_LPAR         0x0001
 397#define PLATFORM_POWERMAC     0x0400
 398
 399/* Compatibility with drivers coming from PPC32 world */
 400#define _machine        (systemcfg->platform)
 401#define _MACH_Pmac      PLATFORM_POWERMAC
 402
 403/*
 404 * List of interrupt controllers.
 405 */
 406#define IC_INVALID    0
 407#define IC_OPEN_PIC   1
 408#define IC_PPC_XIC    2
 409
 410#define XGLUE(a,b) a##b
 411#define GLUE(a,b) XGLUE(a,b)
 412
 413#ifdef __ASSEMBLY__
 414
 415#define _GLOBAL(name) \
 416        .section ".text"; \
 417        .align 2 ; \
 418        .globl name; \
 419        .globl GLUE(.,name); \
 420        .section ".opd","aw"; \
 421name: \
 422        .quad GLUE(.,name); \
 423        .quad .TOC.@tocbase; \
 424        .quad 0; \
 425        .previous; \
 426        .type GLUE(.,name),@function; \
 427GLUE(.,name):
 428
 429#define _STATIC(name) \
 430        .section ".text"; \
 431        .align 2 ; \
 432        .section ".opd","aw"; \
 433name: \
 434        .quad GLUE(.,name); \
 435        .quad .TOC.@tocbase; \
 436        .quad 0; \
 437        .previous; \
 438        .type GLUE(.,name),@function; \
 439GLUE(.,name):
 440
 441#endif /* __ASSEMBLY__ */
 442
 443
 444/* Macros for setting and retrieving special purpose registers */
 445
 446#define mfmsr()         ({unsigned long rval; \
 447                        asm volatile("mfmsr %0" : "=r" (rval)); rval;})
 448
 449#define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
 450                                     : : "r" (v))
 451#define mtmsrd(v)       __mtmsrd((v), 0)
 452
 453#define mfspr(rn)       ({unsigned long rval; \
 454                        asm volatile("mfspr %0," __stringify(rn) \
 455                                     : "=r" (rval)); rval;})
 456#define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
 457
 458#define mftb()          ({unsigned long rval;   \
 459                        asm volatile("mftb %0" : "=r" (rval)); rval;})
 460
 461#define mttbl(v)        asm volatile("mttbl %0":: "r"(v))
 462#define mttbu(v)        asm volatile("mttbu %0":: "r"(v))
 463
 464/* iSeries CTRL register (for runlatch) */
 465
 466#define CTRLT           0x098
 467#define CTRLF           0x088
 468#define RUNLATCH        0x0001
 469
 470/* Size of an exception stack frame contained in the paca. */
 471#define EXC_FRAME_SIZE 64
 472
 473#define mfasr()         ({unsigned long rval; \
 474                        asm volatile("mfasr %0" : "=r" (rval)); rval;})
 475
 476#ifndef __ASSEMBLY__
 477
 478static inline void set_tb(unsigned int upper, unsigned int lower)
 479{
 480        mttbl(0);
 481        mttbu(upper);
 482        mttbl(lower);
 483}
 484
 485#define __get_SP()      ({unsigned long sp; \
 486                        asm volatile("mr %0,1": "=r" (sp)); sp;})
 487
 488extern int have_of;
 489
 490struct task_struct;
 491void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
 492void release_thread(struct task_struct *);
 493
 494/* Prepare to copy thread state - unlazy all lazy status */
 495extern void prepare_to_copy(struct task_struct *tsk);
 496
 497/* Create a new kernel thread. */
 498extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 499
 500/*
 501 * Bus types
 502 */
 503#define MCA_bus 0
 504#define MCA_bus__is_a_macro /* for versions in ksyms.c */
 505
 506/* Lazy FPU handling on uni-processor */
 507extern struct task_struct *last_task_used_math;
 508extern struct task_struct *last_task_used_altivec;
 509
 510
 511#ifdef __KERNEL__
 512/* 64-bit user address space is 41-bits (2TBs user VM) */
 513#define TASK_SIZE_USER64 (0x0000020000000000UL)
 514
 515/* 
 516 * 32-bit user address space is 4GB - 1 page 
 517 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 518 */
 519#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
 520
 521#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
 522                TASK_SIZE_USER32 : TASK_SIZE_USER64)
 523#endif /* __KERNEL__ */
 524
 525
 526/* This decides where the kernel will search for a free chunk of vm
 527 * space during mmap's.
 528 */
 529#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(STACK_TOP_USER32 / 4))
 530#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(STACK_TOP_USER64 / 4))
 531
 532#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)||(ppcdebugset(PPCDBG_BINFMT_32ADDR))) ? \
 533                TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
 534
 535typedef struct {
 536        unsigned long seg;
 537} mm_segment_t;
 538
 539struct thread_struct {
 540        unsigned long   ksp;            /* Kernel stack pointer */
 541        struct pt_regs  *regs;          /* Pointer to saved register state */
 542        mm_segment_t    fs;             /* for get_fs() validation */
 543        double          fpr[32];        /* Complete floating point set */
 544        unsigned long   fpscr;          /* Floating point status (plus pad) */
 545        unsigned long   fpexc_mode;     /* Floating-point exception mode */
 546        unsigned long   pad[3];         /* was saved_msr, saved_softe */
 547#ifdef CONFIG_ALTIVEC
 548        /* Complete AltiVec register set */
 549        vector128       vr[32] __attribute((aligned(16)));
 550        /* AltiVec status */
 551        vector128       vscr __attribute((aligned(16)));
 552        unsigned long   vrsave;
 553        int             used_vr;        /* set if process has used altivec */
 554#endif /* CONFIG_ALTIVEC */
 555};
 556
 557#define ARCH_MIN_TASKALIGN 16
 558
 559#define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 560
 561#define INIT_THREAD  { \
 562        INIT_SP, /* ksp */ \
 563        (struct pt_regs *)INIT_SP - 1, /* regs */ \
 564        KERNEL_DS, /*fs*/ \
 565        {0}, /* fpr */ \
 566        0, /* fpscr */ \
 567        MSR_FE0|MSR_FE1, /* fpexc_mode */ \
 568}
 569
 570/*
 571 * Note: the vm_start and vm_end fields here should *not*
 572 * be in kernel space.  (Could vm_end == vm_start perhaps?)
 573 */
 574#define IOREMAP_MMAP { &ioremap_mm, 0, 0x1000, NULL, \
 575                    PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
 576                    1, NULL, NULL }
 577
 578extern struct mm_struct ioremap_mm;
 579
 580/*
 581 * Return saved PC of a blocked thread. For now, this is the "user" PC
 582 */
 583#define thread_saved_pc(tsk)    \
 584        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 585
 586unsigned long get_wchan(struct task_struct *p);
 587
 588#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 589#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 590
 591/* Get/set floating-point exception mode */
 592#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
 593#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
 594
 595extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 596extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
 597
 598static inline unsigned int __unpack_fe01(unsigned long msr_bits)
 599{
 600        return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
 601}
 602
 603static inline unsigned long __pack_fe01(unsigned int fpmode)
 604{
 605        return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
 606}
 607
 608#define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
 609
 610/*
 611 * Prefetch macros.
 612 */
 613#define ARCH_HAS_PREFETCH
 614#define ARCH_HAS_PREFETCHW
 615#define ARCH_HAS_SPINLOCK_PREFETCH
 616
 617static inline void prefetch(const void *x)
 618{
 619        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 620}
 621
 622static inline void prefetchw(const void *x)
 623{
 624        __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 625}
 626
 627#define spin_lock_prefetch(x)   prefetchw(x)
 628
 629#ifdef CONFIG_SCHED_SMT
 630#define ARCH_HAS_SCHED_DOMAIN
 631#define ARCH_HAS_SCHED_WAKE_IDLE
 632#endif
 633
 634#endif /* ASSEMBLY */
 635
 636/*
 637 * Number of entries in the SLB. If this ever changes we should handle
 638 * it with a use a cpu feature fixup.
 639 */
 640#define SLB_NUM_ENTRIES 64
 641
 642#endif /* __ASM_PPC64_PROCESSOR_H */
 643