LXR linux-bk/include/asm-ppc/system.h

   1/*
   2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
   3 */
   4#ifndef __PPC_SYSTEM_H
   5#define __PPC_SYSTEM_H
   6
   7#include <linux/config.h>
   8#include <linux/kernel.h>
   9
  10#include <asm/atomic.h>
  11#include <asm/hw_irq.h>
  12
  13/*
  14 * Memory barrier.
  15 * The sync instruction guarantees that all memory accesses initiated
  16 * by this processor have been performed (with respect to all other
  17 * mechanisms that access memory).  The eieio instruction is a barrier
  18 * providing an ordering (separately) for (a) cacheable stores and (b)
  19 * loads and stores to non-cacheable memory (e.g. I/O devices).
  20 *
  21 * mb() prevents loads and stores being reordered across this point.
  22 * rmb() prevents loads being reordered across this point.
  23 * wmb() prevents stores being reordered across this point.
  24 * read_barrier_depends() prevents data-dependent loads being reordered
  25 *      across this point (nop on PPC).
  26 *
  27 * We can use the eieio instruction for wmb, but since it doesn't
  28 * give any ordering guarantees about loads, we have to use the
  29 * stronger but slower sync instruction for mb and rmb.
  30 */
  31#define mb()  __asm__ __volatile__ ("sync" : : : "memory")
  32#define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
  33#define wmb()  __asm__ __volatile__ ("eieio" : : : "memory")
  34#define read_barrier_depends()  do { } while(0)
  35
  36#define set_mb(var, value)      do { var = value; mb(); } while (0)
  37#define set_wmb(var, value)     do { var = value; wmb(); } while (0)
  38
  39#ifdef CONFIG_SMP
  40#define smp_mb()        mb()
  41#define smp_rmb()       rmb()
  42#define smp_wmb()       wmb()
  43#define smp_read_barrier_depends()      read_barrier_depends()
  44#else
  45#define smp_mb()        barrier()
  46#define smp_rmb()       barrier()
  47#define smp_wmb()       barrier()
  48#define smp_read_barrier_depends()      do { } while(0)
  49#endif /* CONFIG_SMP */
  50
  51#ifdef __KERNEL__
  52struct task_struct;
  53struct pt_regs;
  54
  55extern void print_backtrace(unsigned long *);
  56extern void show_regs(struct pt_regs * regs);
  57extern void flush_instruction_cache(void);
  58extern void hard_reset_now(void);
  59extern void poweroff_now(void);
  60#ifdef CONFIG_6xx
  61extern long _get_L2CR(void);
  62extern long _get_L3CR(void);
  63extern void _set_L2CR(unsigned long);
  64extern void _set_L3CR(unsigned long);
  65#else
  66#define _get_L2CR()     0L
  67#define _get_L3CR()     0L
  68#define _set_L2CR(val)  do { } while(0)
  69#define _set_L3CR(val)  do { } while(0)
  70#endif
  71extern void via_cuda_init(void);
  72extern void pmac_nvram_init(void);
  73extern void read_rtc_time(void);
  74extern void pmac_find_display(void);
  75extern void giveup_fpu(struct task_struct *);
  76extern void enable_kernel_fp(void);
  77extern void giveup_altivec(struct task_struct *);
  78extern void load_up_altivec(struct task_struct *);
  79extern void giveup_spe(struct task_struct *);
  80extern void load_up_spe(struct task_struct *);
  81extern int fix_alignment(struct pt_regs *);
  82extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
  83extern void cvt_df(double *from, float *to, unsigned long *fpscr);
  84extern int call_rtas(const char *, int, int, unsigned long *, ...);
  85extern void cacheable_memzero(void *p, unsigned int nb);
  86extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
  87extern void bad_page_fault(struct pt_regs *, unsigned long, int);
  88extern void die(const char *, struct pt_regs *, long);
  89
  90struct device_node;
  91extern void note_scsi_host(struct device_node *, void *);
  92
  93extern struct task_struct *__switch_to(struct task_struct *,
  94        struct task_struct *);
  95#define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
  96
  97struct thread_struct;
  98extern struct task_struct *_switch(struct thread_struct *prev,
  99                                   struct thread_struct *next);
 100
 101extern unsigned int rtas_data;
 102
 103static __inline__ unsigned long
 104xchg_u32(volatile void *p, unsigned long val)
 105{
 106        unsigned long prev;
 107
 108        __asm__ __volatile__ ("\n\
 1091:      lwarx   %0,0,%2 \n"
 110        PPC405_ERR77(0,%2)
 111"       stwcx.  %3,0,%2 \n\
 112        bne-    1b"
 113        : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
 114        : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
 115        : "cc", "memory");
 116
 117        return prev;
 118}
 119
 120/*
 121 * This function doesn't exist, so you'll get a linker error
 122 * if something tries to do an invalid xchg().
 123 */
 124extern void __xchg_called_with_bad_pointer(void);
 125
 126#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 127#define tas(ptr) (xchg((ptr),1))
 128
 129static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 130{
 131        switch (size) {
 132        case 4:
 133                return (unsigned long) xchg_u32(ptr, x);
 134#if 0   /* xchg_u64 doesn't exist on 32-bit PPC */
 135        case 8:
 136                return (unsigned long) xchg_u64(ptr, x);
 137#endif /* 0 */
 138        }
 139        __xchg_called_with_bad_pointer();
 140        return x;
 141
 142
 143}
 144
 145extern inline void * xchg_ptr(void * m, void * val)
 146{
 147        return (void *) xchg_u32(m, (unsigned long) val);
 148}
 149
 150
 151#define __HAVE_ARCH_CMPXCHG     1
 152
 153static __inline__ unsigned long
 154__cmpxchg_u32(volatile int *p, int old, int new)
 155{
 156        int prev;
 157
 158        __asm__ __volatile__ ("\n\
 1591:      lwarx   %0,0,%2 \n\
 160        cmpw    0,%0,%3 \n\
 161        bne     2f \n"
 162        PPC405_ERR77(0,%2)
 163"       stwcx.  %4,0,%2 \n\
 164        bne-    1b\n"
 165#ifdef CONFIG_SMP
 166"       sync\n"
 167#endif /* CONFIG_SMP */
 168"2:"
 169        : "=&r" (prev), "=m" (*p)
 170        : "r" (p), "r" (old), "r" (new), "m" (*p)
 171        : "cc", "memory");
 172
 173        return prev;
 174}
 175
 176/* This function doesn't exist, so you'll get a linker error
 177   if something tries to do an invalid cmpxchg().  */
 178extern void __cmpxchg_called_with_bad_pointer(void);
 179
 180static __inline__ unsigned long
 181__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 182{
 183        switch (size) {
 184        case 4:
 185                return __cmpxchg_u32(ptr, old, new);
 186#if 0   /* we don't have __cmpxchg_u64 on 32-bit PPC */
 187        case 8:
 188                return __cmpxchg_u64(ptr, old, new);
 189#endif /* 0 */
 190        }
 191        __cmpxchg_called_with_bad_pointer();
 192        return old;
 193}
 194
 195#define cmpxchg(ptr,o,n)                                                 \
 196  ({                                                                     \
 197     __typeof__(*(ptr)) _o_ = (o);                                       \
 198     __typeof__(*(ptr)) _n_ = (n);                                       \
 199     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 200                                    (unsigned long)_n_, sizeof(*(ptr))); \
 201  })
 202
 203#endif /* __KERNEL__ */
 204#endif /* __PPC_SYSTEM_H */
 205