LXR linux-bk/arch/sh/drivers/pci/pci-auto.c

   1/*
   2 * PCI autoconfiguration library
   3 *
   4 * Author: Matt Porter <mporter@mvista.com>
   5 *
   6 * Copyright 2000, 2001 MontaVista Software Inc.
   7 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
   8 * Copyright 2003 Paul Mundt <lethal@linux-sh.org>
   9 *
  10 * This program is free software; you can redistribute  it and/or modify it
  11 * under  the terms of  the GNU General  Public License as published by the
  12 * Free Software Foundation;  either version 2 of the  License, or (at your
  13 * option) any later version.
  14 */
  15
  16/*
  17 * Modified for MIPS by Jun Sun, jsun@mvista.com
  18 *
  19 * . Simplify the interface between pci_auto and the rest: a single function.
  20 * . Assign resources from low address to upper address.
  21 * . change most int to u32.
  22 *
  23 * Further modified to include it as mips generic code, ppopov@mvista.com.
  24 *
  25 * 2001-10-26  Bradley D. LaRonde <brad@ltc.com>
  26 * - Add a top_bus argument to the "early config" functions so that
  27 *   they can set a fake parent bus pointer to convince the underlying
  28 *   pci ops to use type 1 configuration for sub busses.
  29 * - Set bridge base and limit registers correctly.
  30 * - Align io and memory base properly before and after bridge setup.
  31 * - Don't fall through to pci_setup_bars for bridge.
  32 * - Reformat the debug output to look more like lspci's output.
  33 *
  34 * Cloned for SuperH by M. R. Brown, mrbrown@0xd6.org
  35 *
  36 * 2003-08-05  Paul Mundt <lethal@linux-sh.org>
  37 * - Don't update the BAR values on systems that already have valid addresses
  38 *   and don't want these updated for whatever reason, by way of a new config
  39 *   option check. However, we still read in the old BAR values so that they
  40 *   can still be reported through the debug output.
  41 */
  42
  43#include <linux/kernel.h>
  44#include <linux/init.h>
  45#include <linux/types.h>
  46#include <linux/pci.h>
  47
  48#undef  DEBUG
  49#ifdef  DEBUG
  50#define DBG(x...)       printk(x)
  51#else
  52#define DBG(x...)       
  53#endif
  54
  55/*
  56 * These functions are used early on before PCI scanning is done
  57 * and all of the pci_dev and pci_bus structures have been created.
  58 */
  59static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
  60        int top_bus, int busnr, int devfn)
  61{
  62        static struct pci_dev dev;
  63        static struct pci_bus bus;
  64
  65        dev.bus = &bus;
  66        dev.sysdata = hose;
  67        dev.devfn = devfn;
  68        bus.number = busnr;
  69        bus.ops = hose->pci_ops;
  70
  71        if(busnr != top_bus)
  72                /* Fake a parent bus structure. */
  73                bus.parent = &bus;
  74        else
  75                bus.parent = NULL;
  76
  77        return &dev;
  78}
  79
  80#define EARLY_PCI_OP(rw, size, type)                                    \
  81int early_##rw##_config_##size(struct pci_channel *hose,                \
  82        int top_bus, int bus, int devfn, int offset, type value)        \
  83{                                                                       \
  84        return pci_##rw##_config_##size(                                \
  85                fake_pci_dev(hose, top_bus, bus, devfn),                \
  86                offset, value);                                         \
  87}
  88
  89EARLY_PCI_OP(read, byte, u8 *)
  90EARLY_PCI_OP(read, word, u16 *)
  91EARLY_PCI_OP(read, dword, u32 *)
  92EARLY_PCI_OP(write, byte, u8)
  93EARLY_PCI_OP(write, word, u16)
  94EARLY_PCI_OP(write, dword, u32)
  95
  96static struct resource *io_resource_inuse;
  97static struct resource *mem_resource_inuse;
  98
  99static u32 pciauto_lower_iospc;
 100static u32 pciauto_upper_iospc;
 101
 102static u32 pciauto_lower_memspc;
 103static u32 pciauto_upper_memspc;
 104
 105static void __init 
 106pciauto_setup_bars(struct pci_channel *hose,
 107                   int top_bus,
 108                   int current_bus,
 109                   int pci_devfn,
 110                   int bar_limit)
 111{
 112        u32 bar_response, bar_size, bar_value;
 113        u32 bar, addr_mask, bar_nr = 0;
 114        u32 * upper_limit;
 115        u32 * lower_limit;
 116        int found_mem64 = 0;
 117
 118        for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
 119#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
 120                u32 bar_addr;
 121
 122                /* Read the old BAR value */
 123                early_read_config_dword(hose, top_bus,
 124                                        current_bus,
 125                                        pci_devfn,
 126                                        bar,
 127                                        &bar_addr);
 128#endif
 129
 130                /* Tickle the BAR and get the response */
 131                early_write_config_dword(hose, top_bus,
 132                                         current_bus,
 133                                         pci_devfn,
 134                                         bar,
 135                                         0xffffffff);
 136
 137                early_read_config_dword(hose, top_bus,
 138                                        current_bus,
 139                                        pci_devfn,
 140                                        bar,
 141                                        &bar_response);
 142
 143#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
 144                /* 
 145                 * Write the old BAR value back out, only update the BAR
 146                 * if we implicitly want resources to be updated, which
 147                 * is done by the generic code further down. -- PFM.
 148                 */
 149                early_write_config_dword(hose, top_bus,
 150                                         current_bus,
 151                                         pci_devfn,
 152                                         bar,
 153                                         bar_addr);
 154#endif
 155
 156                /* If BAR is not implemented go to the next BAR */
 157                if (!bar_response)
 158                        continue;
 159
 160                /*
 161                 * Workaround for a BAR that doesn't use its upper word,
 162                 * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
 163                 * bdl <brad@ltc.com>
 164                 */
 165                if (!(bar_response & 0xffff0000))
 166                        bar_response |= 0xffff0000;
 167
 168retry:
 169                /* Check the BAR type and set our address mask */
 170                if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 171                        addr_mask = PCI_BASE_ADDRESS_IO_MASK;
 172                        upper_limit = &pciauto_upper_iospc;
 173                        lower_limit = &pciauto_lower_iospc;
 174                        DBG("        I/O");
 175                } else {
 176                        if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 177                            PCI_BASE_ADDRESS_MEM_TYPE_64)
 178                                found_mem64 = 1;
 179
 180                        addr_mask = PCI_BASE_ADDRESS_MEM_MASK;          
 181                        upper_limit = &pciauto_upper_memspc;
 182                        lower_limit = &pciauto_lower_memspc;
 183                        DBG("        Mem");
 184                }
 185
 186
 187                /* Calculate requested size */
 188                bar_size = ~(bar_response & addr_mask) + 1;
 189
 190                /* Allocate a base address */
 191                bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
 192
 193                if ((bar_value + bar_size) > *upper_limit) {
 194                        if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 195                                if (io_resource_inuse->child) {
 196                                        io_resource_inuse = 
 197                                                io_resource_inuse->child;
 198                                        pciauto_lower_iospc = 
 199                                                io_resource_inuse->start;
 200                                        pciauto_upper_iospc = 
 201                                                io_resource_inuse->end + 1;
 202                                        goto retry;
 203                                }
 204
 205                        } else {
 206                                if (mem_resource_inuse->child) {
 207                                        mem_resource_inuse = 
 208                                                mem_resource_inuse->child;
 209                                        pciauto_lower_memspc = 
 210                                                mem_resource_inuse->start;
 211                                        pciauto_upper_memspc = 
 212                                                mem_resource_inuse->end + 1;
 213                                        goto retry;
 214                                }
 215                        }
 216                        DBG(" unavailable -- skipping, value %x size %x\n",
 217                                        bar_value, bar_size);
 218                        continue;
 219                }
 220
 221#ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
 222                /* Write it out and update our limit */
 223                early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 224                                         bar, bar_value);
 225#endif
 226
 227                *lower_limit = bar_value + bar_size;
 228
 229                /*
 230                 * If we are a 64-bit decoder then increment to the
 231                 * upper 32 bits of the bar and force it to locate
 232                 * in the lower 4GB of memory.
 233                 */ 
 234                if (found_mem64) {
 235                        bar += 4;
 236                        early_write_config_dword(hose, top_bus,
 237                                                 current_bus,
 238                                                 pci_devfn,
 239                                                 bar,
 240                                                 0x00000000);
 241                }
 242
 243                DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
 244
 245                bar_nr++;
 246        }
 247
 248}
 249
 250static void __init
 251pciauto_prescan_setup_bridge(struct pci_channel *hose,
 252                             int top_bus,
 253                             int current_bus,
 254                             int pci_devfn,
 255                             int sub_bus)
 256{
 257        /* Configure bus number registers */
 258        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 259                                PCI_PRIMARY_BUS, current_bus);
 260        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 261                                PCI_SECONDARY_BUS, sub_bus + 1);
 262        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 263                                PCI_SUBORDINATE_BUS, 0xff);
 264
 265        /* Align memory and I/O to 1MB and 4KB boundaries. */
 266        pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 267                & ~(0x100000 - 1);
 268        pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 269                & ~(0x1000 - 1);
 270
 271        /* Set base (lower limit) of address range behind bridge. */
 272        early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 273                PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
 274        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 275                PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
 276        early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 277                PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
 278
 279        /* We don't support prefetchable memory for now, so disable */
 280        early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 281                                PCI_PREF_MEMORY_BASE, 0);
 282        early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 283                                PCI_PREF_MEMORY_LIMIT, 0);
 284}
 285
 286static void __init
 287pciauto_postscan_setup_bridge(struct pci_channel *hose,
 288                              int top_bus,
 289                              int current_bus,
 290                              int pci_devfn,
 291                              int sub_bus)
 292{
 293        u32 temp;
 294
 295        /*
 296         * [jsun] we always bump up baselines a little, so that if there
 297         * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
 298         * spaces.
 299         */
 300        pciauto_lower_memspc += 1;
 301        pciauto_lower_iospc += 1;
 302
 303        /* Configure bus number registers */
 304        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 305                                PCI_SUBORDINATE_BUS, sub_bus);
 306
 307        /* Set upper limit of address range behind bridge. */
 308        early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 309                PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
 310        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 311                PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
 312        early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 313                PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
 314
 315        /* Align memory and I/O to 1MB and 4KB boundaries. */
 316        pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 317                & ~(0x100000 - 1);
 318        pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 319                & ~(0x1000 - 1);
 320
 321        /* Enable memory and I/O accesses, enable bus master */
 322        early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 323                PCI_COMMAND, &temp);
 324        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 325                PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 326                | PCI_COMMAND_MASTER);
 327}
 328
 329static void __init
 330pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
 331                        int top_bus,
 332                        int current_bus,
 333                        int pci_devfn,
 334                        int sub_bus)
 335{
 336        /* Configure bus number registers */
 337        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 338                                PCI_PRIMARY_BUS, current_bus);
 339        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 340                                PCI_SECONDARY_BUS, sub_bus + 1);
 341        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 342                                PCI_SUBORDINATE_BUS, 0xff);
 343
 344        /* Align memory and I/O to 4KB and 4 byte boundaries. */
 345        pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 346                & ~(0x1000 - 1);
 347        pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 348                & ~(0x4 - 1);
 349
 350        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 351                PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
 352        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 353                PCI_CB_IO_BASE_0, pciauto_lower_iospc);
 354}
 355
 356static void __init
 357pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
 358                        int top_bus,
 359                        int current_bus,
 360                        int pci_devfn,
 361                        int sub_bus)
 362{
 363        u32 temp;
 364
 365#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
 366        /*
 367         * [jsun] we always bump up baselines a little, so that if there
 368         * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
 369         * spaces.
 370         */
 371        pciauto_lower_memspc += 1;
 372        pciauto_lower_iospc += 1;
 373#endif
 374
 375        /*
 376         * Configure subordinate bus number.  The PCI subsystem
 377         * bus scan will renumber buses (reserving three additional
 378         * for this PCI<->CardBus bridge for the case where a CardBus
 379         * adapter contains a P2P or CB2CB bridge.
 380         */
 381
 382        early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 383                                PCI_SUBORDINATE_BUS, sub_bus);
 384
 385        /*
 386         * Reserve an additional 4MB for mem space and 16KB for
 387         * I/O space.  This should cover any additional space
 388         * requirement of unusual CardBus devices with
 389         * additional bridges that can consume more address space.
 390         *
 391         * Although pcmcia-cs currently will reprogram bridge
 392         * windows, the goal is to add an option to leave them
 393         * alone and use the bridge window ranges as the regions
 394         * that are searched for free resources upon hot-insertion
 395         * of a device.  This will allow a PCI<->CardBus bridge
 396         * configured by this routine to happily live behind a
 397         * P2P bridge in a system.
 398         */
 399#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)
 400        pciauto_lower_memspc += 0x00400000;
 401        pciauto_lower_iospc += 0x00004000;
 402#endif
 403
 404        /* Align memory and I/O to 4KB and 4 byte boundaries. */
 405        pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 406                & ~(0x1000 - 1);
 407        pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 408                & ~(0x4 - 1);
 409        /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 410        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 411                PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
 412        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 413                PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
 414
 415        /* Enable memory and I/O accesses, enable bus master */
 416        early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 417                PCI_COMMAND, &temp);
 418        early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 419                PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 420                PCI_COMMAND_MASTER);
 421}
 422
 423#define PCIAUTO_IDE_MODE_MASK           0x05
 424
 425static int __init
 426pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
 427{
 428        int sub_bus;
 429        u32 pci_devfn, pci_class, cmdstat, found_multi=0;
 430        unsigned short vid, did;
 431        unsigned char header_type;
 432        int devfn_start = 0;
 433        int devfn_stop = 0xff;
 434
 435        sub_bus = current_bus;
 436        
 437        if (hose->first_devfn)
 438                devfn_start = hose->first_devfn;
 439        if (hose->last_devfn)
 440                devfn_stop = hose->last_devfn;
 441        
 442        for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
 443
 444                if (PCI_FUNC(pci_devfn) && !found_multi)
 445                        continue;
 446
 447                early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 448                                       PCI_VENDOR_ID, &vid);
 449
 450                if (vid == 0xffff) continue;
 451
 452                early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
 453                                       PCI_HEADER_TYPE, &header_type);
 454
 455                if (!PCI_FUNC(pci_devfn))
 456                        found_multi = header_type & 0x80;
 457
 458                early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 459                                       PCI_DEVICE_ID, &did);
 460
 461                early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 462                                        PCI_CLASS_REVISION, &pci_class);
 463
 464                DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
 465                        current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
 466                        pci_class >> 16, vid, did);
 467                if (pci_class & 0xff)
 468                        DBG(" (rev %.2x)", pci_class & 0xff);
 469                DBG("\n");
 470
 471                if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
 472                        DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
 473                                current_bus, sub_bus + 1);
 474#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)
 475                        pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_1);
 476#endif
 477                        pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
 478                                                     pci_devfn, sub_bus);
 479                        DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 480                                sub_bus + 1,
 481                                pciauto_lower_iospc, pciauto_lower_memspc);
 482                        sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 483                        DBG("Back to bus %.2x\n", current_bus);
 484                        pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
 485                                                        pci_devfn, sub_bus);
 486                        continue;
 487                } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
 488                        DBG("  CARDBUS  Bridge: primary=%.2x, secondary=%.2x\n",
 489                                current_bus, sub_bus + 1);
 490                        DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
 491                        /* Place CardBus Socket/ExCA registers */
 492                        pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
 493 
 494                        pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
 495                                        current_bus, pci_devfn, sub_bus);
 496 
 497                        DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 498                                sub_bus + 1,
 499                                pciauto_lower_iospc, pciauto_lower_memspc);
 500                        sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 501                        DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
 502                        pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
 503                                        current_bus, pci_devfn, sub_bus);
 504                        continue;
 505                } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
 506
 507                        unsigned char prg_iface;
 508
 509                        early_read_config_byte(hose, top_bus, current_bus,
 510                                pci_devfn, PCI_CLASS_PROG, &prg_iface);
 511                        if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 512                                DBG("Skipping legacy mode IDE controller\n");
 513                                continue;
 514                        }
 515                }
 516
 517                /*
 518                 * Found a peripheral, enable some standard
 519                 * settings
 520                 */
 521                early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 522                                        PCI_COMMAND, &cmdstat);
 523                early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 524                                         PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
 525                                         PCI_COMMAND_MEMORY |
 526                                         PCI_COMMAND_MASTER);
 527                early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 528                                        PCI_LATENCY_TIMER, 0x80);
 529
 530                /* Allocate PCI I/O and/or memory space */
 531                pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
 532        }
 533        return sub_bus;
 534}
 535
 536int __init
 537pciauto_assign_resources(int busno, struct pci_channel *hose)
 538{
 539        /* setup resource limits */
 540        io_resource_inuse = hose->io_resource;
 541        mem_resource_inuse = hose->mem_resource;
 542
 543        pciauto_lower_iospc = io_resource_inuse->start;
 544        pciauto_upper_iospc = io_resource_inuse->end + 1;
 545        pciauto_lower_memspc = mem_resource_inuse->start;
 546        pciauto_upper_memspc = mem_resource_inuse->end + 1;
 547        DBG("Autoconfig PCI channel 0x%p\n", hose);
 548        DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
 549                busno, pciauto_lower_iospc, pciauto_upper_iospc, 
 550                pciauto_lower_memspc, pciauto_upper_memspc);
 551
 552        return pciauto_bus_scan(hose, busno, busno);
 553}
 554