LXR linux-bk/arch/ppc/platforms/4xx/sycamore.c

   1/*
   2 * arch/ppc/platforms/4xx/sycamore.c
   3 *
   4 * Architecture- / platform-specific boot-time initialization code for
   5 * IBM PowerPC 4xx based boards.
   6 *
   7 * Author: Armin Kuster <akuster@mvista.com>
   8 *
   9 * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
  10 * the terms of the GNU General Public License version 2.  This program
  11 * is licensed "as is" without any warranty of any kind, whether express
  12 * or implied.
  13 */
  14#include <linux/config.h>
  15#include <linux/init.h>
  16#include <linux/smp.h>
  17#include <linux/threads.h>
  18#include <linux/param.h>
  19#include <linux/string.h>
  20#include <linux/pci.h>
  21#include <linux/rtc.h>
  22
  23#include <asm/ocp.h>
  24#include <asm/ppc4xx_pic.h>
  25#include <asm/system.h>
  26#include <asm/pci-bridge.h>
  27#include <asm/machdep.h>
  28#include <asm/page.h>
  29#include <asm/time.h>
  30#include <asm/io.h>
  31#include <asm/ibm_ocp_pci.h>
  32#include <asm/todc.h>
  33
  34#undef DEBUG
  35
  36#ifdef DEBUG
  37#define DBG(x...) printk(x)
  38#else
  39#define DBG(x...)
  40#endif
  41
  42void *kb_cs;
  43void *kb_data;
  44void *sycamore_rtc_base;
  45
  46/*
  47 * Define all of the IRQ senses and polarities.
  48 */
  49
  50static u_char Sycamore_IRQ_initsenses[] __initdata = {
  51        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 0: Uart 0*/
  52        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 1: Uart 1*/
  53        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 2: IIC */
  54        (IRQ_SENSE_EDGE  | IRQ_POLARITY_POSITIVE),      /* 3: External Master */
  55        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 4: PCI ext cmd write*/
  56        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 5: DMA Chan 0 */
  57        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 6: DMA Chan 1 */
  58        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 7: DMA Chan 2 */
  59        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 8: DMA Chan 3 */
  60        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 9: Ethernet wakeup (WOL)*/
  61        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 10: Mal (SEER) */
  62        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 11: Mal TXEOB */
  63        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 12: Mal RXEOB */
  64        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 13: Mal TXDE*/
  65        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 14: Mal RXDE*/
  66        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 15: Ethernet */
  67        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 16: Ext PCI SERR */
  68        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 17: ECC */
  69        (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* 18: PCI PM*/
  70        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 19: Ext Int 7 */
  71        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 20: Ext Int 8 */
  72        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 21: Ext Int 9 */
  73        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 22: Ext Int 10 */
  74        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 23: Ext Int 11 */
  75        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 24: Ext Int 12 */
  76        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 25: Ext Int 0 */
  77        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 26: Ext Int 1 */
  78        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 27: Ext Int 2 */
  79        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 28: Ext Int 3 */
  80        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 29: Ext Int 4 */
  81        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 30: Ext Int 5 */
  82        (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 31: Ext Int 6 */
  83};
  84
  85
  86/* Some IRQs unique to Sycamore.
  87 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
  88 */
  89int __init
  90ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  91{
  92        static char pci_irq_table[][4] =
  93            /*
  94             *      PCI IDSEL/INTPIN->INTLINE
  95             *      A       B       C       D
  96             */
  97        {
  98                {28, 28, 28, 28},       /* IDSEL 1 - PCI slot 1 */
  99                {29, 29, 29, 29},       /* IDSEL 2 - PCI slot 2 */
 100                {30, 30, 30, 30},       /* IDSEL 3 - PCI slot 3 */
 101                {31, 31, 31, 31},       /* IDSEL 4 - PCI slot 4 */
 102        };
 103
 104        const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 105        return PCI_IRQ_TABLE_LOOKUP;
 106};
 107
 108void __init
 109sycamore_setup_arch(void)
 110{
 111#define SYCAMORE_PS2_BASE       0xF0100000
 112#define SYCAMORE_FPGA_BASE      0xF0300000
 113
 114        void *fpga_brdc;
 115        unsigned char fpga_brdc_data;
 116        void *fpga_enable;
 117        void *fpga_polarity;
 118        void *fpga_status;
 119        void *fpga_trigger;
 120
 121        ppc4xx_setup_arch();
 122
 123        ibm_ocp_set_emac(0, 1);
 124
 125        kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
 126        if (!kb_data) {
 127                printk(KERN_CRIT
 128                       "sycamore_setup_arch() kb_data ioremap failed\n");
 129                return;
 130        }
 131
 132        kb_cs = kb_data + 1;
 133
 134        fpga_status = ioremap(SYCAMORE_FPGA_BASE, 8);
 135        if (!fpga_status) {
 136                printk(KERN_CRIT
 137                       "sycamore_setup_arch() fpga_status ioremap failed\n");
 138                return;
 139        }
 140
 141        fpga_enable = fpga_status + 1;
 142        fpga_polarity = fpga_status + 2;
 143        fpga_trigger = fpga_status + 3;
 144        fpga_brdc = fpga_status + 4;
 145
 146        /* split the keyboard and mouse interrupts */
 147        fpga_brdc_data = readb(fpga_brdc);
 148        fpga_brdc_data |= 0x80;
 149        writeb(fpga_brdc_data, fpga_brdc);
 150
 151        writeb(0x3, fpga_enable);
 152
 153        writeb(0x3, fpga_polarity);
 154
 155        writeb(0x3, fpga_trigger);
 156
 157        /* RTC step for the sycamore */
 158        sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
 159        TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
 160                  sycamore_rtc_base, 8);
 161        ibm4xxPIC_InitSenses = Sycamore_IRQ_initsenses;
 162        ibm4xxPIC_NumInitSenses = sizeof(Sycamore_IRQ_initsenses);
 163
 164        /* Identify the system */
 165        printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
 166        printk(KERN_INFO
 167               "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 168}
 169
 170void __init
 171bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 172{
 173#ifdef CONFIG_PCI
 174        unsigned int bar_response, bar;
 175        /*
 176         * Expected PCI mapping:
 177         *
 178         *  PLB addr             PCI memory addr
 179         *  ---------------------       ---------------------
 180         *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
 181         *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
 182         *
 183         *  PLB addr             PCI io addr
 184         *  ---------------------       ---------------------
 185         *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
 186         *
 187         * The following code is simplified by assuming that the bootrom
 188         * has been well behaved in following this mapping.
 189         */
 190
 191#ifdef DEBUG
 192        int i;
 193
 194        printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
 195        printk("PCI bridge regs before fixup \n");
 196        for (i = 0; i <= 3; i++) {
 197                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 198                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 199                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 200                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 201        }
 202        printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 203        printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 204        printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 205        printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 206
 207#endif
 208
 209        /* added for IBM boot rom version 1.15 bios bar changes  -AK */
 210
 211        /* Disable region first */
 212        out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 213        /* PLB starting addr, PCI: 0x80000000 */
 214        out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
 215        /* PCI start addr, 0x80000000 */
 216        out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
 217        /* 512MB range of PLB to PCI */
 218        out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
 219        /* Enable no pre-fetch, enable region */
 220        out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
 221                                                (PPC405_PCI_UPPER_MEM -
 222                                                 PPC405_PCI_MEM_BASE)) | 0x01));
 223
 224        /* Enable inbound region one - 1GB size */
 225        out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
 226
 227        /* Disable outbound region one */
 228        out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 229        out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 230        out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 231        out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 232        out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 233
 234        /* Disable inbound region two */
 235        out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 236
 237        /* Disable outbound region two */
 238        out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 239        out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 240        out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 241        out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 242        out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 243
 244        /* Zero config bars */
 245        for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 246                early_write_config_dword(hose, hose->first_busno,
 247                                         PCI_FUNC(hose->first_busno), bar,
 248                                         0x00000000);
 249                early_read_config_dword(hose, hose->first_busno,
 250                                        PCI_FUNC(hose->first_busno), bar,
 251                                        &bar_response);
 252                DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
 253                    hose->first_busno, PCI_SLOT(hose->first_busno),
 254                    PCI_FUNC(hose->first_busno), bar, bar_response);
 255        }
 256        /* end work arround */
 257
 258#ifdef DEBUG
 259        printk("PCI bridge regs after fixup \n");
 260        for (i = 0; i <= 3; i++) {
 261                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 262                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 263                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 264                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 265        }
 266        printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 267        printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 268        printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 269        printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 270
 271#endif
 272#endif
 273
 274}
 275
 276void __init
 277sycamore_map_io(void)
 278{
 279        ppc4xx_map_io();
 280        io_block_mapping(SYCAMORE_RTC_VADDR,
 281                         SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
 282}
 283
 284void __init
 285platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 286              unsigned long r6, unsigned long r7)
 287{
 288        ppc4xx_init(r3, r4, r5, r6, r7);
 289
 290        ppc_md.setup_arch = sycamore_setup_arch;
 291        ppc_md.setup_io_mappings = sycamore_map_io;
 292
 293#ifdef CONFIG_GEN_RTC
 294        ppc_md.time_init = todc_time_init;
 295        ppc_md.set_rtc_time = todc_set_rtc_time;
 296        ppc_md.get_rtc_time = todc_get_rtc_time;
 297        ppc_md.nvram_read_val = todc_direct_read_val;
 298        ppc_md.nvram_write_val = todc_direct_write_val;
 299#endif
 300}
 301