LXR linux-bk/arch/ppc/platforms/4xx/ep405.c

   1/*
   2 * arch/ppc/platforms/4xx/ep405.c
   3 *
   4 * Embedded Planet 405GP board
   5 * http://www.embeddedplanet.com
   6 *
   7 * Author: Matthew Locke <mlocke@mvista.com>
   8 *
   9 * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  10 * the terms of the GNU General Public License version 2.  This program
  11 * is licensed "as is" without any warranty of any kind, whether express
  12 * or implied.
  13 */
  14#include <linux/config.h>
  15#include <linux/init.h>
  16#include <linux/pci.h>
  17#include <asm/system.h>
  18#include <asm/pci-bridge.h>
  19#include <asm/machdep.h>
  20#include <asm/todc.h>
  21#include <asm/ocp.h>
  22#include <asm/ibm_ocp_pci.h>
  23
  24#undef DEBUG
  25#ifdef DEBUG
  26#define DBG(x...) printk(x)
  27#else
  28#define DBG(x...)
  29#endif
  30
  31u8 *ep405_bcsr;
  32u8 *ep405_nvram;
  33
  34static struct {
  35        u8 cpld_xirq_select;
  36        int pci_idsel;
  37        int irq;
  38} ep405_devtable[] = {
  39#ifdef CONFIG_EP405PC
  40        {0x07, 0x0E, 25},               /* EP405PC: USB */
  41#endif
  42};
  43
  44int __init
  45ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  46{
  47        int i;
  48
  49        /* AFAICT this is only called a few times during PCI setup, so
  50           performance is not critical */
  51        for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
  52                if (idsel == ep405_devtable[i].pci_idsel)
  53                        return ep405_devtable[i].irq;
  54        }
  55        return -1;
  56};
  57
  58void __init
  59ep405_setup_arch(void)
  60{
  61        ppc4xx_setup_arch();
  62
  63        ibm_ocp_set_emac(0, 0);
  64
  65        if (__res.bi_nvramsize == 512*1024) {
  66                /* FIXME: we should properly handle NVRTCs of different sizes */
  67                TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
  68        }
  69}
  70
  71void __init
  72bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
  73{
  74        unsigned int bar_response, bar;
  75        /*
  76         * Expected PCI mapping:
  77         *
  78         *  PLB addr             PCI memory addr
  79         *  ---------------------       ---------------------
  80         *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
  81         *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
  82         *
  83         *  PLB addr             PCI io addr
  84         *  ---------------------       ---------------------
  85         *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
  86         *
  87         */
  88
  89        /* Disable region zero first */
  90        out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
  91        /* PLB starting addr, PCI: 0x80000000 */
  92        out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
  93        /* PCI start addr, 0x80000000 */
  94        out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
  95        /* 512MB range of PLB to PCI */
  96        out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
  97        /* Enable no pre-fetch, enable region */
  98        out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
  99                                                (PPC405_PCI_UPPER_MEM -
 100                                                 PPC405_PCI_MEM_BASE)) | 0x01));
 101
 102        /* Disable region one */
 103        out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 104        out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 105        out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 106        out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 107        out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 108        out_le32((void *) &(pcip->ptm1ms), 0x00000000);
 109
 110        /* Disable region two */
 111        out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 112        out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 113        out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 114        out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 115        out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 116        out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 117
 118        /* Configure PTM (PCI->PLB) region 1 */
 119        out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
 120        /* Disable PTM region 2 */
 121        out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 122
 123        /* Zero config bars */
 124        for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 125                early_write_config_dword(hose, hose->first_busno,
 126                                         PCI_FUNC(hose->first_busno), bar,
 127                                         0x00000000);
 128                early_read_config_dword(hose, hose->first_busno,
 129                                        PCI_FUNC(hose->first_busno), bar,
 130                                        &bar_response);
 131                DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
 132                    hose->first_busno, PCI_SLOT(hose->first_busno),
 133                    PCI_FUNC(hose->first_busno), bar, bar_response);
 134        }
 135        /* end work arround */
 136}
 137
 138void __init
 139ep405_map_io(void)
 140{
 141        bd_t *bip = &__res;
 142
 143        ppc4xx_map_io();
 144
 145        ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
 146
 147        if (bip->bi_nvramsize > 0) {
 148                ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize);
 149        }
 150}
 151
 152void __init
 153ep405_init_IRQ(void)
 154{
 155        int i;
 156
 157        ppc4xx_init_IRQ();
 158
 159        /* Workaround for a bug in the firmware it incorrectly sets
 160           the IRQ polarities for XIRQ0 and XIRQ1 */
 161        mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
 162        mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
 163
 164        /* Activate the XIRQs from the CPLD */
 165        writeb(0xf0, ep405_bcsr+10);
 166
 167        /* Set up IRQ routing */
 168        for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
 169                if ( (ep405_devtable[i].irq >= 25)
 170                     && (ep405_devtable[i].irq) <= 31) {
 171                        writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
 172                        writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6);
 173                }
 174        }
 175}
 176
 177void __init
 178platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 179              unsigned long r6, unsigned long r7)
 180{
 181        ppc4xx_init(r3, r4, r5, r6, r7);
 182
 183        ppc_md.setup_arch = ep405_setup_arch;
 184        ppc_md.setup_io_mappings = ep405_map_io;
 185        ppc_md.init_IRQ = ep405_init_IRQ;
 186
 187        ppc_md.nvram_read_val = todc_direct_read_val;
 188        ppc_md.nvram_write_val = todc_direct_write_val;
 189
 190        if (__res.bi_nvramsize == 512*1024) {
 191                ppc_md.time_init = todc_time_init;
 192                ppc_md.set_rtc_time = todc_set_rtc_time;
 193                ppc_md.get_rtc_time = todc_get_rtc_time;
 194        } else {
 195                printk("EP405: NVRTC size is not 512k (not a DS1557).  Not sure what to do with it\n");
 196        }
 197}
 198