LXR linux-bk/arch/ppc/platforms/4xx/bubinga.c

   1/*
   2 * Support for IBM PPC 405EP evaluation board (Bubinga).
   3 *
   4 * Author: SAW (IBM), derived from walnut.c.
   5 *         Maintained by MontaVista Software <source@mvista.com>
   6 *
   7 * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
   8 * terms of the GNU General Public License version 2. This program is
   9 * licensed "as is" without any warranty of any kind, whether express
  10 * or implied.
  11 */
  12
  13#include <linux/config.h>
  14#include <linux/init.h>
  15#include <linux/smp.h>
  16#include <linux/threads.h>
  17#include <linux/param.h>
  18#include <linux/string.h>
  19#include <linux/blkdev.h>
  20#include <linux/pci.h>
  21#include <linux/rtc.h>
  22#include <linux/tty.h>
  23#include <linux/serial.h>
  24#include <linux/serial_core.h>
  25
  26#include <asm/system.h>
  27#include <asm/pci-bridge.h>
  28#include <asm/processor.h>
  29#include <asm/machdep.h>
  30#include <asm/page.h>
  31#include <asm/time.h>
  32#include <asm/io.h>
  33#include <asm/todc.h>
  34#include <asm/kgdb.h>
  35#include <asm/ocp.h>
  36#include <asm/ibm_ocp_pci.h>
  37
  38#include <platforms/4xx/ibm405ep.h>
  39
  40#undef DEBUG
  41
  42#ifdef DEBUG
  43#define DBG(x...) printk(x)
  44#else
  45#define DBG(x...)
  46#endif
  47
  48extern bd_t __res;
  49
  50void *bubinga_rtc_base;
  51
  52/* Some IRQs unique to the board
  53 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
  54 */
  55int __init
  56ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  57{
  58        static char pci_irq_table[][4] =
  59            /*
  60             *      PCI IDSEL/INTPIN->INTLINE
  61             *      A       B       C       D
  62             */
  63        {
  64                {28, 28, 28, 28},       /* IDSEL 1 - PCI slot 1 */
  65                {29, 29, 29, 29},       /* IDSEL 2 - PCI slot 2 */
  66                {30, 30, 30, 30},       /* IDSEL 3 - PCI slot 3 */
  67                {31, 31, 31, 31},       /* IDSEL 4 - PCI slot 4 */
  68        };
  69
  70        const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
  71        return PCI_IRQ_TABLE_LOOKUP;
  72};
  73
  74/* The serial clock for the chip is an internal clock determined by
  75 * different clock speeds/dividers.
  76 * Calculate the proper input baud rate and setup the serial driver.
  77 */
  78static void __init
  79bubinga_early_serial_map(void)
  80{
  81        u32 uart_div;
  82        int uart_clock;
  83        struct uart_port port;
  84
  85         /* Calculate the serial clock input frequency
  86          *
  87          * The base baud is the PLL OUTA (provided in the board info
  88          * structure) divided by the external UART Divisor, divided
  89          * by 16.
  90          */
  91        uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
  92        uart_clock = __res.bi_pllouta_freq / uart_div;
  93
  94        /* Setup serial port access */
  95        memset(&port, 0, sizeof(port));
  96        port.membase = (void*)ACTING_UART0_IO_BASE;
  97        port.irq = ACTING_UART0_INT;
  98        port.uartclk = uart_clock;
  99        port.regshift = 0;
 100        port.iotype = SERIAL_IO_MEM;
 101        port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
 102        port.line = 0;
 103
 104        if (early_serial_setup(&port) != 0) {
 105                printk("Early serial init of port 0 failed\n");
 106        }
 107
 108        port.membase = (void*)ACTING_UART1_IO_BASE;
 109        port.irq = ACTING_UART1_INT;
 110        port.line = 1;
 111
 112        if (early_serial_setup(&port) != 0) {
 113                printk("Early serial init of port 1 failed\n");
 114        }
 115}
 116
 117void __init
 118bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 119{
 120
 121        unsigned int bar_response, bar;
 122        /*
 123         * Expected PCI mapping:
 124         *
 125         *  PLB addr             PCI memory addr
 126         *  ---------------------       ---------------------
 127         *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
 128         *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
 129         *
 130         *  PLB addr             PCI io addr
 131         *  ---------------------       ---------------------
 132         *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
 133         *
 134         * The following code is simplified by assuming that the bootrom
 135         * has been well behaved in following this mapping.
 136         */
 137
 138#ifdef DEBUG
 139        int i;
 140
 141        printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
 142        printk("PCI bridge regs before fixup \n");
 143        for (i = 0; i <= 3; i++) {
 144                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 145                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 146                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 147                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 148        }
 149        printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 150        printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 151        printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 152        printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 153
 154#endif
 155
 156        /* added for IBM boot rom version 1.15 bios bar changes  -AK */
 157
 158        /* Disable region first */
 159        out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 160        /* PLB starting addr, PCI: 0x80000000 */
 161        out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
 162        /* PCI start addr, 0x80000000 */
 163        out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
 164        /* 512MB range of PLB to PCI */
 165        out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
 166        /* Enable no pre-fetch, enable region */
 167        out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
 168                                                (PPC405_PCI_UPPER_MEM -
 169                                                 PPC405_PCI_MEM_BASE)) | 0x01));
 170
 171        /* Disable region one */
 172        out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 173        out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
 174        out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
 175        out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
 176        out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
 177        out_le32((void *) &(pcip->ptm1ms), 0x00000001);
 178
 179        /* Disable region two */
 180        out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 181        out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
 182        out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
 183        out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
 184        out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 185        out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 186        out_le32((void *) &(pcip->ptm2la), 0x00000000);
 187
 188        /* Zero config bars */
 189        for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 190                early_write_config_dword(hose, hose->first_busno,
 191                                         PCI_FUNC(hose->first_busno), bar,
 192                                         0x00000000);
 193                early_read_config_dword(hose, hose->first_busno,
 194                                        PCI_FUNC(hose->first_busno), bar,
 195                                        &bar_response);
 196                DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
 197                    hose->first_busno, PCI_SLOT(hose->first_busno),
 198                    PCI_FUNC(hose->first_busno), bar, bar_response);
 199        }
 200        /* end work arround */
 201
 202#ifdef DEBUG
 203        printk("PCI bridge regs after fixup \n");
 204        for (i = 0; i <= 3; i++) {
 205                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
 206                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
 207                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
 208                printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
 209        }
 210        printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
 211        printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
 212        printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
 213        printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
 214
 215#endif
 216}
 217
 218void __init
 219bubinga_setup_arch(void)
 220{
 221        ppc4xx_setup_arch();
 222
 223        ibm_ocp_set_emac(0, 1);
 224
 225        bubinga_early_serial_map();
 226
 227        /* RTC step for the evb405ep */
 228        bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR;
 229        TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base,
 230                  bubinga_rtc_base, 8);
 231        /* Identify the system */
 232        printk("IBM Bubinga port (MontaVista Software, Inc. <source@mvista.com>)\n");
 233}
 234
 235void __init
 236bubinga_map_io(void)
 237{
 238        ppc4xx_map_io();
 239        io_block_mapping(BUBINGA_RTC_VADDR,
 240                         BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO);
 241}
 242
 243void __init
 244platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 245              unsigned long r6, unsigned long r7)
 246{
 247        ppc4xx_init(r3, r4, r5, r6, r7);
 248
 249        ppc_md.setup_arch = bubinga_setup_arch;
 250        ppc_md.setup_io_mappings = bubinga_map_io;
 251
 252#ifdef CONFIG_GEN_RTC
 253        ppc_md.time_init = todc_time_init;
 254        ppc_md.set_rtc_time = todc_set_rtc_time;
 255        ppc_md.get_rtc_time = todc_get_rtc_time;
 256        ppc_md.nvram_read_val = todc_direct_read_val;
 257        ppc_md.nvram_write_val = todc_direct_write_val;
 258#endif
 259#ifdef CONFIG_KGDB
 260        ppc_md.early_serial_map = bubinga_early_serial_map;
 261#endif
 262}
 263
 264