LXR linux-bk/include/asm-arm/arch-ebsa285/hardware.h

   1/*
   2 *  linux/include/asm-arm/arch-ebsa285/hardware.h
   3 *
   4 *  Copyright (C) 1998-1999 Russell King.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 *  This file contains the hardware definitions of the EBSA-285.
  11 */
  12#ifndef __ASM_ARCH_HARDWARE_H
  13#define __ASM_ARCH_HARDWARE_H
  14
  15#include <linux/config.h>
  16#include <asm/arch/memory.h>
  17
  18#ifdef CONFIG_ARCH_FOOTBRIDGE
  19/*   Virtual      Physical      Size
  20 * 0xff800000   0x40000000      1MB     X-Bus
  21 * 0xff000000   0x7c000000      1MB     PCI I/O space
  22 * 0xfe000000   0x42000000      1MB     CSR
  23 * 0xfd000000   0x78000000      1MB     Outbound write flush (not supported)
  24 * 0xfc000000   0x79000000      1MB     PCI IACK/special space
  25 * 0xfb000000   0x7a000000      16MB    PCI Config type 1
  26 * 0xfa000000   0x7b000000      16MB    PCI Config type 0
  27 * 0xf9000000   0x50000000      1MB     Cache flush
  28 * 0xf0000000   0x80000000      16MB    ISA memory
  29 */
  30#define XBUS_SIZE               0x00100000
  31#define XBUS_BASE               0xff800000
  32
  33#define PCIO_SIZE               0x00100000
  34#define PCIO_BASE               0xff000000
  35
  36#define ARMCSR_SIZE             0x00100000
  37#define ARMCSR_BASE             0xfe000000
  38
  39#define WFLUSH_SIZE             0x00100000
  40#define WFLUSH_BASE             0xfd000000
  41
  42#define PCIIACK_SIZE            0x00100000
  43#define PCIIACK_BASE            0xfc000000
  44
  45#define PCICFG1_SIZE            0x01000000
  46#define PCICFG1_BASE            0xfb000000
  47
  48#define PCICFG0_SIZE            0x01000000
  49#define PCICFG0_BASE            0xfa000000
  50
  51#define FLUSH_SIZE              0x00100000
  52#define FLUSH_BASE              0xf9000000
  53
  54#define PCIMEM_SIZE             0x01000000
  55#define PCIMEM_BASE             0xf0000000
  56
  57#elif defined(CONFIG_ARCH_CO285)
  58/*
  59 * This is the COEBSA285 cut-down mapping
  60 */
  61#define PCIMEM_SIZE             0x80000000
  62#define PCIMEM_BASE             0x80000000
  63
  64#define FLUSH_SIZE              0x00100000
  65#define FLUSH_BASE              0x7e000000
  66
  67#define WFLUSH_SIZE             0x01000000
  68#define WFLUSH_BASE             0x7d000000
  69
  70#define ARMCSR_SIZE             0x00100000
  71#define ARMCSR_BASE             0x7cf00000
  72
  73#define XBUS_SIZE               0x00020000
  74#define XBUS_BASE               0x7cee0000
  75
  76#define PCIO_SIZE               0x00010000
  77#define PCIO_BASE               0x7ced0000
  78
  79#else
  80
  81#error "Undefined footbridge architecture"
  82
  83#endif
  84
  85#define XBUS_LEDS               ((volatile unsigned char *)(XBUS_BASE + 0x12000))
  86#define XBUS_LED_AMBER          (1 << 0)
  87#define XBUS_LED_GREEN          (1 << 1)
  88#define XBUS_LED_RED            (1 << 2)
  89#define XBUS_LED_TOGGLE         (1 << 8)
  90
  91#define XBUS_SWITCH             ((volatile unsigned char *)(XBUS_BASE + 0x12000))
  92#define XBUS_SWITCH_SWITCH      ((*XBUS_SWITCH) & 15)
  93#define XBUS_SWITCH_J17_13      ((*XBUS_SWITCH) & (1 << 4))
  94#define XBUS_SWITCH_J17_11      ((*XBUS_SWITCH) & (1 << 5))
  95#define XBUS_SWITCH_J17_9       ((*XBUS_SWITCH) & (1 << 6))
  96
  97#define FLUSH_BASE_PHYS         0x50000000
  98#define UNCACHEABLE_ADDR        (ARMCSR_BASE + 0x108)
  99
 100
 101/* PIC irq control */
 102#define PIC_LO                  0x20
 103#define PIC_MASK_LO             0x21
 104#define PIC_HI                  0xA0
 105#define PIC_MASK_HI             0xA1
 106
 107/* GPIO pins */
 108#define GPIO_CCLK               0x800
 109#define GPIO_DSCLK              0x400
 110#define GPIO_E2CLK              0x200
 111#define GPIO_IOLOAD             0x100
 112#define GPIO_RED_LED            0x080
 113#define GPIO_WDTIMER            0x040
 114#define GPIO_DATA               0x020
 115#define GPIO_IOCLK              0x010
 116#define GPIO_DONE               0x008
 117#define GPIO_FAN                0x004
 118#define GPIO_GREEN_LED          0x002
 119#define GPIO_RESET              0x001
 120
 121/* CPLD pins */
 122#define CPLD_DS_ENABLE          8
 123#define CPLD_7111_DISABLE       4
 124#define CPLD_UNMUTE             2
 125#define CPLD_FLASH_WR_ENABLE    1
 126
 127#ifndef __ASSEMBLY__
 128extern void gpio_modify_op(int mask, int set);
 129extern void gpio_modify_io(int mask, int in);
 130extern int  gpio_read(void);
 131extern void cpld_modify(int mask, int set);
 132#endif
 133
 134#define pcibios_assign_all_busses()     1
 135
 136#define PCIBIOS_MIN_IO          0x1000
 137#define PCIBIOS_MIN_MEM         0x81000000
 138
 139#endif
 140