LXR linux-bk/drivers/net/mv643xx

   1#ifndef __MV64340_ETH_H__
   2#define __MV64340_ETH_H__
   3
   4#include <linux/version.h>
   5#include <linux/module.h>
   6#include <linux/kernel.h>
   7#include <linux/spinlock.h>
   8#include <linux/workqueue.h>
   9
  10#include <linux/mv643xx.h>
  11
  12#define BIT0    0x00000001
  13#define BIT1    0x00000002
  14#define BIT2    0x00000004
  15#define BIT3    0x00000008
  16#define BIT4    0x00000010
  17#define BIT5    0x00000020
  18#define BIT6    0x00000040
  19#define BIT7    0x00000080
  20#define BIT8    0x00000100
  21#define BIT9    0x00000200
  22#define BIT10   0x00000400
  23#define BIT11   0x00000800
  24#define BIT12   0x00001000
  25#define BIT13   0x00002000
  26#define BIT14   0x00004000
  27#define BIT15   0x00008000
  28#define BIT16   0x00010000
  29#define BIT17   0x00020000
  30#define BIT18   0x00040000
  31#define BIT19   0x00080000
  32#define BIT20   0x00100000
  33#define BIT21   0x00200000
  34#define BIT22   0x00400000
  35#define BIT23   0x00800000
  36#define BIT24   0x01000000
  37#define BIT25   0x02000000
  38#define BIT26   0x04000000
  39#define BIT27   0x08000000
  40#define BIT28   0x10000000
  41#define BIT29   0x20000000
  42#define BIT30   0x40000000
  43#define BIT31   0x80000000
  44
  45/*
  46 *  The first part is the high level driver of the gigE ethernet ports.
  47 */
  48
  49#define ETH_PORT0_IRQ_NUM 48                    /* main high register, bit0 */
  50#define ETH_PORT1_IRQ_NUM ETH_PORT0_IRQ_NUM+1   /* main high register, bit1 */
  51#define ETH_PORT2_IRQ_NUM ETH_PORT0_IRQ_NUM+2   /* main high register, bit1 */
  52
  53/* Checksum offload for Tx works */
  54#define  MV64340_CHECKSUM_OFFLOAD_TX
  55#define  MV64340_NAPI
  56#define  MV64340_TX_FAST_REFILL
  57#undef   MV64340_COAL
  58
  59/* 
  60 * Number of RX / TX descriptors on RX / TX rings.
  61 * Note that allocating RX descriptors is done by allocating the RX
  62 * ring AND a preallocated RX buffers (skb's) for each descriptor.
  63 * The TX descriptors only allocates the TX descriptors ring,
  64 * with no pre allocated TX buffers (skb's are allocated by higher layers.
  65 */
  66
  67/* Default TX ring size is 1000 descriptors */
  68#define MV64340_TX_QUEUE_SIZE 1000
  69
  70/* Default RX ring size is 400 descriptors */
  71#define MV64340_RX_QUEUE_SIZE 400
  72
  73#define MV64340_TX_COAL 100
  74#ifdef MV64340_COAL
  75#define MV64340_RX_COAL 100
  76#endif
  77
  78
  79/*
  80 * The second part is the low level driver of the gigE ethernet ports.   *
  81 */
  82
  83
  84/*
  85 * Header File for : MV-643xx network interface header 
  86 *
  87 * DESCRIPTION:
  88 *       This header file contains macros typedefs and function declaration for
  89 *       the Marvell Gig Bit Ethernet Controller. 
  90 *
  91 * DEPENDENCIES:
  92 *       None.
  93 *
  94 */
  95
  96/* Default port configuration value */
  97#define PORT_CONFIG_VALUE                       \
  98             ETH_UNICAST_NORMAL_MODE            |   \
  99             ETH_DEFAULT_RX_QUEUE_0             |   \
 100             ETH_DEFAULT_RX_ARP_QUEUE_0         |   \
 101             ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP    |   \
 102             ETH_RECEIVE_BC_IF_IP               |   \
 103             ETH_RECEIVE_BC_IF_ARP              |   \
 104             ETH_CAPTURE_TCP_FRAMES_DIS         |   \
 105             ETH_CAPTURE_UDP_FRAMES_DIS         |   \
 106             ETH_DEFAULT_RX_TCP_QUEUE_0         |   \
 107             ETH_DEFAULT_RX_UDP_QUEUE_0         |   \
 108             ETH_DEFAULT_RX_BPDU_QUEUE_0
 109
 110/* Default port extend configuration value */
 111#define PORT_CONFIG_EXTEND_VALUE                \
 112             ETH_SPAN_BPDU_PACKETS_AS_NORMAL    |   \
 113             ETH_PARTITION_DISABLE
 114
 115
 116/* Default sdma control value */
 117#define PORT_SDMA_CONFIG_VALUE                  \
 118                         ETH_RX_BURST_SIZE_16_64BIT     |       \
 119                         GT_ETH_IPG_INT_RX(0)           |       \
 120                         ETH_TX_BURST_SIZE_16_64BIT;
 121
 122#define GT_ETH_IPG_INT_RX(value)                \
 123            ((value & 0x3fff) << 8)
 124
 125/* Default port serial control value */
 126#define PORT_SERIAL_CONTROL_VALUE               \
 127                        ETH_FORCE_LINK_PASS                     |       \
 128                        ETH_ENABLE_AUTO_NEG_FOR_DUPLX           |       \
 129                        ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL      |       \
 130                        ETH_ADV_SYMMETRIC_FLOW_CTRL             |       \
 131                        ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX       |       \
 132                        ETH_FORCE_BP_MODE_NO_JAM                |       \
 133                        BIT9                                    |       \
 134                        ETH_DO_NOT_FORCE_LINK_FAIL              |       \
 135                        ETH_RETRANSMIT_16_ATTEMPTS              |       \
 136                        ETH_ENABLE_AUTO_NEG_SPEED_GMII          |       \
 137                        ETH_DTE_ADV_0                           |       \
 138                        ETH_DISABLE_AUTO_NEG_BYPASS             |       \
 139                        ETH_AUTO_NEG_NO_CHANGE                  |       \
 140                        ETH_MAX_RX_PACKET_9700BYTE              |       \
 141                        ETH_CLR_EXT_LOOPBACK                    |       \
 142                        ETH_SET_FULL_DUPLEX_MODE                |       \
 143                        ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
 144
 145#define RX_BUFFER_MAX_SIZE  0x4000000
 146#define TX_BUFFER_MAX_SIZE  0x4000000
 147
 148/* MAC accepet/reject macros */
 149#define ACCEPT_MAC_ADDR     0
 150#define REJECT_MAC_ADDR     1
 151
 152/* Buffer offset from buffer pointer */
 153#define RX_BUF_OFFSET                           0x2
 154
 155/* Gigabit Ethernet Unit Global Registers */
 156
 157/* MIB Counters register definitions */
 158#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
 159#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
 160#define ETH_MIB_BAD_OCTETS_RECEIVED        0x8
 161#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
 162#define ETH_MIB_GOOD_FRAMES_RECEIVED       0x10
 163#define ETH_MIB_BAD_FRAMES_RECEIVED        0x14
 164#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
 165#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
 166#define ETH_MIB_FRAMES_64_OCTETS           0x20
 167#define ETH_MIB_FRAMES_65_TO_127_OCTETS    0x24
 168#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
 169#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
 170#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
 171#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
 172#define ETH_MIB_GOOD_OCTETS_SENT_LOW       0x38
 173#define ETH_MIB_GOOD_OCTETS_SENT_HIGH      0x3c
 174#define ETH_MIB_GOOD_FRAMES_SENT           0x40
 175#define ETH_MIB_EXCESSIVE_COLLISION        0x44
 176#define ETH_MIB_MULTICAST_FRAMES_SENT      0x48
 177#define ETH_MIB_BROADCAST_FRAMES_SENT      0x4c
 178#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
 179#define ETH_MIB_FC_SENT                    0x54
 180#define ETH_MIB_GOOD_FC_RECEIVED           0x58
 181#define ETH_MIB_BAD_FC_RECEIVED            0x5c
 182#define ETH_MIB_UNDERSIZE_RECEIVED         0x60
 183#define ETH_MIB_FRAGMENTS_RECEIVED         0x64
 184#define ETH_MIB_OVERSIZE_RECEIVED          0x68
 185#define ETH_MIB_JABBER_RECEIVED            0x6c
 186#define ETH_MIB_MAC_RECEIVE_ERROR          0x70
 187#define ETH_MIB_BAD_CRC_EVENT              0x74
 188#define ETH_MIB_COLLISION                  0x78
 189#define ETH_MIB_LATE_COLLISION             0x7c
 190
 191/* Port serial status reg (PSR) */
 192#define ETH_INTERFACE_GMII_MII                          0
 193#define ETH_INTERFACE_PCM                               BIT0
 194#define ETH_LINK_IS_DOWN                                0
 195#define ETH_LINK_IS_UP                                  BIT1
 196#define ETH_PORT_AT_HALF_DUPLEX                         0
 197#define ETH_PORT_AT_FULL_DUPLEX                         BIT2
 198#define ETH_RX_FLOW_CTRL_DISABLED                       0
 199#define ETH_RX_FLOW_CTRL_ENBALED                        BIT3
 200#define ETH_GMII_SPEED_100_10                           0
 201#define ETH_GMII_SPEED_1000                             BIT4
 202#define ETH_MII_SPEED_10                                0
 203#define ETH_MII_SPEED_100                               BIT5
 204#define ETH_NO_TX                                       0
 205#define ETH_TX_IN_PROGRESS                              BIT7
 206#define ETH_BYPASS_NO_ACTIVE                            0
 207#define ETH_BYPASS_ACTIVE                               BIT8
 208#define ETH_PORT_NOT_AT_PARTITION_STATE                 0
 209#define ETH_PORT_AT_PARTITION_STATE                     BIT9
 210#define ETH_PORT_TX_FIFO_NOT_EMPTY                      0
 211#define ETH_PORT_TX_FIFO_EMPTY                          BIT10
 212
 213
 214/* These macros describes the Port configuration reg (Px_cR) bits */
 215#define ETH_UNICAST_NORMAL_MODE                         0
 216#define ETH_UNICAST_PROMISCUOUS_MODE                    BIT0
 217#define ETH_DEFAULT_RX_QUEUE_0                          0
 218#define ETH_DEFAULT_RX_QUEUE_1                          BIT1
 219#define ETH_DEFAULT_RX_QUEUE_2                          BIT2
 220#define ETH_DEFAULT_RX_QUEUE_3                          (BIT2 | BIT1)
 221#define ETH_DEFAULT_RX_QUEUE_4                          BIT3
 222#define ETH_DEFAULT_RX_QUEUE_5                          (BIT3 | BIT1)
 223#define ETH_DEFAULT_RX_QUEUE_6                          (BIT3 | BIT2)
 224#define ETH_DEFAULT_RX_QUEUE_7                          (BIT3 | BIT2 | BIT1)
 225#define ETH_DEFAULT_RX_ARP_QUEUE_0                      0
 226#define ETH_DEFAULT_RX_ARP_QUEUE_1                      BIT4
 227#define ETH_DEFAULT_RX_ARP_QUEUE_2                      BIT5
 228#define ETH_DEFAULT_RX_ARP_QUEUE_3                      (BIT5 | BIT4)
 229#define ETH_DEFAULT_RX_ARP_QUEUE_4                      BIT6
 230#define ETH_DEFAULT_RX_ARP_QUEUE_5                      (BIT6 | BIT4)
 231#define ETH_DEFAULT_RX_ARP_QUEUE_6                      (BIT6 | BIT5)
 232#define ETH_DEFAULT_RX_ARP_QUEUE_7                      (BIT6 | BIT5 | BIT4)
 233#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP                 0
 234#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP                  BIT7
 235#define ETH_RECEIVE_BC_IF_IP                            0
 236#define ETH_REJECT_BC_IF_IP                             BIT8
 237#define ETH_RECEIVE_BC_IF_ARP                           0
 238#define ETH_REJECT_BC_IF_ARP                            BIT9
 239#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY               BIT12
 240#define ETH_CAPTURE_TCP_FRAMES_DIS                      0
 241#define ETH_CAPTURE_TCP_FRAMES_EN                       BIT14
 242#define ETH_CAPTURE_UDP_FRAMES_DIS                      0
 243#define ETH_CAPTURE_UDP_FRAMES_EN                       BIT15
 244#define ETH_DEFAULT_RX_TCP_QUEUE_0                      0
 245#define ETH_DEFAULT_RX_TCP_QUEUE_1                      BIT16
 246#define ETH_DEFAULT_RX_TCP_QUEUE_2                      BIT17
 247#define ETH_DEFAULT_RX_TCP_QUEUE_3                      (BIT17 | BIT16)
 248#define ETH_DEFAULT_RX_TCP_QUEUE_4                      BIT18
 249#define ETH_DEFAULT_RX_TCP_QUEUE_5                      (BIT18 | BIT16)
 250#define ETH_DEFAULT_RX_TCP_QUEUE_6                      (BIT18 | BIT17)
 251#define ETH_DEFAULT_RX_TCP_QUEUE_7                      (BIT18 | BIT17 | BIT16)
 252#define ETH_DEFAULT_RX_UDP_QUEUE_0                      0
 253#define ETH_DEFAULT_RX_UDP_QUEUE_1                      BIT19
 254#define ETH_DEFAULT_RX_UDP_QUEUE_2                      BIT20
 255#define ETH_DEFAULT_RX_UDP_QUEUE_3                      (BIT20 | BIT19)
 256#define ETH_DEFAULT_RX_UDP_QUEUE_4                      (BIT21
 257#define ETH_DEFAULT_RX_UDP_QUEUE_5                      (BIT21 | BIT19)
 258#define ETH_DEFAULT_RX_UDP_QUEUE_6                      (BIT21 | BIT20)
 259#define ETH_DEFAULT_RX_UDP_QUEUE_7                      (BIT21 | BIT20 | BIT19)
 260#define ETH_DEFAULT_RX_BPDU_QUEUE_0                      0
 261#define ETH_DEFAULT_RX_BPDU_QUEUE_1                     BIT22
 262#define ETH_DEFAULT_RX_BPDU_QUEUE_2                     BIT23
 263#define ETH_DEFAULT_RX_BPDU_QUEUE_3                     (BIT23 | BIT22)
 264#define ETH_DEFAULT_RX_BPDU_QUEUE_4                     BIT24
 265#define ETH_DEFAULT_RX_BPDU_QUEUE_5                     (BIT24 | BIT22)
 266#define ETH_DEFAULT_RX_BPDU_QUEUE_6                     (BIT24 | BIT23)
 267#define ETH_DEFAULT_RX_BPDU_QUEUE_7                     (BIT24 | BIT23 | BIT22)
 268
 269
 270/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
 271#define ETH_CLASSIFY_EN                                 BIT0
 272#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL                 0
 273#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7             BIT1
 274#define ETH_PARTITION_DISABLE                           0
 275#define ETH_PARTITION_ENABLE                            BIT2
 276
 277
 278/* Tx/Rx queue command reg (RQCR/TQCR)*/
 279#define ETH_QUEUE_0_ENABLE                              BIT0
 280#define ETH_QUEUE_1_ENABLE                              BIT1
 281#define ETH_QUEUE_2_ENABLE                              BIT2
 282#define ETH_QUEUE_3_ENABLE                              BIT3
 283#define ETH_QUEUE_4_ENABLE                              BIT4
 284#define ETH_QUEUE_5_ENABLE                              BIT5
 285#define ETH_QUEUE_6_ENABLE                              BIT6
 286#define ETH_QUEUE_7_ENABLE                              BIT7
 287#define ETH_QUEUE_0_DISABLE                             BIT8
 288#define ETH_QUEUE_1_DISABLE                             BIT9
 289#define ETH_QUEUE_2_DISABLE                             BIT10
 290#define ETH_QUEUE_3_DISABLE                             BIT11
 291#define ETH_QUEUE_4_DISABLE                             BIT12
 292#define ETH_QUEUE_5_DISABLE                             BIT13
 293#define ETH_QUEUE_6_DISABLE                             BIT14
 294#define ETH_QUEUE_7_DISABLE                             BIT15
 295
 296
 297/* These macros describes the Port Sdma configuration reg (SDCR) bits */
 298#define ETH_RIFB                                        BIT0
 299#define ETH_RX_BURST_SIZE_1_64BIT                       0
 300#define ETH_RX_BURST_SIZE_2_64BIT                       BIT1
 301#define ETH_RX_BURST_SIZE_4_64BIT                       BIT2
 302#define ETH_RX_BURST_SIZE_8_64BIT                       (BIT2 | BIT1)
 303#define ETH_RX_BURST_SIZE_16_64BIT                      BIT3
 304#define ETH_BLM_RX_NO_SWAP                              BIT4
 305#define ETH_BLM_RX_BYTE_SWAP                            0
 306#define ETH_BLM_TX_NO_SWAP                              BIT5
 307#define ETH_BLM_TX_BYTE_SWAP                            0
 308#define ETH_DESCRIPTORS_BYTE_SWAP                       BIT6
 309#define ETH_DESCRIPTORS_NO_SWAP                         0
 310#define ETH_TX_BURST_SIZE_1_64BIT                       0
 311#define ETH_TX_BURST_SIZE_2_64BIT                       BIT22
 312#define ETH_TX_BURST_SIZE_4_64BIT                       BIT23
 313#define ETH_TX_BURST_SIZE_8_64BIT                       (BIT23 | BIT22)
 314#define ETH_TX_BURST_SIZE_16_64BIT                      BIT24
 315
 316
 317
 318/* These macros describes the Port serial control reg (PSCR) bits */
 319#define ETH_SERIAL_PORT_DISABLE                         0
 320#define ETH_SERIAL_PORT_ENABLE                          BIT0
 321#define ETH_FORCE_LINK_PASS                             BIT1
 322#define ETH_DO_NOT_FORCE_LINK_PASS                      0
 323#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX                   0
 324#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX                  BIT2
 325#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL               0
 326#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL              BIT3
 327#define ETH_ADV_NO_FLOW_CTRL                            0
 328#define ETH_ADV_SYMMETRIC_FLOW_CTRL                     BIT4
 329#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX               0
 330#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS                  BIT5
 331#define ETH_FORCE_BP_MODE_NO_JAM                        0
 332#define ETH_FORCE_BP_MODE_JAM_TX                        BIT7
 333#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR              BIT8
 334#define ETH_FORCE_LINK_FAIL                             0
 335#define ETH_DO_NOT_FORCE_LINK_FAIL                      BIT10
 336#define ETH_RETRANSMIT_16_ATTEMPTS                      0
 337#define ETH_RETRANSMIT_FOREVER                          BIT11
 338#define ETH_DISABLE_AUTO_NEG_SPEED_GMII                 BIT13
 339#define ETH_ENABLE_AUTO_NEG_SPEED_GMII                  0
 340#define ETH_DTE_ADV_0                                   0
 341#define ETH_DTE_ADV_1                                   BIT14
 342#define ETH_DISABLE_AUTO_NEG_BYPASS                     0
 343#define ETH_ENABLE_AUTO_NEG_BYPASS                      BIT15
 344#define ETH_AUTO_NEG_NO_CHANGE                          0
 345#define ETH_RESTART_AUTO_NEG                            BIT16
 346#define ETH_MAX_RX_PACKET_1518BYTE                      0
 347#define ETH_MAX_RX_PACKET_1522BYTE                      BIT17
 348#define ETH_MAX_RX_PACKET_1552BYTE                      BIT18
 349#define ETH_MAX_RX_PACKET_9022BYTE                      (BIT18 | BIT17)
 350#define ETH_MAX_RX_PACKET_9192BYTE                      BIT19
 351#define ETH_MAX_RX_PACKET_9700BYTE                      (BIT19 | BIT17)
 352#define ETH_SET_EXT_LOOPBACK                            BIT20
 353#define ETH_CLR_EXT_LOOPBACK                            0
 354#define ETH_SET_FULL_DUPLEX_MODE                        BIT21
 355#define ETH_SET_HALF_DUPLEX_MODE                        0
 356#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX       BIT22
 357#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX      0
 358#define ETH_SET_GMII_SPEED_TO_10_100                    0
 359#define ETH_SET_GMII_SPEED_TO_1000                      BIT23
 360#define ETH_SET_MII_SPEED_TO_10                         0
 361#define ETH_SET_MII_SPEED_TO_100                        BIT24
 362
 363
 364/* SMI reg */
 365#define ETH_SMI_BUSY            BIT28   /* 0 - Write, 1 - Read          */
 366#define ETH_SMI_READ_VALID      BIT27   /* 0 - Write, 1 - Read          */
 367#define ETH_SMI_OPCODE_WRITE    0       /* Completion of Read operation */
 368#define ETH_SMI_OPCODE_READ     BIT26   /* Operation is in progress             */
 369
 370/* SDMA command status fields macros */
 371
 372/* Tx & Rx descriptors status */
 373#define ETH_ERROR_SUMMARY                   (BIT0)
 374
 375/* Tx & Rx descriptors command */
 376#define ETH_BUFFER_OWNED_BY_DMA             (BIT31)
 377
 378/* Tx descriptors status */
 379#define ETH_LC_ERROR                        (0    )
 380#define ETH_UR_ERROR                        (BIT1 )
 381#define ETH_RL_ERROR                        (BIT2 )
 382#define ETH_LLC_SNAP_FORMAT                 (BIT9 )
 383
 384/* Rx descriptors status */
 385#define ETH_CRC_ERROR                       (0    )
 386#define ETH_OVERRUN_ERROR                   (BIT1 )
 387#define ETH_MAX_FRAME_LENGTH_ERROR          (BIT2 )
 388#define ETH_RESOURCE_ERROR                  ((BIT2 | BIT1))
 389#define ETH_VLAN_TAGGED                     (BIT19)
 390#define ETH_BPDU_FRAME                      (BIT20)
 391#define ETH_TCP_FRAME_OVER_IP_V_4           (0    )
 392#define ETH_UDP_FRAME_OVER_IP_V_4           (BIT21)
 393#define ETH_OTHER_FRAME_TYPE                (BIT22)
 394#define ETH_LAYER_2_IS_ETH_V_2              (BIT23)
 395#define ETH_FRAME_TYPE_IP_V_4               (BIT24)
 396#define ETH_FRAME_HEADER_OK                 (BIT25)
 397#define ETH_RX_LAST_DESC                    (BIT26)
 398#define ETH_RX_FIRST_DESC                   (BIT27)
 399#define ETH_UNKNOWN_DESTINATION_ADDR        (BIT28)
 400#define ETH_RX_ENABLE_INTERRUPT             (BIT29)
 401#define ETH_LAYER_4_CHECKSUM_OK             (BIT30)
 402
 403/* Rx descriptors byte count */
 404#define ETH_FRAME_FRAGMENTED                (BIT2)
 405
 406/* Tx descriptors command */
 407#define ETH_LAYER_4_CHECKSUM_FIRST_DESC         (BIT10)
 408#define ETH_FRAME_SET_TO_VLAN               (BIT15)
 409#define ETH_TCP_FRAME                       (0    )
 410#define ETH_UDP_FRAME                       (BIT16)
 411#define ETH_GEN_TCP_UDP_CHECKSUM            (BIT17)
 412#define ETH_GEN_IP_V_4_CHECKSUM             (BIT18)
 413#define ETH_ZERO_PADDING                    (BIT19)
 414#define ETH_TX_LAST_DESC                    (BIT20)
 415#define ETH_TX_FIRST_DESC                   (BIT21)
 416#define ETH_GEN_CRC                         (BIT22)
 417#define ETH_TX_ENABLE_INTERRUPT             (BIT23)
 418#define ETH_AUTO_MODE                       (BIT30)
 419
 420/* typedefs */
 421
 422typedef enum _eth_func_ret_status {
 423        ETH_OK,                 /* Returned as expected.                    */
 424        ETH_ERROR,              /* Fundamental error.                       */
 425        ETH_RETRY,              /* Could not process request. Try later.    */
 426        ETH_END_OF_JOB,         /* Ring has nothing to process.             */
 427        ETH_QUEUE_FULL,         /* Ring resource error.                     */
 428        ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust.         */
 429} ETH_FUNC_RET_STATUS;
 430
 431typedef enum _eth_target {
 432        ETH_TARGET_DRAM,
 433        ETH_TARGET_DEVICE,
 434        ETH_TARGET_CBS,
 435        ETH_TARGET_PCI0,
 436        ETH_TARGET_PCI1
 437} ETH_TARGET;
 438
 439/* These are for big-endian machines.  Little endian needs different
 440 * definitions.
 441 */
 442#if defined(__BIG_ENDIAN)
 443struct eth_rx_desc {
 444        u16     byte_cnt;       /* Descriptor buffer byte count     */
 445        u16     buf_size;       /* Buffer size                      */
 446        u32     cmd_sts;        /* Descriptor command status        */
 447        u32     next_desc_ptr;  /* Next descriptor pointer          */
 448        u32     buf_ptr;        /* Descriptor buffer pointer        */
 449};
 450
 451struct eth_tx_desc {
 452        u16     byte_cnt;       /* buffer byte count */
 453        u16     l4i_chk;        /* CPU provided TCP checksum */
 454        u32     cmd_sts;        /* Command/status field */
 455        u32     next_desc_ptr;  /* Pointer to next descriptor */
 456        u32     buf_ptr;        /* pointer to buffer for this descriptor */
 457};
 458
 459#elif defined(__LITTLE_ENDIAN)
 460struct eth_rx_desc {
 461        u32     cmd_sts;        /* Descriptor command status        */
 462        u16     buf_size;       /* Buffer size                      */
 463        u16     byte_cnt;       /* Descriptor buffer byte count     */
 464        u32     buf_ptr;        /* Descriptor buffer pointer        */
 465        u32     next_desc_ptr;  /* Next descriptor pointer          */
 466};
 467
 468struct eth_tx_desc {
 469        u32     cmd_sts;        /* Command/status field */
 470        u16     l4i_chk;        /* CPU provided TCP checksum */
 471        u16     byte_cnt;       /* buffer byte count */
 472        u32     buf_ptr;        /* pointer to buffer for this descriptor */
 473        u32     next_desc_ptr;  /* Pointer to next descriptor */
 474};
 475#else
 476#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
 477#endif
 478
 479/* Unified struct for Rx and Tx operations. The user is not required to */
 480/* be familier with neither Tx nor Rx descriptors.                       */
 481struct pkt_info {
 482        unsigned short  byte_cnt;       /* Descriptor buffer byte count     */
 483        unsigned short  l4i_chk;        /* Tx CPU provided TCP Checksum     */
 484        unsigned int    cmd_sts;        /* Descriptor command status        */
 485        dma_addr_t      buf_ptr;        /* Descriptor buffer pointer        */
 486        struct sk_buff  * return_info;  /* User resource return information */
 487};
 488
 489
 490/* Ethernet port specific infomation */
 491
 492struct mv64340_private {
 493        int     port_num;               /* User Ethernet port number */
 494        u8      port_mac_addr[6];       /* User defined port MAC address. */
 495        u32     port_config;            /* User port configuration value */
 496        u32     port_config_extend;     /* User port config extend value */
 497        u32     port_sdma_config;       /* User port SDMA config value */
 498        u32     port_serial_control;    /* User port serial control value */
 499        u32     port_tx_queue_command;  /* Port active Tx queues summary */
 500        u32     port_rx_queue_command;  /* Port active Rx queues summary */
 501
 502        int     rx_resource_err;        /* Rx ring resource error flag */
 503        int     tx_resource_err;        /* Tx ring resource error flag */
 504
 505        /* Tx/Rx rings managment indexes fields. For driver use */
 506
 507        /* Next available and first returning Rx resource */
 508        int rx_curr_desc_q, rx_used_desc_q;
 509
 510        /* Next available and first returning Tx resource */
 511        int tx_curr_desc_q, tx_used_desc_q;
 512#ifdef MV64340_CHECKSUM_OFFLOAD_TX
 513        int tx_first_desc_q;
 514#endif
 515
 516#ifdef MV64340_TX_FAST_REFILL
 517        u32     tx_clean_threshold;
 518#endif
 519
 520        volatile struct eth_rx_desc     * p_rx_desc_area;
 521        dma_addr_t                      rx_desc_dma;
 522        unsigned int                    rx_desc_area_size;
 523        struct sk_buff                  * rx_skb[MV64340_RX_QUEUE_SIZE];
 524
 525        volatile struct eth_tx_desc     * p_tx_desc_area;
 526        dma_addr_t                      tx_desc_dma;
 527        unsigned int                    tx_desc_area_size;
 528        struct sk_buff                  * tx_skb[MV64340_TX_QUEUE_SIZE];
 529
 530        struct work_struct              tx_timeout_task;
 531
 532        /*
 533         * Former struct mv64340_eth_priv members start here
 534         */
 535        struct net_device_stats stats;
 536        spinlock_t lock;
 537        /* Size of Tx Ring per queue */
 538        unsigned int tx_ring_size;
 539        /* Ammont of SKBs outstanding on Tx queue */
 540        unsigned int tx_ring_skbs;
 541        /* Size of Rx Ring per queue */
 542        unsigned int rx_ring_size;
 543        /* Ammount of SKBs allocated to Rx Ring per queue */
 544        unsigned int rx_ring_skbs;
 545
 546        /*
 547         * rx_task used to fill RX ring out of bottom half context 
 548         */
 549        struct work_struct rx_task;
 550
 551        /* 
 552         * Used in case RX Ring is empty, which can be caused when 
 553         * system does not have resources (skb's) 
 554         */
 555        struct timer_list timeout;
 556        long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
 557        unsigned rx_timer_flag;
 558
 559        u32 rx_int_coal;
 560        u32 tx_int_coal;
 561};
 562
 563/* ethernet.h API list */
 564
 565/* Port operation control routines */
 566static void eth_port_init(struct mv64340_private *mp);
 567static void eth_port_reset(unsigned int eth_port_num);
 568static int eth_port_start(struct mv64340_private *mp);
 569
 570static void ethernet_set_config_reg(unsigned int eth_port_num,
 571                                    unsigned int value);
 572static unsigned int ethernet_get_config_reg(unsigned int eth_port_num);
 573
 574/* Port MAC address routines */
 575static void eth_port_uc_addr_set(unsigned int eth_port_num,
 576                                 unsigned char *p_addr);
 577
 578/* PHY and MIB routines */
 579static int ethernet_phy_reset(unsigned int eth_port_num);
 580
 581static int eth_port_write_smi_reg(unsigned int eth_port_num,
 582                                   unsigned int phy_reg,
 583                                   unsigned int value);
 584
 585static int eth_port_read_smi_reg(unsigned int eth_port_num,
 586                                  unsigned int phy_reg,
 587                                  unsigned int *value);
 588
 589static void eth_clear_mib_counters(unsigned int eth_port_num);
 590
 591/* Port data flow control routines */
 592static ETH_FUNC_RET_STATUS eth_port_send(struct mv64340_private *mp,
 593                                         struct pkt_info * p_pkt_info);
 594static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv64340_private *mp,
 595                                              struct pkt_info * p_pkt_info);
 596static ETH_FUNC_RET_STATUS eth_port_receive(struct mv64340_private *mp,
 597                                            struct pkt_info * p_pkt_info);
 598static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv64340_private *mp,
 599                                              struct pkt_info * p_pkt_info);
 600
 601#endif  /* __MV64340_ETH_H__ */
 602