1/* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $ 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * Info: 15 * Contains standard defines and IDs for NAND flash devices 16 * 17 * Changelog: 18 * 01-31-2000 DMW Created 19 * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers 20 * so it can be used by other NAND flash device 21 * drivers. I also changed the copyright since none 22 * of the original contents of this file are specific 23 * to DoC devices. David can whack me with a baseball 24 * bat later if I did something naughty. 25 * 10-11-2000 SJH Added private NAND flash structure for driver 26 * 10-24-2000 SJH Added prototype for 'nand_scan' function 27 * 10-29-2001 TG changed nand_chip structure to support 28 * hardwarespecific function for accessing control lines 29 * 02-21-2002 TG added support for different read/write adress and 30 * ready/busy line access function 31 * 02-26-2002 TG added chip_delay to nand_chip structure to optimize 32 * command delay times for different chips 33 * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate 34 * defines in jffs2/wbuf.c 35 * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if 36 * CONFIG_MTD_NAND_ECC_JFFS2 is not set 37 * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC 38 * 39 * 08-29-2002 tglx nand_chip structure: data_poi for selecting 40 * internal / fs-driver buffer 41 * support for 6byte/512byte hardware ECC 42 * read_ecc, write_ecc extended for different oob-layout 43 * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB, 44 * NAND_YAFFS_OOB 45 * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL 46 * Split manufacturer and device ID structures 47 * 48 * 02-08-2004 tglx added option field to nand structure for chip anomalities 49 * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id 50 * update of nand_chip structure description 51 */ 52#ifndef __LINUX_MTD_NAND_H 53#define __LINUX_MTD_NAND_H 54 55#include <linux/config.h> 56#include <linux/wait.h> 57#include <linux/spinlock.h> 58#include <linux/mtd/mtd.h> 59 60struct mtd_info; 61/* Scan and identify a NAND device */ 62extern int nand_scan (struct mtd_info *mtd, int max_chips); 63/* Free resources held by the NAND device */ 64extern void nand_release (struct mtd_info *mtd); 65 66/* Read raw data from the device without ECC */ 67extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen); 68 69 70/* The maximum number of NAND chips in an array */ 71#define NAND_MAX_CHIPS 8 72 73/* This constant declares the max. oobsize / page, which 74 * is supported now. If you add a chip with bigger oobsize/page 75 * adjust this accordingly. 76 */ 77#define NAND_MAX_OOBSIZE 64 78 79/* 80 * Constants for hardware specific CLE/ALE/NCE function 81*/ 82/* Select the chip by setting nCE to low */ 83#define NAND_CTL_SETNCE 1 84/* Deselect the chip by setting nCE to high */ 85#define NAND_CTL_CLRNCE 2 86/* Select the command latch by setting CLE to high */ 87#define NAND_CTL_SETCLE 3 88/* Deselect the command latch by setting CLE to low */ 89#define NAND_CTL_CLRCLE 4 90/* Select the address latch by setting ALE to high */ 91#define NAND_CTL_SETALE 5 92/* Deselect the address latch by setting ALE to low */ 93#define NAND_CTL_CLRALE 6 94/* Set write protection by setting WP to high. Not used! */ 95#define NAND_CTL_SETWP 7 96/* Clear write protection by setting WP to low. Not used! */ 97#define NAND_CTL_CLRWP 8 98 99/* 100 * Standard NAND flash commands 101 */ 102#define NAND_CMD_READ0 0 103#define NAND_CMD_READ1 1 104#define NAND_CMD_PAGEPROG 0x10 105#define NAND_CMD_READOOB 0x50 106#define NAND_CMD_ERASE1 0x60 107#define NAND_CMD_STATUS 0x70 108#define NAND_CMD_STATUS_MULTI 0x71 109#define NAND_CMD_SEQIN 0x80 110#define NAND_CMD_READID 0x90 111#define NAND_CMD_ERASE2 0xd0 112#define NAND_CMD_RESET 0xff 113 114/* Extended commands for large page devices */ 115#define NAND_CMD_READSTART 0x30 116#define NAND_CMD_CACHEDPROG 0x15 117 118/* Status bits */ 119#define NAND_STATUS_FAIL 0x01 120#define NAND_STATUS_FAIL_N1 0x02 121#define NAND_STATUS_TRUE_READY 0x20 122#define NAND_STATUS_READY 0x40 123#define NAND_STATUS_WP 0x80 124 125/* 126 * Constants for ECC_MODES 127 */ 128 129/* No ECC. Usage is not recommended ! */ 130#define NAND_ECC_NONE 0 131/* Software ECC 3 byte ECC per 256 Byte data */ 132#define NAND_ECC_SOFT 1 133/* Hardware ECC 3 byte ECC per 256 Byte data */ 134#define NAND_ECC_HW3_256 2 135/* Hardware ECC 3 byte ECC per 512 Byte data */ 136#define NAND_ECC_HW3_512 3 137/* Hardware ECC 3 byte ECC per 512 Byte data */ 138#define NAND_ECC_HW6_512 4 139/* Hardware ECC 8 byte ECC per 512 Byte data */ 140#define NAND_ECC_HW8_512 6 141/* Hardware ECC 12 byte ECC per 2048 Byte data */ 142#define NAND_ECC_HW12_2048 7 143 144/* 145 * Constants for Hardware ECC 146*/ 147/* Reset Hardware ECC for read */ 148#define NAND_ECC_READ 0 149/* Reset Hardware ECC for write */ 150#define NAND_ECC_WRITE 1 151/* Enable Hardware ECC before syndrom is read back from flash */ 152#define NAND_ECC_READSYN 2 153 154/* Option constants for bizarre disfunctionality and real 155* features 156*/ 157/* Chip can not auto increment pages */ 158#define NAND_NO_AUTOINCR 0x00000001 159/* Buswitdh is 16 bit */ 160#define NAND_BUSWIDTH_16 0x00000002 161/* Device supports partial programming without padding */ 162#define NAND_NO_PADDING 0x00000004 163/* Chip has cache program function */ 164#define NAND_CACHEPRG 0x00000008 165/* Chip has copy back function */ 166#define NAND_COPYBACK 0x00000010 167/* AND Chip which has 4 banks and a confusing page / block 168 * assignment. See Renesas datasheet for further information */ 169#define NAND_IS_AND 0x00000020 170/* Chip has a array of 4 pages which can be read without 171 * additional ready /busy waits */ 172#define NAND_4PAGE_ARRAY 0x00000040 173 174/* Options valid for Samsung large page devices */ 175#define NAND_SAMSUNG_LP_OPTIONS \ 176 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 177 178/* Macros to identify the above */ 179#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) 180#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 181#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 182#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 183 184/* Mask to zero out the chip options, which come from the id table */ 185#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) 186 187/* Non chip related options */ 188/* Use a flash based bad block table. This option is passed to the 189 * default bad block table function. */ 190#define NAND_USE_FLASH_BBT 0x00010000 191/* The hw ecc generator provides a syndrome instead a ecc value on read 192 * This can only work if we have the ecc bytes directly behind the 193 * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ 194#define NAND_HWECC_SYNDROME 0x00020000 195 196 197/* Options set by nand scan */ 198/* Nand scan has allocated oob_buf */ 199#define NAND_OOBBUF_ALLOC 0x40000000 200/* Nand scan has allocated data_buf */ 201#define NAND_DATABUF_ALLOC 0x80000000 202 203 204/* 205 * nand_state_t - chip states 206 * Enumeration for NAND flash chip state 207 */ 208typedef enum { 209 FL_READY, 210 FL_READING, 211 FL_WRITING, 212 FL_ERASING, 213 FL_SYNCING, 214 FL_CACHEDPRG, 215} nand_state_t; 216 217/* Keep gcc happy */ 218struct nand_chip; 219 220/** 221 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices 222 * @lock: protection lock 223 * @active: the mtd device which holds the controller currently 224 */ 225struct nand_hw_control { 226 spinlock_t lock; 227 struct nand_chip *active; 228}; 229 230/** 231 * struct nand_chip - NAND Private Flash Chip Data 232 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device 233 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device 234 * @read_byte: [REPLACEABLE] read one byte from the chip 235 * @write_byte: [REPLACEABLE] write one byte to the chip 236 * @read_word: [REPLACEABLE] read one word from the chip 237 * @write_word: [REPLACEABLE] write one word to the chip 238 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 239 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 240 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data 241 * @select_chip: [REPLACEABLE] select chip nr 242 * @block_bad: [REPLACEABLE] check, if the block is bad 243 * @block_markbad: [REPLACEABLE] mark the block bad 244 * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines 245 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line 246 * If set to NULL no access to ready/busy is available and the ready/busy information 247 * is read from the chip status register 248 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip 249 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready 250 * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware 251 * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw) 252 * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only 253 * be provided if a hardware ECC is available 254 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support 255 * @scan_bbt: [REPLACEABLE] function to scan bad block table 256 * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines 257 * @eccsize: [INTERN] databytes used per ecc-calculation 258 * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step 259 * @eccsteps: [INTERN] number of ecc calculation steps per page 260 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) 261 * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip 262 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress 263 * @state: [INTERN] the current state of the NAND device 264 * @page_shift: [INTERN] number of address bits in a page (column address bits) 265 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 266 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 267 * @chip_shift: [INTERN] number of address bits in one chip 268 * @data_buf: [INTERN] internal buffer for one page + oob 269 * @oob_buf: [INTERN] oob buffer for one eraseblock 270 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized 271 * @data_poi: [INTERN] pointer to a data buffer 272 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about 273 * special functionality. See the defines for further explanation 274 * @badblockpos: [INTERN] position of the bad block marker in the oob area 275 * @numchips: [INTERN] number of physical chips 276 * @chipsize: [INTERN] the size of one chip for multichip arrays 277 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 278 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf 279 * @autooob: [REPLACEABLE] the default (auto)placement scheme 280 * @bbt: [INTERN] bad block table pointer 281 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup 282 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 283 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan 284 * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices 285 * @priv: [OPTIONAL] pointer to private chip date 286 */ 287 288struct nand_chip { 289 void __iomem *IO_ADDR_R; 290 void __iomem *IO_ADDR_W; 291 292 u_char (*read_byte)(struct mtd_info *mtd); 293 void (*write_byte)(struct mtd_info *mtd, u_char byte); 294 u16 (*read_word)(struct mtd_info *mtd); 295 void (*write_word)(struct mtd_info *mtd, u16 word); 296 297 void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len); 298 void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len); 299 int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len); 300 void (*select_chip)(struct mtd_info *mtd, int chip); 301 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 302 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 303 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 304 int (*dev_ready)(struct mtd_info *mtd); 305 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); 306 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); 307 int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); 308 int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); 309 void (*enable_hwecc)(struct mtd_info *mtd, int mode); 310 void (*erase_cmd)(struct mtd_info *mtd, int page); 311 int (*scan_bbt)(struct mtd_info *mtd); 312 int eccmode; 313 int eccsize; 314 int eccbytes; 315 int eccsteps; 316 int chip_delay; 317 spinlock_t chip_lock; 318 wait_queue_head_t wq; 319 nand_state_t state; 320 int page_shift; 321 int phys_erase_shift; 322 int bbt_erase_shift; 323 int chip_shift; 324 u_char *data_buf; 325 u_char *oob_buf; 326 int oobdirty; 327 u_char *data_poi; 328 unsigned int options; 329 int badblockpos; 330 int numchips; 331 unsigned long chipsize; 332 int pagemask; 333 int pagebuf; 334 struct nand_oobinfo *autooob; 335 uint8_t *bbt; 336 struct nand_bbt_descr *bbt_td; 337 struct nand_bbt_descr *bbt_md; 338 struct nand_bbt_descr *badblock_pattern; 339 struct nand_hw_control *controller; 340 void *priv; 341}; 342 343/* 344 * NAND Flash Manufacturer ID Codes 345 */ 346#define NAND_MFR_TOSHIBA 0x98 347#define NAND_MFR_SAMSUNG 0xec 348#define NAND_MFR_FUJITSU 0x04 349#define NAND_MFR_NATIONAL 0x8f 350#define NAND_MFR_RENESAS 0x07 351#define NAND_MFR_STMICRO 0x20 352 353/** 354 * struct nand_flash_dev - NAND Flash Device ID Structure 355 * 356 * @name: Identify the device type 357 * @id: device ID code 358 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 359 * If the pagesize is 0, then the real pagesize 360 * and the eraseize are determined from the 361 * extended id bytes in the chip 362 * @erasesize: Size of an erase block in the flash device. 363 * @chipsize: Total chipsize in Mega Bytes 364 * @options: Bitfield to store chip relevant options 365 */ 366struct nand_flash_dev { 367 char *name; 368 int id; 369 unsigned long pagesize; 370 unsigned long chipsize; 371 unsigned long erasesize; 372 unsigned long options; 373}; 374 375/** 376 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 377 * @name: Manufacturer name 378 * @id: manufacturer ID code of device. 379*/ 380struct nand_manufacturers { 381 int id; 382 char * name; 383}; 384 385extern struct nand_flash_dev nand_flash_ids[]; 386extern struct nand_manufacturers nand_manuf_ids[]; 387 388/** 389 * struct nand_bbt_descr - bad block table descriptor 390 * @options: options for this descriptor 391 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE 392 * when bbt is searched, then we store the found bbts pages here. 393 * Its an array and supports up to 8 chips now 394 * @offs: offset of the pattern in the oob area of the page 395 * @veroffs: offset of the bbt version counter in the oob are of the page 396 * @version: version read from the bbt page during scan 397 * @len: length of the pattern, if 0 no pattern check is performed 398 * @maxblocks: maximum number of blocks to search for a bbt. This number of 399 * blocks is reserved at the end of the device where the tables are 400 * written. 401 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than 402 * bad) block in the stored bbt 403 * @pattern: pattern to identify bad block table or factory marked good / 404 * bad blocks, can be NULL, if len = 0 405 * 406 * Descriptor for the bad block table marker and the descriptor for the 407 * pattern which identifies good and bad blocks. The assumption is made 408 * that the pattern and the version count are always located in the oob area 409 * of the first block. 410 */ 411struct nand_bbt_descr { 412 int options; 413 int pages[NAND_MAX_CHIPS]; 414 int offs; 415 int veroffs; 416 uint8_t version[NAND_MAX_CHIPS]; 417 int len; 418 int maxblocks; 419 int reserved_block_code; 420 uint8_t *pattern; 421}; 422 423/* Options for the bad block table descriptors */ 424 425/* The number of bits used per block in the bbt on the device */ 426#define NAND_BBT_NRBITS_MSK 0x0000000F 427#define NAND_BBT_1BIT 0x00000001 428#define NAND_BBT_2BIT 0x00000002 429#define NAND_BBT_4BIT 0x00000004 430#define NAND_BBT_8BIT 0x00000008 431/* The bad block table is in the last good block of the device */ 432#define NAND_BBT_LASTBLOCK 0x00000010 433/* The bbt is at the given page, else we must scan for the bbt */ 434#define NAND_BBT_ABSPAGE 0x00000020 435/* The bbt is at the given page, else we must scan for the bbt */ 436#define NAND_BBT_SEARCH 0x00000040 437/* bbt is stored per chip on multichip devices */ 438#define NAND_BBT_PERCHIP 0x00000080 439/* bbt has a version counter at offset veroffs */ 440#define NAND_BBT_VERSION 0x00000100 441/* Create a bbt if none axists */ 442#define NAND_BBT_CREATE 0x00000200 443/* Search good / bad pattern through all pages of a block */ 444#define NAND_BBT_SCANALLPAGES 0x00000400 445/* Scan block empty during good / bad block scan */ 446#define NAND_BBT_SCANEMPTY 0x00000800 447/* Write bbt if neccecary */ 448#define NAND_BBT_WRITE 0x00001000 449/* Read and write back block contents when writing bbt */ 450#define NAND_BBT_SAVECONTENT 0x00002000 451/* Search good / bad pattern on the first and the second page */ 452#define NAND_BBT_SCAN2NDPAGE 0x00004000 453 454/* The maximum number of blocks to scan for a bbt */ 455#define NAND_BBT_SCAN_MAXBLOCKS 4 456 457extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); 458extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs); 459extern int nand_default_bbt (struct mtd_info *mtd); 460extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt); 461extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt); 462 463/* 464* Constants for oob configuration 465*/ 466#define NAND_SMALL_BADBLOCK_POS 5 467#define NAND_LARGE_BADBLOCK_POS 0 468 469#endif /* __LINUX_MTD_NAND_H */ 470