LXR linux-bk/drivers/usb/host/ohci.h

   1/*
   2 * OHCI HCD (Host Controller Driver) for USB.
   3 * 
   4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6 * 
   7 * This file is licenced under the GPL.
   8 */
   9
  10/*
  11 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  12 * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
  13 * host controller implementation.
  14 */
  15typedef __u32 __bitwise __hc32;
  16typedef __u16 __bitwise __hc16;
  17 
  18/*
  19 * OHCI Endpoint Descriptor (ED) ... holds TD queue
  20 * See OHCI spec, section 4.2
  21 *
  22 * This is a "Queue Head" for those transfers, which is why
  23 * both EHCI and UHCI call similar structures a "QH".
  24 */
  25struct ed {
  26        /* first fields are hardware-specified */
  27        __hc32                  hwINFO;         /* endpoint config bitmap */
  28        /* info bits defined by hcd */
  29#define ED_DEQUEUE      (1 << 27)
  30        /* info bits defined by the hardware */
  31#define ED_ISO          (1 << 15)
  32#define ED_SKIP         (1 << 14)
  33#define ED_LOWSPEED     (1 << 13)
  34#define ED_OUT          (0x01 << 11)
  35#define ED_IN           (0x02 << 11)
  36        __hc32                  hwTailP;        /* tail of TD list */
  37        __hc32                  hwHeadP;        /* head of TD list (hc r/w) */
  38#define ED_C            (0x02)                  /* toggle carry */
  39#define ED_H            (0x01)                  /* halted */
  40        __hc32                  hwNextED;       /* next ED in list */
  41
  42        /* rest are purely for the driver's use */
  43        dma_addr_t              dma;            /* addr of ED */
  44        struct td               *dummy;         /* next TD to activate */
  45
  46        /* host's view of schedule */
  47        struct ed               *ed_next;       /* on schedule or rm_list */
  48        struct ed               *ed_prev;       /* for non-interrupt EDs */
  49        struct list_head        td_list;        /* "shadow list" of our TDs */
  50
  51        /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
  52         * usually:  OPER --> UNLINK --> (IDLE | OPER) --> ...
  53         */
  54        u8                      state;          /* ED_{IDLE,UNLINK,OPER} */
  55#define ED_IDLE         0x00            /* NOT linked to HC */
  56#define ED_UNLINK       0x01            /* being unlinked from hc */
  57#define ED_OPER         0x02            /* IS linked to hc */
  58
  59        u8                      type;           /* PIPE_{BULK,...} */
  60
  61        /* periodic scheduling params (for intr and iso) */
  62        u8                      branch;
  63        u16                     interval;
  64        u16                     load;
  65        u16                     last_iso;       /* iso only */
  66
  67        /* HC may see EDs on rm_list until next frame (frame_no == tick) */
  68        u16                     tick;
  69} __attribute__ ((aligned(16)));
  70
  71#define ED_MASK ((u32)~0x0f)            /* strip hw status in low addr bits */
  72
  73 
  74/*
  75 * OHCI Transfer Descriptor (TD) ... one per transfer segment
  76 * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
  77 * and 4.3.2 (iso)
  78 */
  79struct td {
  80        /* first fields are hardware-specified */
  81        __hc32          hwINFO;         /* transfer info bitmask */
  82
  83        /* hwINFO bits for both general and iso tds: */
  84#define TD_CC       0xf0000000                  /* condition code */
  85#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
  86//#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
  87#define TD_DI       0x00E00000                  /* frames before interrupt */
  88#define TD_DI_SET(X) (((X) & 0x07)<< 21)
  89        /* these two bits are available for definition/use by HCDs in both
  90         * general and iso tds ... others are available for only one type
  91         */
  92#define TD_DONE     0x00020000                  /* retired to donelist */
  93#define TD_ISO      0x00010000                  /* copy of ED_ISO */
  94
  95        /* hwINFO bits for general tds: */
  96#define TD_EC       0x0C000000                  /* error count */
  97#define TD_T        0x03000000                  /* data toggle state */
  98#define TD_T_DATA0  0x02000000                          /* DATA0 */
  99#define TD_T_DATA1  0x03000000                          /* DATA1 */
 100#define TD_T_TOGGLE 0x00000000                          /* uses ED_C */
 101#define TD_DP       0x00180000                  /* direction/pid */
 102#define TD_DP_SETUP 0x00000000                  /* SETUP pid */
 103#define TD_DP_IN    0x00100000                          /* IN pid */
 104#define TD_DP_OUT   0x00080000                          /* OUT pid */
 105                                                        /* 0x00180000 rsvd */
 106#define TD_R        0x00040000                  /* round: short packets OK? */
 107
 108        /* (no hwINFO #defines yet for iso tds) */
 109
 110        __hc32          hwCBP;          /* Current Buffer Pointer (or 0) */
 111        __hc32          hwNextTD;       /* Next TD Pointer */
 112        __hc32          hwBE;           /* Memory Buffer End Pointer */
 113
 114        /* PSW is only for ISO */
 115#define MAXPSW 1                /* hardware allows 8 */
 116        __hc16          hwPSW [MAXPSW];
 117
 118        /* rest are purely for the driver's use */
 119        __u8            index;
 120        struct ed       *ed;
 121        struct td       *td_hash;       /* dma-->td hashtable */
 122        struct td       *next_dl_td;
 123        struct urb      *urb;
 124
 125        dma_addr_t      td_dma;         /* addr of this TD */
 126        dma_addr_t      data_dma;       /* addr of data it points to */
 127
 128        struct list_head td_list;       /* "shadow list", TDs on same ED */
 129} __attribute__ ((aligned(32)));        /* c/b/i need 16; only iso needs 32 */
 130
 131#define TD_MASK ((u32)~0x1f)            /* strip hw status in low addr bits */
 132
 133/*
 134 * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW
 135 */
 136#define TD_CC_NOERROR      0x00
 137#define TD_CC_CRC          0x01
 138#define TD_CC_BITSTUFFING  0x02
 139#define TD_CC_DATATOGGLEM  0x03
 140#define TD_CC_STALL        0x04
 141#define TD_DEVNOTRESP      0x05
 142#define TD_PIDCHECKFAIL    0x06
 143#define TD_UNEXPECTEDPID   0x07
 144#define TD_DATAOVERRUN     0x08
 145#define TD_DATAUNDERRUN    0x09
 146    /* 0x0A, 0x0B reserved for hardware */
 147#define TD_BUFFEROVERRUN   0x0C
 148#define TD_BUFFERUNDERRUN  0x0D
 149    /* 0x0E, 0x0F reserved for HCD */
 150#define TD_NOTACCESSED     0x0F
 151
 152
 153/* map OHCI TD status codes (CC) to errno values */ 
 154static const int cc_to_error [16] = { 
 155        /* No  Error  */               0,
 156        /* CRC Error  */               -EILSEQ,
 157        /* Bit Stuff  */               -EPROTO,
 158        /* Data Togg  */               -EILSEQ,
 159        /* Stall      */               -EPIPE,
 160        /* DevNotResp */               -ETIMEDOUT,
 161        /* PIDCheck   */               -EPROTO,
 162        /* UnExpPID   */               -EPROTO,
 163        /* DataOver   */               -EOVERFLOW,
 164        /* DataUnder  */               -EREMOTEIO,
 165        /* (for hw)   */               -EIO,
 166        /* (for hw)   */               -EIO,
 167        /* BufferOver */               -ECOMM,
 168        /* BuffUnder  */               -ENOSR,
 169        /* (for HCD)  */               -EALREADY,
 170        /* (for HCD)  */               -EALREADY 
 171};
 172
 173
 174/*
 175 * The HCCA (Host Controller Communications Area) is a 256 byte
 176 * structure defined section 4.4.1 of the OHCI spec. The HC is
 177 * told the base address of it.  It must be 256-byte aligned.
 178 */
 179struct ohci_hcca {
 180#define NUM_INTS 32
 181        __hc32  int_table [NUM_INTS];   /* periodic schedule */
 182
 183        /* 
 184         * OHCI defines u16 frame_no, followed by u16 zero pad.
 185         * Since some processors can't do 16 bit bus accesses,
 186         * portable access must be a 32 bit byteswapped access.
 187         */
 188        __hc32  frame_no;               /* current frame number */
 189        __hc32  done_head;              /* info returned for an interrupt */
 190        u8      reserved_for_hc [116];
 191        u8      what [4];               /* spec only identifies 252 bytes :) */
 192} __attribute__ ((aligned(256)));
 193
 194#define ohci_frame_no(ohci) ((u16)hc32_to_cpup(ohci,&(ohci)->hcca->frame_no))
 195  
 196/*
 197 * This is the structure of the OHCI controller's memory mapped I/O region.
 198 * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
 199 * Layout is in section 7 (and appendix B) of the spec.
 200 */
 201struct ohci_regs {
 202        /* control and status registers (section 7.1) */
 203        __hc32  revision;
 204        __hc32  control;
 205        __hc32  cmdstatus;
 206        __hc32  intrstatus;
 207        __hc32  intrenable;
 208        __hc32  intrdisable;
 209
 210        /* memory pointers (section 7.2) */
 211        __hc32  hcca;
 212        __hc32  ed_periodcurrent;
 213        __hc32  ed_controlhead;
 214        __hc32  ed_controlcurrent;
 215        __hc32  ed_bulkhead;
 216        __hc32  ed_bulkcurrent;
 217        __hc32  donehead;
 218
 219        /* frame counters (section 7.3) */
 220        __hc32  fminterval;
 221        __hc32  fmremaining;
 222        __hc32  fmnumber;
 223        __hc32  periodicstart;
 224        __hc32  lsthresh;
 225
 226        /* Root hub ports (section 7.4) */
 227        struct  ohci_roothub_regs {
 228                __hc32  a;
 229                __hc32  b;
 230                __hc32  status;
 231#define MAX_ROOT_PORTS  15      /* maximum OHCI root hub ports (RH_A_NDP) */
 232                __hc32  portstatus [MAX_ROOT_PORTS];
 233        } roothub;
 234
 235        /* and optional "legacy support" registers (appendix B) at 0x0100 */
 236
 237} __attribute__ ((aligned(32)));
 238
 239
 240/* OHCI CONTROL AND STATUS REGISTER MASKS */
 241
 242/*
 243 * HcControl (control) register masks
 244 */
 245#define OHCI_CTRL_CBSR  (3 << 0)        /* control/bulk service ratio */
 246#define OHCI_CTRL_PLE   (1 << 2)        /* periodic list enable */
 247#define OHCI_CTRL_IE    (1 << 3)        /* isochronous enable */
 248#define OHCI_CTRL_CLE   (1 << 4)        /* control list enable */
 249#define OHCI_CTRL_BLE   (1 << 5)        /* bulk list enable */
 250#define OHCI_CTRL_HCFS  (3 << 6)        /* host controller functional state */
 251#define OHCI_CTRL_IR    (1 << 8)        /* interrupt routing */
 252#define OHCI_CTRL_RWC   (1 << 9)        /* remote wakeup connected */
 253#define OHCI_CTRL_RWE   (1 << 10)       /* remote wakeup enable */
 254
 255/* pre-shifted values for HCFS */
 256#       define OHCI_USB_RESET   (0 << 6)
 257#       define OHCI_USB_RESUME  (1 << 6)
 258#       define OHCI_USB_OPER    (2 << 6)
 259#       define OHCI_USB_SUSPEND (3 << 6)
 260
 261/*
 262 * HcCommandStatus (cmdstatus) register masks
 263 */
 264#define OHCI_HCR        (1 << 0)        /* host controller reset */
 265#define OHCI_CLF        (1 << 1)        /* control list filled */
 266#define OHCI_BLF        (1 << 2)        /* bulk list filled */
 267#define OHCI_OCR        (1 << 3)        /* ownership change request */
 268#define OHCI_SOC        (3 << 16)       /* scheduling overrun count */
 269
 270/*
 271 * masks used with interrupt registers:
 272 * HcInterruptStatus (intrstatus)
 273 * HcInterruptEnable (intrenable)
 274 * HcInterruptDisable (intrdisable)
 275 */
 276#define OHCI_INTR_SO    (1 << 0)        /* scheduling overrun */
 277#define OHCI_INTR_WDH   (1 << 1)        /* writeback of done_head */
 278#define OHCI_INTR_SF    (1 << 2)        /* start frame */
 279#define OHCI_INTR_RD    (1 << 3)        /* resume detect */
 280#define OHCI_INTR_UE    (1 << 4)        /* unrecoverable error */
 281#define OHCI_INTR_FNO   (1 << 5)        /* frame number overflow */
 282#define OHCI_INTR_RHSC  (1 << 6)        /* root hub status change */
 283#define OHCI_INTR_OC    (1 << 30)       /* ownership change */
 284#define OHCI_INTR_MIE   (1 << 31)       /* master interrupt enable */
 285
 286
 287/* OHCI ROOT HUB REGISTER MASKS */
 288 
 289/* roothub.portstatus [i] bits */
 290#define RH_PS_CCS            0x00000001         /* current connect status */
 291#define RH_PS_PES            0x00000002         /* port enable status*/
 292#define RH_PS_PSS            0x00000004         /* port suspend status */
 293#define RH_PS_POCI           0x00000008         /* port over current indicator */
 294#define RH_PS_PRS            0x00000010         /* port reset status */
 295#define RH_PS_PPS            0x00000100         /* port power status */
 296#define RH_PS_LSDA           0x00000200         /* low speed device attached */
 297#define RH_PS_CSC            0x00010000         /* connect status change */
 298#define RH_PS_PESC           0x00020000         /* port enable status change */
 299#define RH_PS_PSSC           0x00040000         /* port suspend status change */
 300#define RH_PS_OCIC           0x00080000         /* over current indicator change */
 301#define RH_PS_PRSC           0x00100000         /* port reset status change */
 302
 303/* roothub.status bits */
 304#define RH_HS_LPS            0x00000001         /* local power status */
 305#define RH_HS_OCI            0x00000002         /* over current indicator */
 306#define RH_HS_DRWE           0x00008000         /* device remote wakeup enable */
 307#define RH_HS_LPSC           0x00010000         /* local power status change */
 308#define RH_HS_OCIC           0x00020000         /* over current indicator change */
 309#define RH_HS_CRWE           0x80000000         /* clear remote wakeup enable */
 310
 311/* roothub.b masks */
 312#define RH_B_DR         0x0000ffff              /* device removable flags */
 313#define RH_B_PPCM       0xffff0000              /* port power control mask */
 314
 315/* roothub.a masks */
 316#define RH_A_NDP        (0xff << 0)             /* number of downstream ports */
 317#define RH_A_PSM        (1 << 8)                /* power switching mode */
 318#define RH_A_NPS        (1 << 9)                /* no power switching */
 319#define RH_A_DT         (1 << 10)               /* device type (mbz) */
 320#define RH_A_OCPM       (1 << 11)               /* over current protection mode */
 321#define RH_A_NOCP       (1 << 12)               /* no over current protection */
 322#define RH_A_POTPGT     (0xff << 24)            /* power on to power good time */
 323
 324
 325/* hcd-private per-urb state */
 326typedef struct urb_priv {
 327        struct ed               *ed;
 328        u16                     length;         // # tds in this request
 329        u16                     td_cnt;         // tds already serviced
 330        struct list_head        pending;
 331        struct td               *td [0];        // all TDs in this request
 332
 333} urb_priv_t;
 334
 335#define TD_HASH_SIZE    64    /* power'o'two */
 336// sizeof (struct td) ~= 64 == 2^6 ... 
 337#define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
 338
 339
 340/*
 341 * This is the full ohci controller description
 342 *
 343 * Note how the "proper" USB information is just
 344 * a subset of what the full implementation needs. (Linus)
 345 */
 346
 347struct ohci_hcd {
 348        spinlock_t              lock;
 349
 350        /*
 351         * I/O memory used to communicate with the HC (dma-consistent)
 352         */
 353        struct ohci_regs __iomem *regs;
 354
 355        /*
 356         * main memory used to communicate with the HC (dma-consistent).
 357         * hcd adds to schedule for a live hc any time, but removals finish
 358         * only at the start of the next frame.
 359         */
 360        struct ohci_hcca        *hcca;
 361        dma_addr_t              hcca_dma;
 362
 363        struct ed               *ed_rm_list;            /* to be removed */
 364
 365        struct ed               *ed_bulktail;           /* last in bulk list */
 366        struct ed               *ed_controltail;        /* last in ctrl list */
 367        struct ed               *periodic [NUM_INTS];   /* shadow int_table */
 368
 369        /*
 370         * OTG controllers and transceivers need software interaction;
 371         * other external transceivers should be software-transparent 
 372         */
 373        struct otg_transceiver  *transceiver;
 374        unsigned                power_budget;
 375
 376        /*
 377         * memory management for queue data structures
 378         */
 379        struct dma_pool         *td_cache;
 380        struct dma_pool         *ed_cache;
 381        struct td               *td_hash [TD_HASH_SIZE];
 382        struct list_head        pending;
 383
 384        /*
 385         * driver state
 386         */
 387        int                     load [NUM_INTS];
 388        u32                     hc_control;     /* copy of hc control reg */
 389        unsigned long           next_statechange;       /* suspend/resume */
 390        u32                     fminterval;             /* saved register */
 391
 392        struct work_struct      rh_resume;
 393
 394        unsigned long           flags;          /* for HC bugs */
 395#define OHCI_QUIRK_AMD756       0x01                    /* erratum #4 */
 396#define OHCI_QUIRK_SUPERIO      0x02                    /* natsemi */
 397#define OHCI_QUIRK_INITRESET    0x04                    /* SiS, OPTi, ... */
 398#define OHCI_BIG_ENDIAN         0x08                    /* big endian HC */
 399        // there are also chip quirks/bugs in init logic
 400
 401};
 402
 403/* convert between an hcd pointer and the corresponding ohci_hcd */
 404static inline struct ohci_hcd *hcd_to_ohci (struct usb_hcd *hcd)
 405{
 406        return (struct ohci_hcd *) (hcd->hcd_priv);
 407}
 408static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci)
 409{
 410        return container_of ((void *) ohci, struct usb_hcd, hcd_priv);
 411}
 412
 413/*-------------------------------------------------------------------------*/
 414
 415#ifndef DEBUG
 416#define STUB_DEBUG_FILES
 417#endif  /* DEBUG */
 418
 419#define ohci_dbg(ohci, fmt, args...) \
 420        dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
 421#define ohci_err(ohci, fmt, args...) \
 422        dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
 423#define ohci_info(ohci, fmt, args...) \
 424        dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
 425#define ohci_warn(ohci, fmt, args...) \
 426        dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
 427
 428#ifdef OHCI_VERBOSE_DEBUG
 429#       define ohci_vdbg ohci_dbg
 430#else
 431#       define ohci_vdbg(ohci, fmt, args...) do { } while (0)
 432#endif
 433
 434/*-------------------------------------------------------------------------*/
 435
 436/*
 437 * While most USB host controllers implement their registers and
 438 * in-memory communication descriptors in little-endian format,
 439 * a minority (notably the IBM STB04XXX and the Motorola MPC5200
 440 * processors) implement them in big endian format.
 441 *
 442 * This attempts to support either format at compile time without a
 443 * runtime penalty, or both formats with the additional overhead
 444 * of checking a flag bit.
 445 */
 446
 447#ifdef CONFIG_USB_OHCI_BIG_ENDIAN
 448
 449#ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
 450#define big_endian(ohci)        (ohci->flags & OHCI_BIG_ENDIAN) /* either */
 451#else
 452#define big_endian(ohci)        1               /* only big endian */
 453#endif
 454
 455/*
 456 * Big-endian read/write functions are arch-specific.
 457 * Other arches can be added if/when they're needed.
 458 */
 459#if defined(CONFIG_PPC)
 460#define readl_be(addr)          in_be32((__force unsigned *)addr)
 461#define writel_be(val, addr)    out_be32((__force unsigned *)addr, val)
 462#endif
 463
 464static inline unsigned int ohci_readl (const struct ohci_hcd *ohci,
 465                                                        __hc32 __iomem * regs)
 466{
 467        return big_endian(ohci) ? readl_be (regs) : readl ((__force u32 *)regs);
 468}
 469
 470static inline void ohci_writel (const struct ohci_hcd *ohci,
 471                                const unsigned int val, __hc32 __iomem *regs)
 472{
 473        big_endian(ohci) ? writel_be (val, regs) :
 474                           writel (val, (__force u32 *)regs);
 475}
 476
 477#else   /* !CONFIG_USB_OHCI_BIG_ENDIAN */
 478
 479#define big_endian(ohci)        0               /* only little endian */
 480
 481#ifdef CONFIG_ARCH_LH7A404
 482        /* Marc Singer: at the time this code was written, the LH7A404
 483         * had a problem reading the USB host registers.  This
 484         * implementation of the ohci_readl function performs the read
 485         * twice as a work-around.
 486         */
 487static inline unsigned int
 488ohci_readl (const struct ohci_hcd *ohci, const __hc32 *regs)
 489{
 490        *(volatile __force unsigned int*) regs;
 491        return *(volatile __force unsigned int*) regs;
 492}
 493#else
 494        /* Standard version of ohci_readl uses standard, platform
 495         * specific implementation. */
 496static inline unsigned int
 497ohci_readl (const struct ohci_hcd *ohci, __hc32 __iomem * regs)
 498{
 499        return readl(regs);
 500}
 501#endif
 502
 503static inline void ohci_writel (const struct ohci_hcd *ohci,
 504                                const unsigned int val, __hc32 __iomem *regs)
 505{
 506        writel (val, regs);
 507}
 508
 509#endif  /* !CONFIG_USB_OHCI_BIG_ENDIAN */
 510
 511/*-------------------------------------------------------------------------*/
 512
 513/* cpu to ohci */
 514static inline __hc16 cpu_to_hc16 (const struct ohci_hcd *ohci, const u16 x)
 515{
 516        return big_endian(ohci) ? (__force __hc16)cpu_to_be16(x) : (__force __hc16)cpu_to_le16(x);
 517}
 518
 519static inline __hc16 cpu_to_hc16p (const struct ohci_hcd *ohci, const u16 *x)
 520{
 521        return big_endian(ohci) ? cpu_to_be16p(x) : cpu_to_le16p(x);
 522}
 523
 524static inline __hc32 cpu_to_hc32 (const struct ohci_hcd *ohci, const u32 x)
 525{
 526        return big_endian(ohci) ? (__force __hc32)cpu_to_be32(x) : (__force __hc32)cpu_to_le32(x);
 527}
 528
 529static inline __hc32 cpu_to_hc32p (const struct ohci_hcd *ohci, const u32 *x)
 530{
 531        return big_endian(ohci) ? cpu_to_be32p(x) : cpu_to_le32p(x);
 532}
 533
 534/* ohci to cpu */
 535static inline u16 hc16_to_cpu (const struct ohci_hcd *ohci, const __hc16 x)
 536{
 537        return big_endian(ohci) ? be16_to_cpu((__force __be16)x) : le16_to_cpu((__force __le16)x);
 538}
 539
 540static inline u16 hc16_to_cpup (const struct ohci_hcd *ohci, const __hc16 *x)
 541{
 542        return big_endian(ohci) ? be16_to_cpup((__force __be16 *)x) : le16_to_cpup((__force __le16 *)x);
 543}
 544
 545static inline u32 hc32_to_cpu (const struct ohci_hcd *ohci, const __hc32 x)
 546{
 547        return big_endian(ohci) ? be32_to_cpu((__force __be32)x) : le32_to_cpu((__force __le32)x);
 548}
 549
 550static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x)
 551{
 552        return big_endian(ohci) ? be32_to_cpup((__force __be32 *)x) : le32_to_cpup((__force __le32 *)x);
 553}
 554
 555/*-------------------------------------------------------------------------*/
 556
 557static inline void disable (struct ohci_hcd *ohci)
 558{
 559        ohci_to_hcd(ohci)->state = USB_STATE_HALT;
 560}
 561
 562#define FI                      0x2edf          /* 12000 bits per frame (-1) */
 563#define FSMP(fi)                (0x7fff & ((6 * ((fi) - 210)) / 7))
 564#define LSTHRESH                0x628           /* lowspeed bit threshold */
 565
 566static inline void periodic_reinit (struct ohci_hcd *ohci)
 567{
 568        u32     fi = ohci->fminterval & 0x0ffff;
 569
 570        ohci_writel (ohci, ((9 * fi) / 10) & 0x3fff,
 571                                                &ohci->regs->periodicstart);
 572}
 573
 574/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
 575 * The erratum (#4) description is incorrect.  AMD's workaround waits
 576 * till some bits (mostly reserved) are clear; ok for all revs.
 577 */
 578#define read_roothub(hc, register, mask) ({ \
 579        u32 temp = ohci_readl (hc, &hc->regs->roothub.register); \
 580        if (temp == -1) \
 581                disable (hc); \
 582        else if (hc->flags & OHCI_QUIRK_AMD756) \
 583                while (temp & mask) \
 584                        temp = ohci_readl (hc, &hc->regs->roothub.register); \
 585        temp; })
 586
 587static u32 roothub_a (struct ohci_hcd *hc)
 588        { return read_roothub (hc, a, 0xfc0fe000); }
 589static inline u32 roothub_b (struct ohci_hcd *hc)
 590        { return ohci_readl (hc, &hc->regs->roothub.b); }
 591static inline u32 roothub_status (struct ohci_hcd *hc)
 592        { return ohci_readl (hc, &hc->regs->roothub.status); }
 593static u32 roothub_portstatus (struct ohci_hcd *hc, int i)
 594        { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
 595