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25#include <linux/config.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/blkdev.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include "scsi.h"
34#include "hosts.h"
35#include <linux/libata.h>
36
37#define DRV_NAME "ata_sil"
38#define DRV_VERSION "0.51"
39
40enum {
41 sil_3112 = 0,
42
43 SIL_IDE0_TF = 0x80,
44 SIL_IDE0_CTL = 0x8A,
45 SIL_IDE0_BMDMA = 0x00,
46 SIL_IDE0_SCR = 0x100,
47
48 SIL_IDE1_TF = 0xC0,
49 SIL_IDE1_CTL = 0xCA,
50 SIL_IDE1_BMDMA = 0x08,
51 SIL_IDE1_SCR = 0x180,
52};
53
54static void sil_set_piomode (struct ata_port *ap, struct ata_device *adev,
55 unsigned int pio);
56static void sil_set_udmamode (struct ata_port *ap, struct ata_device *adev,
57 unsigned int udma);
58static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
59static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
60static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
61static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
62
63static struct pci_device_id sil_pci_tbl[] = {
64 { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
65 { }
66};
67
68static struct pci_driver sil_pci_driver = {
69 .name = DRV_NAME,
70 .id_table = sil_pci_tbl,
71 .probe = sil_init_one,
72 .remove = ata_pci_remove_one,
73};
74
75static Scsi_Host_Template sil_sht = {
76 .module = THIS_MODULE,
77 .name = DRV_NAME,
78 .queuecommand = ata_scsi_queuecmd,
79 .eh_strategy_handler = ata_scsi_error,
80 .can_queue = ATA_DEF_QUEUE,
81 .this_id = ATA_SHT_THIS_ID,
82 .sg_tablesize = ATA_MAX_PRD,
83 .max_sectors = ATA_MAX_SECTORS,
84 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
85 .emulated = ATA_SHT_EMULATED,
86 .use_clustering = ATA_SHT_USE_CLUSTERING,
87 .proc_name = DRV_NAME,
88 .dma_boundary = ATA_DMA_BOUNDARY,
89 .slave_configure = ata_scsi_slave_config,
90};
91
92static struct ata_port_operations sil_ops = {
93 .port_disable = ata_port_disable,
94 .dev_config = sil_dev_config,
95 .set_piomode = sil_set_piomode,
96 .set_udmamode = sil_set_udmamode,
97 .tf_load = ata_tf_load_mmio,
98 .tf_read = ata_tf_read_mmio,
99 .check_status = ata_check_status_mmio,
100 .exec_command = ata_exec_command_mmio,
101 .phy_reset = sata_phy_reset,
102 .phy_config = pata_phy_config,
103 .bmdma_start = ata_bmdma_start_mmio,
104 .fill_sg = ata_fill_sg,
105 .eng_timeout = ata_eng_timeout,
106 .irq_handler = ata_interrupt,
107 .scr_read = sil_scr_read,
108 .scr_write = sil_scr_write,
109 .port_start = ata_port_start,
110 .port_stop = ata_port_stop,
111};
112
113static struct ata_port_info sil_port_info[] = {
114
115 {
116 .sht = &sil_sht,
117 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
118 ATA_FLAG_SRST | ATA_FLAG_MMIO,
119 .pio_mask = 0x03,
120 .udma_mask = 0x7f,
121 .port_ops = &sil_ops,
122 },
123};
124
125MODULE_AUTHOR("Jeff Garzik");
126MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
127MODULE_LICENSE("GPL");
128MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
129
130static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
131{
132 unsigned long offset = ap->ioaddr.scr_addr;
133
134 switch (sc_reg) {
135 case SCR_STATUS:
136 return offset + 4;
137 case SCR_ERROR:
138 return offset + 8;
139 case SCR_CONTROL:
140 return offset;
141 default:
142
143 break;
144 }
145
146 return 0;
147}
148
149static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
150{
151 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
152 if (mmio)
153 return readl(mmio);
154 return 0xffffffffU;
155}
156
157static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
158{
159 void *mmio = (void *) sil_scr_addr(ap, sc_reg);
160 if (mmio)
161 writel(val, mmio);
162}
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184
185static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
186{
187 const char *s = &dev->product[0];
188 unsigned int len = strnlen(s, sizeof(dev->product));
189
190
191 while ((len > 0) && (s[len - 1] == ' '))
192 len--;
193
194
195 if (!memcmp(s, "Maxtor ", 7)) {
196 printk(KERN_INFO "ata%u(%u): applying pessimistic Maxtor errata fix\n",
197 ap->id, dev->devno);
198 ap->udma_mask &= ATA_UDMA5;
199 return;
200 }
201
202
203 if ((len > 4) && (!memcmp(s, "ST", 2))) {
204 if ((!memcmp(s + len - 2, "AS", 2)) ||
205 (!memcmp(s + len - 3, "ASL", 3))) {
206 printk(KERN_INFO "ata%u(%u): applying pessimistic Seagate errata fix\n",
207 ap->id, dev->devno);
208 ap->host->max_sectors = 15;
209 ap->host->hostt->max_sectors = 15;
210 return;
211 }
212 }
213}
214
215static void sil_set_piomode (struct ata_port *ap, struct ata_device *adev,
216 unsigned int pio)
217{
218
219
220
221}
222
223static void sil_set_udmamode (struct ata_port *ap, struct ata_device *adev,
224 unsigned int udma)
225{
226
227
228
229}
230
231static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
232{
233 static int printed_version;
234 struct ata_probe_ent *probe_ent = NULL;
235 unsigned long base;
236 void *mmio_base;
237 int rc;
238
239 if (!printed_version++)
240 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
241
242
243
244
245
246 rc = pci_enable_device(pdev);
247 if (rc)
248 return rc;
249
250 rc = pci_request_regions(pdev, DRV_NAME);
251 if (rc)
252 goto err_out;
253
254 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
255 if (rc)
256 goto err_out_regions;
257
258 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
259 if (probe_ent == NULL) {
260 rc = -ENOMEM;
261 goto err_out_regions;
262 }
263
264 memset(probe_ent, 0, sizeof(*probe_ent));
265 INIT_LIST_HEAD(&probe_ent->node);
266 probe_ent->pdev = pdev;
267 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
268 probe_ent->sht = sil_port_info[ent->driver_data].sht;
269 probe_ent->n_ports = 2;
270 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
271 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
272 probe_ent->irq = pdev->irq;
273 probe_ent->irq_flags = SA_SHIRQ;
274 probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
275
276 mmio_base = ioremap(pci_resource_start(pdev, 5),
277 pci_resource_len(pdev, 5));
278 if (mmio_base == NULL) {
279 rc = -ENOMEM;
280 goto err_out_free_ent;
281 }
282
283 probe_ent->mmio_base = mmio_base;
284
285 base = (unsigned long) mmio_base;
286 probe_ent->port[0].cmd_addr = base + SIL_IDE0_TF;
287 probe_ent->port[0].ctl_addr = base + SIL_IDE0_CTL;
288 probe_ent->port[0].bmdma_addr = base + SIL_IDE0_BMDMA;
289 probe_ent->port[0].scr_addr = base + SIL_IDE0_SCR;
290 ata_std_ports(&probe_ent->port[0]);
291
292 probe_ent->port[1].cmd_addr = base + SIL_IDE1_TF;
293 probe_ent->port[1].ctl_addr = base + SIL_IDE1_CTL;
294 probe_ent->port[1].bmdma_addr = base + SIL_IDE1_BMDMA;
295 probe_ent->port[1].scr_addr = base + SIL_IDE1_SCR;
296 ata_std_ports(&probe_ent->port[1]);
297
298 pci_set_master(pdev);
299
300
301 ata_device_add(probe_ent);
302 kfree(probe_ent);
303
304 return 0;
305
306err_out_free_ent:
307 kfree(probe_ent);
308err_out_regions:
309 pci_release_regions(pdev);
310err_out:
311 pci_disable_device(pdev);
312 return rc;
313}
314
315static int __init sil_init(void)
316{
317 int rc;
318
319 rc = pci_module_init(&sil_pci_driver);
320 if (rc)
321 return rc;
322
323 return 0;
324}
325
326static void __exit sil_exit(void)
327{
328 pci_unregister_driver(&sil_pci_driver);
329}
330
331
332module_init(sil_init);
333module_exit(sil_exit);
334