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24#include <linux/config.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include "scsi.h"
33#include "hosts.h"
34#include <linux/libata.h>
35#include <asm/io.h>
36
37#undef DIRECT_HDMA
38
39#define DRV_NAME "sata_promise"
40#define DRV_VERSION "0.86"
41
42
43enum {
44 PDC_PRD_TBL = 0x44,
45
46 PDC_PKT_SUBMIT = 0x40,
47 PDC_HDMA_PKT_SUBMIT = 0x100,
48 PDC_INT_SEQMASK = 0x40,
49 PDC_TBG_MODE = 0x41,
50 PDC_FLASH_CTL = 0x44,
51 PDC_CTLSTAT = 0x60,
52 PDC_SATA_PLUG_CSR = 0x6C,
53 PDC_SLEW_CTL = 0x470,
54 PDC_HDMA_CTLSTAT = 0x12C,
55 PDC_20621_SEQCTL = 0x400,
56 PDC_20621_SEQMASK = 0x480,
57 PDC_20621_GENERAL_CTL = 0x484,
58 PDC_20621_PAGE_SIZE = (32 * 1024),
59
60
61 PDC_20621_DIMM_WINDOW = 0x0C,
62 PDC_20621_DIMM_BASE = 0x00200000,
63 PDC_20621_DIMM_DATA = (64 * 1024),
64 PDC_DIMM_DATA_STEP = (256 * 1024),
65 PDC_DIMM_WINDOW_STEP = (8 * 1024),
66 PDC_DIMM_HOST_PRD = (6 * 1024),
67 PDC_DIMM_HOST_PKT = (128 * 0),
68 PDC_DIMM_HPKT_PRD = (128 * 1),
69 PDC_DIMM_ATA_PKT = (128 * 2),
70 PDC_DIMM_APKT_PRD = (128 * 3),
71 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
72 PDC_PAGE_WINDOW = 0x40,
73 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
74 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
75 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
76
77 PDC_CHIP0_OFS = 0xC0000,
78
79 board_2037x = 0,
80 board_20319 = 1,
81 board_20621 = 2,
82
83 PDC_FLAG_20621 = (1 << 30),
84 PDC_HDMA_RESET = (1 << 11),
85};
86
87
88struct pdc_port_priv {
89 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
90 u8 *pkt;
91 dma_addr_t pkt_dma;
92};
93
94
95static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
96static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
97static void pdc_sata_set_piomode (struct ata_port *ap, struct ata_device *adev,
98 unsigned int pio);
99static void pdc_sata_set_udmamode (struct ata_port *ap, struct ata_device *adev,
100 unsigned int udma);
101static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
102static void pdc_dma_start(struct ata_queued_cmd *qc);
103static void pdc20621_dma_start(struct ata_queued_cmd *qc);
104static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
105static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
106static void pdc_eng_timeout(struct ata_port *ap);
107static void pdc_20621_phy_reset (struct ata_port *ap);
108static int pdc_port_start(struct ata_port *ap);
109static void pdc_port_stop(struct ata_port *ap);
110static void pdc_fill_sg(struct ata_queued_cmd *qc);
111static void pdc20621_fill_sg(struct ata_queued_cmd *qc);
112static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
113static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
114static void pdc20621_host_stop(struct ata_host_set *host_set);
115static inline void pdc_dma_complete (struct ata_port *ap,
116 struct ata_queued_cmd *qc);
117
118
119static Scsi_Host_Template pdc_sata_sht = {
120 .module = THIS_MODULE,
121 .name = DRV_NAME,
122 .queuecommand = ata_scsi_queuecmd,
123 .eh_strategy_handler = ata_scsi_error,
124 .can_queue = ATA_DEF_QUEUE,
125 .this_id = ATA_SHT_THIS_ID,
126 .sg_tablesize = ATA_MAX_PRD,
127 .max_sectors = ATA_MAX_SECTORS,
128 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
129 .emulated = ATA_SHT_EMULATED,
130 .use_clustering = ATA_SHT_USE_CLUSTERING,
131 .proc_name = DRV_NAME,
132 .dma_boundary = ATA_DMA_BOUNDARY,
133 .slave_configure = ata_scsi_slave_config,
134};
135
136static struct ata_port_operations pdc_sata_ops = {
137 .port_disable = ata_port_disable,
138 .set_piomode = pdc_sata_set_piomode,
139 .set_udmamode = pdc_sata_set_udmamode,
140 .tf_load = pdc_tf_load_mmio,
141 .tf_read = ata_tf_read_mmio,
142 .check_status = ata_check_status_mmio,
143 .exec_command = pdc_exec_command_mmio,
144 .phy_reset = sata_phy_reset,
145 .phy_config = pata_phy_config,
146 .bmdma_start = pdc_dma_start,
147 .fill_sg = pdc_fill_sg,
148 .eng_timeout = pdc_eng_timeout,
149 .irq_handler = pdc_interrupt,
150 .scr_read = pdc_sata_scr_read,
151 .scr_write = pdc_sata_scr_write,
152 .port_start = pdc_port_start,
153 .port_stop = pdc_port_stop,
154};
155
156static struct ata_port_operations pdc_20621_ops = {
157 .port_disable = ata_port_disable,
158 .set_piomode = pdc_sata_set_piomode,
159 .set_udmamode = pdc_sata_set_udmamode,
160 .tf_load = pdc_tf_load_mmio,
161 .tf_read = ata_tf_read_mmio,
162 .check_status = ata_check_status_mmio,
163 .exec_command = pdc_exec_command_mmio,
164 .phy_reset = pdc_20621_phy_reset,
165 .phy_config = pata_phy_config,
166 .bmdma_start = pdc20621_dma_start,
167 .fill_sg = pdc20621_fill_sg,
168 .eng_timeout = pdc_eng_timeout,
169 .irq_handler = pdc20621_interrupt,
170 .port_start = pdc_port_start,
171 .port_stop = pdc_port_stop,
172 .host_stop = pdc20621_host_stop,
173};
174
175static struct ata_port_info pdc_port_info[] = {
176
177 {
178 .sht = &pdc_sata_sht,
179 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
180 ATA_FLAG_SRST | ATA_FLAG_MMIO,
181 .pio_mask = 0x03,
182 .udma_mask = 0x7f,
183 .port_ops = &pdc_sata_ops,
184 },
185
186
187 {
188 .sht = &pdc_sata_sht,
189 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
190 ATA_FLAG_SRST | ATA_FLAG_MMIO,
191 .pio_mask = 0x03,
192 .udma_mask = 0x7f,
193 .port_ops = &pdc_sata_ops,
194 },
195
196
197 {
198 .sht = &pdc_sata_sht,
199 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
200 ATA_FLAG_SRST | ATA_FLAG_MMIO |
201 PDC_FLAG_20621,
202 .pio_mask = 0x03,
203 .udma_mask = 0x7f,
204 .port_ops = &pdc_20621_ops,
205 },
206
207};
208
209static struct pci_device_id pdc_sata_pci_tbl[] = {
210 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
211 board_2037x },
212 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
213 board_2037x },
214 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
215 board_2037x },
216 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
217 board_2037x },
218 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
219 board_20319 },
220 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
221 board_20319 },
222 { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
223 board_20621 },
224 { }
225};
226
227
228static struct pci_driver pdc_sata_pci_driver = {
229 .name = DRV_NAME,
230 .id_table = pdc_sata_pci_tbl,
231 .probe = pdc_sata_init_one,
232 .remove = ata_pci_remove_one,
233};
234
235
236static void pdc20621_host_stop(struct ata_host_set *host_set)
237{
238 void *mmio = host_set->private_data;
239
240 assert(mmio != NULL);
241 iounmap(mmio);
242}
243
244static int pdc_port_start(struct ata_port *ap)
245{
246 struct pci_dev *pdev = ap->host_set->pdev;
247 struct pdc_port_priv *pp;
248 int rc;
249
250 rc = ata_port_start(ap);
251 if (rc)
252 return rc;
253
254 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
255 if (!pp) {
256 rc = -ENOMEM;
257 goto err_out;
258 }
259
260 pp->pkt = pci_alloc_consistent(pdev, 128, &pp->pkt_dma);
261 if (!pp->pkt) {
262 rc = -ENOMEM;
263 goto err_out_kfree;
264 }
265
266 ap->private_data = pp;
267
268 return 0;
269
270err_out_kfree:
271 kfree(pp);
272err_out:
273 ata_port_stop(ap);
274 return rc;
275}
276
277
278static void pdc_port_stop(struct ata_port *ap)
279{
280 struct pci_dev *pdev = ap->host_set->pdev;
281 struct pdc_port_priv *pp = ap->private_data;
282
283 ap->private_data = NULL;
284 pci_free_consistent(pdev, 128, pp->pkt, pp->pkt_dma);
285 kfree(pp);
286 ata_port_stop(ap);
287}
288
289
290static void pdc_20621_phy_reset (struct ata_port *ap)
291{
292 VPRINTK("ENTER\n");
293 ap->cbl = ATA_CBL_SATA;
294 ata_port_probe(ap);
295 ata_bus_reset(ap);
296}
297
298static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
299{
300 if (sc_reg > SCR_CONTROL)
301 return 0xffffffffU;
302 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
303}
304
305
306static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
307 u32 val)
308{
309 if (sc_reg > SCR_CONTROL)
310 return;
311 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
312}
313
314static void pdc_sata_set_piomode (struct ata_port *ap, struct ata_device *adev,
315 unsigned int pio)
316{
317
318}
319
320
321static void pdc_sata_set_udmamode (struct ata_port *ap, struct ata_device *adev,
322 unsigned int udma)
323{
324
325}
326
327enum pdc_packet_bits {
328 PDC_PKT_READ = (1 << 2),
329 PDC_PKT_NODATA = (1 << 3),
330
331 PDC_PKT_SIZEMASK = (1 << 7) | (1 << 6) | (1 << 5),
332 PDC_PKT_CLEAR_BSY = (1 << 4),
333 PDC_PKT_WAIT_DRDY = (1 << 3) | (1 << 4),
334 PDC_LAST_REG = (1 << 3),
335
336 PDC_REG_DEVCTL = (1 << 3) | (1 << 2) | (1 << 1),
337};
338
339static inline unsigned int pdc_pkt_header(struct ata_taskfile *tf,
340 dma_addr_t sg_table,
341 unsigned int devno, u8 *buf)
342{
343 u8 dev_reg;
344 u32 *buf32 = (u32 *) buf;
345
346
347
348
349 switch (tf->protocol) {
350 case ATA_PROT_DMA_READ:
351 buf32[0] = cpu_to_le32(PDC_PKT_READ);
352 break;
353
354 case ATA_PROT_DMA_WRITE:
355 buf32[0] = 0;
356 break;
357
358 case ATA_PROT_NODATA:
359 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
360 break;
361
362 default:
363 BUG();
364 break;
365 }
366
367 buf32[1] = cpu_to_le32(sg_table);
368 buf32[2] = 0;
369
370 if (devno == 0)
371 dev_reg = ATA_DEVICE_OBS;
372 else
373 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
374
375
376 buf[12] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
377 buf[13] = dev_reg;
378
379
380 buf[14] = (1 << 5) | PDC_REG_DEVCTL;
381 buf[15] = tf->ctl;
382
383 return 16;
384}
385
386static inline unsigned int pdc_pkt_footer(struct ata_taskfile *tf, u8 *buf,
387 unsigned int i)
388{
389 if (tf->flags & ATA_TFLAG_DEVICE) {
390 buf[i++] = (1 << 5) | ATA_REG_DEVICE;
391 buf[i++] = tf->device;
392 }
393
394
395 buf[i++] = (1 << 5) | PDC_LAST_REG | ATA_REG_CMD;
396 buf[i++] = tf->command;
397
398 return i;
399}
400
401static inline unsigned int pdc_prep_lba28(struct ata_taskfile *tf, u8 *buf, unsigned int i)
402{
403
404
405
406 buf[i++] = (1 << 5) | ATA_REG_FEATURE;
407 buf[i++] = tf->feature;
408
409 buf[i++] = (1 << 5) | ATA_REG_NSECT;
410 buf[i++] = tf->nsect;
411
412 buf[i++] = (1 << 5) | ATA_REG_LBAL;
413 buf[i++] = tf->lbal;
414
415 buf[i++] = (1 << 5) | ATA_REG_LBAM;
416 buf[i++] = tf->lbam;
417
418 buf[i++] = (1 << 5) | ATA_REG_LBAH;
419 buf[i++] = tf->lbah;
420
421 return i;
422}
423
424static inline unsigned int pdc_prep_lba48(struct ata_taskfile *tf, u8 *buf, unsigned int i)
425{
426
427
428
429 buf[i++] = (2 << 5) | ATA_REG_FEATURE;
430 buf[i++] = tf->hob_feature;
431 buf[i++] = tf->feature;
432
433 buf[i++] = (2 << 5) | ATA_REG_NSECT;
434 buf[i++] = tf->hob_nsect;
435 buf[i++] = tf->nsect;
436
437 buf[i++] = (2 << 5) | ATA_REG_LBAL;
438 buf[i++] = tf->hob_lbal;
439 buf[i++] = tf->lbal;
440
441 buf[i++] = (2 << 5) | ATA_REG_LBAM;
442 buf[i++] = tf->hob_lbam;
443 buf[i++] = tf->lbam;
444
445 buf[i++] = (2 << 5) | ATA_REG_LBAH;
446 buf[i++] = tf->hob_lbah;
447 buf[i++] = tf->lbah;
448
449 return i;
450}
451
452static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
453 unsigned int portno,
454 unsigned int total_len)
455{
456 u32 addr;
457 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
458 u32 *buf32 = (u32 *) buf;
459
460
461 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
462 (PDC_DIMM_DATA_STEP * portno);
463 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
464 buf32[dw] = cpu_to_le32(addr);
465 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
466
467 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
468 PDC_20621_DIMM_BASE +
469 (PDC_DIMM_WINDOW_STEP * portno) +
470 PDC_DIMM_APKT_PRD,
471 buf32[dw], buf32[dw + 1]);
472}
473
474static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
475 unsigned int portno,
476 unsigned int total_len)
477{
478 u32 addr;
479 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
480 u32 *buf32 = (u32 *) buf;
481
482
483 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
484 (PDC_DIMM_DATA_STEP * portno);
485
486 buf32[dw] = cpu_to_le32(addr);
487 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
488
489 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
490 PDC_20621_DIMM_BASE +
491 (PDC_DIMM_WINDOW_STEP * portno) +
492 PDC_DIMM_HPKT_PRD,
493 buf32[dw], buf32[dw + 1]);
494}
495
496static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
497 unsigned int devno, u8 *buf,
498 unsigned int portno)
499{
500 unsigned int i, dw;
501 u32 *buf32 = (u32 *) buf;
502 u8 dev_reg;
503
504 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
505 (PDC_DIMM_WINDOW_STEP * portno) +
506 PDC_DIMM_APKT_PRD;
507 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
508
509 i = PDC_DIMM_ATA_PKT;
510
511
512
513
514 if (tf->protocol == ATA_PROT_DMA_READ)
515 buf[i++] = PDC_PKT_READ;
516 else if (tf->protocol == ATA_PROT_NODATA)
517 buf[i++] = PDC_PKT_NODATA;
518 else
519 buf[i++] = 0;
520 buf[i++] = 0;
521 buf[i++] = portno + 1;
522 buf[i++] = 0xff;
523
524
525 dw = i >> 2;
526 buf32[dw] = cpu_to_le32(dimm_sg);
527 buf32[dw + 1] = 0;
528 i += 8;
529
530 if (devno == 0)
531 dev_reg = ATA_DEVICE_OBS;
532 else
533 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
534
535
536 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
537 buf[i++] = dev_reg;
538
539
540 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
541 buf[i++] = tf->ctl;
542
543 return i;
544}
545
546static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
547 unsigned int portno)
548{
549 unsigned int dw;
550 u32 tmp, *buf32 = (u32 *) buf;
551
552 unsigned int host_sg = PDC_20621_DIMM_BASE +
553 (PDC_DIMM_WINDOW_STEP * portno) +
554 PDC_DIMM_HOST_PRD;
555 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
556 (PDC_DIMM_WINDOW_STEP * portno) +
557 PDC_DIMM_HPKT_PRD;
558 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
559 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
560
561 dw = PDC_DIMM_HOST_PKT >> 2;
562
563
564
565
566 if (tf->protocol == ATA_PROT_DMA_READ)
567 tmp = PDC_PKT_READ;
568 else
569 tmp = 0;
570 tmp |= ((portno + 1 + 4) << 16);
571 tmp |= (0xff << 24);
572 buf32[dw + 0] = cpu_to_le32(tmp);
573 buf32[dw + 1] = cpu_to_le32(host_sg);
574 buf32[dw + 2] = cpu_to_le32(dimm_sg);
575 buf32[dw + 3] = 0;
576
577 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
578 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
579 PDC_DIMM_HOST_PKT,
580 buf32[dw + 0],
581 buf32[dw + 1],
582 buf32[dw + 2],
583 buf32[dw + 3]);
584}
585
586static void pdc20621_fill_sg(struct ata_queued_cmd *qc)
587{
588 struct scatterlist *sg = qc->sg;
589 struct ata_port *ap = qc->ap;
590 struct pdc_port_priv *pp = ap->private_data;
591 void *mmio = ap->host_set->mmio_base;
592 void *dimm_mmio = ap->host_set->private_data;
593 unsigned int portno = ap->port_no;
594 unsigned int i, last, idx, total_len = 0, sgt_len;
595 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
596
597 VPRINTK("ata%u: ENTER\n", ap->id);
598
599
600 mmio += PDC_CHIP0_OFS;
601
602
603
604
605 last = qc->n_elem;
606 idx = 0;
607 for (i = 0; i < last; i++) {
608 buf[idx++] = cpu_to_le32(sg[i].dma_address);
609 buf[idx++] = cpu_to_le32(sg[i].length);
610 total_len += sg[i].length;
611 }
612 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
613 sgt_len = idx * 4;
614
615
616
617
618 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
619 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
620
621 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
622 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
623
624 if (qc->tf.flags & ATA_TFLAG_LBA48)
625 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
626 else
627 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
628
629 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
630
631
632 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
633 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
634 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
635 PDC_DIMM_HOST_PRD,
636 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
637
638
639 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
640
641 readl(dimm_mmio);
642
643 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
644}
645
646#ifdef DIRECT_HDMA
647static void pdc20621_push_hdma(struct ata_queued_cmd *qc)
648{
649 struct ata_port *ap = qc->ap;
650 struct ata_host_set *host_set = ap->host_set;
651 unsigned int port_no = ap->port_no;
652 void *mmio = host_set->mmio_base;
653 unsigned int rw = (qc->flags & ATA_QCFLAG_WRITE);
654 u32 tmp;
655
656 unsigned int host_sg = PDC_20621_DIMM_BASE +
657 (PDC_DIMM_WINDOW_STEP * port_no) +
658 PDC_DIMM_HOST_PRD;
659 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
660 (PDC_DIMM_WINDOW_STEP * port_no) +
661 PDC_DIMM_HPKT_PRD;
662
663
664 mmio += PDC_CHIP0_OFS;
665
666 tmp = readl(mmio + PDC_HDMA_CTLSTAT) & 0xffffff00;
667 tmp |= port_no + 1 + 4;
668 if (!rw)
669 tmp |= (1 << 6);
670 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
671 readl(mmio + PDC_HDMA_CTLSTAT);
672
673 writel(host_sg, mmio + 0x108);
674 writel(dimm_sg, mmio + 0x10C);
675 writel(0, mmio + 0x128);
676
677 tmp |= (1 << 7);
678 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
679 readl(mmio + PDC_HDMA_CTLSTAT);
680}
681#endif
682
683#ifdef ATA_VERBOSE_DEBUG
684static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
685{
686 struct ata_port *ap = qc->ap;
687 unsigned int port_no = ap->port_no;
688 void *dimm_mmio = ap->host_set->private_data;
689
690 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
691 dimm_mmio += PDC_DIMM_HOST_PKT;
692
693 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
694 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
695 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
696 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
697}
698#else
699static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
700#endif
701
702static void pdc20621_dma_start(struct ata_queued_cmd *qc)
703{
704 struct ata_port *ap = qc->ap;
705 struct ata_host_set *host_set = ap->host_set;
706 unsigned int port_no = ap->port_no;
707 void *mmio = host_set->mmio_base;
708 unsigned int rw = (qc->flags & ATA_QCFLAG_WRITE);
709 u8 seq = (u8) (port_no + 1);
710 unsigned int doing_hdma = 0, port_ofs;
711
712
713 mmio += PDC_CHIP0_OFS;
714
715 VPRINTK("ata%u: ENTER\n", ap->id);
716
717 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
718
719
720 if (rw) {
721 doing_hdma = 1;
722 seq += 4;
723 }
724
725 wmb();
726
727 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
728 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
729
730 if (doing_hdma) {
731 pdc20621_dump_hdma(qc);
732#ifdef DIRECT_HDMA
733 pdc20621_push_hdma(qc);
734#else
735 writel(port_ofs + PDC_DIMM_HOST_PKT,
736 mmio + PDC_HDMA_PKT_SUBMIT);
737 readl(mmio + PDC_HDMA_PKT_SUBMIT);
738#endif
739 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
740 port_ofs + PDC_DIMM_HOST_PKT,
741 port_ofs + PDC_DIMM_HOST_PKT,
742 seq);
743 } else {
744 writel(port_ofs + PDC_DIMM_ATA_PKT,
745 (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
746 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
747 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
748 port_ofs + PDC_DIMM_ATA_PKT,
749 port_ofs + PDC_DIMM_ATA_PKT,
750 seq);
751 }
752}
753
754static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
755 struct ata_queued_cmd *qc,
756 unsigned int doing_hdma,
757 void *mmio)
758{
759 unsigned int port_no = ap->port_no;
760 unsigned int port_ofs =
761 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
762 u8 status;
763 unsigned int handled = 0;
764
765 VPRINTK("ENTER\n");
766
767 switch (qc->tf.protocol) {
768 case ATA_PROT_DMA_READ:
769
770 if (doing_hdma) {
771 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
772 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
773 pdc_dma_complete(ap, qc);
774 }
775
776
777 else {
778 u8 seq = (u8) (port_no + 1 + 4);
779 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
780 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
781
782
783 pdc20621_dump_hdma(qc);
784 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
785 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
786#ifdef DIRECT_HDMA
787 pdc20621_push_hdma(qc);
788#else
789 writel(port_ofs + PDC_DIMM_HOST_PKT,
790 mmio + PDC_HDMA_PKT_SUBMIT);
791 readl(mmio + PDC_HDMA_PKT_SUBMIT);
792#endif
793 }
794 handled = 1;
795 break;
796
797 case ATA_PROT_DMA_WRITE:
798
799 if (doing_hdma) {
800 u8 seq = (u8) (port_no + 1);
801 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
802 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
803
804
805 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
806 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
807 writel(port_ofs + PDC_DIMM_ATA_PKT,
808 (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
809 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
810 }
811
812
813 else {
814 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
815 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
816 pdc_dma_complete(ap, qc);
817 }
818 handled = 1;
819 break;
820
821 case ATA_PROT_NODATA:
822 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
823 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
824 ata_qc_complete(qc, status, 0);
825 handled = 1;
826 break;
827
828 default:
829 ap->stats.idle_irq++;
830 break;
831 }
832
833 return handled;
834}
835
836static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
837{
838 struct ata_host_set *host_set = dev_instance;
839 struct ata_port *ap;
840 u32 mask = 0;
841 unsigned int i, tmp, port_no;
842 unsigned int handled = 0;
843 void *mmio_base;
844
845 VPRINTK("ENTER\n");
846
847 if (!host_set || !host_set->mmio_base) {
848 VPRINTK("QUICK EXIT\n");
849 return IRQ_NONE;
850 }
851
852 mmio_base = host_set->mmio_base;
853
854
855 mmio_base += PDC_CHIP0_OFS;
856 mask = readl(mmio_base + PDC_20621_SEQMASK);
857 VPRINTK("mask == 0x%x\n", mask);
858
859 if (mask == 0xffffffff) {
860 VPRINTK("QUICK EXIT 2\n");
861 return IRQ_NONE;
862 }
863 mask &= 0xffff;
864 if (!mask) {
865 VPRINTK("QUICK EXIT 3\n");
866 return IRQ_NONE;
867 }
868
869 spin_lock_irq(&host_set->lock);
870
871 for (i = 1; i < 9; i++) {
872 port_no = i - 1;
873 if (port_no > 3)
874 port_no -= 4;
875 if (port_no >= host_set->n_ports)
876 ap = NULL;
877 else
878 ap = host_set->ports[port_no];
879 tmp = mask & (1 << i);
880 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
881 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
882 struct ata_queued_cmd *qc;
883
884 qc = ata_qc_from_tag(ap, ap->active_tag);
885 if (qc && ((qc->flags & ATA_QCFLAG_POLL) == 0))
886 handled += pdc20621_host_intr(ap, qc, (i > 4),
887 mmio_base);
888 }
889 }
890
891 spin_unlock_irq(&host_set->lock);
892
893 VPRINTK("mask == 0x%x\n", mask);
894
895 VPRINTK("EXIT\n");
896
897 return IRQ_RETVAL(handled);
898}
899
900static void pdc_fill_sg(struct ata_queued_cmd *qc)
901{
902 struct pdc_port_priv *pp = qc->ap->private_data;
903 unsigned int i;
904
905 VPRINTK("ENTER\n");
906
907 ata_fill_sg(qc);
908
909 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, qc->dev->devno, pp->pkt);
910
911 if (qc->tf.flags & ATA_TFLAG_LBA48)
912 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
913 else
914 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
915
916 pdc_pkt_footer(&qc->tf, pp->pkt, i);
917}
918
919static inline void pdc_dma_complete (struct ata_port *ap,
920 struct ata_queued_cmd *qc)
921{
922
923 ata_qc_complete(ata_qc_from_tag(ap, ap->active_tag),
924 ata_wait_idle(ap), 0);
925}
926
927static void pdc_eng_timeout(struct ata_port *ap)
928{
929 u8 drv_stat;
930 struct ata_queued_cmd *qc;
931
932 DPRINTK("ENTER\n");
933
934 qc = ata_qc_from_tag(ap, ap->active_tag);
935 if (!qc) {
936 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
937 ap->id);
938 goto out;
939 }
940
941 switch (qc->tf.protocol) {
942 case ATA_PROT_DMA_READ:
943 case ATA_PROT_DMA_WRITE:
944 printk(KERN_ERR "ata%u: DMA timeout\n", ap->id);
945 ata_qc_complete(ata_qc_from_tag(ap, ap->active_tag),
946 ata_wait_idle(ap) | ATA_ERR, 0);
947 break;
948
949 case ATA_PROT_NODATA:
950 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
951
952 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x\n",
953 ap->id, qc->tf.command, drv_stat);
954
955 ata_qc_complete(qc, drv_stat, 1);
956 break;
957
958 default:
959 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
960
961 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
962 ap->id, qc->tf.command, drv_stat);
963
964 ata_qc_complete(qc, drv_stat, 1);
965 break;
966 }
967
968out:
969 DPRINTK("EXIT\n");
970}
971
972static inline unsigned int pdc_host_intr( struct ata_port *ap,
973 struct ata_queued_cmd *qc)
974{
975 u8 status;
976 unsigned int handled = 0;
977
978 switch (qc->tf.protocol) {
979 case ATA_PROT_DMA_READ:
980 case ATA_PROT_DMA_WRITE:
981 pdc_dma_complete(ap, qc);
982 handled = 1;
983 break;
984
985 case ATA_PROT_NODATA:
986 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
987 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
988 ata_qc_complete(qc, status, 0);
989 handled = 1;
990 break;
991
992 default:
993 ap->stats.idle_irq++;
994 break;
995 }
996
997 return handled;
998}
999
1000static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
1001{
1002 struct ata_host_set *host_set = dev_instance;
1003 struct ata_port *ap;
1004 u32 mask = 0;
1005 unsigned int i, tmp;
1006 unsigned int handled = 0;
1007 void *mmio_base;
1008
1009 VPRINTK("ENTER\n");
1010
1011 if (!host_set || !host_set->mmio_base) {
1012 VPRINTK("QUICK EXIT\n");
1013 return IRQ_NONE;
1014 }
1015
1016 mmio_base = host_set->mmio_base;
1017
1018
1019 mask = readl(mmio_base + PDC_INT_SEQMASK);
1020
1021 if (mask == 0xffffffff) {
1022 VPRINTK("QUICK EXIT 2\n");
1023 return IRQ_NONE;
1024 }
1025 mask &= 0xffff;
1026 if (!mask) {
1027 VPRINTK("QUICK EXIT 3\n");
1028 return IRQ_NONE;
1029 }
1030
1031 spin_lock_irq(&host_set->lock);
1032
1033 for (i = 0; i < host_set->n_ports; i++) {
1034 VPRINTK("port %u\n", i);
1035 ap = host_set->ports[i];
1036 tmp = mask & (1 << (i + 1));
1037 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
1038 struct ata_queued_cmd *qc;
1039
1040 qc = ata_qc_from_tag(ap, ap->active_tag);
1041 if (qc && ((qc->flags & ATA_QCFLAG_POLL) == 0))
1042 handled += pdc_host_intr(ap, qc);
1043 }
1044 }
1045
1046 spin_unlock_irq(&host_set->lock);
1047
1048 VPRINTK("EXIT\n");
1049
1050 return IRQ_RETVAL(handled);
1051}
1052
1053static void pdc_dma_start(struct ata_queued_cmd *qc)
1054{
1055 struct ata_port *ap = qc->ap;
1056 struct pdc_port_priv *pp = ap->private_data;
1057 unsigned int port_no = ap->port_no;
1058 u8 seq = (u8) (port_no + 1);
1059
1060 VPRINTK("ENTER, ap %p\n", ap);
1061
1062 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
1063 readl(ap->host_set->mmio_base + (seq * 4));
1064
1065 pp->pkt[2] = seq;
1066 wmb();
1067 writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
1068 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
1069}
1070
1071static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
1072{
1073 if ((tf->protocol != ATA_PROT_DMA_READ) &&
1074 (tf->protocol != ATA_PROT_DMA_WRITE))
1075 ata_tf_load_mmio(ap, tf);
1076}
1077
1078
1079static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
1080{
1081 if ((tf->protocol != ATA_PROT_DMA_READ) &&
1082 (tf->protocol != ATA_PROT_DMA_WRITE))
1083 ata_exec_command_mmio(ap, tf);
1084}
1085
1086
1087static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
1088{
1089 port->cmd_addr = base;
1090 port->data_addr = base;
1091 port->error_addr = base + 0x4;
1092 port->nsect_addr = base + 0x8;
1093 port->lbal_addr = base + 0xc;
1094 port->lbam_addr = base + 0x10;
1095 port->lbah_addr = base + 0x14;
1096 port->device_addr = base + 0x18;
1097 port->cmdstat_addr = base + 0x1c;
1098 port->ctl_addr = base + 0x38;
1099}
1100
1101static void pdc_20621_init(struct ata_probe_ent *pe)
1102{
1103 u32 tmp;
1104 void *mmio = pe->mmio_base;
1105
1106 mmio += PDC_CHIP0_OFS;
1107
1108
1109
1110
1111 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1112 tmp |= PDC_PAGE_WINDOW;
1113 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1114
1115
1116
1117
1118 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1119 tmp |= PDC_HDMA_RESET;
1120 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1121 readl(mmio + PDC_HDMA_CTLSTAT);
1122
1123 udelay(10);
1124
1125 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1126 tmp &= ~PDC_HDMA_RESET;
1127 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1128 readl(mmio + PDC_HDMA_CTLSTAT);
1129}
1130
1131static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
1132{
1133 void *mmio = pe->mmio_base;
1134 u32 tmp;
1135
1136 if (chip_id == board_20621)
1137 return;
1138
1139
1140
1141
1142 tmp = readl(mmio + PDC_FLASH_CTL);
1143 if ((tmp & (1 << 16)) == 0)
1144 writel(tmp | (1 << 16), mmio + PDC_FLASH_CTL);
1145
1146
1147 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
1148 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
1149
1150
1151 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
1152 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
1153
1154
1155 tmp = readl(mmio + PDC_TBG_MODE);
1156 tmp &= ~0x30000;
1157 tmp |= 0x10000;
1158 writel(tmp, mmio + PDC_TBG_MODE);
1159
1160
1161 tmp = readl(mmio + PDC_SLEW_CTL);
1162 tmp &= 0xFFFFF03F;
1163 tmp |= 0x00000900;
1164 writel(tmp, mmio + PDC_SLEW_CTL);
1165}
1166
1167static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1168{
1169 static int printed_version;
1170 struct ata_probe_ent *probe_ent = NULL;
1171 unsigned long base;
1172 void *mmio_base, *dimm_mmio = NULL;
1173 unsigned int board_idx = (unsigned int) ent->driver_data;
1174 unsigned int have_20621 = (board_idx == board_20621);
1175 int rc;
1176
1177 if (!printed_version++)
1178 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1179
1180
1181
1182
1183
1184 rc = pci_enable_device(pdev);
1185 if (rc)
1186 return rc;
1187
1188 rc = pci_request_regions(pdev, DRV_NAME);
1189 if (rc)
1190 goto err_out;
1191
1192 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1193 if (rc)
1194 goto err_out_regions;
1195
1196 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1197 if (probe_ent == NULL) {
1198 rc = -ENOMEM;
1199 goto err_out_regions;
1200 }
1201
1202 memset(probe_ent, 0, sizeof(*probe_ent));
1203 probe_ent->pdev = pdev;
1204 INIT_LIST_HEAD(&probe_ent->node);
1205
1206 mmio_base = ioremap(pci_resource_start(pdev, 3),
1207 pci_resource_len(pdev, 3));
1208 if (mmio_base == NULL) {
1209 rc = -ENOMEM;
1210 goto err_out_free_ent;
1211 }
1212 base = (unsigned long) mmio_base;
1213
1214 if (have_20621) {
1215 dimm_mmio = ioremap(pci_resource_start(pdev, 4),
1216 pci_resource_len(pdev, 4));
1217 if (!dimm_mmio) {
1218 rc = -ENOMEM;
1219 goto err_out_iounmap;
1220 }
1221 }
1222
1223 probe_ent->sht = pdc_port_info[board_idx].sht;
1224 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
1225 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1226 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1227 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1228
1229 probe_ent->irq = pdev->irq;
1230 probe_ent->irq_flags = SA_SHIRQ;
1231 probe_ent->mmio_base = mmio_base;
1232
1233 if (have_20621) {
1234 probe_ent->private_data = dimm_mmio;
1235 base += PDC_CHIP0_OFS;
1236 }
1237
1238 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1239 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1240
1241 if (!have_20621) {
1242 probe_ent->port[0].scr_addr = base + 0x400;
1243 probe_ent->port[1].scr_addr = base + 0x500;
1244 }
1245
1246
1247 switch (board_idx) {
1248 case board_20319:
1249 case board_20621:
1250 probe_ent->n_ports = 4;
1251
1252 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1253 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1254
1255 if (!have_20621) {
1256 probe_ent->port[2].scr_addr = base + 0x600;
1257 probe_ent->port[3].scr_addr = base + 0x700;
1258 }
1259 break;
1260 case board_2037x:
1261 probe_ent->n_ports = 2;
1262 break;
1263 default:
1264 BUG();
1265 break;
1266 }
1267
1268 pci_set_master(pdev);
1269
1270
1271 if (have_20621)
1272 pdc_20621_init(probe_ent);
1273 else
1274 pdc_host_init(board_idx, probe_ent);
1275
1276
1277 ata_device_add(probe_ent);
1278 kfree(probe_ent);
1279
1280 return 0;
1281
1282err_out_iounmap:
1283 iounmap(mmio_base);
1284err_out_free_ent:
1285 kfree(probe_ent);
1286err_out_regions:
1287 pci_release_regions(pdev);
1288err_out:
1289 pci_disable_device(pdev);
1290 return rc;
1291}
1292
1293
1294static int __init pdc_sata_init(void)
1295{
1296 int rc;
1297
1298 rc = pci_module_init(&pdc_sata_pci_driver);
1299 if (rc)
1300 return rc;
1301
1302 return 0;
1303}
1304
1305
1306static void __exit pdc_sata_exit(void)
1307{
1308 pci_unregister_driver(&pdc_sata_pci_driver);
1309}
1310
1311
1312MODULE_AUTHOR("Jeff Garzik");
1313MODULE_DESCRIPTION("Promise SATA low-level driver");
1314MODULE_LICENSE("GPL");
1315MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1316
1317module_init(pdc_sata_init);
1318module_exit(pdc_sata_exit);
1319
