LXR linux-bk/drivers/net/tulip/tulip.h

   1/*
   2        drivers/net/tulip/tulip.h
   3
   4        Copyright 2000,2001  The Linux Kernel Team
   5        Written/copyright 1994-2001 by Donald Becker.
   6
   7        This software may be used and distributed according to the terms
   8        of the GNU General Public License, incorporated herein by reference.
   9
  10        Please refer to Documentation/DocBook/tulip.{pdf,ps,html}
  11        for more information on this driver, or visit the project
  12        Web page at http://sourceforge.net/projects/tulip/
  13
  14*/
  15
  16#ifndef __NET_TULIP_H__
  17#define __NET_TULIP_H__
  18
  19#include <linux/config.h>
  20#include <linux/kernel.h>
  21#include <linux/types.h>
  22#include <linux/spinlock.h>
  23#include <linux/netdevice.h>
  24#include <linux/timer.h>
  25#include <linux/delay.h>
  26#include <asm/io.h>
  27#include <asm/irq.h>
  28
  29
  30
  31/* undefine, or define to various debugging levels (>4 == obscene levels) */
  32#define TULIP_DEBUG 1
  33
  34/* undefine USE_IO_OPS for MMIO, define for PIO */
  35#ifdef CONFIG_TULIP_MMIO
  36# undef USE_IO_OPS
  37#else
  38# define USE_IO_OPS 1
  39#endif
  40
  41
  42
  43struct tulip_chip_table {
  44        char *chip_name;
  45        int io_size;
  46        int valid_intrs;        /* CSR7 interrupt enable settings */
  47        int flags;
  48        void (*media_timer) (unsigned long data);
  49};
  50
  51
  52enum tbl_flag {
  53        HAS_MII                 = 0x0001,
  54        HAS_MEDIA_TABLE         = 0x0002,
  55        CSR12_IN_SROM           = 0x0004,
  56        ALWAYS_CHECK_MII        = 0x0008,
  57        HAS_ACPI                = 0x0010,
  58        MC_HASH_ONLY            = 0x0020, /* Hash-only multicast filter. */
  59        HAS_PNICNWAY            = 0x0080,
  60        HAS_NWAY                = 0x0040, /* Uses internal NWay xcvr. */
  61        HAS_INTR_MITIGATION     = 0x0100,
  62        IS_ASIX                 = 0x0200,
  63        HAS_8023X               = 0x0400,
  64        COMET_MAC_ADDR          = 0x0800,
  65        HAS_PCI_MWI             = 0x1000,
  66        HAS_PHY_IRQ             = 0x2000,
  67};
  68
  69
  70/* chip types.  careful!  order is VERY IMPORTANT here, as these
  71 * are used throughout the driver as indices into arrays */
  72/* Note 21142 == 21143. */
  73enum chips {
  74        DC21040 = 0,
  75        DC21041 = 1,
  76        DC21140 = 2,
  77        DC21142 = 3, DC21143 = 3,
  78        LC82C168,
  79        MX98713,
  80        MX98715,
  81        MX98725,
  82        AX88140,
  83        PNIC2,
  84        COMET,
  85        COMPEX9881,
  86        I21145,
  87        DM910X,
  88        CONEXANT,
  89};
  90
  91
  92enum MediaIs {
  93        MediaIsFD = 1,
  94        MediaAlwaysFD = 2,
  95        MediaIsMII = 4,
  96        MediaIsFx = 8,
  97        MediaIs100 = 16
  98};
  99
 100
 101/* Offsets to the Command and Status Registers, "CSRs".  All accesses
 102   must be longword instructions and quadword aligned. */
 103enum tulip_offsets {
 104        CSR0 = 0,
 105        CSR1 = 0x08,
 106        CSR2 = 0x10,
 107        CSR3 = 0x18,
 108        CSR4 = 0x20,
 109        CSR5 = 0x28,
 110        CSR6 = 0x30,
 111        CSR7 = 0x38,
 112        CSR8 = 0x40,
 113        CSR9 = 0x48,
 114        CSR10 = 0x50,
 115        CSR11 = 0x58,
 116        CSR12 = 0x60,
 117        CSR13 = 0x68,
 118        CSR14 = 0x70,
 119        CSR15 = 0x78,
 120};
 121
 122/* register offset and bits for CFDD PCI config reg */
 123enum pci_cfg_driver_reg {
 124        CFDD = 0x40,
 125        CFDD_Sleep = (1 << 31),
 126        CFDD_Snooze = (1 << 30),
 127};
 128
 129
 130/* The bits in the CSR5 status registers, mostly interrupt sources. */
 131enum status_bits {
 132        TimerInt = 0x800,
 133        SytemError = 0x2000,
 134        TPLnkFail = 0x1000,
 135        TPLnkPass = 0x10,
 136        NormalIntr = 0x10000,
 137        AbnormalIntr = 0x8000,
 138        RxJabber = 0x200,
 139        RxDied = 0x100,
 140        RxNoBuf = 0x80,
 141        RxIntr = 0x40,
 142        TxFIFOUnderflow = 0x20,
 143        TxJabber = 0x08,
 144        TxNoBuf = 0x04,
 145        TxDied = 0x02,
 146        TxIntr = 0x01,
 147};
 148
 149
 150enum tulip_mode_bits {
 151        TxThreshold             = (1 << 22),
 152        FullDuplex              = (1 << 9),
 153        TxOn                    = 0x2000,
 154        AcceptBroadcast         = 0x0100,
 155        AcceptAllMulticast      = 0x0080,
 156        AcceptAllPhys           = 0x0040,
 157        AcceptRunt              = 0x0008,
 158        RxOn                    = 0x0002,
 159        RxTx                    = (TxOn | RxOn),
 160};
 161
 162
 163enum tulip_busconfig_bits {
 164        MWI                     = (1 << 24),
 165        MRL                     = (1 << 23),
 166        MRM                     = (1 << 21),
 167        CALShift                = 14,
 168        BurstLenShift           = 8,
 169};
 170
 171
 172/* The Tulip Rx and Tx buffer descriptors. */
 173struct tulip_rx_desc {
 174        s32 status;
 175        s32 length;
 176        u32 buffer1;
 177        u32 buffer2;
 178};
 179
 180
 181struct tulip_tx_desc {
 182        s32 status;
 183        s32 length;
 184        u32 buffer1;
 185        u32 buffer2;            /* We use only buffer 1.  */
 186};
 187
 188
 189enum desc_status_bits {
 190        DescOwned = 0x80000000,
 191        RxDescFatalErr = 0x8000,
 192        RxWholePkt = 0x0300,
 193};
 194
 195
 196enum t21143_csr6_bits {
 197        csr6_sc = (1<<31),
 198        csr6_ra = (1<<30),
 199        csr6_ign_dest_msb = (1<<26),
 200        csr6_mbo = (1<<25),
 201        csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
 202        csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
 203        csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
 204        csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
 205        csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
 206        csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
 207        csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
 208        csr6_trh = (1<<15),  /* Transmit Threshold high bit */
 209        csr6_trl = (1<<14),  /* Transmit Threshold low bit */
 210
 211        /***************************************************************
 212         * This table shows transmit threshold values based on media   *
 213         * and these two registers (from PNIC1 & 2 docs) Note: this is *
 214         * all meaningless if sf is set.                               *
 215         ***************************************************************/
 216
 217        /***********************************
 218         * (trh,trl) * 100BaseTX * 10BaseT *
 219         ***********************************
 220         *   (0,0)   *     128   *    72   *
 221         *   (0,1)   *     256   *    96   *
 222         *   (1,0)   *     512   *   128   *
 223         *   (1,1)   *    1024   *   160   *
 224         ***********************************/
 225
 226        csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
 227        csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
 228        csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
 229        /* set both and you get (PHY) loopback */
 230        csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
 231        csr6_pm = (1<<7),    /* Pass All Multicast */
 232        csr6_pr = (1<<6),    /* Promiscuous mode */
 233        csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
 234        csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
 235        csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
 236        csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
 237        csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
 238
 239        csr6_mask_capture = (csr6_sc | csr6_ca),
 240        csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
 241        csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
 242        csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
 243        csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
 244        csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
 245        csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
 246        csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
 247};
 248
 249
 250/* Keep the ring sizes a power of two for efficiency.
 251   Making the Tx ring too large decreases the effectiveness of channel
 252   bonding and packet priority.
 253   There are no ill effects from too-large receive rings. */
 254#define TX_RING_SIZE    16
 255#define RX_RING_SIZE    32
 256
 257#define MEDIA_MASK     31
 258
 259#define PKT_BUF_SZ              1536    /* Size of each temporary Rx buffer. */
 260
 261#define TULIP_MIN_CACHE_LINE    8       /* in units of 32-bit words */
 262
 263#if defined(__sparc__) || defined(__hppa__)
 264/* The UltraSparc PCI controllers will disconnect at every 64-byte
 265 * crossing anyways so it makes no sense to tell Tulip to burst
 266 * any more than that.
 267 */
 268#define TULIP_MAX_CACHE_LINE    16      /* in units of 32-bit words */
 269#else
 270#define TULIP_MAX_CACHE_LINE    32      /* in units of 32-bit words */
 271#endif
 272
 273
 274/* Ring-wrap flag in length field, use for last ring entry.
 275        0x01000000 means chain on buffer2 address,
 276        0x02000000 means use the ring start address in CSR2/3.
 277   Note: Some work-alike chips do not function correctly in chained mode.
 278   The ASIX chip works only in chained mode.
 279   Thus we indicates ring mode, but always write the 'next' field for
 280   chained mode as well.
 281*/
 282#define DESC_RING_WRAP 0x02000000
 283
 284
 285#define EEPROM_SIZE 512         /* 2 << EEPROM_ADDRLEN */
 286
 287
 288#define RUN_AT(x) (jiffies + (x))
 289
 290#if defined(__i386__)                   /* AKA get_unaligned() */
 291#define get_u16(ptr) (*(u16 *)(ptr))
 292#else
 293#define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
 294#endif
 295
 296struct medialeaf {
 297        u8 type;
 298        u8 media;
 299        unsigned char *leafdata;
 300};
 301
 302
 303struct mediatable {
 304        u16 defaultmedia;
 305        u8 leafcount;
 306        u8 csr12dir;            /* General purpose pin directions. */
 307        unsigned has_mii:1;
 308        unsigned has_nonmii:1;
 309        unsigned has_reset:6;
 310        u32 csr15dir;
 311        u32 csr15val;           /* 21143 NWay setting. */
 312        struct medialeaf mleaf[0];
 313};
 314
 315
 316struct mediainfo {
 317        struct mediainfo *next;
 318        int info_type;
 319        int index;
 320        unsigned char *info;
 321};
 322
 323struct ring_info {
 324        struct sk_buff  *skb;
 325        dma_addr_t      mapping;
 326};
 327
 328
 329struct tulip_private {
 330        const char *product_name;
 331        struct net_device *next_module;
 332        struct tulip_rx_desc *rx_ring;
 333        struct tulip_tx_desc *tx_ring;
 334        dma_addr_t rx_ring_dma;
 335        dma_addr_t tx_ring_dma;
 336        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 337        struct ring_info tx_buffers[TX_RING_SIZE];
 338        /* The addresses of receive-in-place skbuffs. */
 339        struct ring_info rx_buffers[RX_RING_SIZE];
 340        u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
 341        int chip_id;
 342        int revision;
 343        int flags;
 344        struct net_device_stats stats;
 345        struct timer_list timer;        /* Media selection timer. */
 346        u32 mc_filter[2];
 347        spinlock_t lock;
 348        spinlock_t mii_lock;
 349        unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 350        unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 351
 352#ifdef CONFIG_NET_HW_FLOWCONTROL
 353#define RX_A_NBF_STOP 0xffffff3f /* To disable RX and RX-NOBUF ints. */
 354        int fc_bit;
 355        int mit_sel;
 356        int mit_change; /* Signal for Interrupt Mitigtion */
 357#endif
 358        unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 359        unsigned int full_duplex_lock:1;
 360        unsigned int fake_addr:1;       /* Multiport board faked address. */
 361        unsigned int default_port:4;    /* Last dev->if_port value. */
 362        unsigned int media2:4;  /* Secondary monitored media port. */
 363        unsigned int medialock:1;       /* Don't sense media type. */
 364        unsigned int mediasense:1;      /* Media sensing in progress. */
 365        unsigned int nway:1, nwayset:1;         /* 21143 internal NWay. */
 366        unsigned int csr0;      /* CSR0 setting. */
 367        unsigned int csr6;      /* Current CSR6 control settings. */
 368        unsigned char eeprom[EEPROM_SIZE];      /* Serial EEPROM contents. */
 369        void (*link_change) (struct net_device * dev, int csr5);
 370        u16 sym_advertise, mii_advertise; /* NWay capabilities advertised.  */
 371        u16 lpar;               /* 21143 Link partner ability. */
 372        u16 advertising[4];
 373        signed char phys[4], mii_cnt;   /* MII device addresses. */
 374        struct mediatable *mtable;
 375        int cur_index;          /* Current media index. */
 376        int saved_if_port;
 377        struct pci_dev *pdev;
 378        int ttimer;
 379        int susp_rx;
 380        unsigned long nir;
 381        unsigned long base_addr;
 382        int csr12_shadow;
 383        int pad0;               /* Used for 8-byte alignment */
 384};
 385
 386
 387struct eeprom_fixup {
 388        char *name;
 389        unsigned char addr0;
 390        unsigned char addr1;
 391        unsigned char addr2;
 392        u16 newtable[32];       /* Max length below. */
 393};
 394
 395
 396/* 21142.c */
 397extern u16 t21142_csr14[];
 398void t21142_timer(unsigned long data);
 399void t21142_start_nway(struct net_device *dev);
 400void t21142_lnk_change(struct net_device *dev, int csr5);
 401
 402
 403/* PNIC2.c */
 404void pnic2_lnk_change(struct net_device *dev, int csr5);
 405void pnic2_timer(unsigned long data);
 406void pnic2_start_nway(struct net_device *dev);
 407void pnic2_lnk_change(struct net_device *dev, int csr5);
 408
 409/* eeprom.c */
 410void tulip_parse_eeprom(struct net_device *dev);
 411int tulip_read_eeprom(long ioaddr, int location, int addr_len);
 412
 413/* interrupt.c */
 414extern unsigned int tulip_max_interrupt_work;
 415extern int tulip_rx_copybreak;
 416irqreturn_t tulip_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
 417int tulip_refill_rx(struct net_device *dev);
 418
 419/* media.c */
 420int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
 421void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
 422void tulip_select_media(struct net_device *dev, int startup);
 423int tulip_check_duplex(struct net_device *dev);
 424void tulip_find_mii (struct net_device *dev, int board_idx);
 425
 426/* pnic.c */
 427void pnic_do_nway(struct net_device *dev);
 428void pnic_lnk_change(struct net_device *dev, int csr5);
 429void pnic_timer(unsigned long data);
 430
 431/* timer.c */
 432void tulip_timer(unsigned long data);
 433void mxic_timer(unsigned long data);
 434void comet_timer(unsigned long data);
 435
 436/* tulip_core.c */
 437extern int tulip_debug;
 438extern const char * const medianame[];
 439extern const char tulip_media_cap[];
 440extern struct tulip_chip_table tulip_tbl[];
 441extern u8 t21040_csr13[];
 442
 443#ifndef USE_IO_OPS
 444#undef inb
 445#undef inw
 446#undef inl
 447#undef outb
 448#undef outw
 449#undef outl
 450#define inb(addr) readb((void*)(addr))
 451#define inw(addr) readw((void*)(addr))
 452#define inl(addr) readl((void*)(addr))
 453#define outb(val,addr) writeb((val), (void*)(addr))
 454#define outw(val,addr) writew((val), (void*)(addr))
 455#define outl(val,addr) writel((val), (void*)(addr))
 456#endif /* !USE_IO_OPS */
 457
 458
 459
 460static inline void tulip_start_rxtx(struct tulip_private *tp)
 461{
 462        long ioaddr = tp->base_addr;
 463        outl(tp->csr6 | RxTx, ioaddr + CSR6);
 464        barrier();
 465        (void) inl(ioaddr + CSR6); /* mmio sync */
 466}
 467
 468static inline void tulip_stop_rxtx(struct tulip_private *tp)
 469{
 470        long ioaddr = tp->base_addr;
 471        u32 csr6 = inl(ioaddr + CSR6);
 472
 473        if (csr6 & RxTx) {
 474                outl(csr6 & ~RxTx, ioaddr + CSR6);
 475                barrier();
 476                (void) inl(ioaddr + CSR6); /* mmio sync */
 477        }
 478}
 479
 480static inline void tulip_restart_rxtx(struct tulip_private *tp)
 481{
 482        tulip_stop_rxtx(tp);
 483        udelay(5);
 484        tulip_start_rxtx(tp);
 485}
 486
 487#endif /* __NET_TULIP_H__ */
 488