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133#ifndef __INC_SKDRV2ND_H
134#define __INC_SKDRV2ND_H
135
136#include "h/skqueue.h"
137#include "h/skgehwt.h"
138#include "h/sktimer.h"
139#include "h/ski2c.h"
140#include "h/skgepnmi.h"
141#include "h/skvpd.h"
142#include "h/skgehw.h"
143#include "h/skgeinit.h"
144#include "h/skaddr.h"
145#include "h/skgesirq.h"
146#include "h/skcsum.h"
147#include "h/skrlmt.h"
148#include "h/skgedrv.h"
149
150#define SK_PCI_ISCOMPLIANT(result, pdev) { \
151 result = SK_FALSE; \
152 \
153 if (pdev->vendor == 0x10b7) { \
154 \
155 if ((pdev->device == 0x1700)) { \
156 result = SK_TRUE; \
157 } \
158 \
159 } else if (pdev->vendor == 0x1148) { \
160 \
161 \
162 if ((pdev->device == 0x4300) || \
163 (pdev->device == 0x4320)) { \
164 result = SK_TRUE; \
165 } \
166 \
167 } else if (pdev->vendor == 0x1186) { \
168 \
169 if ((pdev->device == 0x4c00)) { \
170 result = SK_TRUE; \
171 } \
172 \
173 } else if (pdev->vendor == 0x11ab) { \
174 \
175 if ((pdev->device == 0x4320)) { \
176 result = SK_TRUE; \
177 } \
178 \
179 } else if (pdev->vendor == 0x1371) { \
180 \
181 if ((pdev->device == 0x434e)) { \
182 result = SK_TRUE; \
183 } \
184 \
185 } else if (pdev->vendor == 0x1737) { \
186 \
187 \
188 if ((pdev->device == 0x1032) || \
189 (pdev->device == 0x1064)) { \
190 result = SK_TRUE; \
191 } \
192 } else { \
193 result = SK_FALSE; \
194 } \
195}
196
197
198extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
199extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
200extern SK_U64 SkOsGetTime(SK_AC*);
201extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
202extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
203extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
204extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
205extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
206extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
207extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
208
209struct s_DrvRlmtMbuf {
210 SK_MBUF *pNext;
211 SK_U8 *pData;
212 unsigned Size;
213 unsigned Length;
214 SK_U32 PortIdx;
215#ifdef SK_RLMT_MBUF_PRIVATE
216 SK_RLMT_MBUF Rlmt;
217#endif
218 struct sk_buff *pOs;
219};
220
221
222
223
224
225#if SK_TICKS_PER_SEC == 100
226#define SK_PNMI_HUNDREDS_SEC(t) (t)
227#else
228#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t) * 100) / \
229 (SK_TICKS_PER_SEC))
230#endif
231
232
233
234
235#define SkOsGetTimeCurrent(pAC, pUsec) {\
236 struct timeval t;\
237 do_gettimeofday(&t);\
238 *pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\
239}
240
241
242
243
244
245#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
246#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
247#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
248#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
249#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
250
251typedef struct s_IOCTL SK_GE_IOCTL;
252
253struct s_IOCTL {
254 char* pData;
255 unsigned int Len;
256};
257
258
259
260
261
262
263#define TX_RING_SIZE (8*1024)
264#define RX_RING_SIZE (24*1024)
265
266
267
268
269#define ETH_BUF_SIZE 1540
270#define ETH_MAX_MTU 1514
271#define ETH_MIN_MTU 60
272#define ETH_MULTICAST_BIT 0x01
273#define SK_JUMBO_MTU 9000
274
275
276
277
278#define TX_PRIO_LOW 0
279#define TX_PRIO_HIGH 1
280
281
282
283
284#define DESCR_ALIGN 64
285
286
287
288
289#define SK_DRIVER_RESET(pAC, IoC) 0
290#define SK_DRIVER_SENDEVENT(pAC, IoC) 0
291#define SK_DRIVER_SELFTEST(pAC, IoC) 0
292
293#define SK_DRIVER_GET_MTU(pAc,IoC,i) 0
294#define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0
295#define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0
296
297
298
299
300
301#define SK_DRV_TIMER 11
302#define SK_DRV_MODERATION_TIMER 1
303#define SK_DRV_MODERATION_TIMER_LENGTH 1000000
304#define SK_DRV_RX_CLEANUP_TIMER 2
305#define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000
306
307
308
309
310
311#define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6
312#define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6
313#define C_LEN_ETHERMAC_HEADER_LENTYPE 2
314#define C_LEN_ETHERMAC_HEADER ( (C_LEN_ETHERMAC_HEADER_DEST_ADDR) + \
315 (C_LEN_ETHERMAC_HEADER_SRC_ADDR) + \
316 (C_LEN_ETHERMAC_HEADER_LENTYPE) )
317
318#define C_LEN_ETHERMTU_MINSIZE 46
319#define C_LEN_ETHERMTU_MAXSIZE_STD 1500
320#define C_LEN_ETHERMTU_MAXSIZE_JUMBO 9000
321
322#define C_LEN_ETHERNET_MINSIZE ( (C_LEN_ETHERMAC_HEADER) + \
323 (C_LEN_ETHERMTU_MINSIZE) )
324
325#define C_OFFSET_IPHEADER C_LEN_ETHERMAC_HEADER
326#define C_OFFSET_IPHEADER_IPPROTO 9
327#define C_OFFSET_TCPHEADER_TCPCS 16
328#define C_OFFSET_UDPHEADER_UDPCS 6
329
330#define C_OFFSET_IPPROTO ( (C_LEN_ETHERMAC_HEADER) + \
331 (C_OFFSET_IPHEADER_IPPROTO) )
332
333#define C_PROTO_ID_UDP 17
334#define C_PROTO_ID_TCP 6
335
336
337
338typedef struct s_RxD RXD;
339
340struct s_RxD {
341 volatile SK_U32 RBControl;
342 SK_U32 VNextRxd;
343 SK_U32 VDataLow;
344 SK_U32 VDataHigh;
345 SK_U32 FrameStat;
346 SK_U32 TimeStamp;
347 SK_U32 TcpSums;
348 SK_U32 TcpSumStarts;
349 RXD *pNextRxd;
350 struct sk_buff *pMBuf;
351};
352
353typedef struct s_TxD TXD;
354
355struct s_TxD {
356 volatile SK_U32 TBControl;
357 SK_U32 VNextTxd;
358 SK_U32 VDataLow;
359 SK_U32 VDataHigh;
360 SK_U32 FrameStat;
361 SK_U32 TcpSumOfs;
362 SK_U16 TcpSumSt;
363 SK_U16 TcpSumWr;
364 SK_U32 TcpReserved;
365 TXD *pNextTxd;
366 struct sk_buff *pMBuf;
367};
368
369
370
371#define DRIVER_IRQS ((IS_IRQ_SW) | \
372 (IS_R1_F) |(IS_R2_F) | \
373 (IS_XS1_F) |(IS_XA1_F) | \
374 (IS_XS2_F) |(IS_XA2_F))
375
376#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
377 (IS_EXT_REG) |(IS_TIMINT) | \
378 (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
379 (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
380 (IS_MAC1) |(IS_LNK_SYNC_M1)| \
381 (IS_MAC2) |(IS_LNK_SYNC_M2)| \
382 (IS_R1_C) |(IS_R2_C) | \
383 (IS_XS1_C) |(IS_XA1_C) | \
384 (IS_XS2_C) |(IS_XA2_C))
385
386#define IRQ_MASK ((IS_IRQ_SW) | \
387 (IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \
388 (IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \
389 (IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \
390 (IS_HW_ERR) |(IS_I2C_READY)| \
391 (IS_EXT_REG) |(IS_TIMINT) | \
392 (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
393 (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
394 (IS_MAC1) |(IS_MAC2) | \
395 (IS_R1_C) |(IS_R2_C) | \
396 (IS_XS1_C) |(IS_XA1_C) | \
397 (IS_XS2_C) |(IS_XA2_C))
398
399#define IRQ_HWE_MASK (IS_ERR_MSK)
400
401typedef struct s_DevNet DEV_NET;
402
403struct s_DevNet {
404 struct proc_dir_entry *proc;
405 int PortNr;
406 int NetNr;
407 int Mtu;
408 int Up;
409 SK_AC *pAC;
410};
411
412typedef struct s_TxPort TX_PORT;
413
414struct s_TxPort {
415
416 caddr_t pTxDescrRing;
417 SK_U64 VTxDescrRing;
418 TXD *pTxdRingHead;
419 TXD *pTxdRingTail;
420 TXD *pTxdRingPrev;
421 int TxdRingFree;
422 spinlock_t TxDesRingLock;
423 caddr_t HwAddr;
424 int PortIndex;
425};
426
427typedef struct s_RxPort RX_PORT;
428
429struct s_RxPort {
430
431 caddr_t pRxDescrRing;
432 SK_U64 VRxDescrRing;
433 RXD *pRxdRingHead;
434 RXD *pRxdRingTail;
435 RXD *pRxdRingPrev;
436 int RxdRingFree;
437 spinlock_t RxDesRingLock;
438 int RxFillLimit;
439 caddr_t HwAddr;
440 int PortIndex;
441};
442
443
444
445#define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F))
446#define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F))
447#define IRQ_MASK_TX_ONLY ((IRQ_EOF_AS_TX)| (IRQ_EOF_SY_TX))
448#define IRQ_MASK_RX_ONLY ((IS_R1_F) | (IS_R2_F))
449#define IRQ_MASK_SP_ONLY (SPECIAL_IRQS)
450#define IRQ_MASK_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
451#define IRQ_MASK_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY))
452#define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
453#define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
454
455#define C_INT_MOD_NONE 1
456#define C_INT_MOD_STATIC 2
457#define C_INT_MOD_DYNAMIC 4
458
459#define C_CLK_FREQ_GENESIS 53215000
460#define C_CLK_FREQ_YUKON 78215000
461
462#define C_INTS_PER_SEC_DEFAULT 2000
463#define C_INT_MOD_ENABLE_PERCENTAGE 50
464#define C_INT_MOD_DISABLE_PERCENTAGE 50
465
466typedef struct s_DynIrqModInfo DIM_INFO;
467struct s_DynIrqModInfo {
468 unsigned long PrevTimeVal;
469 unsigned int PrevSysLoad;
470 unsigned int PrevUsedTime;
471 unsigned int PrevTotalTime;
472 int PrevUsedDescrRatio;
473 int NbrProcessedDescr;
474 SK_U64 PrevPort0RxIntrCts;
475 SK_U64 PrevPort1RxIntrCts;
476 SK_U64 PrevPort0TxIntrCts;
477 SK_U64 PrevPort1TxIntrCts;
478 SK_BOOL ModJustEnabled;
479
480 int MaxModIntsPerSec;
481 int MaxModIntsPerSecUpperLimit;
482 int MaxModIntsPerSecLowerLimit;
483
484 long MaskIrqModeration;
485 SK_BOOL DisplayStats;
486 SK_BOOL AutoSizing;
487 int IntModTypeSelect;
488
489 SK_TIMER ModTimer;
490};
491
492typedef struct s_PerStrm PER_STRM;
493
494#define SK_ALLOC_IRQ 0x00000001
495
496
497
498
499
500
501struct s_AC {
502 SK_GEINIT GIni;
503 SK_PNMI Pnmi;
504 SK_VPD vpd;
505 SK_QUEUE Event;
506 SK_HWT Hwt;
507 SK_TIMCTRL Tim;
508 SK_I2C I2c;
509 SK_ADDR Addr;
510 SK_CSUM Csum;
511 SK_RLMT Rlmt;
512 spinlock_t SlowPathLock;
513 SK_PNMI_STRUCT_DATA PnmiStruct;
514 int RlmtMode;
515 int RlmtNets;
516
517 SK_IOC IoBase;
518 int BoardLevel;
519 char DeviceStr[80];
520 SK_U32 AllocFlag;
521 struct pci_dev *PciDev;
522 SK_U32 PciDevId;
523 struct SK_NET_DEVICE *dev[2];
524 char Name[30];
525 struct SK_NET_DEVICE *Next;
526 int RxBufSize;
527 struct net_device_stats stats;
528 int Index;
529
530
531 int RxQueueSize;
532 int TxSQueueSize;
533 int TxAQueueSize;
534
535 int PromiscCount;
536 int AllMultiCount;
537 int MulticCount;
538
539
540
541 int HWRevision;
542 int ActivePort;
543 int MaxPorts;
544 int TxDescrPerRing;
545 int RxDescrPerRing;
546
547 caddr_t pDescrMem;
548 dma_addr_t pDescrMemDMA;
549
550
551 TX_PORT TxPort[SK_MAX_MACS][2];
552 RX_PORT RxPort[SK_MAX_MACS];
553
554 unsigned int CsOfs1;
555 unsigned int CsOfs2;
556 SK_U32 CsOfs;
557
558 SK_BOOL CheckQueue;
559 SK_TIMER DrvCleanupTimer;
560 DIM_INFO DynIrqModInfo;
561
562
563 int PortUp;
564 int PortDown;
565 int ChipsetType;
566
567
568
569};
570
571
572#endif
573
574