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27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/delay.h>
32#include <linux/crc32.h>
33#include <linux/init.h>
34
35#include <asm/io.h>
36
37#define SiS190_VERSION "1.1"
38#define MODULENAME "SiS190"
39#define SiS190_DRIVER_NAME MODULENAME " Gigabit Ethernet driver " SiS190_VERSION
40#define PFX MODULENAME ": "
41
42#ifdef SiS190_DEBUG
43#define assert(expr) \
44 if(unlikely(!(expr))) { \
45 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
46 #expr,__FILE__,__FUNCTION__,__LINE__); \
47 }
48#else
49#define assert(expr) do {} while (0)
50#endif
51
52
53#define MAX_UNITS 8
54
55
56static int max_interrupt_work = 20;
57
58
59
60static int multicast_filter_limit = 32;
61
62
63#define MAC_ADDR_LEN 6
64
65
66#define MAX_ETH_FRAME_SIZE 1536
67
68#define TX_FIFO_THRESH 256
69
70#define RX_FIFO_THRESH 7
71#define RX_DMA_BURST 6
72#define TX_DMA_BURST 6
73#define EarlyTxThld 0x3F
74#define RxPacketMaxSize 0x0800
75#define InterFrameGap 0x03
76
77#define NUM_TX_DESC 64
78#define NUM_RX_DESC 64
79#define TX_DESC_TOTAL_SIZE (NUM_TX_DESC * sizeof (struct TxDesc))
80#define RX_DESC_TOTAL_SIZE (NUM_RX_DESC * sizeof (struct RxDesc))
81#define RX_BUF_SIZE 1536
82
83#define SiS190_MIN_IO_SIZE 0x80
84#define TX_TIMEOUT (6*HZ)
85
86
87#define EhnMIIread 0x0000
88#define EhnMIIwrite 0x0020
89#define EhnMIIdataShift 16
90#define EhnMIIpmdShift 6
91#define EhnMIIregShift 11
92#define EhnMIIreq 0x0010
93#define EhnMIInotDone 0x0010
94
95
96
97
98#define BIT_0 0x0001
99#define BIT_1 0x0002
100#define BIT_2 0x0004
101#define BIT_3 0x0008
102#define BIT_4 0x0010
103#define BIT_5 0x0020
104#define BIT_6 0x0040
105#define BIT_7 0x0080
106#define BIT_8 0x0100
107#define BIT_9 0x0200
108#define BIT_10 0x0400
109#define BIT_11 0x0800
110#define BIT_12 0x1000
111#define BIT_13 0x2000
112#define BIT_14 0x4000
113#define BIT_15 0x8000
114#define BIT_16 0x10000
115#define BIT_17 0x20000
116#define BIT_18 0x40000
117#define BIT_19 0x80000
118#define BIT_20 0x100000
119#define BIT_21 0x200000
120#define BIT_22 0x400000
121#define BIT_23 0x800000
122#define BIT_24 0x1000000
123#define BIT_25 0x2000000
124#define BIT_26 0x04000000
125#define BIT_27 0x08000000
126#define BIT_28 0x10000000
127#define BIT_29 0x20000000
128#define BIT_30 0x40000000
129#define BIT_31 0x80000000
130
131
132#define SiS_W8(reg, val8) writeb ((val8), ioaddr + (reg))
133#define SiS_W16(reg, val16) writew ((val16), ioaddr + (reg))
134#define SiS_W32(reg, val32) writel ((val32), ioaddr + (reg))
135#define SiS_R8(reg) readb (ioaddr + (reg))
136#define SiS_R16(reg) readw (ioaddr + (reg))
137#define SiS_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
138
139static struct {
140 const char *name;
141} board_info[] __devinitdata = {
142 { "SiS190 Gigabit Ethernet" },
143};
144
145static struct pci_device_id sis190_pci_tbl[] __devinitdata = {
146 { 0x1039, 0x0190, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { 0,},
148};
149
150MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
151
152enum SiS190_registers {
153 TxControl = 0x0,
154 TxDescStartAddr = 0x4,
155 TxNextDescAddr = 0x0c,
156 RxControl = 0x10,
157 RxDescStartAddr = 0x14,
158 RxNextDescAddr = 0x1c,
159 IntrStatus = 0x20,
160 IntrMask = 0x24,
161 IntrControl = 0x28,
162 IntrTimer = 0x2c,
163 PMControl = 0x30,
164 ROMControl = 0x38,
165 ROMInterface = 0x3c,
166 StationControl = 0x40,
167 GMIIControl = 0x44,
168 TxMacControl = 0x50,
169 RxMacControl = 0x60,
170 RxMacAddr = 0x62,
171 RxHashTable = 0x68,
172 RxWakeOnLan = 0x70,
173 RxMPSControl = 0x78,
174};
175
176enum sis190_register_content {
177
178
179 SoftInt = 0x40000000,
180 Timeup = 0x20000000,
181 PauseFrame = 0x80000,
182 MagicPacket = 0x40000,
183 WakeupFrame = 0x20000,
184 LinkChange = 0x10000,
185 RxQEmpty = 0x80,
186 RxQInt = 0x40,
187 TxQ1Empty = 0x20,
188 TxQ1Int = 0x10,
189 TxQ0Empty = 0x08,
190 TxQ0Int = 0x04,
191 RxHalt = 0x02,
192 TxHalt = 0x01,
193
194
195 RxRES = 0x00200000,
196 RxCRC = 0x00080000,
197 RxRUNT = 0x00100000,
198 RxRWT = 0x00400000,
199
200
201 CmdReset = 0x10,
202 CmdRxEnb = 0x08,
203 CmdTxEnb = 0x01,
204 RxBufEmpty = 0x01,
205
206
207 Cfg9346_Lock = 0x00,
208 Cfg9346_Unlock = 0xC0,
209
210
211 AcceptErr = 0x20,
212 AcceptRunt = 0x10,
213 AcceptBroadcast = 0x0800,
214 AcceptMulticast = 0x0400,
215 AcceptMyPhys = 0x0200,
216 AcceptAllPhys = 0x0100,
217
218
219 RxCfgFIFOShift = 13,
220 RxCfgDMAShift = 8,
221
222
223 TxInterFrameGapShift = 24,
224 TxDMAShift = 8,
225
226
227 TBI_Enable = 0x80,
228 TxFlowCtrl = 0x40,
229 RxFlowCtrl = 0x20,
230
231 _1000bpsF = 0x1c,
232 _1000bpsH = 0x0c,
233 _100bpsF = 0x18,
234 _100bpsH = 0x08,
235 _10bpsF = 0x14,
236 _10bpsH = 0x04,
237
238 LinkStatus = 0x02,
239 FullDup = 0x01,
240
241
242 PHY_CTRL_REG = 0,
243 PHY_STAT_REG = 1,
244 PHY_AUTO_NEGO_REG = 4,
245 PHY_1000_CTRL_REG = 9,
246
247
248 PHY_Restart_Auto_Nego = 0x0200,
249 PHY_Enable_Auto_Nego = 0x1000,
250
251
252 PHY_Auto_Neco_Comp = 0x0020,
253
254
255 PHY_Cap_10_Half = 0x0020,
256 PHY_Cap_10_Full = 0x0040,
257 PHY_Cap_100_Half = 0x0080,
258 PHY_Cap_100_Full = 0x0100,
259
260
261 PHY_Cap_1000_Full = 0x0200,
262
263 PHY_Cap_Null = 0x0,
264
265
266 _10_Half = 0x01,
267 _10_Full = 0x02,
268 _100_Half = 0x04,
269 _100_Full = 0x08,
270 _1000_Full = 0x10,
271
272
273 TBILinkOK = 0x02000000,
274};
275
276const static struct {
277 const char *name;
278 u8 version;
279 u32 RxConfigMask;
280} sis_chip_info[] = {
281 { "SiS-0190", 0x00, 0xff7e1880,},
282};
283
284enum _DescStatusBit {
285 OWNbit = 0x80000000,
286 INTbit = 0x40000000,
287 DEFbit = 0x200000,
288 CRCbit = 0x20000,
289 PADbit = 0x10000,
290 ENDbit = 0x80000000,
291};
292
293struct TxDesc {
294 u32 PSize;
295 u32 status;
296 u32 buf_addr;
297 u32 buf_Len;
298};
299
300struct RxDesc {
301 u32 PSize;
302 u32 status;
303 u32 buf_addr;
304 u32 buf_Len;
305};
306
307struct sis190_private {
308 void *mmio_addr;
309 struct pci_dev *pci_dev;
310 struct net_device_stats stats;
311 spinlock_t lock;
312 int chipset;
313 unsigned long cur_rx;
314 unsigned long cur_tx;
315 unsigned long dirty_tx;
316 dma_addr_t tx_dma;
317 dma_addr_t rx_dma;
318 struct TxDesc *TxDescArray;
319 struct RxDesc *RxDescArray;
320 unsigned char *RxBufferRings;
321 unsigned char *RxBufferRing[NUM_RX_DESC];
322 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
323};
324
325MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>");
326MODULE_DESCRIPTION("SiS SiS190 Gigabit Ethernet driver");
327MODULE_LICENSE("GPL");
328MODULE_PARM(media, "1-" __MODULE_STRING(MAX_UNITS) "i");
329
330static int SiS190_open(struct net_device *dev);
331static int SiS190_start_xmit(struct sk_buff *skb, struct net_device *dev);
332static irqreturn_t SiS190_interrupt(int irq, void *dev_instance,
333 struct pt_regs *regs);
334static void SiS190_init_ring(struct net_device *dev);
335static void SiS190_hw_start(struct net_device *dev);
336static int SiS190_close(struct net_device *dev);
337static void SiS190_set_rx_mode(struct net_device *dev);
338static void SiS190_tx_timeout(struct net_device *dev);
339static struct net_device_stats *SiS190_get_stats(struct net_device *netdev);
340
341static const u32 sis190_intr_mask =
342 RxQEmpty | RxQInt | TxQ1Empty | TxQ1Int | TxQ0Empty | TxQ0Int | RxHalt |
343 TxHalt;
344
345void
346smdio_write(void *ioaddr, int RegAddr, int value)
347{
348
349 u32 l;
350 u16 i;
351 u32 pmd;
352
353 pmd = 1;
354
355 l = 0;
356 l = EhnMIIwrite | (((u32) RegAddr) << EhnMIIregShift) | EhnMIIreq |
357 (((u32) value) << EhnMIIdataShift) | (((u32) pmd) <<
358 EhnMIIpmdShift);
359
360 SiS_W32(GMIIControl, l);
361
362 udelay(1000);
363
364 for (i = 0; i < 1000; i++) {
365 if (SiS_R32(GMIIControl) & EhnMIInotDone) {
366 udelay(100);
367 } else {
368 break;
369 }
370 }
371
372 if (i > 999)
373 printk(KERN_ERR PFX "Phy write Error!!!\n");
374
375}
376
377int
378smdio_read(void *ioaddr, int RegAddr)
379{
380
381 u32 l;
382 u16 i;
383 u32 pmd;
384
385 pmd = 1;
386 l = 0;
387 l = EhnMIIread | EhnMIIreq | (((u32) RegAddr) << EhnMIIregShift) |
388 (((u32) pmd) << EhnMIIpmdShift);
389
390 SiS_W32(GMIIControl, l);
391
392 udelay(1000);
393
394 for (i = 0; i < 1000; i++) {
395 if ((l == SiS_R32(GMIIControl)) & EhnMIInotDone) {
396 udelay(100);
397 } else {
398 break;
399 }
400
401 if (i > 999)
402 printk(KERN_ERR PFX "Phy Read Error!!!\n");
403 }
404 l = SiS_R32(GMIIControl);
405
406 return ((u16) (l >> EhnMIIdataShift));
407
408}
409
410int
411ReadEEprom(void *ioaddr, u32 RegAddr)
412{
413 u16 data;
414 u32 i;
415 u32 ulValue;
416
417 if (!(SiS_R32(ROMControl) & BIT_1)) {
418 return 0;
419 }
420
421 ulValue = (BIT_7 | (0x2 << 8) | (RegAddr << 10));
422
423 SiS_W32(ROMInterface, ulValue);
424
425 for (i = 0; i < 200; i++) {
426
427 if (!(SiS_R32(ROMInterface) & BIT_7))
428 break;
429
430 udelay(1000);
431 }
432
433 data = (u16) ((SiS_R32(ROMInterface) & 0xffff0000) >> 16);
434
435 return data;
436}
437
438static int __devinit
439SiS190_init_board(struct pci_dev *pdev, struct net_device **dev_out,
440 void **ioaddr_out)
441{
442 void *ioaddr = NULL;
443 struct net_device *dev;
444 struct sis190_private *tp;
445 u16 rc;
446 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
447
448 assert(pdev != NULL);
449 assert(ioaddr_out != NULL);
450
451 *ioaddr_out = NULL;
452 *dev_out = NULL;
453
454 dev = alloc_etherdev(sizeof (*tp));
455 if (dev == NULL) {
456 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
457 return -ENOMEM;
458 }
459
460 SET_MODULE_OWNER(dev);
461 SET_NETDEV_DEV(dev, &pdev->dev);
462 tp = dev->priv;
463
464
465 rc = pci_enable_device(pdev);
466 if (rc)
467 goto err_out;
468
469 rc = pci_set_dma_mask(pdev, 0xffffffffULL);
470 if (rc)
471 goto err_out_disable;
472
473 mmio_start = pci_resource_start(pdev, 0);
474 mmio_end = pci_resource_end(pdev, 0);
475 mmio_flags = pci_resource_flags(pdev, 0);
476 mmio_len = pci_resource_len(pdev, 0);
477
478
479 if (!(mmio_flags & IORESOURCE_MEM)) {
480 printk(KERN_ERR PFX
481 "region #0 not an MMIO resource, aborting\n");
482 rc = -ENODEV;
483 goto err_out_disable;
484 }
485
486 if (mmio_len < SiS190_MIN_IO_SIZE) {
487 printk(KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
488 rc = -ENODEV;
489 goto err_out_disable;
490 }
491
492 rc = pci_request_regions(pdev, dev->name);
493 if (rc)
494 goto err_out_disable;
495
496
497 pci_set_master(pdev);
498
499
500 ioaddr = ioremap(mmio_start, mmio_len);
501 if (ioaddr == NULL) {
502 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
503 rc = -EIO;
504 goto err_out_free_res;
505 }
506
507 SiS_W32(IntrControl, 0x8000);
508 udelay(1000);
509 SiS_W32(IntrControl, 0x0);
510
511 SiS_W32(TxControl, 0x1a00);
512 SiS_W32(RxControl, 0x1a00);
513 udelay(1000);
514
515 *ioaddr_out = ioaddr;
516 *dev_out = dev;
517 return 0;
518
519err_out_free_res:
520 pci_release_regions(pdev);
521
522err_out_disable:
523 pci_disable_device(pdev);
524err_out:
525 free_netdev(dev);
526 return rc;
527}
528
529static int __devinit
530SiS190_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
531{
532 struct net_device *dev = NULL;
533 struct sis190_private *tp = NULL;
534 void *ioaddr = NULL;
535 static int board_idx = -1;
536 static int printed_version = 0;
537 int i, rc;
538 u16 reg31;
539 int val;
540
541 assert(pdev != NULL);
542 assert(ent != NULL);
543
544 board_idx++;
545
546 if (!printed_version) {
547 printk(KERN_INFO SiS190_DRIVER_NAME " loaded\n");
548 printed_version = 1;
549 }
550
551 i = SiS190_init_board(pdev, &dev, &ioaddr);
552 if (i < 0) {
553 return i;
554 }
555
556 tp = dev->priv;
557 assert(ioaddr != NULL);
558 assert(dev != NULL);
559 assert(tp != NULL);
560
561
562
563
564 if (SiS_R32(ROMControl) & 0x2) {
565
566 for (i = 0; i < 6; i += 2) {
567 SiS_W16(RxMacAddr + i, ReadEEprom(ioaddr, 3 + (i / 2)));
568 }
569
570 } else {
571
572 SiS_W32(RxMacAddr, 0x11111100);
573 SiS_W32(RxMacAddr + 2, 0x00111111);
574 }
575
576 for (i = 0; i < MAC_ADDR_LEN; i++) {
577 dev->dev_addr[i] = SiS_R8(RxMacAddr + i);
578 printk("SiS_R8(RxMacAddr+%x)= %x ", i, SiS_R8(RxMacAddr + i));
579 }
580
581 dev->open = SiS190_open;
582 dev->hard_start_xmit = SiS190_start_xmit;
583 dev->get_stats = SiS190_get_stats;
584 dev->stop = SiS190_close;
585 dev->tx_timeout = SiS190_tx_timeout;
586 dev->set_multicast_list = SiS190_set_rx_mode;
587 dev->watchdog_timeo = TX_TIMEOUT;
588 dev->irq = pdev->irq;
589 dev->base_addr = (unsigned long) ioaddr;
590
591
592 tp = dev->priv;
593 tp->pci_dev = pdev;
594 tp->mmio_addr = ioaddr;
595
596 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", dev->name,
597 sis_chip_info[tp->chipset].name);
598
599 spin_lock_init(&tp->lock);
600 rc = register_netdev(dev);
601 if (rc) {
602 iounmap(ioaddr);
603 pci_release_regions(pdev);
604 pci_disable_device(pdev);
605 free_netdev(dev);
606 return rc;
607 }
608
609 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", dev->name,
610 sis_chip_info[tp->chipset].name);
611
612 pci_set_drvdata(pdev, dev);
613
614 printk(KERN_INFO "%s: %s at 0x%lx, "
615 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
616 "IRQ %d\n",
617 dev->name,
618 board_info[ent->driver_data].name,
619 dev->base_addr,
620 dev->dev_addr[0], dev->dev_addr[1],
621 dev->dev_addr[2], dev->dev_addr[3],
622 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
623
624 val = smdio_read(ioaddr, PHY_AUTO_NEGO_REG);
625
626 printk(KERN_INFO "%s: Auto-negotiation Enabled.\n", dev->name);
627
628
629 smdio_write(ioaddr, PHY_AUTO_NEGO_REG,
630 PHY_Cap_10_Half | PHY_Cap_10_Full |
631 PHY_Cap_100_Half | PHY_Cap_100_Full | (val & 0x1F));
632
633
634 smdio_write(ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
635
636
637 smdio_write(ioaddr, PHY_CTRL_REG,
638 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
639 udelay(100);
640
641
642 for (i = 10000; i > 0; i--) {
643
644 if (smdio_read(ioaddr, PHY_STAT_REG) & PHY_Auto_Neco_Comp) {
645 udelay(100);
646 reg31 = smdio_read(ioaddr, 31);
647 reg31 &= 0x1c;
648 switch (reg31) {
649 case _1000bpsF:
650 SiS_W16(0x40, 0x1c01);
651 printk
652 ("SiS190 Link on 1000 bps Full Duplex mode. \n");
653 break;
654 case _1000bpsH:
655 SiS_W16(0x40, 0x0c01);
656 printk
657 ("SiS190 Link on 1000 bps Half Duplex mode. \n");
658 break;
659 case _100bpsF:
660 SiS_W16(0x40, 0x1801);
661 printk
662 ("SiS190 Link on 100 bps Full Duplex mode. \n");
663 break;
664 case _100bpsH:
665 SiS_W16(0x40, 0x0801);
666 printk
667 ("SiS190 Link on 100 bps Half Duplex mode. \n");
668 break;
669 case _10bpsF:
670 SiS_W16(0x40, 0x1401);
671 printk
672 ("SiS190 Link on 10 bps Full Duplex mode. \n");
673 break;
674 case _10bpsH:
675 SiS_W16(0x40, 0x0401);
676 printk
677 ("SiS190 Link on 10 bps Half Duplex mode. \n");
678 break;
679 default:
680 printk(KERN_ERR PFX
681 "Error! SiS190 Can not detect mode !!! \n");
682 break;
683 }
684
685 break;
686 } else {
687 udelay(100);
688 }
689 }
690 return 0;
691}
692
693static void __devexit
694SiS190_remove_one(struct pci_dev *pdev)
695{
696 struct net_device *dev = pci_get_drvdata(pdev);
697 struct sis190_private *tp = (struct sis190_private *) (dev->priv);
698
699 assert(dev != NULL);
700 assert(tp != NULL);
701
702 unregister_netdev(dev);
703 iounmap(tp->mmio_addr);
704 pci_release_regions(pdev);
705
706 free_netdev(dev);
707 pci_set_drvdata(pdev, NULL);
708}
709
710static int
711SiS190_open(struct net_device *dev)
712{
713 struct sis190_private *tp = dev->priv;
714 int rc;
715
716 rc = request_irq(dev->irq, SiS190_interrupt, SA_SHIRQ, dev->name, dev);
717 if (rc)
718 goto out;
719
720
721
722
723
724 tp->TxDescArray = pci_alloc_consistent(tp->pci_dev, TX_DESC_TOTAL_SIZE,
725 &tp->tx_dma);
726 if (!tp->TxDescArray) {
727 rc = -ENOMEM;
728 goto err_out;
729 }
730
731 tp->RxDescArray = pci_alloc_consistent(tp->pci_dev, RX_DESC_TOTAL_SIZE,
732 &tp->rx_dma);
733 if (!tp->RxDescArray) {
734 rc = -ENOMEM;
735 goto err_out_free_tx;
736 }
737
738 tp->RxBufferRings = kmalloc(RX_BUF_SIZE * NUM_RX_DESC, GFP_KERNEL);
739 if (tp->RxBufferRings == NULL) {
740 printk(KERN_INFO "%s: allocate RxBufferRing failed\n",
741 dev->name);
742 rc = -ENOMEM;
743 goto err_out_free_rx;
744 }
745
746 SiS190_init_ring(dev);
747 SiS190_hw_start(dev);
748
749out:
750 return rc;
751
752err_out_free_rx:
753 pci_free_consistent(tp->pci_dev, RX_DESC_TOTAL_SIZE, tp->RxDescArray,
754 tp->rx_dma);
755err_out_free_tx:
756 pci_free_consistent(tp->pci_dev, TX_DESC_TOTAL_SIZE, tp->TxDescArray,
757 tp->tx_dma);
758err_out:
759 free_irq(dev->irq, dev);
760 return rc;
761}
762
763static void
764SiS190_hw_start(struct net_device *dev)
765{
766 struct sis190_private *tp = dev->priv;
767 void *ioaddr = tp->mmio_addr;
768
769
770
771 SiS_W32(IntrControl, 0x8000);
772 udelay(1000);
773 SiS_W32(IntrControl, 0x0);
774
775 SiS_W32(0x0, 0x01a00);
776 SiS_W32(0x4, tp->tx_dma);
777
778 SiS_W32(0x10, 0x1a00);
779 SiS_W32(0x14, tp->rx_dma);
780
781 SiS_W32(0x20, 0xffffffff);
782 SiS_W32(0x24, 0x0);
783 SiS_W16(0x40, 0x1901);
784 SiS_W32(0x44, 0x0);
785 SiS_W32(0x50, 0x60);
786 SiS_W16(0x60, 0x02);
787 SiS_W32(0x68, 0x0);
788 SiS_W32(0x6c, 0x0);
789 SiS_W32(0x70, 0x0);
790 SiS_W32(0x74, 0x0);
791
792
793
794 tp->cur_rx = 0;
795
796 udelay(10);
797
798 SiS190_set_rx_mode(dev);
799
800
801 SiS_W32(IntrMask, sis190_intr_mask);
802
803 SiS_W32(0x0, 0x1a01);
804 SiS_W32(0x10, 0x1a1d);
805
806 netif_start_queue(dev);
807
808}
809
810static void
811SiS190_init_ring(struct net_device *dev)
812{
813 struct sis190_private *tp = dev->priv;
814 int i;
815
816 tp->cur_rx = 0;
817 tp->cur_tx = 0;
818 tp->dirty_tx = 0;
819 memset(tp->TxDescArray, 0x0, NUM_TX_DESC * sizeof (struct TxDesc));
820 memset(tp->RxDescArray, 0x0, NUM_RX_DESC * sizeof (struct RxDesc));
821
822 for (i = 0; i < NUM_TX_DESC; i++) {
823 tp->Tx_skbuff[i] = NULL;
824 }
825 for (i = 0; i < NUM_RX_DESC; i++) {
826 struct RxDesc *desc = tp->RxDescArray + i;
827
828 desc->PSize = 0x0;
829
830 if (i == (NUM_RX_DESC - 1))
831 desc->buf_Len = BIT_31 + RX_BUF_SIZE;
832 else
833 desc->buf_Len = RX_BUF_SIZE;
834
835 tp->RxBufferRing[i] = tp->RxBufferRings + i * RX_BUF_SIZE;
836 desc->buf_addr = pci_map_single(tp->pci_dev,
837 tp->RxBufferRing[i], RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
838 desc->status = OWNbit | INTbit;
839 }
840
841}
842
843static void
844SiS190_tx_clear(struct sis190_private *tp)
845{
846 int i;
847
848 tp->cur_tx = 0;
849 for (i = 0; i < NUM_TX_DESC; i++) {
850 if (tp->Tx_skbuff[i] != NULL) {
851 struct sk_buff *skb;
852
853 skb = tp->Tx_skbuff[i];
854 pci_unmap_single(tp->pci_dev,
855 le32_to_cpu(tp->TxDescArray[i].buf_addr),
856 skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len,
857 PCI_DMA_TODEVICE);
858 dev_kfree_skb(skb);
859 tp->Tx_skbuff[i] = NULL;
860 tp->stats.tx_dropped++;
861 }
862 }
863}
864
865static void
866SiS190_tx_timeout(struct net_device *dev)
867{
868 struct sis190_private *tp = dev->priv;
869 void *ioaddr = tp->mmio_addr;
870 u8 tmp8;
871
872
873 tmp8 = SiS_R8(TxControl);
874 if (tmp8 & CmdTxEnb)
875 SiS_W8(TxControl, tmp8 & ~CmdTxEnb);
876
877
878 SiS_W32(IntrMask, 0x0000);
879
880
881 spin_lock_irq(&tp->lock);
882 SiS190_tx_clear(tp);
883 spin_unlock_irq(&tp->lock);
884
885
886 SiS190_hw_start(dev);
887
888 netif_wake_queue(dev);
889}
890
891static int
892SiS190_start_xmit(struct sk_buff *skb, struct net_device *dev)
893{
894 struct sis190_private *tp = dev->priv;
895 void *ioaddr = tp->mmio_addr;
896 int entry = tp->cur_tx % NUM_TX_DESC;
897 u32 len;
898
899 if (unlikely(skb->len < ETH_ZLEN)) {
900 skb = skb_padto(skb, ETH_ZLEN);
901 if (skb == NULL)
902 goto drop_tx;
903 len = ETH_ZLEN;
904 } else {
905 len = skb->len;
906 }
907
908 spin_lock_irq(&tp->lock);
909
910 if ((le32_to_cpu(tp->TxDescArray[entry].status) & OWNbit) == 0) {
911 dma_addr_t mapping;
912
913 mapping = pci_map_single(tp->pci_dev, skb->data, len,
914 PCI_DMA_TODEVICE);
915
916 tp->Tx_skbuff[entry] = skb;
917 tp->TxDescArray[entry].buf_addr = cpu_to_le32(mapping);
918 tp->TxDescArray[entry].PSize = cpu_to_le32(len);
919
920 if (entry != (NUM_TX_DESC - 1))
921 tp->TxDescArray[entry].buf_Len = cpu_to_le32(len);
922 else
923 tp->TxDescArray[entry].buf_Len =
924 cpu_to_le32(len | ENDbit);
925
926 tp->TxDescArray[entry].status |=
927 cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
928
929 SiS_W32(TxControl, 0x1a11);
930
931 dev->trans_start = jiffies;
932
933 tp->cur_tx++;
934 } else {
935 spin_unlock_irq(&tp->lock);
936 goto drop_tx;
937 }
938
939 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
940 netif_stop_queue(dev);
941
942 spin_unlock_irq(&tp->lock);
943
944 return 0;
945
946drop_tx:
947 tp->stats.tx_dropped++;
948 if (skb)
949 dev_kfree_skb(skb);
950 return 0;
951}
952
953static void
954SiS190_tx_interrupt(struct net_device *dev, struct sis190_private *tp,
955 void *ioaddr)
956{
957 unsigned long dirty_tx, tx_left = 0;
958 int entry = tp->cur_tx % NUM_TX_DESC;
959
960 assert(dev != NULL);
961 assert(tp != NULL);
962 assert(ioaddr != NULL);
963
964 dirty_tx = tp->dirty_tx;
965 tx_left = tp->cur_tx - dirty_tx;
966
967 while (tx_left > 0) {
968 if ((le32_to_cpu(tp->TxDescArray[entry].status) & OWNbit) == 0) {
969 struct sk_buff *skb;
970
971 skb = tp->Tx_skbuff[entry];
972
973 pci_unmap_single(tp->pci_dev,
974 le32_to_cpu(tp->TxDescArray[entry].buf_addr),
975 skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len,
976 PCI_DMA_TODEVICE);
977
978 dev_kfree_skb_irq(skb);
979 tp->Tx_skbuff[entry] = NULL;
980 tp->stats.tx_packets++;
981 dirty_tx++;
982 tx_left--;
983 entry++;
984 }
985 }
986
987 if (tp->dirty_tx != dirty_tx) {
988 tp->dirty_tx = dirty_tx;
989 netif_wake_queue(dev);
990 }
991}
992
993static void
994SiS190_rx_interrupt(struct net_device *dev, struct sis190_private *tp,
995 void *ioaddr)
996{
997 int cur_rx = tp->cur_rx;
998 struct RxDesc *desc = tp->RxDescArray + cur_rx;
999
1000 assert(dev != NULL);
1001 assert(tp != NULL);
1002 assert(ioaddr != NULL);
1003
1004 while ((desc->status & OWNbit) == 0) {
1005
1006 if (desc->PSize & 0x0080000) {
1007 printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name);
1008 tp->stats.rx_errors++;
1009 tp->stats.rx_length_errors++;
1010 } else if (!(desc->PSize & 0x0010000)) {
1011 printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name);
1012 tp->stats.rx_errors++;
1013 tp->stats.rx_crc_errors++;
1014 } else {
1015 struct sk_buff *skb;
1016 int pkt_size;
1017
1018 pkt_size = (int) (desc->PSize & 0x0000FFFF) - 4;
1019 pci_dma_sync_single(tp->pci_dev, desc->buf_addr,
1020 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1021 skb = dev_alloc_skb(pkt_size + 2);
1022 if (skb != NULL) {
1023 skb->dev = dev;
1024 skb_reserve(skb, 2);
1025 eth_copy_and_sum(skb, tp->RxBufferRing[cur_rx],
1026 pkt_size, 0);
1027 skb_put(skb, pkt_size);
1028 skb->protocol = eth_type_trans(skb, dev);
1029 netif_rx(skb);
1030
1031 desc->PSize = 0x0;
1032
1033 if (cur_rx == (NUM_RX_DESC - 1))
1034 desc->buf_Len = ENDbit + RX_BUF_SIZE;
1035 else
1036 desc->buf_Len = RX_BUF_SIZE;
1037
1038 dev->last_rx = jiffies;
1039 tp->stats.rx_bytes += pkt_size;
1040 tp->stats.rx_packets++;
1041
1042 desc->status = OWNbit | INTbit;
1043 } else {
1044 printk(KERN_WARNING
1045 "%s: Memory squeeze, deferring packet.\n",
1046 dev->name);
1047
1048
1049 tp->stats.rx_dropped++;
1050 }
1051 }
1052
1053 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
1054 desc = tp->RxDescArray + cur_rx;
1055 }
1056
1057 tp->cur_rx = cur_rx;
1058}
1059
1060
1061static irqreturn_t
1062SiS190_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1063{
1064 struct net_device *dev = (struct net_device *) dev_instance;
1065 struct sis190_private *tp = dev->priv;
1066 int boguscnt = max_interrupt_work;
1067 void *ioaddr = tp->mmio_addr;
1068 unsigned long status = 0;
1069 int handled = 0;
1070
1071 do {
1072 status = SiS_R32(IntrStatus);
1073
1074
1075
1076 SiS_W32(IntrStatus, status);
1077
1078 if ((status & (TxQ0Int | RxQInt)) == 0)
1079 break;
1080
1081
1082 if (status & (RxQInt)) {
1083 SiS190_rx_interrupt(dev, tp, ioaddr);
1084 }
1085
1086 if (status & (TxQ0Int)) {
1087 spin_lock(&tp->lock);
1088 SiS190_tx_interrupt(dev, tp, ioaddr);
1089 spin_unlock(&tp->lock);
1090 }
1091
1092 boguscnt--;
1093 } while (boguscnt > 0);
1094
1095 if (boguscnt <= 0) {
1096 printk(KERN_WARNING "%s: Too much work at interrupt!\n",
1097 dev->name);
1098
1099 SiS_W32(IntrStatus, 0xffffffff);
1100 }
1101
1102 return IRQ_RETVAL(handled);
1103}
1104
1105static int
1106SiS190_close(struct net_device *dev)
1107{
1108 struct sis190_private *tp = dev->priv;
1109 void *ioaddr = tp->mmio_addr;
1110 int i;
1111
1112 netif_stop_queue(dev);
1113
1114 spin_lock_irq(&tp->lock);
1115
1116
1117
1118 SiS_W32(TxControl, 0x1a00);
1119 SiS_W32(RxControl, 0x1a00);
1120
1121
1122 SiS_W32(IntrMask, 0x0000);
1123
1124
1125
1126
1127 spin_unlock_irq(&tp->lock);
1128
1129 synchronize_irq(dev->irq);
1130 free_irq(dev->irq, dev);
1131
1132 SiS190_tx_clear(tp);
1133 pci_free_consistent(tp->pci_dev, TX_DESC_TOTAL_SIZE, tp->TxDescArray,
1134 tp->tx_dma);
1135 pci_free_consistent(tp->pci_dev, RX_DESC_TOTAL_SIZE, tp->RxDescArray,
1136 tp->rx_dma);
1137 tp->TxDescArray = NULL;
1138 for (i = 0; i < NUM_RX_DESC; i++) {
1139 pci_unmap_single(tp->pci_dev, tp->RxDescArray[i].buf_addr,
1140 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1141 tp->RxBufferRing[i] = NULL;
1142 }
1143 tp->RxDescArray = NULL;
1144 kfree(tp->RxBufferRings);
1145
1146 return 0;
1147}
1148
1149static void
1150SiS190_set_rx_mode(struct net_device *dev)
1151{
1152 struct sis190_private *tp = dev->priv;
1153 void *ioaddr = tp->mmio_addr;
1154 unsigned long flags;
1155 u32 mc_filter[2];
1156 int i, rx_mode;
1157 u32 tmp = 0;
1158
1159 if (dev->flags & IFF_PROMISC) {
1160
1161 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1162 dev->name);
1163 rx_mode =
1164 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1165 AcceptAllPhys;
1166 mc_filter[1] = mc_filter[0] = 0xffffffff;
1167 } else if ((dev->mc_count > multicast_filter_limit)
1168 || (dev->flags & IFF_ALLMULTI)) {
1169
1170 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1171 mc_filter[1] = mc_filter[0] = 0xffffffff;
1172 } else {
1173 struct dev_mc_list *mclist;
1174 rx_mode = AcceptBroadcast | AcceptMyPhys;
1175 mc_filter[1] = mc_filter[0] = 0;
1176 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1177 i++, mclist = mclist->next) {
1178 int bit_nr =
1179 ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1180 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1181 rx_mode |= AcceptMulticast;
1182 }
1183 }
1184
1185 spin_lock_irqsave(&tp->lock, flags);
1186
1187 tmp = rx_mode | 0x2;
1188
1189 SiS_W16(RxMacControl, tmp);
1190 SiS_W32(RxHashTable, mc_filter[0]);
1191 SiS_W32(RxHashTable + 4, mc_filter[1]);
1192
1193 spin_unlock_irqrestore(&tp->lock, flags);
1194}
1195
1196struct net_device_stats *
1197SiS190_get_stats(struct net_device *dev)
1198{
1199 struct sis190_private *tp = dev->priv;
1200 return &tp->stats;
1201}
1202
1203static struct pci_driver sis190_pci_driver = {
1204 .name = MODULENAME,
1205 .id_table = sis190_pci_tbl,
1206 .probe = SiS190_init_one,
1207 .remove = SiS190_remove_one,
1208};
1209
1210static int __init
1211SiS190_init_module(void)
1212{
1213 return pci_module_init(&sis190_pci_driver);
1214}
1215
1216static void __exit
1217SiS190_cleanup_module(void)
1218{
1219 pci_unregister_driver(&sis190_pci_driver);
1220}
1221
1222module_init(SiS190_init_module);
1223module_exit(SiS190_cleanup_module);
1224
