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146#include <linux/module.h>
147#include <linux/kernel.h>
148#include <linux/string.h>
149#include <linux/errno.h>
150#include <linux/ioport.h>
151#include <linux/slab.h>
152#include <linux/interrupt.h>
153#include <linux/delay.h>
154#include <linux/init.h>
155#include <linux/crc32.h>
156#include <linux/netdevice.h>
157#include <linux/etherdevice.h>
158#include <linux/skbuff.h>
159#include <linux/ethtool.h>
160#include <linux/time.h>
161#include <linux/types.h>
162#include <linux/unistd.h>
163#include <linux/ctype.h>
164
165#include <asm/bitops.h>
166#include <asm/io.h>
167#include <asm/dma.h>
168#include <asm/uaccess.h>
169
170#include "ewrk3.h"
171
172#define DRV_NAME "ewrk3"
173#define DRV_VERSION "0.48"
174
175static char version[] __initdata =
176DRV_NAME ":v" DRV_VERSION " 2002/10/18 davies@maniac.ultranet.com\n";
177
178#ifdef EWRK3_DEBUG
179static int ewrk3_debug = EWRK3_DEBUG;
180#else
181static int ewrk3_debug = 1;
182#endif
183
184#define EWRK3_NDA 0xffe0
185
186#define PROBE_LENGTH 32
187#define ETH_PROM_SIG 0xAA5500FFUL
188
189#ifndef EWRK3_SIGNATURE
190#define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
191#define EWRK3_STRLEN 8
192#endif
193
194#ifndef EWRK3_RAM_BASE_ADDRESSES
195#define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
196#endif
197
198
199
200
201#define EWRK3_IO_BASE 0x100
202#define EWRK3_IOP_INC 0x20
203#define EWRK3_TOTAL_SIZE 0x20
204
205
206#ifndef MAX_NUM_EWRK3S
207#define MAX_NUM_EWRK3S 21
208#endif
209
210#ifndef EWRK3_EISA_IO_PORTS
211#define EWRK3_EISA_IO_PORTS 0x0c00
212#endif
213
214#ifndef MAX_EISA_SLOTS
215#define MAX_EISA_SLOTS 16
216#define EISA_SLOT_INC 0x1000
217#endif
218
219#define QUEUE_PKT_TIMEOUT (1*HZ)
220
221
222
223
224#define IO_ONLY 0x00
225#define SHMEM_2K 0x800
226#define SHMEM_32K 0x8000
227#define SHMEM_64K 0x10000
228
229
230
231
232#define ENABLE_IRQs { \
233 icr |= lp->irq_mask;\
234 outb(icr, EWRK3_ICR); \
235}
236
237#define DISABLE_IRQs { \
238 icr = inb(EWRK3_ICR);\
239 icr &= ~lp->irq_mask;\
240 outb(icr, EWRK3_ICR); \
241}
242
243
244
245
246#define START_EWRK3 { \
247 csr = inb(EWRK3_CSR);\
248 csr &= ~(CSR_TXD|CSR_RXD);\
249 outb(csr, EWRK3_CSR); \
250}
251
252#define STOP_EWRK3 { \
253 csr = (CSR_TXD|CSR_RXD);\
254 outb(csr, EWRK3_CSR); \
255}
256
257
258
259
260#define EWRK3_PKT_STAT_SZ 16
261#define EWRK3_PKT_BIN_SZ 128
262
263
264struct ewrk3_stats {
265 u32 bins[EWRK3_PKT_STAT_SZ];
266 u32 unicast;
267 u32 multicast;
268 u32 broadcast;
269 u32 excessive_collisions;
270 u32 tx_underruns;
271 u32 excessive_underruns;
272};
273
274struct ewrk3_private {
275 char adapter_name[80];
276 u_long shmem_base;
277 u_long shmem_length;
278 struct net_device_stats stats;
279 struct ewrk3_stats pktStats;
280 u_char irq_mask;
281 u_char mPage;
282 u_char lemac;
283 u_char hard_strapped;
284 u_char txc;
285 u_char *mctbl;
286 u_char led_mask;
287 spinlock_t hw_lock;
288};
289
290
291
292
293#define FORCE_2K_MODE { \
294 shmem_length = SHMEM_2K;\
295 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR);\
296}
297
298
299
300
301static int ewrk3_open(struct net_device *dev);
302static int ewrk3_queue_pkt(struct sk_buff *skb, struct net_device *dev);
303static irqreturn_t ewrk3_interrupt(int irq, void *dev_id, struct pt_regs *regs);
304static int ewrk3_close(struct net_device *dev);
305static struct net_device_stats *ewrk3_get_stats(struct net_device *dev);
306static void set_multicast_list(struct net_device *dev);
307static int ewrk3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
308
309
310
311
312static int ewrk3_hw_init(struct net_device *dev, u_long iobase);
313static void ewrk3_init(struct net_device *dev);
314static int ewrk3_rx(struct net_device *dev);
315static int ewrk3_tx(struct net_device *dev);
316static void ewrk3_timeout(struct net_device *dev);
317
318static void EthwrkSignature(char *name, char *eeprom_image);
319static int DevicePresent(u_long iobase);
320static void SetMulticastFilter(struct net_device *dev);
321static int EISA_signature(char *name, s32 eisa_id);
322
323static int Read_EEPROM(u_long iobase, u_char eaddr);
324static int Write_EEPROM(short data, u_long iobase, u_char eaddr);
325static u_char get_hw_addr(struct net_device *dev, u_char * eeprom_image, char chipType);
326
327static void isa_probe(struct net_device *dev, u_long iobase);
328static void eisa_probe(struct net_device *dev, u_long iobase);
329static struct net_device *alloc_device(struct net_device *dev, u_long iobase);
330static int ewrk3_dev_index(char *s);
331static struct net_device *insert_device(struct net_device *dev, u_long iobase, int (*init) (struct net_device *));
332
333
334#ifdef MODULE
335static int autoprobed = 1, loading_module = 1;
336
337#else
338static u_char irq[] =
339{5, 0, 10, 3, 11, 9, 15, 12};
340static int autoprobed, loading_module;
341
342#endif
343
344static char name[EWRK3_STRLEN + 1];
345static int num_ewrk3s, num_eth;
346
347
348
349
350#define INIT_EWRK3 {\
351 outb(EEPROM_INIT, EWRK3_IOPR);\
352 mdelay(1);\
353}
354
355int __init ewrk3_probe(struct net_device *dev)
356{
357 int tmp = num_ewrk3s, status = -ENODEV;
358 u_long iobase = dev->base_addr;
359
360 SET_MODULE_OWNER(dev);
361
362 if ((iobase == 0) && loading_module) {
363 printk("Autoprobing is not supported when loading a module based driver.\n");
364 status = -EIO;
365 } else {
366
367 isa_probe(dev, iobase);
368 eisa_probe(dev, iobase);
369
370 if ((tmp == num_ewrk3s) && (iobase != 0) && loading_module) {
371 printk("%s: ewrk3_probe() cannot find device at 0x%04lx.\n", dev->name,
372 iobase);
373 }
374
375
376
377
378 for (; (dev->priv == NULL) && (dev->next != NULL); dev = dev->next);
379
380 if (dev->priv)
381 status = 0;
382 if (iobase == 0)
383 autoprobed = 1;
384 }
385
386 return status;
387}
388
389static int __init
390ewrk3_hw_init(struct net_device *dev, u_long iobase)
391{
392 struct ewrk3_private *lp;
393 int i, status = 0;
394 u_long mem_start, shmem_length;
395 u_char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
396 u_char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
397
398
399
400
401
402 if (iobase > 0x400)
403 eisa_cr = inb(EISA_CR);
404 INIT_EWRK3;
405
406 nicsr = inb(EWRK3_CSR);
407
408 icr = inb(EWRK3_ICR);
409 icr &= 0x70;
410 outb(icr, EWRK3_ICR);
411
412 if (nicsr == (CSR_TXD | CSR_RXD)) {
413
414
415 for (chksum = 0, i = 0; i < EEPROM_MAX; i += 2) {
416 union {
417 short val;
418 char c[2];
419 } tmp;
420
421 tmp.val = (short) Read_EEPROM(iobase, (i >> 1));
422 eeprom_image[i] = tmp.c[0];
423 eeprom_image[i + 1] = tmp.c[1];
424 chksum += eeprom_image[i] + eeprom_image[i + 1];
425 }
426
427 if (chksum != 0) {
428 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
429 status = -ENXIO;
430 } else {
431 EthwrkSignature(name, eeprom_image);
432 if (*name != '\0') {
433 dev->base_addr = iobase;
434
435 if (iobase > 0x400) {
436 outb(eisa_cr, EISA_CR);
437 }
438 lemac = eeprom_image[EEPROM_CHIPVER];
439 cmr = inb(EWRK3_CMR);
440
441 if (((lemac == LeMAC) && ((cmr & CMR_NO_EEPROM) != CMR_NO_EEPROM)) ||
442 ((lemac == LeMAC2) && !(cmr & CMR_HS))) {
443 printk("%s: %s at %#4lx", dev->name, name, iobase);
444 hard_strapped = 1;
445 } else if ((iobase & 0x0fff) == EWRK3_EISA_IO_PORTS) {
446
447 printk("%s: %s at %#4lx (EISA slot %ld)",
448 dev->name, name, iobase, ((iobase >> 12) & 0x0f));
449 } else {
450 printk("%s: %s at %#4lx", dev->name, name, iobase);
451 }
452
453 if (!status) {
454 printk(", h/w address ");
455 if (lemac != LeMAC2)
456 DevicePresent(iobase);
457 status = get_hw_addr(dev, eeprom_image, lemac);
458 for (i = 0; i < ETH_ALEN - 1; i++) {
459 printk("%2.2x:", dev->dev_addr[i]);
460 }
461 printk("%2.2x,\n", dev->dev_addr[i]);
462
463 if (status) {
464 printk(" which has an EEPROM CRC error.\n");
465 status = -ENXIO;
466 } else {
467 if (lemac == LeMAC2) {
468 cmr &= ~(CMR_RA | CMR_WB | CMR_LINK | CMR_POLARITY | CMR_0WS);
469 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD)
470 cmr |= CMR_RA;
471 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND)
472 cmr |= CMR_WB;
473 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL)
474 cmr |= CMR_POLARITY;
475 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK)
476 cmr |= CMR_LINK;
477 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA)
478 cmr |= CMR_0WS;
479 }
480 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM)
481 cmr |= CMR_DRAM;
482 outb(cmr, EWRK3_CMR);
483
484 cr = inb(EWRK3_CR);
485 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
486 if (cr & SETUP_APD)
487 cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
488 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
489 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
490 outb(cr, EWRK3_CR);
491
492
493
494
495
496 mem_start = inb(EWRK3_MBR);
497 shmem_length = 0;
498 if (mem_start != 0) {
499 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
500 mem_start *= SHMEM_64K;
501 shmem_length = SHMEM_64K;
502 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
503 mem_start *= SHMEM_32K;
504 shmem_length = SHMEM_32K;
505 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
506 mem_start = mem_start * SHMEM_2K + 0x80000;
507 shmem_length = SHMEM_2K;
508 } else {
509 status = -ENXIO;
510 }
511 }
512
513
514
515
516
517
518 if (!status) {
519 if (hard_strapped) {
520 printk(" is hard strapped.\n");
521 } else if (mem_start) {
522 printk(" has a %dk RAM window", (int) (shmem_length >> 10));
523 printk(" at 0x%.5lx", mem_start);
524 } else {
525 printk(" is in I/O only mode");
526 }
527
528
529 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
530 GFP_KERNEL);
531 if (dev->priv == NULL) {
532 return -ENOMEM;
533 }
534 lp = (struct ewrk3_private *) dev->priv;
535 memset(dev->priv, 0, sizeof(struct ewrk3_private));
536 lp->shmem_base = mem_start;
537 lp->shmem_length = shmem_length;
538 lp->lemac = lemac;
539 lp->hard_strapped = hard_strapped;
540 lp->led_mask = CR_LED;
541 spin_lock_init(&lp->hw_lock);
542
543 lp->mPage = 64;
544 if (cmr & CMR_DRAM)
545 lp->mPage <<= 1;
546
547 sprintf(lp->adapter_name, "%s (%s)", name, dev->name);
548 request_region(iobase, EWRK3_TOTAL_SIZE, lp->adapter_name);
549
550 lp->irq_mask = ICR_TNEM | ICR_TXDM | ICR_RNEM | ICR_RXDM;
551
552 if (!hard_strapped) {
553
554
555
556 icr |= ICR_IE;
557 outb(icr, EWRK3_ICR);
558
559
560 dev->dma = 0;
561
562
563
564 if (dev->irq < 2) {
565#ifndef MODULE
566 u_char irqnum;
567 unsigned long irq_mask;
568
569
570 irq_mask = probe_irq_on();
571
572
573
574
575 icr |= ICR_TNEM;
576 outb(1, EWRK3_TDQ);
577 outb(icr, EWRK3_ICR);
578
579 irqnum = irq[((icr & IRQ_SEL) >> 4)];
580
581 mdelay(20);
582 dev->irq = probe_irq_off(irq_mask);
583 if ((dev->irq) && (irqnum == dev->irq)) {
584 printk(" and uses IRQ%d.\n", dev->irq);
585 } else {
586 if (!dev->irq) {
587 printk(" and failed to detect IRQ line.\n");
588 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
589 printk(" and an illegal IRQ line detected.\n");
590 } else {
591 printk(", but incorrect IRQ line detected.\n");
592 }
593 status = -ENXIO;
594 }
595
596 DISABLE_IRQs;
597
598#endif
599 } else {
600 printk(" and requires IRQ%d.\n", dev->irq);
601 }
602 }
603 if (status)
604 release_region(iobase, EWRK3_TOTAL_SIZE);
605 } else {
606 status = -ENXIO;
607 }
608 }
609 }
610 } else {
611 status = -ENXIO;
612 }
613 }
614
615 if (!status) {
616 if (ewrk3_debug > 1) {
617 printk(version);
618 }
619
620 dev->open = ewrk3_open;
621 dev->hard_start_xmit = ewrk3_queue_pkt;
622 dev->stop = ewrk3_close;
623 dev->get_stats = ewrk3_get_stats;
624 dev->set_multicast_list = set_multicast_list;
625 dev->do_ioctl = ewrk3_ioctl;
626 dev->tx_timeout = ewrk3_timeout;
627 dev->watchdog_timeo = QUEUE_PKT_TIMEOUT;
628
629 dev->mem_start = 0;
630
631
632 ether_setup(dev);
633 }
634 } else {
635 status = -ENXIO;
636 }
637 return status;
638}
639
640
641static int ewrk3_open(struct net_device *dev)
642{
643 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
644 u_long iobase = dev->base_addr;
645 int i, status = 0;
646 u_char icr, csr;
647
648
649
650
651 STOP_EWRK3;
652
653 if (!lp->hard_strapped) {
654 if (request_irq(dev->irq, (void *) ewrk3_interrupt, 0, "ewrk3", dev)) {
655 printk("ewrk3_open(): Requested IRQ%d is busy\n", dev->irq);
656 status = -EAGAIN;
657 } else {
658
659
660
661
662 ewrk3_init(dev);
663
664 if (ewrk3_debug > 1) {
665 printk("%s: ewrk3 open with irq %d\n", dev->name, dev->irq);
666 printk(" physical address: ");
667 for (i = 0; i < 5; i++) {
668 printk("%2.2x:", (u_char) dev->dev_addr[i]);
669 }
670 printk("%2.2x\n", (u_char) dev->dev_addr[i]);
671 if (lp->shmem_length == 0) {
672 printk(" no shared memory, I/O only mode\n");
673 } else {
674 printk(" start of shared memory: 0x%08lx\n", lp->shmem_base);
675 printk(" window length: 0x%04lx\n", lp->shmem_length);
676 }
677 printk(" # of DRAMS: %d\n", ((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
678 printk(" csr: 0x%02x\n", inb(EWRK3_CSR));
679 printk(" cr: 0x%02x\n", inb(EWRK3_CR));
680 printk(" icr: 0x%02x\n", inb(EWRK3_ICR));
681 printk(" cmr: 0x%02x\n", inb(EWRK3_CMR));
682 printk(" fmqc: 0x%02x\n", inb(EWRK3_FMQC));
683 }
684 netif_start_queue(dev);
685
686
687
688 icr = inb(EWRK3_ICR);
689 ENABLE_IRQs;
690
691 }
692 } else {
693 printk(KERN_ERR "%s: ewrk3 available for hard strapped set up only.\n", dev->name);
694 printk(KERN_ERR " Run the 'ewrk3setup' utility or remove the hard straps.\n");
695 return -EINVAL;
696 }
697
698 return status;
699}
700
701
702
703
704static void ewrk3_init(struct net_device *dev)
705{
706 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
707 u_char csr, page;
708 u_long iobase = dev->base_addr;
709 int i;
710
711
712
713
714 set_multicast_list(dev);
715
716
717
718
719
720 for (i=0; i<ETH_ALEN; i++)
721 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
722
723
724
725
726 while (inb(EWRK3_TQ));
727 while (inb(EWRK3_TDQ));
728 while (inb(EWRK3_RQ));
729 while (inb(EWRK3_FMQ));
730
731
732
733
734 for (page = 1; page < lp->mPage; page++) {
735 outb(page, EWRK3_FMQ);
736 }
737
738 START_EWRK3;
739}
740
741
742
743
744
745static void ewrk3_timeout(struct net_device *dev)
746{
747 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
748 u_char icr, csr;
749 u_long iobase = dev->base_addr;
750
751 if (!lp->hard_strapped)
752 {
753 printk(KERN_WARNING"%s: transmit timed/locked out, status %04x, resetting.\n",
754 dev->name, inb(EWRK3_CSR));
755
756
757
758
759 DISABLE_IRQs;
760
761
762
763
764 STOP_EWRK3;
765
766 ewrk3_init(dev);
767
768
769
770
771 ENABLE_IRQs;
772
773 dev->trans_start = jiffies;
774 netif_wake_queue(dev);
775 }
776}
777
778
779
780
781static int ewrk3_queue_pkt (struct sk_buff *skb, struct net_device *dev)
782{
783 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
784 u_long iobase = dev->base_addr;
785 u_long buf = 0;
786 u_char icr;
787 u_char page;
788
789 spin_lock_irq (&lp->hw_lock);
790 DISABLE_IRQs;
791
792
793 if (inb (EWRK3_FMQC) == 0) {
794 printk (KERN_WARNING "%s: ewrk3_queue_pkt(): No free resources...\n",
795 dev->name);
796 printk (KERN_WARNING "%s: ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",
797 dev->name, inb (EWRK3_CSR), inb (EWRK3_ICR),
798 inb (EWRK3_FMQC));
799 goto err_out;
800 }
801
802
803
804
805 if ((page = inb (EWRK3_FMQ)) >= lp->mPage) {
806 printk ("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
807 (u_char) page);
808 goto err_out;
809 }
810
811
812
813
814
815 if (lp->shmem_length == IO_ONLY) {
816 outb (page, EWRK3_IOPR);
817 } else if (lp->shmem_length == SHMEM_2K) {
818 buf = lp->shmem_base;
819 outb (page, EWRK3_MPR);
820 } else if (lp->shmem_length == SHMEM_32K) {
821 buf = ((((short) page << 11) & 0x7800) + lp->shmem_base);
822 outb ((page >> 4), EWRK3_MPR);
823 } else if (lp->shmem_length == SHMEM_64K) {
824 buf = ((((short) page << 11) & 0xf800) + lp->shmem_base);
825 outb ((page >> 5), EWRK3_MPR);
826 } else {
827 printk (KERN_ERR "%s: Oops - your private data area is hosed!\n",
828 dev->name);
829 BUG ();
830 }
831
832
833
834
835
836 if (lp->shmem_length == IO_ONLY) {
837 int i;
838 u_char *p = skb->data;
839 outb ((char) (TCR_QMODE | TCR_PAD | TCR_IFC), EWRK3_DATA);
840 outb ((char) (skb->len & 0xff), EWRK3_DATA);
841 outb ((char) ((skb->len >> 8) & 0xff), EWRK3_DATA);
842 outb ((char) 0x04, EWRK3_DATA);
843 for (i = 0; i < skb->len; i++) {
844 outb (*p++, EWRK3_DATA);
845 }
846 outb (page, EWRK3_TQ);
847 } else {
848 isa_writeb ((char) (TCR_QMODE | TCR_PAD | TCR_IFC), buf);
849 buf += 1;
850 isa_writeb ((char) (skb->len & 0xff), buf);
851 buf += 1;
852 if (lp->txc) {
853 isa_writeb ((char)
854 (((skb->len >> 8) & 0xff) | XCT), buf);
855 buf += 1;
856 isa_writeb (0x04, buf);
857 buf += 1;
858 isa_writeb (0x00, (buf + skb->len));
859 isa_memcpy_toio (buf, skb->data, PRELOAD);
860 outb (page, EWRK3_TQ);
861 isa_memcpy_toio (buf + PRELOAD,
862 skb->data + PRELOAD,
863 skb->len - PRELOAD);
864 isa_writeb (0xff, (buf + skb->len));
865 } else {
866 isa_writeb ((char)
867 ((skb->len >> 8) & 0xff), buf);
868 buf += 1;
869 isa_writeb (0x04, buf);
870 buf += 1;
871 isa_memcpy_toio (buf, skb->data, skb->len);
872 outb (page, EWRK3_TQ);
873 }
874 }
875
876 ENABLE_IRQs;
877 spin_unlock_irq (&lp->hw_lock);
878
879 lp->stats.tx_bytes += skb->len;
880 dev->trans_start = jiffies;
881 dev_kfree_skb (skb);
882
883
884 if (inb (EWRK3_FMQC) == 0)
885 netif_stop_queue (dev);
886
887 return 0;
888
889err_out:
890 ENABLE_IRQs;
891 spin_unlock_irq (&lp->hw_lock);
892 return 1;
893}
894
895
896
897
898static irqreturn_t ewrk3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
899{
900 struct net_device *dev = dev_id;
901 struct ewrk3_private *lp;
902 u_long iobase;
903 u_char icr, cr, csr;
904
905 lp = (struct ewrk3_private *) dev->priv;
906 iobase = dev->base_addr;
907
908
909 csr = inb(EWRK3_CSR);
910
911
912
913
914 spin_lock(&lp->hw_lock);
915 DISABLE_IRQs;
916
917 cr = inb(EWRK3_CR);
918 cr |= lp->led_mask;
919 outb(cr, EWRK3_CR);
920
921 if (csr & CSR_RNE)
922 ewrk3_rx(dev);
923
924 if (csr & CSR_TNE)
925 ewrk3_tx(dev);
926
927
928
929
930
931
932
933 if (inb(EWRK3_FMQC)) {
934 lp->irq_mask |= ICR_TXDM | ICR_RXDM;
935 csr &= ~(CSR_TXD | CSR_RXD);
936 outb(csr, EWRK3_CSR);
937 netif_wake_queue(dev);
938 } else {
939 lp->irq_mask &= ~(ICR_TXDM | ICR_RXDM);
940 }
941
942
943 cr &= ~(lp->led_mask);
944 outb(cr, EWRK3_CR);
945 ENABLE_IRQs;
946 spin_unlock(&lp->hw_lock);
947 return IRQ_HANDLED;
948}
949
950
951static int ewrk3_rx(struct net_device *dev)
952{
953 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
954 u_long iobase = dev->base_addr;
955 int i, status = 0;
956 u_char page;
957 u_long buf = 0;
958
959 while (inb(EWRK3_RQC) && !status) {
960 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
961
962
963
964 if (lp->shmem_length == IO_ONLY) {
965 outb(page, EWRK3_IOPR);
966 } else if (lp->shmem_length == SHMEM_2K) {
967 buf = lp->shmem_base;
968 outb(page, EWRK3_MPR);
969 } else if (lp->shmem_length == SHMEM_32K) {
970 buf = ((((short) page << 11) & 0x7800) + lp->shmem_base);
971 outb((page >> 4), EWRK3_MPR);
972 } else if (lp->shmem_length == SHMEM_64K) {
973 buf = ((((short) page << 11) & 0xf800) + lp->shmem_base);
974 outb((page >> 5), EWRK3_MPR);
975 } else {
976 status = -1;
977 printk("%s: Oops - your private data area is hosed!\n", dev->name);
978 }
979
980 if (!status) {
981 char rx_status;
982 int pkt_len;
983
984 if (lp->shmem_length == IO_ONLY) {
985 rx_status = inb(EWRK3_DATA);
986 pkt_len = inb(EWRK3_DATA);
987 pkt_len |= ((u_short) inb(EWRK3_DATA) << 8);
988 } else {
989 rx_status = isa_readb(buf);
990 buf += 1;
991 pkt_len = isa_readw(buf);
992 buf += 3;
993 }
994
995 if (!(rx_status & R_ROK)) {
996 lp->stats.rx_errors++;
997 if (rx_status & R_DBE)
998 lp->stats.rx_frame_errors++;
999 if (rx_status & R_CRC)
1000 lp->stats.rx_crc_errors++;
1001 if (rx_status & R_PLL)
1002 lp->stats.rx_fifo_errors++;
1003 } else {
1004 struct sk_buff *skb;
1005
1006 if ((skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1007 unsigned char *p;
1008 skb->dev = dev;
1009 skb_reserve(skb, 2);
1010 p = skb_put(skb, pkt_len);
1011
1012 if (lp->shmem_length == IO_ONLY) {
1013 *p = inb(EWRK3_DATA);
1014 for (i = 0; i < pkt_len; i++) {
1015 *p++ = inb(EWRK3_DATA);
1016 }
1017 } else {
1018 isa_memcpy_fromio(p, buf, pkt_len);
1019 }
1020
1021 for (i = 1; i < EWRK3_PKT_STAT_SZ - 1; i++) {
1022 if (pkt_len < i * EWRK3_PKT_BIN_SZ) {
1023 lp->pktStats.bins[i]++;
1024 i = EWRK3_PKT_STAT_SZ;
1025 }
1026 }
1027 p = skb->data;
1028 if (p[0] & 0x01) {
1029 if ((*(s16 *) & p[0] == -1) && (*(s16 *) & p[2] == -1) && (*(s16 *) & p[4] == -1)) {
1030 lp->pktStats.broadcast++;
1031 } else {
1032 lp->pktStats.multicast++;
1033 }
1034 } else if ((*(s16 *) & p[0] == *(s16 *) & dev->dev_addr[0]) &&
1035 (*(s16 *) & p[2] == *(s16 *) & dev->dev_addr[2]) &&
1036 (*(s16 *) & p[4] == *(s16 *) & dev->dev_addr[4])) {
1037 lp->pktStats.unicast++;
1038 }
1039 lp->pktStats.bins[0]++;
1040 if (lp->pktStats.bins[0] == 0) {
1041 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1042 }
1043
1044
1045
1046
1047 skb->protocol = eth_type_trans(skb, dev);
1048 netif_rx(skb);
1049
1050
1051
1052
1053 dev->last_rx = jiffies;
1054 lp->stats.rx_packets++;
1055 lp->stats.rx_bytes += pkt_len;
1056 } else {
1057 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1058 lp->stats.rx_dropped++;
1059 break;
1060 }
1061 }
1062 }
1063
1064
1065
1066 outb(page, EWRK3_FMQ);
1067 } else {
1068 printk("ewrk3_rx(): Illegal page number, page %d\n", page);
1069 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n", inb(EWRK3_CSR), inb(EWRK3_ICR), inb(EWRK3_FMQC));
1070 }
1071 }
1072 return status;
1073}
1074
1075
1076
1077
1078
1079static int ewrk3_tx(struct net_device *dev)
1080{
1081 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
1082 u_long iobase = dev->base_addr;
1083 u_char tx_status;
1084
1085 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1086 if (tx_status & T_VSTS) {
1087 if (tx_status & T_TXE) {
1088 lp->stats.tx_errors++;
1089 if (tx_status & T_NCL)
1090 lp->stats.tx_carrier_errors++;
1091 if (tx_status & T_LCL)
1092 lp->stats.tx_window_errors++;
1093 if (tx_status & T_CTU) {
1094 if ((tx_status & T_COLL) ^ T_XUR) {
1095 lp->pktStats.tx_underruns++;
1096 } else {
1097 lp->pktStats.excessive_underruns++;
1098 }
1099 } else if (tx_status & T_COLL) {
1100 if ((tx_status & T_COLL) ^ T_XCOLL) {
1101 lp->stats.collisions++;
1102 } else {
1103 lp->pktStats.excessive_collisions++;
1104 }
1105 }
1106 } else {
1107 lp->stats.tx_packets++;
1108 }
1109 }
1110 }
1111
1112 return 0;
1113}
1114
1115static int ewrk3_close(struct net_device *dev)
1116{
1117 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
1118 u_long iobase = dev->base_addr;
1119 u_char icr, csr;
1120
1121 netif_stop_queue(dev);
1122
1123 if (ewrk3_debug > 1) {
1124 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1125 dev->name, inb(EWRK3_CSR));
1126 }
1127
1128
1129
1130 DISABLE_IRQs;
1131
1132 STOP_EWRK3;
1133
1134
1135
1136
1137
1138
1139
1140 while (inb(EWRK3_TQ));
1141 while (inb(EWRK3_TDQ));
1142 while (inb(EWRK3_RQ));
1143
1144 if (!lp->hard_strapped) {
1145 free_irq(dev->irq, dev);
1146 }
1147 return 0;
1148}
1149
1150static struct net_device_stats *ewrk3_get_stats(struct net_device *dev)
1151{
1152 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
1153
1154
1155 return &lp->stats;
1156}
1157
1158
1159
1160
1161static void set_multicast_list(struct net_device *dev)
1162{
1163 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
1164 u_long iobase = dev->base_addr;
1165 u_char csr;
1166
1167 csr = inb(EWRK3_CSR);
1168
1169 if (lp->shmem_length == IO_ONLY) {
1170 lp->mctbl = (char *) PAGE0_HTE;
1171 } else {
1172 lp->mctbl = (char *) (lp->shmem_base + PAGE0_HTE);
1173 }
1174
1175 csr &= ~(CSR_PME | CSR_MCE);
1176 if (dev->flags & IFF_PROMISC) {
1177 csr |= CSR_PME;
1178 outb(csr, EWRK3_CSR);
1179 } else {
1180 SetMulticastFilter(dev);
1181 csr |= CSR_MCE;
1182 outb(csr, EWRK3_CSR);
1183 }
1184}
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194static void SetMulticastFilter(struct net_device *dev)
1195{
1196 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
1197 struct dev_mc_list *dmi = dev->mc_list;
1198 u_long iobase = dev->base_addr;
1199 int i;
1200 char *addrs, bit, byte;
1201 short *p = (short *) lp->mctbl;
1202 u16 hashcode;
1203 u32 crc;
1204
1205 spin_lock_irq(&lp->hw_lock);
1206
1207 if (lp->shmem_length == IO_ONLY) {
1208 outb(0, EWRK3_IOPR);
1209 outw(EEPROM_OFFSET(lp->mctbl), EWRK3_PIR1);
1210 } else {
1211 outb(0, EWRK3_MPR);
1212 }
1213
1214 if (dev->flags & IFF_ALLMULTI) {
1215 for (i = 0; i < (HASH_TABLE_LEN >> 3); i++) {
1216 if (lp->shmem_length == IO_ONLY) {
1217 outb(0xff, EWRK3_DATA);
1218 } else {
1219 isa_writew(0xffff, (int) p);
1220 p++;
1221 i++;
1222 }
1223 }
1224 } else {
1225
1226 if (lp->shmem_length == IO_ONLY) {
1227 for (i = 0; i < (HASH_TABLE_LEN >> 4) - 1; i++) {
1228 outb(0x00, EWRK3_DATA);
1229 }
1230 outb(0x80, EWRK3_DATA);
1231 i++;
1232 for (; i < (HASH_TABLE_LEN >> 3); i++) {
1233 outb(0x00, EWRK3_DATA);
1234 }
1235 } else {
1236 isa_memset_io((int) lp->mctbl, 0, (HASH_TABLE_LEN >> 3));
1237 isa_writeb(0x80, (int) (lp->mctbl + (HASH_TABLE_LEN >> 4) - 1));
1238 }
1239
1240
1241 for (i = 0; i < dev->mc_count; i++) {
1242 addrs = dmi->dmi_addr;
1243 dmi = dmi->next;
1244 if ((*addrs & 0x01) == 1) {
1245 crc = ether_crc_le(ETH_ALEN, addrs);
1246 hashcode = crc & ((1 << 9) - 1);
1247
1248 byte = hashcode >> 3;
1249 bit = 1 << (hashcode & 0x07);
1250
1251 if (lp->shmem_length == IO_ONLY) {
1252 u_char tmp;
1253
1254 outw((short) ((long) lp->mctbl) + byte, EWRK3_PIR1);
1255 tmp = inb(EWRK3_DATA);
1256 tmp |= bit;
1257 outw((short) ((long) lp->mctbl) + byte, EWRK3_PIR1);
1258 outb(tmp, EWRK3_DATA);
1259 } else {
1260 isa_writeb(isa_readb((int)(lp->mctbl + byte)) | bit, (int)(lp->mctbl + byte));
1261 }
1262 }
1263 }
1264 }
1265
1266 spin_unlock_irq(&lp->hw_lock);
1267}
1268
1269
1270
1271
1272static void __init isa_probe(struct net_device *dev, u_long ioaddr)
1273{
1274 int i = num_ewrk3s, maxSlots;
1275 u_long iobase;
1276
1277 if (!ioaddr && autoprobed)
1278 return;
1279 if (ioaddr >= 0x400)
1280 return;
1281
1282 if (ioaddr == 0) {
1283 iobase = EWRK3_IO_BASE;
1284 maxSlots = 24;
1285 } else {
1286 iobase = ioaddr;
1287 maxSlots = i + 1;
1288 }
1289
1290 for (; (i < maxSlots) && (dev != NULL); iobase += EWRK3_IOP_INC, i++) {
1291 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1292 if (DevicePresent(iobase) == 0) {
1293 if ((dev = alloc_device(dev, iobase)) != NULL) {
1294 if (ewrk3_hw_init(dev, iobase) == 0) {
1295 num_ewrk3s++;
1296 }
1297 num_eth++;
1298 }
1299 }
1300 } else if (autoprobed) {
1301 printk("%s: region already allocated at 0x%04lx.\n", dev->name, iobase);
1302 }
1303 }
1304
1305 return;
1306}
1307
1308
1309
1310
1311
1312static void __init eisa_probe(struct net_device *dev, u_long ioaddr)
1313{
1314 int i, maxSlots;
1315 u_long iobase;
1316 char name[EWRK3_STRLEN];
1317
1318 if (!ioaddr && autoprobed)
1319 return;
1320 if (ioaddr < 0x1000)
1321 return;
1322
1323 if (ioaddr == 0) {
1324 iobase = EISA_SLOT_INC;
1325 i = 1;
1326 maxSlots = MAX_EISA_SLOTS;
1327 } else {
1328 iobase = ioaddr;
1329 i = (ioaddr >> 12);
1330 maxSlots = i + 1;
1331 }
1332
1333 for (i = 1; (i < maxSlots) && (dev != NULL); i++, iobase += EISA_SLOT_INC) {
1334 if (EISA_signature(name, EISA_ID) == 0) {
1335 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1336 if (DevicePresent(iobase) == 0) {
1337 if ((dev = alloc_device(dev, iobase)) != NULL) {
1338 if (ewrk3_hw_init(dev, iobase) == 0) {
1339 num_ewrk3s++;
1340 }
1341 num_eth++;
1342 }
1343 }
1344 } else if (autoprobed) {
1345 printk("%s: region already allocated at 0x%04lx.\n", dev->name, iobase);
1346 }
1347 }
1348 }
1349
1350 return;
1351}
1352
1353
1354
1355
1356
1357
1358
1359static struct net_device * __init alloc_device(struct net_device *dev, u_long iobase)
1360{
1361 struct net_device *adev = NULL;
1362 int fixed = 0, new_dev = 0;
1363
1364 num_eth = ewrk3_dev_index(dev->name);
1365 if (loading_module)
1366 return dev;
1367
1368 while (1) {
1369 if (((dev->base_addr == EWRK3_NDA) || (dev->base_addr == 0)) && !adev) {
1370 adev = dev;
1371 } else if ((dev->priv == NULL) && (dev->base_addr == iobase)) {
1372 fixed = 1;
1373 } else {
1374 if (dev->next == NULL) {
1375 new_dev = 1;
1376 } else if (strncmp(dev->next->name, "eth", 3) != 0) {
1377 new_dev = 1;
1378 }
1379 }
1380 if ((dev->next == NULL) || new_dev || fixed)
1381 break;
1382 dev = dev->next;
1383 num_eth++;
1384 }
1385 if (adev && !fixed) {
1386 dev = adev;
1387 num_eth = ewrk3_dev_index(dev->name);
1388 new_dev = 0;
1389 }
1390 if (((dev->next == NULL) &&
1391 ((dev->base_addr != EWRK3_NDA) && (dev->base_addr != 0)) && !fixed) ||
1392 new_dev) {
1393 num_eth++;
1394 dev = insert_device(dev, iobase, ewrk3_probe);
1395 }
1396 return dev;
1397}
1398
1399
1400
1401
1402
1403static struct net_device * __init
1404insert_device(struct net_device *dev, u_long iobase, int (*init) (struct net_device *))
1405{
1406 struct net_device *new;
1407
1408 new = (struct net_device *) kmalloc(sizeof(struct net_device) + 8, GFP_KERNEL);
1409 if (new == NULL) {
1410 printk("eth%d: Device not initialised, insufficient memory\n", num_eth);
1411 return NULL;
1412 } else {
1413 new->next = dev->next;
1414 dev->next = new;
1415 dev = dev->next;
1416 if (num_eth > 9999) {
1417 sprintf(dev->name, "eth????");
1418 } else {
1419 sprintf(dev->name, "eth%d", num_eth);
1420 }
1421 dev->base_addr = iobase;
1422 dev->init = init;
1423 }
1424
1425 return dev;
1426}
1427
1428static int __init
1429ewrk3_dev_index(char *s)
1430{
1431 int i = 0, j = 0;
1432
1433 for (; *s; s++) {
1434 if (isdigit(*s)) {
1435 j = 1;
1436 i = (i * 10) + (*s - '0');
1437 } else if (j)
1438 break;
1439 }
1440
1441 return i;
1442}
1443
1444
1445
1446
1447static int Read_EEPROM(u_long iobase, u_char eaddr)
1448{
1449 int i;
1450
1451 outb((eaddr & 0x3f), EWRK3_PIR1);
1452 outb(EEPROM_RD, EWRK3_IOPR);
1453 for (i = 0; i < 5000; i++)
1454 inb(EWRK3_CSR);
1455
1456 return inw(EWRK3_EPROM1);
1457}
1458
1459
1460
1461
1462static int Write_EEPROM(short data, u_long iobase, u_char eaddr)
1463{
1464 int i;
1465
1466 outb(EEPROM_WR_EN, EWRK3_IOPR);
1467 for (i = 0; i < 5000; i++)
1468 inb(EWRK3_CSR);
1469 outw(data, EWRK3_EPROM1);
1470 outb((eaddr & 0x3f), EWRK3_PIR1);
1471 outb(EEPROM_WR, EWRK3_IOPR);
1472 for (i = 0; i < 75000; i++)
1473 inb(EWRK3_CSR);
1474 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1475 for (i = 0; i < 5000; i++)
1476 inb(EWRK3_CSR);
1477
1478 return 0;
1479}
1480
1481
1482
1483
1484static void __init EthwrkSignature(char *name, char *eeprom_image)
1485{
1486 int i;
1487 char *signatures[] = EWRK3_SIGNATURE;
1488
1489 for (i=0; *signatures[i] != '\0'; i++)
1490 if( !strncmp(eeprom_image+EEPROM_PNAME7, signatures[i], strlen(signatures[i])) )
1491 break;
1492
1493 if (*signatures[i] != '\0') {
1494 memcpy(name, eeprom_image+EEPROM_PNAME7, EWRK3_STRLEN);
1495 name[EWRK3_STRLEN] = '\0';
1496 } else
1497 name[0] = '\0';
1498
1499 return;
1500}
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514static int __init DevicePresent(u_long iobase)
1515{
1516 union {
1517 struct {
1518 u32 a;
1519 u32 b;
1520 } llsig;
1521 char Sig[sizeof(u32) << 1];
1522 }
1523 dev;
1524 short sigLength;
1525 char data;
1526 int i, j, status = 0;
1527
1528 dev.llsig.a = ETH_PROM_SIG;
1529 dev.llsig.b = ETH_PROM_SIG;
1530 sigLength = sizeof(u32) << 1;
1531
1532 for (i = 0, j = 0; j < sigLength && i < PROBE_LENGTH + sigLength - 1; i++) {
1533 data = inb(EWRK3_APROM);
1534 if (dev.Sig[j] == data) {
1535 j++;
1536 } else {
1537 if (data == dev.Sig[0]) {
1538 j = 1;
1539 } else {
1540 j = 0;
1541 }
1542 }
1543 }
1544
1545 if (j != sigLength) {
1546 status = -ENODEV;
1547 }
1548 return status;
1549}
1550
1551static u_char __init get_hw_addr(struct net_device *dev, u_char * eeprom_image, char chipType)
1552{
1553 int i, j, k;
1554 u_short chksum;
1555 u_char crc, lfsr, sd, status = 0;
1556 u_long iobase = dev->base_addr;
1557 u16 tmp;
1558
1559 if (chipType == LeMAC2) {
1560 for (crc = 0x6a, j = 0; j < ETH_ALEN; j++) {
1561 sd = dev->dev_addr[j] = eeprom_image[EEPROM_PADDR0 + j];
1562 outb(dev->dev_addr[j], EWRK3_PAR0 + j);
1563 for (k = 0; k < 8; k++, sd >>= 1) {
1564 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1565 crc = (crc >> 1) + lfsr;
1566 }
1567 }
1568 if (crc != eeprom_image[EEPROM_PA_CRC])
1569 status = -1;
1570 } else {
1571 for (i = 0, k = 0; i < ETH_ALEN;) {
1572 k <<= 1;
1573 if (k > 0xffff)
1574 k -= 0xffff;
1575
1576 k += (u_char) (tmp = inb(EWRK3_APROM));
1577 dev->dev_addr[i] = (u_char) tmp;
1578 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1579 i++;
1580 k += (u_short) ((tmp = inb(EWRK3_APROM)) << 8);
1581 dev->dev_addr[i] = (u_char) tmp;
1582 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1583 i++;
1584
1585 if (k > 0xffff)
1586 k -= 0xffff;
1587 }
1588 if (k == 0xffff)
1589 k = 0;
1590 chksum = inb(EWRK3_APROM);
1591 chksum |= (inb(EWRK3_APROM) << 8);
1592 if (k != chksum)
1593 status = -1;
1594 }
1595
1596 return status;
1597}
1598
1599
1600
1601
1602static int __init EISA_signature(char *name, s32 eisa_id)
1603{
1604 u_long i;
1605 char *signatures[] = EWRK3_SIGNATURE;
1606 char ManCode[EWRK3_STRLEN];
1607 union {
1608 s32 ID;
1609 char Id[4];
1610 } Eisa;
1611 int status = 0;
1612
1613 *name = '\0';
1614 for (i = 0; i < 4; i++) {
1615 Eisa.Id[i] = inb(eisa_id + i);
1616 }
1617
1618 ManCode[0] = (((Eisa.Id[0] >> 2) & 0x1f) + 0x40);
1619 ManCode[1] = (((Eisa.Id[1] & 0xe0) >> 5) + ((Eisa.Id[0] & 0x03) << 3) + 0x40);
1620 ManCode[2] = (((Eisa.Id[2] >> 4) & 0x0f) + 0x30);
1621 ManCode[3] = ((Eisa.Id[2] & 0x0f) + 0x30);
1622 ManCode[4] = (((Eisa.Id[3] >> 4) & 0x0f) + 0x30);
1623 ManCode[5] = '\0';
1624
1625 for (i = 0; (*signatures[i] != '\0') && (*name == '\0'); i++) {
1626 if (strstr(ManCode, signatures[i]) != NULL) {
1627 strcpy(name, ManCode);
1628 status = 1;
1629 }
1630 }
1631
1632 return status;
1633}
1634
1635static int ewrk3_ethtool_ioctl(struct net_device *dev, void *useraddr)
1636{
1637 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
1638 u_long iobase = dev->base_addr;
1639 u32 ethcmd;
1640
1641 if (get_user(ethcmd, (u32 *)useraddr))
1642 return -EFAULT;
1643
1644 switch (ethcmd) {
1645
1646
1647 case ETHTOOL_GDRVINFO: {
1648 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1649 int fwrev = Read_EEPROM(dev->base_addr, EEPROM_REVLVL);
1650
1651 strcpy(info.driver, DRV_NAME);
1652 strcpy(info.version, DRV_VERSION);
1653 sprintf(info.fw_version, "%d", fwrev);
1654 strcpy(info.bus_info, "N/A");
1655 info.eedump_len = EEPROM_MAX;
1656 if (copy_to_user(useraddr, &info, sizeof(info)))
1657 return -EFAULT;
1658 return 0;
1659 }
1660
1661
1662 case ETHTOOL_GSET: {
1663 struct ethtool_cmd ecmd = { ETHTOOL_GSET };
1664 u_char cr = inb(EWRK3_CR);
1665
1666 switch (lp->adapter_name[4]) {
1667 case '3':
1668 ecmd.supported = SUPPORTED_BNC;
1669 ecmd.port = PORT_BNC;
1670 break;
1671
1672 case '4':
1673 ecmd.supported = SUPPORTED_TP;
1674 ecmd.port = PORT_TP;
1675 break;
1676
1677 case '5':
1678 ecmd.supported = SUPPORTED_TP | SUPPORTED_BNC | SUPPORTED_AUI;
1679 ecmd.autoneg = !(cr & CR_APD);
1680
1681
1682
1683
1684 if (!ecmd.autoneg)
1685 ecmd.port = (cr & CR_PSEL) ? PORT_BNC : PORT_TP;
1686 break;
1687 }
1688
1689 ecmd.supported |= SUPPORTED_10baseT_Half;
1690 ecmd.speed = SPEED_10;
1691 ecmd.duplex = DUPLEX_HALF;
1692
1693 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
1694 return -EFAULT;
1695 return 0;
1696 }
1697
1698
1699 case ETHTOOL_SSET: {
1700 struct ethtool_cmd ecmd;
1701 u_char cr;
1702 u_long flags;
1703
1704
1705 if (lp->adapter_name[4] != '5')
1706 return -EOPNOTSUPP;
1707
1708 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
1709 return -EFAULT;
1710
1711
1712 if (ecmd.speed != SPEED_10)
1713 return -EINVAL;
1714 if (ecmd.port != PORT_TP && ecmd.port != PORT_BNC)
1715 return -EINVAL;
1716 if (ecmd.transceiver != XCVR_INTERNAL)
1717 return -EINVAL;
1718 if (ecmd.duplex != DUPLEX_HALF)
1719 return -EINVAL;
1720 if (ecmd.phy_address != 0)
1721 return -EINVAL;
1722
1723 spin_lock_irqsave(&lp->hw_lock, flags);
1724 cr = inb(EWRK3_CR);
1725
1726
1727
1728 if (ecmd.autoneg) {
1729 cr &= ~CR_APD;
1730 } else {
1731 cr |= CR_APD;
1732 if (ecmd.port == PORT_TP)
1733 cr &= ~CR_PSEL;
1734 else
1735 cr |= CR_PSEL;
1736 }
1737
1738
1739 outb(cr, EWRK3_CR);
1740
1741 spin_unlock_irqrestore(&lp->hw_lock, flags);
1742 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
1743 return -EFAULT;
1744 return 0;
1745 }
1746
1747
1748 case ETHTOOL_GLINK: {
1749 struct ethtool_value edata = { ETHTOOL_GLINK };
1750 u_char cmr = inb(EWRK3_CMR);
1751
1752
1753 if (lp->adapter_name[4] == '3')
1754 return -EOPNOTSUPP;
1755
1756
1757
1758 edata.data = !(cmr & CMR_LINK);
1759
1760 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1761 return -EFAULT;
1762 return 0;
1763 }
1764
1765
1766 case ETHTOOL_PHYS_ID: {
1767 struct ethtool_value edata;
1768 u_long flags;
1769 u_char cr;
1770 int count;
1771
1772 if (copy_from_user(&edata, useraddr, sizeof(edata)))
1773 return -EFAULT;
1774
1775
1776 count = edata.data << 2;
1777
1778 spin_lock_irqsave(&lp->hw_lock, flags);
1779
1780
1781 if (lp->led_mask == 0) {
1782 spin_unlock_irqrestore(&lp->hw_lock, flags);
1783 return -EBUSY;
1784 }
1785
1786
1787 lp->led_mask = 0;
1788
1789 while (count--) {
1790
1791 cr = inb(EWRK3_CR);
1792 outb(cr ^ CR_LED, EWRK3_CR);
1793
1794
1795 spin_unlock_irqrestore(&lp->hw_lock, flags);
1796 set_current_state(TASK_UNINTERRUPTIBLE);
1797 schedule_timeout(HZ>>2);
1798 spin_lock_irqsave(&lp->hw_lock, flags);
1799
1800
1801 if (signal_pending(current))
1802 break;
1803 }
1804
1805 lp->led_mask = CR_LED;
1806 cr = inb(EWRK3_CR);
1807 outb(cr & ~CR_LED, EWRK3_CR);
1808 spin_unlock_irqrestore(&lp->hw_lock, flags);
1809 return signal_pending(current) ? -ERESTARTSYS : 0;
1810 }
1811
1812 }
1813
1814 return -EOPNOTSUPP;
1815}
1816
1817
1818
1819
1820
1821static int ewrk3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1822{
1823 struct ewrk3_private *lp = (struct ewrk3_private *) dev->priv;
1824 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1825 u_long iobase = dev->base_addr;
1826 int i, j, status = 0;
1827 u_char csr;
1828 unsigned long flags;
1829 union ewrk3_addr {
1830 u_char addr[HASH_TABLE_LEN * ETH_ALEN];
1831 u_short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1832 };
1833
1834 union ewrk3_addr *tmp;
1835
1836
1837 if (cmd == SIOCETHTOOL)
1838 return ewrk3_ethtool_ioctl(dev, (void *)rq->ifr_data);
1839
1840
1841 if (cmd != EWRK3IOCTL)
1842 return -EOPNOTSUPP;
1843
1844 tmp = kmalloc(sizeof(union ewrk3_addr), GFP_KERNEL);
1845 if(tmp==NULL)
1846 return -ENOMEM;
1847
1848 switch (ioc->cmd) {
1849 case EWRK3_GET_HWADDR:
1850 for (i = 0; i < ETH_ALEN; i++) {
1851 tmp->addr[i] = dev->dev_addr[i];
1852 }
1853 ioc->len = ETH_ALEN;
1854 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1855 status = -EFAULT;
1856 break;
1857
1858 case EWRK3_SET_HWADDR:
1859 if (capable(CAP_NET_ADMIN)) {
1860 spin_lock_irqsave(&lp->hw_lock, flags);
1861 csr = inb(EWRK3_CSR);
1862 csr |= (CSR_TXD | CSR_RXD);
1863 outb(csr, EWRK3_CSR);
1864 spin_unlock_irqrestore(&lp->hw_lock, flags);
1865
1866 if (copy_from_user(tmp->addr, ioc->data, ETH_ALEN)) {
1867 status = -EFAULT;
1868 break;
1869 }
1870 spin_lock_irqsave(&lp->hw_lock, flags);
1871 for (i = 0; i < ETH_ALEN; i++) {
1872 dev->dev_addr[i] = tmp->addr[i];
1873 outb(tmp->addr[i], EWRK3_PAR0 + i);
1874 }
1875
1876 csr = inb(EWRK3_CSR);
1877 csr &= ~(CSR_TXD | CSR_RXD);
1878 outb(csr, EWRK3_CSR);
1879 spin_unlock_irqrestore(&lp->hw_lock, flags);
1880 } else {
1881 status = -EPERM;
1882 }
1883
1884 break;
1885 case EWRK3_SET_PROM:
1886 if (capable(CAP_NET_ADMIN)) {
1887 spin_lock_irqsave(&lp->hw_lock, flags);
1888 csr = inb(EWRK3_CSR);
1889 csr |= CSR_PME;
1890 csr &= ~CSR_MCE;
1891 outb(csr, EWRK3_CSR);
1892 spin_unlock_irqrestore(&lp->hw_lock, flags);
1893 } else {
1894 status = -EPERM;
1895 }
1896
1897 break;
1898 case EWRK3_CLR_PROM:
1899 if (capable(CAP_NET_ADMIN)) {
1900 spin_lock_irqsave(&lp->hw_lock, flags);
1901 csr = inb(EWRK3_CSR);
1902 csr &= ~CSR_PME;
1903 outb(csr, EWRK3_CSR);
1904 spin_unlock_irqrestore(&lp->hw_lock, flags);
1905 } else {
1906 status = -EPERM;
1907 }
1908
1909 break;
1910 case EWRK3_GET_MCA:
1911 spin_lock_irqsave(&lp->hw_lock, flags);
1912 if (lp->shmem_length == IO_ONLY) {
1913 outb(0, EWRK3_IOPR);
1914 outw(PAGE0_HTE, EWRK3_PIR1);
1915 for (i = 0; i < (HASH_TABLE_LEN >> 3); i++) {
1916 tmp->addr[i] = inb(EWRK3_DATA);
1917 }
1918 } else {
1919 outb(0, EWRK3_MPR);
1920 isa_memcpy_fromio(tmp->addr, lp->shmem_base + PAGE0_HTE, (HASH_TABLE_LEN >> 3));
1921 }
1922 spin_unlock_irqrestore(&lp->hw_lock, flags);
1923
1924 ioc->len = (HASH_TABLE_LEN >> 3);
1925 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1926 status = -EFAULT;
1927
1928 break;
1929 case EWRK3_SET_MCA:
1930 if (capable(CAP_NET_ADMIN)) {
1931 if (ioc->len > 1024)
1932 {
1933 status = -EINVAL;
1934 break;
1935 }
1936 if (copy_from_user(tmp->addr, ioc->data, ETH_ALEN * ioc->len)) {
1937 status = -EFAULT;
1938 break;
1939 }
1940 set_multicast_list(dev);
1941 } else {
1942 status = -EPERM;
1943 }
1944
1945 break;
1946 case EWRK3_CLR_MCA:
1947 if (capable(CAP_NET_ADMIN)) {
1948 set_multicast_list(dev);
1949 } else {
1950 status = -EPERM;
1951 }
1952
1953 break;
1954 case EWRK3_MCA_EN:
1955 if (capable(CAP_NET_ADMIN)) {
1956 spin_lock_irqsave(&lp->hw_lock, flags);
1957 csr = inb(EWRK3_CSR);
1958 csr |= CSR_MCE;
1959 csr &= ~CSR_PME;
1960 outb(csr, EWRK3_CSR);
1961 spin_unlock_irqrestore(&lp->hw_lock, flags);
1962 } else {
1963 status = -EPERM;
1964 }
1965
1966 break;
1967 case EWRK3_GET_STATS: {
1968 struct ewrk3_stats *tmp_stats =
1969 kmalloc(sizeof(lp->pktStats), GFP_KERNEL);
1970 if (!tmp_stats) {
1971 status = -ENOMEM;
1972 break;
1973 }
1974
1975 spin_lock_irqsave(&lp->hw_lock, flags);
1976 memcpy(tmp_stats, &lp->pktStats, sizeof(lp->pktStats));
1977 spin_unlock_irqrestore(&lp->hw_lock, flags);
1978
1979 ioc->len = sizeof(lp->pktStats);
1980 if (copy_to_user(ioc->data, tmp_stats, sizeof(lp->pktStats)))
1981 status = -EFAULT;
1982 kfree(tmp_stats);
1983 break;
1984 }
1985 case EWRK3_CLR_STATS:
1986 if (capable(CAP_NET_ADMIN)) {
1987 spin_lock_irqsave(&lp->hw_lock, flags);
1988 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1989 spin_unlock_irqrestore(&lp->hw_lock,flags);
1990 } else {
1991 status = -EPERM;
1992 }
1993
1994 break;
1995 case EWRK3_GET_CSR:
1996 tmp->addr[0] = inb(EWRK3_CSR);
1997 ioc->len = 1;
1998 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
1999 status = -EFAULT;
2000 break;
2001 case EWRK3_SET_CSR:
2002 if (capable(CAP_NET_ADMIN)) {
2003 if (copy_from_user(tmp->addr, ioc->data, 1)) {
2004 status = -EFAULT;
2005 break;
2006 }
2007 outb(tmp->addr[0], EWRK3_CSR);
2008 } else {
2009 status = -EPERM;
2010 }
2011
2012 break;
2013 case EWRK3_GET_EEPROM:
2014 if (capable(CAP_NET_ADMIN)) {
2015 for (i = 0; i < (EEPROM_MAX >> 1); i++) {
2016 tmp->val[i] = (short) Read_EEPROM(iobase, i);
2017 }
2018 i = EEPROM_MAX;
2019 tmp->addr[i++] = inb(EWRK3_CMR);
2020 for (j = 0; j < ETH_ALEN; j++) {
2021 tmp->addr[i++] = inb(EWRK3_PAR0 + j);
2022 }
2023 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
2024 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
2025 status = -EFAULT;
2026 } else {
2027 status = -EPERM;
2028 }
2029
2030 break;
2031 case EWRK3_SET_EEPROM:
2032 if (capable(CAP_NET_ADMIN)) {
2033 if (copy_from_user(tmp->addr, ioc->data, EEPROM_MAX)) {
2034 status = -EFAULT;
2035 break;
2036 }
2037 for (i = 0; i < (EEPROM_MAX >> 1); i++) {
2038 Write_EEPROM(tmp->val[i], iobase, i);
2039 }
2040 } else {
2041 status = -EPERM;
2042 }
2043
2044 break;
2045 case EWRK3_GET_CMR:
2046 tmp->addr[0] = inb(EWRK3_CMR);
2047 ioc->len = 1;
2048 if (copy_to_user(ioc->data, tmp->addr, ioc->len))
2049 status = -EFAULT;
2050 break;
2051 case EWRK3_SET_TX_CUT_THRU:
2052 if (capable(CAP_NET_ADMIN)) {
2053 lp->txc = 1;
2054 } else {
2055 status = -EPERM;
2056 }
2057
2058 break;
2059 case EWRK3_CLR_TX_CUT_THRU:
2060 if (capable(CAP_NET_ADMIN)) {
2061 lp->txc = 0;
2062 } else {
2063 status = -EPERM;
2064 }
2065
2066 break;
2067 default:
2068 status = -EOPNOTSUPP;
2069 }
2070 kfree(tmp);
2071 return status;
2072}
2073
2074#ifdef MODULE
2075static struct net_device *ewrk3_devs[MAX_NUM_EWRK3S];
2076static int ndevs;
2077static int io[MAX_NUM_EWRK3S+1] = { 0x300, 0, };
2078static int irq[MAX_NUM_EWRK3S+1] = { 5, 0, };
2079
2080
2081MODULE_PARM(io, "0-21i");
2082MODULE_PARM(irq, "0-21i");
2083MODULE_PARM_DESC(io, "EtherWORKS 3 I/O base address(es)");
2084MODULE_PARM_DESC(irq, "EtherWORKS 3 IRQ number(s)");
2085
2086static void ewrk3_exit_module(void)
2087{
2088 int i;
2089
2090 for( i=0; i<ndevs; i++ ) {
2091 unregister_netdev(ewrk3_devs[i]);
2092 if (ewrk3_devs[i]->priv) {
2093 kfree(ewrk3_devs[i]->priv);
2094 ewrk3_devs[i]->priv = NULL;
2095 }
2096 ewrk3_devs[i]->irq = 0;
2097
2098 release_region(ewrk3_devs[i]->base_addr, EWRK3_TOTAL_SIZE);
2099 free_netdev(ewrk3_devs[i]);
2100 ewrk3_devs[i] = NULL;
2101 }
2102}
2103
2104static int ewrk3_init_module(void)
2105{
2106 int i=0;
2107
2108 while( io[i] && irq[i] ) {
2109 ewrk3_devs[ndevs] = kmalloc(sizeof(struct net_device), GFP_KERNEL);
2110 if (!ewrk3_devs[ndevs])
2111 goto error;
2112 memset(ewrk3_devs[ndevs], 0, sizeof(struct net_device));
2113 ewrk3_devs[ndevs]->base_addr = io[i];
2114 ewrk3_devs[ndevs]->irq = irq[i];
2115 ewrk3_devs[ndevs]->init = ewrk3_probe;
2116
2117 if (register_netdev(ewrk3_devs[ndevs]) == 0)
2118 ndevs++;
2119 else
2120 kfree(ewrk3_devs[ndevs]);
2121
2122 i++;
2123 }
2124
2125 return ndevs ? 0 : -EIO;
2126
2127error:
2128 ewrk3_exit_module();
2129 return -ENOMEM;
2130}
2131
2132
2133
2134module_exit(ewrk3_exit_module);
2135module_init(ewrk3_init_module);
2136#endif
2137MODULE_LICENSE("GPL");
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148