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52#define DRV_NAME "D-Link DL2000-based linux driver"
53#define DRV_VERSION "v1.17a"
54#define DRV_RELDATE "2002/10/04"
55#include "dl2k.h"
56
57static char version[] __devinitdata =
58 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
59#define MAX_UNITS 8
60static int mtu[MAX_UNITS];
61static int vlan[MAX_UNITS];
62static int jumbo[MAX_UNITS];
63static char *media[MAX_UNITS];
64static int tx_flow=-1;
65static int rx_flow=-1;
66static int copy_thresh;
67static int rx_coalesce=10;
68static int rx_timeout=200;
69static int tx_coalesce=16;
70
71
72MODULE_AUTHOR ("Edward Peng");
73MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
74MODULE_LICENSE("GPL");
75MODULE_PARM (mtu, "1-" __MODULE_STRING (MAX_UNITS) "i");
76MODULE_PARM (media, "1-" __MODULE_STRING (MAX_UNITS) "s");
77MODULE_PARM (vlan, "1-" __MODULE_STRING (MAX_UNITS) "i");
78MODULE_PARM (jumbo, "1-" __MODULE_STRING (MAX_UNITS) "i");
79MODULE_PARM (tx_flow, "i");
80MODULE_PARM (rx_flow, "i");
81MODULE_PARM (copy_thresh, "i");
82MODULE_PARM (rx_coalesce, "i");
83MODULE_PARM (rx_timeout, "i");
84MODULE_PARM (tx_coalesce, "i");
85
86
87
88#define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
89 UpdateStats | LinkEvent)
90#define EnableInt() \
91writew(DEFAULT_INTR, ioaddr + IntEnable)
92
93static int max_intrloop = 50;
94static int multicast_filter_limit = 0x40;
95
96static int rio_open (struct net_device *dev);
97static void rio_timer (unsigned long data);
98static void rio_tx_timeout (struct net_device *dev);
99static void alloc_list (struct net_device *dev);
100static int start_xmit (struct sk_buff *skb, struct net_device *dev);
101static irqreturn_t rio_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
102static void rio_free_tx (struct net_device *dev, int irq);
103static void tx_error (struct net_device *dev, int tx_status);
104static int receive_packet (struct net_device *dev);
105static void rio_error (struct net_device *dev, int int_status);
106static int change_mtu (struct net_device *dev, int new_mtu);
107static void set_multicast (struct net_device *dev);
108static struct net_device_stats *get_stats (struct net_device *dev);
109static int clear_stats (struct net_device *dev);
110static int rio_ethtool_ioctl (struct net_device *dev, void *useraddr);
111static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
112static int rio_close (struct net_device *dev);
113static int find_miiphy (struct net_device *dev);
114static int parse_eeprom (struct net_device *dev);
115static int read_eeprom (long ioaddr, int eep_addr);
116static int mii_wait_link (struct net_device *dev, int wait);
117static int mii_set_media (struct net_device *dev);
118static int mii_get_media (struct net_device *dev);
119static int mii_set_media_pcs (struct net_device *dev);
120static int mii_get_media_pcs (struct net_device *dev);
121static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
122static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
123 u16 data);
124
125static int __devinit
126rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
127{
128 struct net_device *dev;
129 struct netdev_private *np;
130 static int card_idx;
131 int chip_idx = ent->driver_data;
132 int err, irq;
133 long ioaddr;
134 static int version_printed;
135 void *ring_space;
136 dma_addr_t ring_dma;
137
138 if (!version_printed++)
139 printk ("%s", version);
140
141 err = pci_enable_device (pdev);
142 if (err)
143 return err;
144
145 irq = pdev->irq;
146 err = pci_request_regions (pdev, "dl2k");
147 if (err)
148 goto err_out_disable;
149
150 pci_set_master (pdev);
151 dev = alloc_etherdev (sizeof (*np));
152 if (!dev) {
153 err = -ENOMEM;
154 goto err_out_res;
155 }
156 SET_MODULE_OWNER (dev);
157 SET_NETDEV_DEV(dev, &pdev->dev);
158
159#ifdef MEM_MAPPING
160 ioaddr = pci_resource_start (pdev, 1);
161 ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
162 if (!ioaddr) {
163 err = -ENOMEM;
164 goto err_out_dev;
165 }
166#else
167 ioaddr = pci_resource_start (pdev, 0);
168#endif
169 dev->base_addr = ioaddr;
170 dev->irq = irq;
171 np = dev->priv;
172 np->chip_id = chip_idx;
173 np->pdev = pdev;
174 spin_lock_init (&np->tx_lock);
175 spin_lock_init (&np->rx_lock);
176
177
178 np->an_enable = 1;
179 np->tx_coalesce = 1;
180 if (card_idx < MAX_UNITS) {
181 if (media[card_idx] != NULL) {
182 np->an_enable = 0;
183 if (strcmp (media[card_idx], "auto") == 0 ||
184 strcmp (media[card_idx], "autosense") == 0 ||
185 strcmp (media[card_idx], "0") == 0 ) {
186 np->an_enable = 2;
187 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
188 strcmp (media[card_idx], "4") == 0) {
189 np->speed = 100;
190 np->full_duplex = 1;
191 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
192 || strcmp (media[card_idx], "3") == 0) {
193 np->speed = 100;
194 np->full_duplex = 0;
195 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
196 strcmp (media[card_idx], "2") == 0) {
197 np->speed = 10;
198 np->full_duplex = 1;
199 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
200 strcmp (media[card_idx], "1") == 0) {
201 np->speed = 10;
202 np->full_duplex = 0;
203 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
204 strcmp (media[card_idx], "6") == 0) {
205 np->speed=1000;
206 np->full_duplex=1;
207 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
208 strcmp (media[card_idx], "5") == 0) {
209 np->speed = 1000;
210 np->full_duplex = 0;
211 } else {
212 np->an_enable = 1;
213 }
214 }
215 if (jumbo[card_idx] != 0) {
216 np->jumbo = 1;
217 dev->mtu = MAX_JUMBO;
218 } else {
219 np->jumbo = 0;
220 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
221 dev->mtu = mtu[card_idx];
222 }
223 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
224 vlan[card_idx] : 0;
225 if (rx_coalesce > 0 && rx_timeout > 0) {
226 np->rx_coalesce = rx_coalesce;
227 np->rx_timeout = rx_timeout;
228 np->coalesce = 1;
229 }
230 np->tx_flow = (tx_flow == 0) ? 0 : 1;
231 np->rx_flow = (rx_flow == 0) ? 0 : 1;
232
233 if (tx_coalesce < 1)
234 tx_coalesce = 1;
235 else if (tx_coalesce > TX_RING_SIZE-1)
236 tx_coalesce = TX_RING_SIZE - 1;
237 }
238 dev->open = &rio_open;
239 dev->hard_start_xmit = &start_xmit;
240 dev->stop = &rio_close;
241 dev->get_stats = &get_stats;
242 dev->set_multicast_list = &set_multicast;
243 dev->do_ioctl = &rio_ioctl;
244 dev->tx_timeout = &rio_tx_timeout;
245 dev->watchdog_timeo = TX_TIMEOUT;
246 dev->change_mtu = &change_mtu;
247#if 0
248 dev->features = NETIF_F_IP_CSUM;
249#endif
250 pci_set_drvdata (pdev, dev);
251
252 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
253 if (!ring_space)
254 goto err_out_iounmap;
255 np->tx_ring = (struct netdev_desc *) ring_space;
256 np->tx_ring_dma = ring_dma;
257
258 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
259 if (!ring_space)
260 goto err_out_unmap_tx;
261 np->rx_ring = (struct netdev_desc *) ring_space;
262 np->rx_ring_dma = ring_dma;
263
264
265 parse_eeprom (dev);
266
267
268 err = find_miiphy (dev);
269 if (err)
270 goto err_out_unmap_rx;
271
272
273 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
274 np->link_status = 0;
275
276 if (np->phy_media) {
277
278 if (np->an_enable == 2) {
279 np->an_enable = 1;
280 }
281 mii_set_media_pcs (dev);
282 } else {
283
284
285 if (np->speed == 1000)
286 np->an_enable = 1;
287 mii_set_media (dev);
288 }
289 pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
290
291 err = register_netdev (dev);
292 if (err)
293 goto err_out_unmap_rx;
294
295 card_idx++;
296
297 printk (KERN_INFO "%s: %s, %02x:%02x:%02x:%02x:%02x:%02x, IRQ %d\n",
298 dev->name, np->name,
299 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
300 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], irq);
301 if (tx_coalesce > 1)
302 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
303 tx_coalesce);
304 if (np->coalesce)
305 printk(KERN_INFO "rx_coalesce:\t%d packets\n"
306 KERN_INFO "rx_timeout: \t%d ns\n",
307 np->rx_coalesce, np->rx_timeout*640);
308 if (np->vlan)
309 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
310 return 0;
311
312 err_out_unmap_rx:
313 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
314 err_out_unmap_tx:
315 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
316 err_out_iounmap:
317#ifdef MEM_MAPPING
318 iounmap ((void *) ioaddr);
319
320 err_out_dev:
321#endif
322 free_netdev (dev);
323
324 err_out_res:
325 pci_release_regions (pdev);
326
327 err_out_disable:
328 pci_disable_device (pdev);
329 return err;
330}
331
332int
333find_miiphy (struct net_device *dev)
334{
335 int i, phy_found = 0;
336 struct netdev_private *np;
337 long ioaddr;
338 np = dev->priv;
339 ioaddr = dev->base_addr;
340 np->phy_addr = 1;
341
342 for (i = 31; i >= 0; i--) {
343 int mii_status = mii_read (dev, i, 1);
344 if (mii_status != 0xffff && mii_status != 0x0000) {
345 np->phy_addr = i;
346 phy_found++;
347 }
348 }
349 if (!phy_found) {
350 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
351 return -ENODEV;
352 }
353 return 0;
354}
355
356int
357parse_eeprom (struct net_device *dev)
358{
359 int i, j;
360 long ioaddr = dev->base_addr;
361 u8 sromdata[256];
362 u8 *psib;
363 u32 crc;
364 PSROM_t psrom = (PSROM_t) sromdata;
365 struct netdev_private *np = dev->priv;
366
367 int cid, next;
368
369#ifdef MEM_MAPPING
370 ioaddr = pci_resource_start (np->pdev, 0);
371#endif
372
373 for (i = 0; i < 128; i++) {
374 ((u16 *) sromdata)[i] = le16_to_cpu (read_eeprom (ioaddr, i));
375 }
376#ifdef MEM_MAPPING
377 ioaddr = dev->base_addr;
378#endif
379
380 crc = ~ether_crc_le (256 - 4, sromdata);
381 if (psrom->crc != crc) {
382 printk (KERN_ERR "%s: EEPROM data CRC error.\n", dev->name);
383 return -1;
384 }
385
386
387 for (i = 0; i < 6; i++)
388 dev->dev_addr[i] = psrom->mac_addr[i];
389
390
391 i = 0x30;
392 psib = (u8 *) sromdata;
393 do {
394 cid = psib[i++];
395 next = psib[i++];
396 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
397 printk (KERN_ERR "Cell data error\n");
398 return -1;
399 }
400 switch (cid) {
401 case 0:
402 break;
403 case 1:
404 return 0;
405 case 2:
406 np->duplex_polarity = psib[i];
407 writeb (readb (ioaddr + PhyCtrl) | psib[i],
408 ioaddr + PhyCtrl);
409 break;
410 case 3:
411 np->wake_polarity = psib[i];
412 break;
413 case 9:
414 j = (next - i > 255) ? 255 : next - i;
415 memcpy (np->name, &(psib[i]), j);
416 break;
417 case 4:
418 case 5:
419 case 6:
420 case 7:
421 case 8:
422 break;
423 default:
424 return -1;
425 }
426 i = next;
427 } while (1);
428
429 return 0;
430}
431
432static int
433rio_open (struct net_device *dev)
434{
435 struct netdev_private *np = dev->priv;
436 long ioaddr = dev->base_addr;
437 int i;
438 u16 macctrl;
439
440 i = request_irq (dev->irq, &rio_interrupt, SA_SHIRQ, dev->name, dev);
441 if (i)
442 return i;
443
444
445 writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
446 ioaddr + ASICCtrl + 2);
447 mdelay(10);
448
449
450 writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
451
452
453 if (np->jumbo != 0)
454 writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
455
456 alloc_list (dev);
457
458
459 for (i = 0; i < 6; i++)
460 writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
461
462 set_multicast (dev);
463 if (np->coalesce) {
464 writel (np->rx_coalesce | np->rx_timeout << 16,
465 ioaddr + RxDMAIntCtrl);
466 }
467
468 writeb (0x20, ioaddr + RxDMAPollPeriod);
469 writeb (0xff, ioaddr + TxDMAPollPeriod);
470 writeb (0x30, ioaddr + RxDMABurstThresh);
471 writeb (0x30, ioaddr + RxDMAUrgentThresh);
472 writel (0x0007ffff, ioaddr + RmonStatMask);
473
474 clear_stats (dev);
475
476
477 if (np->vlan) {
478
479 writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
480 ioaddr + RxDMAIntCtrl);
481
482 writew (np->vlan, ioaddr + VLANId);
483
484 writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
485
486
487 writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
488 ioaddr + MACCtrl);
489 }
490
491 init_timer (&np->timer);
492 np->timer.expires = jiffies + 1*HZ;
493 np->timer.data = (unsigned long) dev;
494 np->timer.function = &rio_timer;
495 add_timer (&np->timer);
496
497
498 writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
499 ioaddr + MACCtrl);
500
501 macctrl = 0;
502 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
503 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
504 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
505 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
506 writew(macctrl, ioaddr + MACCtrl);
507
508 netif_start_queue (dev);
509
510
511 EnableInt ();
512 return 0;
513}
514
515static void
516rio_timer (unsigned long data)
517{
518 struct net_device *dev = (struct net_device *)data;
519 struct netdev_private *np = dev->priv;
520 unsigned int entry;
521 int next_tick = 1*HZ;
522 unsigned long flags;
523
524 spin_lock_irqsave(&np->rx_lock, flags);
525
526 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
527 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
528
529 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
530 struct sk_buff *skb;
531 entry = np->old_rx % RX_RING_SIZE;
532
533 if (np->rx_skbuff[entry] == NULL) {
534 skb = dev_alloc_skb (np->rx_buf_sz);
535 if (skb == NULL) {
536 np->rx_ring[entry].fraginfo = 0;
537 printk (KERN_INFO
538 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
539 dev->name, entry);
540 break;
541 }
542 np->rx_skbuff[entry] = skb;
543 skb->dev = dev;
544
545 skb_reserve (skb, 2);
546 np->rx_ring[entry].fraginfo =
547 cpu_to_le64 (pci_map_single
548 (np->pdev, skb->tail, np->rx_buf_sz,
549 PCI_DMA_FROMDEVICE));
550 }
551 np->rx_ring[entry].fraginfo |=
552 cpu_to_le64 (np->rx_buf_sz) << 48;
553 np->rx_ring[entry].status = 0;
554 }
555 }
556 spin_unlock_irqrestore (&np->rx_lock, flags);
557 np->timer.expires = jiffies + next_tick;
558 add_timer(&np->timer);
559}
560
561static void
562rio_tx_timeout (struct net_device *dev)
563{
564 long ioaddr = dev->base_addr;
565
566 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
567 dev->name, readl (ioaddr + TxStatus));
568 rio_free_tx(dev, 0);
569 dev->if_port = 0;
570 dev->trans_start = jiffies;
571}
572
573
574static void
575alloc_list (struct net_device *dev)
576{
577 struct netdev_private *np = dev->priv;
578 int i;
579
580 np->cur_rx = np->cur_tx = 0;
581 np->old_rx = np->old_tx = 0;
582 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
583
584
585 for (i = 0; i < TX_RING_SIZE; i++) {
586 np->tx_skbuff[i] = 0;
587 np->tx_ring[i].status = cpu_to_le64 (TFDDone);
588 np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
589 ((i+1)%TX_RING_SIZE) *
590 sizeof (struct netdev_desc));
591 }
592
593
594 for (i = 0; i < RX_RING_SIZE; i++) {
595 np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
596 ((i + 1) % RX_RING_SIZE) *
597 sizeof (struct netdev_desc));
598 np->rx_ring[i].status = 0;
599 np->rx_ring[i].fraginfo = 0;
600 np->rx_skbuff[i] = 0;
601 }
602
603
604 for (i = 0; i < RX_RING_SIZE; i++) {
605
606 struct sk_buff *skb = dev_alloc_skb (np->rx_buf_sz);
607 np->rx_skbuff[i] = skb;
608 if (skb == NULL) {
609 printk (KERN_ERR
610 "%s: alloc_list: allocate Rx buffer error! ",
611 dev->name);
612 break;
613 }
614 skb->dev = dev;
615 skb_reserve (skb, 2);
616
617 np->rx_ring[i].fraginfo =
618 cpu_to_le64 ( pci_map_single (
619 np->pdev, skb->tail, np->rx_buf_sz,
620 PCI_DMA_FROMDEVICE));
621 np->rx_ring[i].fraginfo |= cpu_to_le64 (np->rx_buf_sz) << 48;
622 }
623
624
625 writel (cpu_to_le32 (np->rx_ring_dma), dev->base_addr + RFDListPtr0);
626 writel (0, dev->base_addr + RFDListPtr1);
627
628 return;
629}
630
631static int
632start_xmit (struct sk_buff *skb, struct net_device *dev)
633{
634 struct netdev_private *np = dev->priv;
635 struct netdev_desc *txdesc;
636 unsigned entry;
637 u32 ioaddr;
638 u64 tfc_vlan_tag = 0;
639
640 if (np->link_status == 0) {
641 dev_kfree_skb(skb);
642 return 0;
643 }
644 ioaddr = dev->base_addr;
645 entry = np->cur_tx % TX_RING_SIZE;
646 np->tx_skbuff[entry] = skb;
647 txdesc = &np->tx_ring[entry];
648
649#if 0
650 if (skb->ip_summed == CHECKSUM_HW) {
651 txdesc->status |=
652 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
653 IPChecksumEnable);
654 }
655#endif
656 if (np->vlan) {
657 tfc_vlan_tag =
658 cpu_to_le64 (VLANTagInsert) |
659 (cpu_to_le64 (np->vlan) << 32) |
660 (cpu_to_le64 (skb->priority) << 45);
661 }
662 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
663 skb->len,
664 PCI_DMA_TODEVICE));
665 txdesc->fraginfo |= cpu_to_le64 (skb->len) << 48;
666
667
668
669 if (entry % np->tx_coalesce == 0 || np->speed == 10)
670 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
671 WordAlignDisable |
672 TxDMAIndicate |
673 (1 << FragCountShift));
674 else
675 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
676 WordAlignDisable |
677 (1 << FragCountShift));
678
679
680 writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
681
682 writel(10000, ioaddr + CountDown);
683 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
684 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
685 < TX_QUEUE_LEN - 1 && np->speed != 10) {
686
687 } else if (!netif_queue_stopped(dev)) {
688 netif_stop_queue (dev);
689 }
690
691
692 if (readl (dev->base_addr + TFDListPtr0) == 0) {
693 writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
694 dev->base_addr + TFDListPtr0);
695 writel (0, dev->base_addr + TFDListPtr1);
696 }
697
698
699 dev->trans_start = jiffies;
700 return 0;
701}
702
703static irqreturn_t
704rio_interrupt (int irq, void *dev_instance, struct pt_regs *rgs)
705{
706 struct net_device *dev = dev_instance;
707 struct netdev_private *np;
708 unsigned int_status;
709 long ioaddr;
710 int cnt = max_intrloop;
711 int handled = 0;
712
713 ioaddr = dev->base_addr;
714 np = dev->priv;
715 while (1) {
716 int_status = readw (ioaddr + IntStatus);
717 writew (int_status, ioaddr + IntStatus);
718 int_status &= DEFAULT_INTR;
719 if (int_status == 0 || --cnt < 0)
720 break;
721 handled = 1;
722
723 if (int_status & RxDMAComplete)
724 receive_packet (dev);
725
726 if ((int_status & (TxDMAComplete|IntRequested))) {
727 int tx_status;
728 tx_status = readl (ioaddr + TxStatus);
729 if (tx_status & 0x01)
730 tx_error (dev, tx_status);
731
732 rio_free_tx (dev, 1);
733 }
734
735
736 if (int_status &
737 (HostError | LinkEvent | UpdateStats))
738 rio_error (dev, int_status);
739 }
740 if (np->cur_tx != np->old_tx)
741 writel (100, ioaddr + CountDown);
742 return IRQ_RETVAL(handled);
743}
744
745static void
746rio_free_tx (struct net_device *dev, int irq)
747{
748 struct netdev_private *np = (struct netdev_private *) dev->priv;
749 int entry = np->old_tx % TX_RING_SIZE;
750 int tx_use = 0;
751 unsigned long flag = 0;
752
753 if (irq)
754 spin_lock(&np->tx_lock);
755 else
756 spin_lock_irqsave(&np->tx_lock, flag);
757
758
759 while (entry != np->cur_tx) {
760 struct sk_buff *skb;
761
762 if (!(np->tx_ring[entry].status & TFDDone))
763 break;
764 skb = np->tx_skbuff[entry];
765 pci_unmap_single (np->pdev,
766 np->tx_ring[entry].fraginfo,
767 skb->len, PCI_DMA_TODEVICE);
768 if (irq)
769 dev_kfree_skb_irq (skb);
770 else
771 dev_kfree_skb (skb);
772
773 np->tx_skbuff[entry] = 0;
774 entry = (entry + 1) % TX_RING_SIZE;
775 tx_use++;
776 }
777 if (irq)
778 spin_unlock(&np->tx_lock);
779 else
780 spin_unlock_irqrestore(&np->tx_lock, flag);
781 np->old_tx = entry;
782
783
784
785
786 if (netif_queue_stopped(dev) &&
787 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
788 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
789 netif_wake_queue (dev);
790 }
791}
792
793static void
794tx_error (struct net_device *dev, int tx_status)
795{
796 struct netdev_private *np;
797 long ioaddr = dev->base_addr;
798 int frame_id;
799 int i;
800
801 np = dev->priv;
802
803 frame_id = (tx_status & 0xffff0000);
804 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
805 dev->name, tx_status, frame_id);
806 np->stats.tx_errors++;
807
808 if (tx_status & 0x10) {
809 np->stats.tx_fifo_errors++;
810 writew (readw (ioaddr + TxStartThresh) + 0x10,
811 ioaddr + TxStartThresh);
812
813 writew (TxReset | DMAReset | FIFOReset | NetworkReset,
814 ioaddr + ASICCtrl + 2);
815
816 for (i = 50; i > 0; i--) {
817 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
818 break;
819 mdelay (1);
820 }
821 rio_free_tx (dev, 1);
822
823 writel (np->tx_ring_dma +
824 np->old_tx * sizeof (struct netdev_desc),
825 dev->base_addr + TFDListPtr0);
826 writel (0, dev->base_addr + TFDListPtr1);
827
828
829 }
830
831 if (tx_status & 0x04) {
832 np->stats.tx_fifo_errors++;
833
834 writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
835
836 for (i = 50; i > 0; i--) {
837 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
838 break;
839 mdelay (1);
840 }
841
842 }
843
844#ifdef ETHER_STATS
845 if (tx_status & 0x08)
846 np->stats.collisions16++;
847#else
848 if (tx_status & 0x08)
849 np->stats.collisions++;
850#endif
851
852 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
853}
854
855static int
856receive_packet (struct net_device *dev)
857{
858 struct netdev_private *np = (struct netdev_private *) dev->priv;
859 int entry = np->cur_rx % RX_RING_SIZE;
860 int cnt = 30;
861
862
863 while (1) {
864 struct netdev_desc *desc = &np->rx_ring[entry];
865 int pkt_len;
866 u64 frame_status;
867
868 if (!(desc->status & RFDDone) ||
869 !(desc->status & FrameStart) || !(desc->status & FrameEnd))
870 break;
871
872
873 pkt_len = le64_to_cpu (desc->status & 0xffff);
874 frame_status = le64_to_cpu (desc->status);
875 if (--cnt < 0)
876 break;
877 pci_dma_sync_single (np->pdev, desc->fraginfo, np->rx_buf_sz,
878 PCI_DMA_FROMDEVICE);
879
880 if (frame_status & RFS_Errors) {
881 np->stats.rx_errors++;
882 if (frame_status & (RxRuntFrame | RxLengthError))
883 np->stats.rx_length_errors++;
884 if (frame_status & RxFCSError)
885 np->stats.rx_crc_errors++;
886 if (frame_status & RxAlignmentError && np->speed != 1000)
887 np->stats.rx_frame_errors++;
888 if (frame_status & RxFIFOOverrun)
889 np->stats.rx_fifo_errors++;
890 } else {
891 struct sk_buff *skb;
892
893
894 if (pkt_len > copy_thresh) {
895 pci_unmap_single (np->pdev, desc->fraginfo,
896 np->rx_buf_sz,
897 PCI_DMA_FROMDEVICE);
898 skb_put (skb = np->rx_skbuff[entry], pkt_len);
899 np->rx_skbuff[entry] = NULL;
900 } else if ((skb = dev_alloc_skb (pkt_len + 2)) != NULL) {
901 skb->dev = dev;
902
903 skb_reserve (skb, 2);
904 eth_copy_and_sum (skb,
905 np->rx_skbuff[entry]->tail,
906 pkt_len, 0);
907 skb_put (skb, pkt_len);
908 }
909 skb->protocol = eth_type_trans (skb, dev);
910#if 0
911
912 if (np->pci_rev_id >= 0x0c &&
913 !(frame_status & (TCPError | UDPError | IPError))) {
914 skb->ip_summed = CHECKSUM_UNNECESSARY;
915 }
916#endif
917 netif_rx (skb);
918 dev->last_rx = jiffies;
919 }
920 entry = (entry + 1) % RX_RING_SIZE;
921 }
922 spin_lock(&np->rx_lock);
923 np->cur_rx = entry;
924
925 entry = np->old_rx;
926 while (entry != np->cur_rx) {
927 struct sk_buff *skb;
928
929 if (np->rx_skbuff[entry] == NULL) {
930 skb = dev_alloc_skb (np->rx_buf_sz);
931 if (skb == NULL) {
932 np->rx_ring[entry].fraginfo = 0;
933 printk (KERN_INFO
934 "%s: receive_packet: "
935 "Unable to re-allocate Rx skbuff.#%d\n",
936 dev->name, entry);
937 break;
938 }
939 np->rx_skbuff[entry] = skb;
940 skb->dev = dev;
941
942 skb_reserve (skb, 2);
943 np->rx_ring[entry].fraginfo =
944 cpu_to_le64 (pci_map_single
945 (np->pdev, skb->tail, np->rx_buf_sz,
946 PCI_DMA_FROMDEVICE));
947 }
948 np->rx_ring[entry].fraginfo |=
949 cpu_to_le64 (np->rx_buf_sz) << 48;
950 np->rx_ring[entry].status = 0;
951 entry = (entry + 1) % RX_RING_SIZE;
952 }
953 np->old_rx = entry;
954 spin_unlock(&np->rx_lock);
955 return 0;
956}
957
958static void
959rio_error (struct net_device *dev, int int_status)
960{
961 long ioaddr = dev->base_addr;
962 struct netdev_private *np = dev->priv;
963 u16 macctrl;
964
965
966 if (int_status & LinkEvent) {
967 if (mii_wait_link (dev, 10) == 0) {
968 printk (KERN_INFO "%s: Link up\n", dev->name);
969 if (np->phy_media)
970 mii_get_media_pcs (dev);
971 else
972 mii_get_media (dev);
973 if (np->speed == 1000)
974 np->tx_coalesce = tx_coalesce;
975 else
976 np->tx_coalesce = 1;
977 macctrl = 0;
978 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
979 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
980 macctrl |= (np->tx_flow) ?
981 TxFlowControlEnable : 0;
982 macctrl |= (np->rx_flow) ?
983 RxFlowControlEnable : 0;
984 writew(macctrl, ioaddr + MACCtrl);
985 np->link_status = 1;
986 netif_carrier_on(dev);
987 } else {
988 printk (KERN_INFO "%s: Link off\n", dev->name);
989 np->link_status = 0;
990 netif_carrier_off(dev);
991 }
992 }
993
994
995 if (int_status & UpdateStats) {
996 get_stats (dev);
997 }
998
999
1000
1001 if (int_status & HostError) {
1002 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1003 dev->name, int_status);
1004 writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
1005 mdelay (500);
1006 }
1007}
1008
1009static struct net_device_stats *
1010get_stats (struct net_device *dev)
1011{
1012 long ioaddr = dev->base_addr;
1013 struct netdev_private *np = dev->priv;
1014#ifdef MEM_MAPPING
1015 int i;
1016#endif
1017 unsigned int stat_reg;
1018
1019
1020
1021
1022 np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
1023 np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
1024 np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
1025 np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
1026
1027 np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
1028 np->stats.collisions += readl (ioaddr + SingleColFrames)
1029 + readl (ioaddr + MultiColFrames);
1030
1031
1032 stat_reg = readw (ioaddr + FramesAbortXSColls);
1033 np->stats.tx_aborted_errors += stat_reg;
1034 np->stats.tx_errors += stat_reg;
1035
1036 stat_reg = readw (ioaddr + CarrierSenseErrors);
1037 np->stats.tx_carrier_errors += stat_reg;
1038 np->stats.tx_errors += stat_reg;
1039
1040
1041 readl (ioaddr + McstOctetXmtOk);
1042 readw (ioaddr + BcstFramesXmtdOk);
1043 readl (ioaddr + McstFramesXmtdOk);
1044 readw (ioaddr + BcstFramesRcvdOk);
1045 readw (ioaddr + MacControlFramesRcvd);
1046 readw (ioaddr + FrameTooLongErrors);
1047 readw (ioaddr + InRangeLengthErrors);
1048 readw (ioaddr + FramesCheckSeqErrors);
1049 readw (ioaddr + FramesLostRxErrors);
1050 readl (ioaddr + McstOctetXmtOk);
1051 readl (ioaddr + BcstOctetXmtOk);
1052 readl (ioaddr + McstFramesXmtdOk);
1053 readl (ioaddr + FramesWDeferredXmt);
1054 readl (ioaddr + LateCollisions);
1055 readw (ioaddr + BcstFramesXmtdOk);
1056 readw (ioaddr + MacControlFramesXmtd);
1057 readw (ioaddr + FramesWEXDeferal);
1058
1059#ifdef MEM_MAPPING
1060 for (i = 0x100; i <= 0x150; i += 4)
1061 readl (ioaddr + i);
1062#endif
1063 readw (ioaddr + TxJumboFrames);
1064 readw (ioaddr + RxJumboFrames);
1065 readw (ioaddr + TCPCheckSumErrors);
1066 readw (ioaddr + UDPCheckSumErrors);
1067 readw (ioaddr + IPCheckSumErrors);
1068 return &np->stats;
1069}
1070
1071static int
1072clear_stats (struct net_device *dev)
1073{
1074 long ioaddr = dev->base_addr;
1075#ifdef MEM_MAPPING
1076 int i;
1077#endif
1078
1079
1080
1081 readl (ioaddr + FramesRcvOk);
1082 readl (ioaddr + FramesXmtOk);
1083 readl (ioaddr + OctetRcvOk);
1084 readl (ioaddr + OctetXmtOk);
1085
1086 readl (ioaddr + McstFramesRcvdOk);
1087 readl (ioaddr + SingleColFrames);
1088 readl (ioaddr + MultiColFrames);
1089 readl (ioaddr + LateCollisions);
1090
1091 readw (ioaddr + FrameTooLongErrors);
1092 readw (ioaddr + InRangeLengthErrors);
1093 readw (ioaddr + FramesCheckSeqErrors);
1094 readw (ioaddr + FramesLostRxErrors);
1095
1096
1097 readw (ioaddr + FramesAbortXSColls);
1098 readw (ioaddr + CarrierSenseErrors);
1099
1100
1101 readl (ioaddr + McstOctetXmtOk);
1102 readw (ioaddr + BcstFramesXmtdOk);
1103 readl (ioaddr + McstFramesXmtdOk);
1104 readw (ioaddr + BcstFramesRcvdOk);
1105 readw (ioaddr + MacControlFramesRcvd);
1106 readl (ioaddr + McstOctetXmtOk);
1107 readl (ioaddr + BcstOctetXmtOk);
1108 readl (ioaddr + McstFramesXmtdOk);
1109 readl (ioaddr + FramesWDeferredXmt);
1110 readw (ioaddr + BcstFramesXmtdOk);
1111 readw (ioaddr + MacControlFramesXmtd);
1112 readw (ioaddr + FramesWEXDeferal);
1113#ifdef MEM_MAPPING
1114 for (i = 0x100; i <= 0x150; i += 4)
1115 readl (ioaddr + i);
1116#endif
1117 readw (ioaddr + TxJumboFrames);
1118 readw (ioaddr + RxJumboFrames);
1119 readw (ioaddr + TCPCheckSumErrors);
1120 readw (ioaddr + UDPCheckSumErrors);
1121 readw (ioaddr + IPCheckSumErrors);
1122 return 0;
1123}
1124
1125
1126int
1127change_mtu (struct net_device *dev, int new_mtu)
1128{
1129 struct netdev_private *np = dev->priv;
1130 int max = (np->jumbo) ? MAX_JUMBO : 1536;
1131
1132 if ((new_mtu < 68) || (new_mtu > max)) {
1133 return -EINVAL;
1134 }
1135
1136 dev->mtu = new_mtu;
1137
1138 return 0;
1139}
1140
1141static void
1142set_multicast (struct net_device *dev)
1143{
1144 long ioaddr = dev->base_addr;
1145 u32 hash_table[2];
1146 u16 rx_mode = 0;
1147 struct netdev_private *np = dev->priv;
1148
1149 hash_table[0] = hash_table[1] = 0;
1150
1151 hash_table[1] |= cpu_to_le32(0x02000000);
1152 if (dev->flags & IFF_PROMISC) {
1153
1154 rx_mode = ReceiveAllFrames;
1155 } else if ((dev->flags & IFF_ALLMULTI) ||
1156 (dev->mc_count > multicast_filter_limit)) {
1157
1158 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1159 } else if (dev->mc_count > 0) {
1160 int i;
1161 struct dev_mc_list *mclist;
1162
1163
1164 rx_mode =
1165 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1166 for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1167 i++, mclist=mclist->next)
1168 {
1169 int bit, index = 0;
1170 int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1171
1172
1173 for (bit = 0; bit < 6; bit++)
1174 if (crc & (1 << (31 - bit)))
1175 index |= (1 << bit);
1176 hash_table[index / 32] |= (1 << (index % 32));
1177 }
1178 } else {
1179 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1180 }
1181 if (np->vlan) {
1182
1183 rx_mode |= ReceiveVLANMatch;
1184 }
1185
1186 writel (hash_table[0], ioaddr + HashTable0);
1187 writel (hash_table[1], ioaddr + HashTable1);
1188 writew (rx_mode, ioaddr + ReceiveMode);
1189}
1190
1191static int
1192rio_ethtool_ioctl (struct net_device *dev, void *useraddr)
1193{
1194 struct netdev_private *np = dev->priv;
1195 u32 ethcmd;
1196
1197 if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd)))
1198 return -EFAULT;
1199 switch (ethcmd) {
1200 case ETHTOOL_GDRVINFO: {
1201 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1202 strcpy(info.driver, "DL2K");
1203 strcpy(info.version, DRV_VERSION);
1204 strcpy(info.bus_info, pci_name(np->pdev));
1205 memset(&info.fw_version, 0, sizeof(info.fw_version));
1206 if (copy_to_user(useraddr, &info, sizeof(info)))
1207 return -EFAULT;
1208 return 0;
1209 }
1210
1211 case ETHTOOL_GSET: {
1212 struct ethtool_cmd cmd = { ETHTOOL_GSET };
1213 if (np->phy_media) {
1214
1215 cmd.supported = SUPPORTED_Autoneg |
1216 SUPPORTED_FIBRE;
1217 cmd.advertising= ADVERTISED_Autoneg |
1218 ADVERTISED_FIBRE;
1219 cmd.port = PORT_FIBRE;
1220 cmd.transceiver = XCVR_INTERNAL;
1221 } else {
1222
1223 cmd.supported = SUPPORTED_10baseT_Half |
1224 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1225 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1226 SUPPORTED_Autoneg | SUPPORTED_MII;
1227 cmd.advertising = ADVERTISED_10baseT_Half |
1228 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1229 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
1230 ADVERTISED_Autoneg | ADVERTISED_MII;
1231 cmd.port = PORT_MII;
1232 cmd.transceiver = XCVR_INTERNAL;
1233 }
1234 if ( np->link_status ) {
1235 cmd.speed = np->speed;
1236 cmd.duplex = np->full_duplex ?
1237 DUPLEX_FULL : DUPLEX_HALF;
1238 } else {
1239 cmd.speed = -1;
1240 cmd.duplex = -1;
1241 }
1242 if ( np->an_enable)
1243 cmd.autoneg = AUTONEG_ENABLE;
1244 else
1245 cmd.autoneg = AUTONEG_DISABLE;
1246
1247 cmd.phy_address = np->phy_addr;
1248
1249 if (copy_to_user(useraddr, &cmd,
1250 sizeof(cmd)))
1251 return -EFAULT;
1252 return 0;
1253 }
1254 case ETHTOOL_SSET: {
1255 struct ethtool_cmd cmd;
1256 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
1257 return -EFAULT;
1258 netif_carrier_off(dev);
1259 if (cmd.autoneg == AUTONEG_ENABLE) {
1260 if (np->an_enable)
1261 return 0;
1262 else {
1263 np->an_enable = 1;
1264 mii_set_media(dev);
1265 return 0;
1266 }
1267 } else {
1268 np->an_enable = 0;
1269 if (np->speed == 1000){
1270 cmd.speed = SPEED_100;
1271 cmd.duplex = DUPLEX_FULL;
1272 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manul 100Mbps, Full duplex.\n");
1273 }
1274 switch(cmd.speed + cmd.duplex){
1275
1276 case SPEED_10 + DUPLEX_HALF:
1277 np->speed = 10;
1278 np->full_duplex = 0;
1279 break;
1280
1281 case SPEED_10 + DUPLEX_FULL:
1282 np->speed = 10;
1283 np->full_duplex = 1;
1284 break;
1285 case SPEED_100 + DUPLEX_HALF:
1286 np->speed = 100;
1287 np->full_duplex = 0;
1288 break;
1289 case SPEED_100 + DUPLEX_FULL:
1290 np->speed = 100;
1291 np->full_duplex = 1;
1292 break;
1293 case SPEED_1000 + DUPLEX_HALF:
1294 case SPEED_1000 + DUPLEX_FULL:
1295 default:
1296 return -EINVAL;
1297 }
1298 mii_set_media(dev);
1299 }
1300 return 0;
1301 }
1302#ifdef ETHTOOL_GLINK
1303 case ETHTOOL_GLINK:{
1304 struct ethtool_value link = { ETHTOOL_GLINK };
1305 link.data = np->link_status;
1306 if (copy_to_user(useraddr, &link, sizeof(link)))
1307 return -EFAULT;
1308 return 0;
1309 }
1310#endif
1311 default:
1312 return -EOPNOTSUPP;
1313 }
1314}
1315
1316
1317static int
1318rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1319{
1320 int phy_addr;
1321 struct netdev_private *np = dev->priv;
1322 struct mii_data *miidata = (struct mii_data *) &rq->ifr_data;
1323
1324 struct netdev_desc *desc;
1325 int i;
1326
1327 phy_addr = np->phy_addr;
1328 switch (cmd) {
1329 case SIOCETHTOOL:
1330 return rio_ethtool_ioctl (dev, (void *) rq->ifr_data);
1331 case SIOCDEVPRIVATE:
1332 break;
1333
1334 case SIOCDEVPRIVATE + 1:
1335 miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
1336 break;
1337 case SIOCDEVPRIVATE + 2:
1338 mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
1339 break;
1340 case SIOCDEVPRIVATE + 3:
1341 break;
1342 case SIOCDEVPRIVATE + 4:
1343 break;
1344 case SIOCDEVPRIVATE + 5:
1345 netif_stop_queue (dev);
1346 break;
1347 case SIOCDEVPRIVATE + 6:
1348 netif_wake_queue (dev);
1349 break;
1350 case SIOCDEVPRIVATE + 7:
1351 printk
1352 ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
1353 netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
1354 np->old_rx);
1355 break;
1356 case SIOCDEVPRIVATE + 8:
1357 printk("TX ring:\n");
1358 for (i = 0; i < TX_RING_SIZE; i++) {
1359 desc = &np->tx_ring[i];
1360 printk
1361 ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
1362 i,
1363 (u32) (np->tx_ring_dma + i * sizeof (*desc)),
1364 (u32) desc->next_desc,
1365 (u32) desc->status, (u32) (desc->fraginfo >> 32),
1366 (u32) desc->fraginfo);
1367 printk ("\n");
1368 }
1369 printk ("\n");
1370 break;
1371
1372 default:
1373 return -EOPNOTSUPP;
1374 }
1375 return 0;
1376}
1377
1378#define EEP_READ 0x0200
1379#define EEP_BUSY 0x8000
1380
1381
1382int
1383read_eeprom (long ioaddr, int eep_addr)
1384{
1385 int i = 1000;
1386 outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
1387 while (i-- > 0) {
1388 if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
1389 return inw (ioaddr + EepromData);
1390 }
1391 }
1392 return 0;
1393}
1394
1395enum phy_ctrl_bits {
1396 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1397 MII_DUPLEX = 0x08,
1398};
1399
1400#define mii_delay() readb(ioaddr)
1401static void
1402mii_sendbit (struct net_device *dev, u32 data)
1403{
1404 long ioaddr = dev->base_addr + PhyCtrl;
1405 data = (data) ? MII_DATA1 : 0;
1406 data |= MII_WRITE;
1407 data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
1408 writeb (data, ioaddr);
1409 mii_delay ();
1410 writeb (data | MII_CLK, ioaddr);
1411 mii_delay ();
1412}
1413
1414static int
1415mii_getbit (struct net_device *dev)
1416{
1417 long ioaddr = dev->base_addr + PhyCtrl;
1418 u8 data;
1419
1420 data = (readb (ioaddr) & 0xf8) | MII_READ;
1421 writeb (data, ioaddr);
1422 mii_delay ();
1423 writeb (data | MII_CLK, ioaddr);
1424 mii_delay ();
1425 return ((readb (ioaddr) >> 1) & 1);
1426}
1427
1428static void
1429mii_send_bits (struct net_device *dev, u32 data, int len)
1430{
1431 int i;
1432 for (i = len - 1; i >= 0; i--) {
1433 mii_sendbit (dev, data & (1 << i));
1434 }
1435}
1436
1437static int
1438mii_read (struct net_device *dev, int phy_addr, int reg_num)
1439{
1440 u32 cmd;
1441 int i;
1442 u32 retval = 0;
1443
1444
1445 mii_send_bits (dev, 0xffffffff, 32);
1446
1447
1448 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1449 mii_send_bits (dev, cmd, 14);
1450
1451 if (mii_getbit (dev))
1452 goto err_out;
1453
1454 for (i = 0; i < 16; i++) {
1455 retval |= mii_getbit (dev);
1456 retval <<= 1;
1457 }
1458
1459 mii_getbit (dev);
1460 return (retval >> 1) & 0xffff;
1461
1462 err_out:
1463 return 0;
1464}
1465static int
1466mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1467{
1468 u32 cmd;
1469
1470
1471 mii_send_bits (dev, 0xffffffff, 32);
1472
1473
1474 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1475 mii_send_bits (dev, cmd, 32);
1476
1477 mii_getbit (dev);
1478 return 0;
1479}
1480static int
1481mii_wait_link (struct net_device *dev, int wait)
1482{
1483 BMSR_t bmsr;
1484 int phy_addr;
1485 struct netdev_private *np;
1486
1487 np = dev->priv;
1488 phy_addr = np->phy_addr;
1489
1490 do {
1491 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1492 if (bmsr.bits.link_status)
1493 return 0;
1494 mdelay (1);
1495 } while (--wait > 0);
1496 return -1;
1497}
1498static int
1499mii_get_media (struct net_device *dev)
1500{
1501 ANAR_t negotiate;
1502 BMSR_t bmsr;
1503 BMCR_t bmcr;
1504 MSCR_t mscr;
1505 MSSR_t mssr;
1506 int phy_addr;
1507 struct netdev_private *np;
1508
1509 np = dev->priv;
1510 phy_addr = np->phy_addr;
1511
1512 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1513 if (np->an_enable) {
1514 if (!bmsr.bits.an_complete) {
1515
1516 return -1;
1517 }
1518 negotiate.image = mii_read (dev, phy_addr, MII_ANAR) &
1519 mii_read (dev, phy_addr, MII_ANLPAR);
1520 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1521 mssr.image = mii_read (dev, phy_addr, MII_MSSR);
1522 if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) {
1523 np->speed = 1000;
1524 np->full_duplex = 1;
1525 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1526 } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) {
1527 np->speed = 1000;
1528 np->full_duplex = 0;
1529 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1530 } else if (negotiate.bits.media_100BX_FD) {
1531 np->speed = 100;
1532 np->full_duplex = 1;
1533 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1534 } else if (negotiate.bits.media_100BX_HD) {
1535 np->speed = 100;
1536 np->full_duplex = 0;
1537 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1538 } else if (negotiate.bits.media_10BT_FD) {
1539 np->speed = 10;
1540 np->full_duplex = 1;
1541 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1542 } else if (negotiate.bits.media_10BT_HD) {
1543 np->speed = 10;
1544 np->full_duplex = 0;
1545 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1546 }
1547 if (negotiate.bits.pause) {
1548 np->tx_flow &= 1;
1549 np->rx_flow &= 1;
1550 } else if (negotiate.bits.asymmetric) {
1551 np->tx_flow = 0;
1552 np->rx_flow &= 1;
1553 }
1554
1555 } else {
1556 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1557 if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) {
1558 printk (KERN_INFO "Operating at 100 Mbps, ");
1559 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) {
1560 printk (KERN_INFO "Operating at 10 Mbps, ");
1561 } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
1562 printk (KERN_INFO "Operating at 1000 Mbps, ");
1563 }
1564 if (bmcr.bits.duplex_mode) {
1565 printk ("Full duplex\n");
1566 } else {
1567 printk ("Half duplex\n");
1568 }
1569 }
1570 if (np->tx_flow)
1571 printk(KERN_INFO "Enable Tx Flow Control\n");
1572 else
1573 printk(KERN_INFO "Disable Tx Flow Control\n");
1574 if (np->rx_flow)
1575 printk(KERN_INFO "Enable Rx Flow Control\n");
1576 else
1577 printk(KERN_INFO "Disable Rx Flow Control\n");
1578
1579 return 0;
1580}
1581
1582static int
1583mii_set_media (struct net_device *dev)
1584{
1585 PHY_SCR_t pscr;
1586 BMCR_t bmcr;
1587 BMSR_t bmsr;
1588 ANAR_t anar;
1589 int phy_addr;
1590 struct netdev_private *np;
1591 np = dev->priv;
1592 phy_addr = np->phy_addr;
1593
1594
1595 if (np->an_enable) {
1596
1597 bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
1598 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1599 anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD;
1600 anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD;
1601 anar.bits.media_100BT4 = bmsr.bits.media_100BT4;
1602 anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD;
1603 anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD;
1604 anar.bits.pause = 1;
1605 anar.bits.asymmetric = 1;
1606 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1607
1608
1609 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1610 pscr.bits.mdi_crossover_mode = 3;
1611 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1612
1613
1614 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1615 bmcr.image = 0;
1616 bmcr.bits.an_enable = 1;
1617 bmcr.bits.restart_an = 1;
1618 bmcr.bits.reset = 1;
1619 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1620 mdelay(1);
1621 } else {
1622
1623
1624 pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
1625 pscr.bits.mdi_crossover_mode = 0;
1626 mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
1627
1628
1629 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1630 bmcr.bits.reset = 1;
1631 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1632
1633
1634 bmcr.image = 0x1940;
1635 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1636 mdelay (100);
1637
1638
1639 mii_write (dev, phy_addr, MII_ANAR, 0);
1640
1641
1642 bmcr.image = 0;
1643 bmcr.bits.power_down = 1;
1644 if (np->speed == 100) {
1645 bmcr.bits.speed100 = 1;
1646 bmcr.bits.speed1000 = 0;
1647 printk (KERN_INFO "Manual 100 Mbps, ");
1648 } else if (np->speed == 10) {
1649 bmcr.bits.speed100 = 0;
1650 bmcr.bits.speed1000 = 0;
1651 printk (KERN_INFO "Manual 10 Mbps, ");
1652 }
1653 if (np->full_duplex) {
1654 bmcr.bits.duplex_mode = 1;
1655 printk ("Full duplex\n");
1656 } else {
1657 bmcr.bits.duplex_mode = 0;
1658 printk ("Half duplex\n");
1659 }
1660#if 0
1661
1662 mscr.image = mii_read (dev, phy_addr, MII_MSCR);
1663 mscr.bits.cfg_enable = 1;
1664 mscr.bits.cfg_value = 0;
1665#endif
1666 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1667 mdelay(10);
1668 }
1669 return 0;
1670}
1671
1672static int
1673mii_get_media_pcs (struct net_device *dev)
1674{
1675 ANAR_PCS_t negotiate;
1676 BMSR_t bmsr;
1677 BMCR_t bmcr;
1678 int phy_addr;
1679 struct netdev_private *np;
1680
1681 np = dev->priv;
1682 phy_addr = np->phy_addr;
1683
1684 bmsr.image = mii_read (dev, phy_addr, PCS_BMSR);
1685 if (np->an_enable) {
1686 if (!bmsr.bits.an_complete) {
1687
1688 return -1;
1689 }
1690 negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) &
1691 mii_read (dev, phy_addr, PCS_ANLPAR);
1692 np->speed = 1000;
1693 if (negotiate.bits.full_duplex) {
1694 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1695 np->full_duplex = 1;
1696 } else {
1697 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1698 np->full_duplex = 0;
1699 }
1700 if (negotiate.bits.pause) {
1701 np->tx_flow &= 1;
1702 np->rx_flow &= 1;
1703 } else if (negotiate.bits.asymmetric) {
1704 np->tx_flow = 0;
1705 np->rx_flow &= 1;
1706 }
1707
1708 } else {
1709 bmcr.image = mii_read (dev, phy_addr, PCS_BMCR);
1710 printk (KERN_INFO "Operating at 1000 Mbps, ");
1711 if (bmcr.bits.duplex_mode) {
1712 printk ("Full duplex\n");
1713 } else {
1714 printk ("Half duplex\n");
1715 }
1716 }
1717 if (np->tx_flow)
1718 printk(KERN_INFO "Enable Tx Flow Control\n");
1719 else
1720 printk(KERN_INFO "Disable Tx Flow Control\n");
1721 if (np->rx_flow)
1722 printk(KERN_INFO "Enable Rx Flow Control\n");
1723 else
1724 printk(KERN_INFO "Disable Rx Flow Control\n");
1725
1726 return 0;
1727}
1728
1729static int
1730mii_set_media_pcs (struct net_device *dev)
1731{
1732 BMCR_t bmcr;
1733 ESR_t esr;
1734 ANAR_PCS_t anar;
1735 int phy_addr;
1736 struct netdev_private *np;
1737 np = dev->priv;
1738 phy_addr = np->phy_addr;
1739
1740
1741 if (np->an_enable) {
1742
1743 esr.image = mii_read (dev, phy_addr, PCS_ESR);
1744 anar.image = mii_read (dev, phy_addr, MII_ANAR);
1745 anar.bits.half_duplex =
1746 esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD;
1747 anar.bits.full_duplex =
1748 esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD;
1749 anar.bits.pause = 1;
1750 anar.bits.asymmetric = 1;
1751 mii_write (dev, phy_addr, MII_ANAR, anar.image);
1752
1753
1754 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1755 bmcr.image = 0;
1756 bmcr.bits.an_enable = 1;
1757 bmcr.bits.restart_an = 1;
1758 bmcr.bits.reset = 1;
1759 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1760 mdelay(1);
1761 } else {
1762
1763
1764 bmcr.image = 0;
1765 bmcr.bits.reset = 1;
1766 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1767 mdelay(10);
1768 bmcr.image = 0;
1769 bmcr.bits.an_enable = 0;
1770 if (np->full_duplex) {
1771 bmcr.bits.duplex_mode = 1;
1772 printk (KERN_INFO "Manual full duplex\n");
1773 } else {
1774 bmcr.bits.duplex_mode = 0;
1775 printk (KERN_INFO "Manual half duplex\n");
1776 }
1777 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1778 mdelay(10);
1779
1780
1781 mii_write (dev, phy_addr, MII_ANAR, 0);
1782 }
1783 return 0;
1784}
1785
1786
1787static int
1788rio_close (struct net_device *dev)
1789{
1790 long ioaddr = dev->base_addr;
1791 struct netdev_private *np = dev->priv;
1792 struct sk_buff *skb;
1793 int i;
1794
1795 netif_stop_queue (dev);
1796
1797
1798 writew (0, ioaddr + IntEnable);
1799
1800
1801 writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
1802 synchronize_irq (dev->irq);
1803 free_irq (dev->irq, dev);
1804 del_timer_sync (&np->timer);
1805
1806
1807 for (i = 0; i < RX_RING_SIZE; i++) {
1808 np->rx_ring[i].status = 0;
1809 np->rx_ring[i].fraginfo = 0;
1810 skb = np->rx_skbuff[i];
1811 if (skb) {
1812 pci_unmap_single (np->pdev, np->rx_ring[i].fraginfo,
1813 skb->len, PCI_DMA_FROMDEVICE);
1814 dev_kfree_skb (skb);
1815 np->rx_skbuff[i] = 0;
1816 }
1817 }
1818 for (i = 0; i < TX_RING_SIZE; i++) {
1819 skb = np->tx_skbuff[i];
1820 if (skb) {
1821 pci_unmap_single (np->pdev, np->tx_ring[i].fraginfo,
1822 skb->len, PCI_DMA_TODEVICE);
1823 dev_kfree_skb (skb);
1824 np->tx_skbuff[i] = 0;
1825 }
1826 }
1827
1828 return 0;
1829}
1830
1831static void __devexit
1832rio_remove1 (struct pci_dev *pdev)
1833{
1834 struct net_device *dev = pci_get_drvdata (pdev);
1835
1836 if (dev) {
1837 struct netdev_private *np = dev->priv;
1838
1839 unregister_netdev (dev);
1840 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1841 np->rx_ring_dma);
1842 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1843 np->tx_ring_dma);
1844#ifdef MEM_MAPPING
1845 iounmap ((char *) (dev->base_addr));
1846#endif
1847 free_netdev (dev);
1848 pci_release_regions (pdev);
1849 pci_disable_device (pdev);
1850 }
1851 pci_set_drvdata (pdev, NULL);
1852}
1853
1854static struct pci_driver rio_driver = {
1855 .name = "dl2k",
1856 .id_table = rio_pci_tbl,
1857 .probe = rio_probe1,
1858 .remove = __devexit_p(rio_remove1),
1859};
1860
1861static int __init
1862rio_init (void)
1863{
1864 return pci_module_init (&rio_driver);
1865}
1866
1867static void __exit
1868rio_exit (void)
1869{
1870 pci_unregister_driver (&rio_driver);
1871}
1872
1873module_init (rio_init);
1874module_exit (rio_exit);
1875
1876
1877
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