1
2
3
4
5
6
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/types.h>
10#include <linux/netdevice.h>
11#include <linux/ethtool.h>
12#include <linux/mii.h>
13#include <linux/if_ether.h>
14#include <linux/etherdevice.h>
15#include <linux/pci.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/version.h>
19
20#include <asm/uaccess.h>
21#include <asm/io.h>
22#include <asm/irq.h>
23
24#include "b44.h"
25
26#define DRV_MODULE_NAME "b44"
27#define PFX DRV_MODULE_NAME ": "
28#define DRV_MODULE_VERSION "0.92"
29#define DRV_MODULE_RELDATE "Nov 4, 2003"
30
31#define B44_DEF_MSG_ENABLE \
32 (NETIF_MSG_DRV | \
33 NETIF_MSG_PROBE | \
34 NETIF_MSG_LINK | \
35 NETIF_MSG_TIMER | \
36 NETIF_MSG_IFDOWN | \
37 NETIF_MSG_IFUP | \
38 NETIF_MSG_RX_ERR | \
39 NETIF_MSG_TX_ERR)
40
41
42
43
44#define B44_TX_TIMEOUT (5 * HZ)
45
46
47#define B44_MIN_MTU 60
48#define B44_MAX_MTU 1500
49
50#define B44_RX_RING_SIZE 512
51#define B44_DEF_RX_RING_PENDING 200
52#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
53 B44_RX_RING_SIZE)
54#define B44_TX_RING_SIZE 512
55#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
56#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
57 B44_TX_RING_SIZE)
58
59#define TX_RING_GAP(BP) \
60 (B44_TX_RING_SIZE - (BP)->tx_pending)
61#define TX_BUFFS_AVAIL(BP) \
62 (((BP)->tx_cons <= (BP)->tx_prod) ? \
63 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
64 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
65#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
66
67#define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
68
69
70#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
71
72static char version[] __devinitdata =
73 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
74
75MODULE_AUTHOR("David S. Miller (davem@redhat.com)");
76MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
77MODULE_LICENSE("GPL");
78MODULE_PARM(b44_debug, "i");
79MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
80
81static int b44_debug = -1;
82
83static struct pci_device_id b44_pci_tbl[] = {
84 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
85 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
86 { }
87};
88
89MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
90
91static void b44_halt(struct b44 *);
92static void b44_init_rings(struct b44 *);
93static int b44_init_hw(struct b44 *);
94
95static int b44_wait_bit(struct b44 *bp, unsigned long reg,
96 u32 bit, unsigned long timeout, const int clear)
97{
98 unsigned long i;
99
100 for (i = 0; i < timeout; i++) {
101 u32 val = br32(reg);
102
103 if (clear && !(val & bit))
104 break;
105 if (!clear && (val & bit))
106 break;
107 udelay(10);
108 }
109 if (i == timeout) {
110 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
111 "%lx to %s.\n",
112 bp->dev->name,
113 bit, reg,
114 (clear ? "clear" : "set"));
115 return -ENODEV;
116 }
117 return 0;
118}
119
120
121
122
123
124
125
126
127#define SBID_SDRAM 0
128#define SBID_PCI_MEM 1
129#define SBID_PCI_CFG 2
130#define SBID_PCI_DMA 3
131#define SBID_SDRAM_SWAPPED 4
132#define SBID_ENUM 5
133#define SBID_REG_SDRAM 6
134#define SBID_REG_ILINE20 7
135#define SBID_REG_EMAC 8
136#define SBID_REG_CODEC 9
137#define SBID_REG_USB 10
138#define SBID_REG_PCI 11
139#define SBID_REG_MIPS 12
140#define SBID_REG_EXTIF 13
141#define SBID_EXTIF 14
142#define SBID_EJTAG 15
143#define SBID_MAX 16
144
145static u32 ssb_get_addr(struct b44 *bp, u32 id, u32 instance)
146{
147 switch (id) {
148 case SBID_PCI_DMA:
149 return 0x40000000;
150 case SBID_ENUM:
151 return 0x18000000;
152 case SBID_REG_EMAC:
153 return 0x18000000;
154 case SBID_REG_CODEC:
155 return 0x18001000;
156 case SBID_REG_PCI:
157 return 0x18002000;
158 default:
159 return 0;
160 };
161}
162
163static u32 ssb_get_core_rev(struct b44 *bp)
164{
165 return (br32(B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
166}
167
168static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
169{
170 u32 bar_orig, pci_rev, val;
171
172 pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
173 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN,
174 ssb_get_addr(bp, SBID_REG_PCI, 0));
175 pci_rev = ssb_get_core_rev(bp);
176
177 val = br32(B44_SBINTVEC);
178 val |= cores;
179 bw32(B44_SBINTVEC, val);
180
181 val = br32(SSB_PCI_TRANS_2);
182 val |= SSB_PCI_PREF | SSB_PCI_BURST;
183 bw32(SSB_PCI_TRANS_2, val);
184
185 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
186
187 return pci_rev;
188}
189
190static void ssb_core_disable(struct b44 *bp)
191{
192 if (br32(B44_SBTMSLOW) & SBTMSLOW_RESET)
193 return;
194
195 bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
196 b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
197 b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
198 bw32(B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
199 SBTMSLOW_REJECT | SBTMSLOW_RESET));
200 br32(B44_SBTMSLOW);
201 udelay(1);
202 bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
203 br32(B44_SBTMSLOW);
204 udelay(1);
205}
206
207static void ssb_core_reset(struct b44 *bp)
208{
209 u32 val;
210
211 ssb_core_disable(bp);
212 bw32(B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
213 br32(B44_SBTMSLOW);
214 udelay(1);
215
216
217 if (br32(B44_SBTMSHIGH) & SBTMSHIGH_SERR)
218 bw32(B44_SBTMSHIGH, 0);
219
220 val = br32(B44_SBIMSTATE);
221 if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
222 bw32(B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
223
224 bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
225 br32(B44_SBTMSLOW);
226 udelay(1);
227
228 bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK));
229 br32(B44_SBTMSLOW);
230 udelay(1);
231}
232
233static int ssb_core_unit(struct b44 *bp)
234{
235#if 0
236 u32 val = br32(B44_SBADMATCH0);
237 u32 base;
238
239 type = val & SBADMATCH0_TYPE_MASK;
240 switch (type) {
241 case 0:
242 base = val & SBADMATCH0_BS0_MASK;
243 break;
244
245 case 1:
246 base = val & SBADMATCH0_BS1_MASK;
247 break;
248
249 case 2:
250 default:
251 base = val & SBADMATCH0_BS2_MASK;
252 break;
253 };
254#endif
255 return 0;
256}
257
258static int ssb_is_core_up(struct b44 *bp)
259{
260 return ((br32(B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
261 == SBTMSLOW_CLOCK);
262}
263
264static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
265{
266 u32 val;
267
268 val = ((u32) data[2]) << 24;
269 val |= ((u32) data[3]) << 16;
270 val |= ((u32) data[4]) << 8;
271 val |= ((u32) data[5]) << 0;
272 bw32(B44_CAM_DATA_LO, val);
273 val = (CAM_DATA_HI_VALID |
274 (((u32) data[0]) << 8) |
275 (((u32) data[1]) << 0));
276 bw32(B44_CAM_DATA_HI, val);
277 bw32(B44_CAM_CTRL, (CAM_CTRL_WRITE |
278 (index << CAM_CTRL_INDEX_SHIFT)));
279 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
280}
281
282static inline void __b44_disable_ints(struct b44 *bp)
283{
284 bw32(B44_IMASK, 0);
285}
286
287static void b44_disable_ints(struct b44 *bp)
288{
289 __b44_disable_ints(bp);
290
291
292 br32(B44_IMASK);
293}
294
295static void b44_enable_ints(struct b44 *bp)
296{
297 bw32(B44_IMASK, bp->imask);
298}
299
300static int b44_readphy(struct b44 *bp, int reg, u32 *val)
301{
302 int err;
303
304 bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
305 bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
306 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
307 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
308 (reg << MDIO_DATA_RA_SHIFT) |
309 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
310 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
311 *val = br32(B44_MDIO_DATA) & MDIO_DATA_DATA;
312
313 return err;
314}
315
316static int b44_writephy(struct b44 *bp, int reg, u32 val)
317{
318 bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
319 bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
320 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
321 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
322 (reg << MDIO_DATA_RA_SHIFT) |
323 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
324 (val & MDIO_DATA_DATA)));
325 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
326}
327
328static int b44_phy_reset(struct b44 *bp)
329{
330 u32 val;
331 int err;
332
333 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
334 if (err)
335 return err;
336 udelay(100);
337 err = b44_readphy(bp, MII_BMCR, &val);
338 if (!err) {
339 if (val & BMCR_RESET) {
340 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
341 bp->dev->name);
342 err = -ENODEV;
343 }
344 }
345
346 return 0;
347}
348
349static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
350{
351 u32 val;
352
353 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
354 bp->flags |= pause_flags;
355
356 val = br32(B44_RXCONFIG);
357 if (pause_flags & B44_FLAG_RX_PAUSE)
358 val |= RXCONFIG_FLOW;
359 else
360 val &= ~RXCONFIG_FLOW;
361 bw32(B44_RXCONFIG, val);
362
363 val = br32(B44_MAC_FLOW);
364 if (pause_flags & B44_FLAG_TX_PAUSE)
365 val |= (MAC_FLOW_PAUSE_ENAB |
366 (0xc0 & MAC_FLOW_RX_HI_WATER));
367 else
368 val &= ~MAC_FLOW_PAUSE_ENAB;
369 bw32(B44_MAC_FLOW, val);
370}
371
372static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
373{
374 u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
375 B44_FLAG_RX_PAUSE);
376
377 if (local & ADVERTISE_PAUSE_CAP) {
378 if (local & ADVERTISE_PAUSE_ASYM) {
379 if (remote & LPA_PAUSE_CAP)
380 pause_enab |= (B44_FLAG_TX_PAUSE |
381 B44_FLAG_RX_PAUSE);
382 else if (remote & LPA_PAUSE_ASYM)
383 pause_enab |= B44_FLAG_RX_PAUSE;
384 } else {
385 if (remote & LPA_PAUSE_CAP)
386 pause_enab |= (B44_FLAG_TX_PAUSE |
387 B44_FLAG_RX_PAUSE);
388 }
389 } else if (local & ADVERTISE_PAUSE_ASYM) {
390 if ((remote & LPA_PAUSE_CAP) &&
391 (remote & LPA_PAUSE_ASYM))
392 pause_enab |= B44_FLAG_TX_PAUSE;
393 }
394
395 __b44_set_flow_ctrl(bp, pause_enab);
396}
397
398static int b44_setup_phy(struct b44 *bp)
399{
400 u32 val;
401 int err;
402
403 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
404 goto out;
405 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
406 val & MII_ALEDCTRL_ALLMSK)) != 0)
407 goto out;
408 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
409 goto out;
410 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
411 val | MII_TLEDCTRL_ENABLE)) != 0)
412 goto out;
413
414 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
415 u32 adv = ADVERTISE_CSMA;
416
417 if (bp->flags & B44_FLAG_ADV_10HALF)
418 adv |= ADVERTISE_10HALF;
419 if (bp->flags & B44_FLAG_ADV_10FULL)
420 adv |= ADVERTISE_10FULL;
421 if (bp->flags & B44_FLAG_ADV_100HALF)
422 adv |= ADVERTISE_100HALF;
423 if (bp->flags & B44_FLAG_ADV_100FULL)
424 adv |= ADVERTISE_100FULL;
425
426 if (bp->flags & B44_FLAG_PAUSE_AUTO)
427 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
428
429 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
430 goto out;
431 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
432 BMCR_ANRESTART))) != 0)
433 goto out;
434 } else {
435 u32 bmcr;
436
437 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
438 goto out;
439 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
440 if (bp->flags & B44_FLAG_100_BASE_T)
441 bmcr |= BMCR_SPEED100;
442 if (bp->flags & B44_FLAG_FULL_DUPLEX)
443 bmcr |= BMCR_FULLDPLX;
444 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
445 goto out;
446
447
448
449
450
451 b44_set_flow_ctrl(bp, 0, 0);
452 }
453
454out:
455 return err;
456}
457
458static void b44_stats_update(struct b44 *bp)
459{
460 unsigned long reg;
461 u32 *val;
462
463 val = &bp->hw_stats.tx_good_octets;
464 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
465 *val++ += br32(reg);
466 }
467 val = &bp->hw_stats.rx_good_octets;
468 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
469 *val++ += br32(reg);
470 }
471}
472
473static void b44_link_report(struct b44 *bp)
474{
475 if (!netif_carrier_ok(bp->dev)) {
476 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
477 } else {
478 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
479 bp->dev->name,
480 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
481 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
482
483 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
484 "%s for RX.\n",
485 bp->dev->name,
486 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
487 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
488 }
489}
490
491static void b44_check_phy(struct b44 *bp)
492{
493 u32 bmsr, aux;
494
495 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
496 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
497 (bmsr != 0xffff)) {
498 if (aux & MII_AUXCTRL_SPEED)
499 bp->flags |= B44_FLAG_100_BASE_T;
500 else
501 bp->flags &= ~B44_FLAG_100_BASE_T;
502 if (aux & MII_AUXCTRL_DUPLEX)
503 bp->flags |= B44_FLAG_FULL_DUPLEX;
504 else
505 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
506
507 if (!netif_carrier_ok(bp->dev) &&
508 (bmsr & BMSR_LSTATUS)) {
509 u32 val = br32(B44_TX_CTRL);
510 u32 local_adv, remote_adv;
511
512 if (bp->flags & B44_FLAG_FULL_DUPLEX)
513 val |= TX_CTRL_DUPLEX;
514 else
515 val &= ~TX_CTRL_DUPLEX;
516 bw32(B44_TX_CTRL, val);
517
518 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
519 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
520 !b44_readphy(bp, MII_LPA, &remote_adv))
521 b44_set_flow_ctrl(bp, local_adv, remote_adv);
522
523
524 netif_carrier_on(bp->dev);
525 b44_link_report(bp);
526 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
527
528 netif_carrier_off(bp->dev);
529 b44_link_report(bp);
530 }
531
532 if (bmsr & BMSR_RFAULT)
533 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
534 bp->dev->name);
535 if (bmsr & BMSR_JCD)
536 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
537 bp->dev->name);
538 }
539}
540
541static void b44_timer(unsigned long __opaque)
542{
543 struct b44 *bp = (struct b44 *) __opaque;
544
545 spin_lock_irq(&bp->lock);
546
547 b44_check_phy(bp);
548
549 b44_stats_update(bp);
550
551 spin_unlock_irq(&bp->lock);
552
553 bp->timer.expires = jiffies + HZ;
554 add_timer(&bp->timer);
555}
556
557static void b44_tx(struct b44 *bp)
558{
559 u32 cur, cons;
560
561 cur = br32(B44_DMATX_STAT) & DMATX_STAT_CDMASK;
562 cur /= sizeof(struct dma_desc);
563
564
565 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
566 struct ring_info *rp = &bp->tx_buffers[cons];
567 struct sk_buff *skb = rp->skb;
568
569 if (unlikely(skb == NULL))
570 BUG();
571
572 pci_unmap_single(bp->pdev,
573 pci_unmap_addr(rp, mapping),
574 skb->len,
575 PCI_DMA_TODEVICE);
576 rp->skb = NULL;
577 dev_kfree_skb_irq(skb);
578 }
579
580 bp->tx_cons = cons;
581 if (netif_queue_stopped(bp->dev) &&
582 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
583 netif_wake_queue(bp->dev);
584
585 bw32(B44_GPTIMER, 0);
586}
587
588
589
590
591
592
593static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
594{
595 struct dma_desc *dp;
596 struct ring_info *src_map, *map;
597 struct rx_header *rh;
598 struct sk_buff *skb;
599 dma_addr_t mapping;
600 int dest_idx;
601 u32 ctrl;
602
603 src_map = NULL;
604 if (src_idx >= 0)
605 src_map = &bp->rx_buffers[src_idx];
606 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
607 map = &bp->rx_buffers[dest_idx];
608 skb = dev_alloc_skb(RX_PKT_BUF_SZ);
609 if (skb == NULL)
610 return -ENOMEM;
611
612 skb->dev = bp->dev;
613 mapping = pci_map_single(bp->pdev, skb->data,
614 RX_PKT_BUF_SZ,
615 PCI_DMA_FROMDEVICE);
616 skb_reserve(skb, bp->rx_offset);
617
618 rh = (struct rx_header *)
619 (skb->data - bp->rx_offset);
620 rh->len = 0;
621 rh->flags = 0;
622
623 map->skb = skb;
624 pci_unmap_addr_set(map, mapping, mapping);
625
626 if (src_map != NULL)
627 src_map->skb = NULL;
628
629 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
630 if (dest_idx == (B44_RX_RING_SIZE - 1))
631 ctrl |= DESC_CTRL_EOT;
632
633 dp = &bp->rx_ring[dest_idx];
634 dp->ctrl = cpu_to_le32(ctrl);
635 dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
636
637 return RX_PKT_BUF_SZ;
638}
639
640static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
641{
642 struct dma_desc *src_desc, *dest_desc;
643 struct ring_info *src_map, *dest_map;
644 struct rx_header *rh;
645 int dest_idx;
646 u32 ctrl;
647
648 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
649 dest_desc = &bp->rx_ring[dest_idx];
650 dest_map = &bp->rx_buffers[dest_idx];
651 src_desc = &bp->rx_ring[src_idx];
652 src_map = &bp->rx_buffers[src_idx];
653
654 dest_map->skb = src_map->skb;
655 rh = (struct rx_header *) src_map->skb->data;
656 rh->len = 0;
657 rh->flags = 0;
658 pci_unmap_addr_set(dest_map, mapping,
659 pci_unmap_addr(src_map, mapping));
660
661 ctrl = src_desc->ctrl;
662 if (dest_idx == (B44_RX_RING_SIZE - 1))
663 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
664 else
665 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
666
667 dest_desc->ctrl = ctrl;
668 dest_desc->addr = src_desc->addr;
669 src_map->skb = NULL;
670}
671
672static int b44_rx(struct b44 *bp, int budget)
673{
674 int received;
675 u32 cons, prod;
676
677 received = 0;
678 prod = br32(B44_DMARX_STAT) & DMARX_STAT_CDMASK;
679 prod /= sizeof(struct dma_desc);
680 cons = bp->rx_cons;
681
682 while (cons != prod && budget > 0) {
683 struct ring_info *rp = &bp->rx_buffers[cons];
684 struct sk_buff *skb = rp->skb;
685 dma_addr_t map = pci_unmap_addr(rp, mapping);
686 struct rx_header *rh;
687 u16 len;
688
689 pci_dma_sync_single(bp->pdev, map,
690 RX_PKT_BUF_SZ,
691 PCI_DMA_FROMDEVICE);
692 rh = (struct rx_header *) skb->data;
693 len = cpu_to_le16(rh->len);
694 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
695 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
696 drop_it:
697 b44_recycle_rx(bp, cons, bp->rx_prod);
698 drop_it_no_recycle:
699 bp->stats.rx_dropped++;
700 goto next_pkt;
701 }
702
703 if (len == 0) {
704 int i = 0;
705
706 do {
707 udelay(2);
708 barrier();
709 len = cpu_to_le16(rh->len);
710 } while (len == 0 && i++ < 5);
711 if (len == 0)
712 goto drop_it;
713 }
714
715
716 len -= 4;
717
718 if (len > RX_COPY_THRESHOLD) {
719 int skb_size;
720 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
721 if (skb_size < 0)
722 goto drop_it;
723 pci_unmap_single(bp->pdev, map,
724 skb_size, PCI_DMA_FROMDEVICE);
725
726 skb_put(skb, len+bp->rx_offset);
727 skb_pull(skb,bp->rx_offset);
728 } else {
729 struct sk_buff *copy_skb;
730
731 b44_recycle_rx(bp, cons, bp->rx_prod);
732 copy_skb = dev_alloc_skb(len + 2);
733 if (copy_skb == NULL)
734 goto drop_it_no_recycle;
735
736 copy_skb->dev = bp->dev;
737 skb_reserve(copy_skb, 2);
738 skb_put(copy_skb, len);
739
740 memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
741
742 skb = copy_skb;
743 }
744 skb->ip_summed = CHECKSUM_NONE;
745 skb->protocol = eth_type_trans(skb, bp->dev);
746 netif_receive_skb(skb);
747 bp->dev->last_rx = jiffies;
748 received++;
749 budget--;
750 next_pkt:
751 bp->rx_prod = (bp->rx_prod + 1) &
752 (B44_RX_RING_SIZE - 1);
753 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
754 }
755
756 bp->rx_cons = cons;
757 bw32(B44_DMARX_PTR, cons * sizeof(struct dma_desc));
758
759 return received;
760}
761
762static int b44_poll(struct net_device *netdev, int *budget)
763{
764 struct b44 *bp = netdev->priv;
765 int done;
766
767 spin_lock_irq(&bp->lock);
768
769 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
770
771 b44_tx(bp);
772
773 }
774 spin_unlock_irq(&bp->lock);
775
776 done = 1;
777 if (bp->istat & ISTAT_RX) {
778 int orig_budget = *budget;
779 int work_done;
780
781 if (orig_budget > netdev->quota)
782 orig_budget = netdev->quota;
783
784 work_done = b44_rx(bp, orig_budget);
785
786 *budget -= work_done;
787 netdev->quota -= work_done;
788
789 if (work_done >= orig_budget)
790 done = 0;
791 }
792
793 if (bp->istat & ISTAT_ERRORS) {
794 spin_lock_irq(&bp->lock);
795 b44_halt(bp);
796 b44_init_rings(bp);
797 b44_init_hw(bp);
798 netif_wake_queue(bp->dev);
799 spin_unlock_irq(&bp->lock);
800 done = 1;
801 }
802
803 if (done) {
804 netif_rx_complete(netdev);
805 b44_enable_ints(bp);
806 }
807
808 return (done ? 0 : 1);
809}
810
811static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
812{
813 struct net_device *dev = dev_id;
814 struct b44 *bp = dev->priv;
815 unsigned long flags;
816 u32 istat, imask;
817 int handled = 0;
818
819 spin_lock_irqsave(&bp->lock, flags);
820
821 istat = br32(B44_ISTAT);
822 imask = br32(B44_IMASK);
823
824
825
826
827 istat &= imask;
828 if (istat) {
829 handled = 1;
830 if (netif_rx_schedule_prep(dev)) {
831
832
833
834 bp->istat = istat;
835 __b44_disable_ints(bp);
836 __netif_rx_schedule(dev);
837 } else {
838 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
839 dev->name);
840 }
841
842 bw32(B44_ISTAT, istat);
843 br32(B44_ISTAT);
844 }
845 spin_unlock_irqrestore(&bp->lock, flags);
846 return IRQ_RETVAL(handled);
847}
848
849static void b44_tx_timeout(struct net_device *dev)
850{
851 struct b44 *bp = dev->priv;
852
853 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
854 dev->name);
855
856 spin_lock_irq(&bp->lock);
857
858 b44_halt(bp);
859 b44_init_rings(bp);
860 b44_init_hw(bp);
861
862 spin_unlock_irq(&bp->lock);
863
864 b44_enable_ints(bp);
865
866 netif_wake_queue(dev);
867}
868
869static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
870{
871 struct b44 *bp = dev->priv;
872 dma_addr_t mapping;
873 u32 len, entry, ctrl;
874
875 len = skb->len;
876 spin_lock_irq(&bp->lock);
877
878
879 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
880 netif_stop_queue(dev);
881 spin_unlock_irq(&bp->lock);
882 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
883 dev->name);
884 return 1;
885 }
886
887 entry = bp->tx_prod;
888 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
889
890 bp->tx_buffers[entry].skb = skb;
891 pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
892
893 ctrl = (len & DESC_CTRL_LEN);
894 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
895 if (entry == (B44_TX_RING_SIZE - 1))
896 ctrl |= DESC_CTRL_EOT;
897
898 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
899 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
900
901 entry = NEXT_TX(entry);
902
903 bp->tx_prod = entry;
904
905 wmb();
906
907 bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
908 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
909 bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
910 if (bp->flags & B44_FLAG_REORDER_BUG)
911 br32(B44_DMATX_PTR);
912
913 if (TX_BUFFS_AVAIL(bp) < 1)
914 netif_stop_queue(dev);
915
916 spin_unlock_irq(&bp->lock);
917
918 dev->trans_start = jiffies;
919
920 return 0;
921}
922
923static int b44_change_mtu(struct net_device *dev, int new_mtu)
924{
925 struct b44 *bp = dev->priv;
926
927 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
928 return -EINVAL;
929
930 if (!netif_running(dev)) {
931
932
933
934 dev->mtu = new_mtu;
935 return 0;
936 }
937
938 spin_lock_irq(&bp->lock);
939 b44_halt(bp);
940 dev->mtu = new_mtu;
941 b44_init_rings(bp);
942 b44_init_hw(bp);
943 spin_unlock_irq(&bp->lock);
944
945 b44_enable_ints(bp);
946
947 return 0;
948}
949
950
951
952
953
954
955
956
957static void b44_free_rings(struct b44 *bp)
958{
959 struct ring_info *rp;
960 int i;
961
962 for (i = 0; i < B44_RX_RING_SIZE; i++) {
963 rp = &bp->rx_buffers[i];
964
965 if (rp->skb == NULL)
966 continue;
967 pci_unmap_single(bp->pdev,
968 pci_unmap_addr(rp, mapping),
969 RX_PKT_BUF_SZ,
970 PCI_DMA_FROMDEVICE);
971 dev_kfree_skb_any(rp->skb);
972 rp->skb = NULL;
973 }
974
975
976 for (i = 0; i < B44_TX_RING_SIZE; i++) {
977 rp = &bp->tx_buffers[i];
978
979 if (rp->skb == NULL)
980 continue;
981 pci_unmap_single(bp->pdev,
982 pci_unmap_addr(rp, mapping),
983 rp->skb->len,
984 PCI_DMA_TODEVICE);
985 dev_kfree_skb_any(rp->skb);
986 rp->skb = NULL;
987 }
988}
989
990
991
992
993
994
995
996
997static void b44_init_rings(struct b44 *bp)
998{
999 int i;
1000
1001 b44_free_rings(bp);
1002
1003 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1004 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1005
1006 for (i = 0; i < bp->rx_pending; i++) {
1007 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1008 break;
1009 }
1010}
1011
1012
1013
1014
1015
1016static void b44_free_consistent(struct b44 *bp)
1017{
1018 if (bp->rx_buffers) {
1019 kfree(bp->rx_buffers);
1020 bp->rx_buffers = NULL;
1021 }
1022 if (bp->tx_buffers) {
1023 kfree(bp->tx_buffers);
1024 bp->tx_buffers = NULL;
1025 }
1026 if (bp->rx_ring) {
1027 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1028 bp->rx_ring, bp->rx_ring_dma);
1029 bp->rx_ring = NULL;
1030 }
1031 if (bp->tx_ring) {
1032 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1033 bp->tx_ring, bp->tx_ring_dma);
1034 bp->tx_ring = NULL;
1035 }
1036}
1037
1038
1039
1040
1041
1042static int b44_alloc_consistent(struct b44 *bp)
1043{
1044 int size;
1045
1046 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1047 bp->rx_buffers = kmalloc(size, GFP_KERNEL);
1048 if (!bp->rx_buffers)
1049 goto out_err;
1050 memset(bp->rx_buffers, 0, size);
1051
1052 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1053 bp->tx_buffers = kmalloc(size, GFP_KERNEL);
1054 if (!bp->tx_buffers)
1055 goto out_err;
1056 memset(bp->tx_buffers, 0, size);
1057
1058 size = DMA_TABLE_BYTES;
1059 bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1060 if (!bp->rx_ring)
1061 goto out_err;
1062
1063 bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1064 if (!bp->tx_ring)
1065 goto out_err;
1066
1067 return 0;
1068
1069out_err:
1070 b44_free_consistent(bp);
1071 return -ENOMEM;
1072}
1073
1074
1075static void b44_clear_stats(struct b44 *bp)
1076{
1077 unsigned long reg;
1078
1079 bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1080 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1081 br32(reg);
1082 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1083 br32(reg);
1084}
1085
1086
1087static void b44_chip_reset(struct b44 *bp)
1088{
1089 if (ssb_is_core_up(bp)) {
1090 bw32(B44_RCV_LAZY, 0);
1091 bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
1092 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1093 bw32(B44_DMATX_CTRL, 0);
1094 bp->tx_prod = bp->tx_cons = 0;
1095 if (br32(B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1096 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1097 100, 0);
1098 }
1099 bw32(B44_DMARX_CTRL, 0);
1100 bp->rx_prod = bp->rx_cons = 0;
1101 } else {
1102 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1103 SBINTVEC_ENET0 :
1104 SBINTVEC_ENET1));
1105 }
1106
1107 ssb_core_reset(bp);
1108
1109 b44_clear_stats(bp);
1110
1111
1112 bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1113 (0x0d & MDIO_CTRL_MAXF_MASK)));
1114 br32(B44_MDIO_CTRL);
1115
1116 if (!(br32(B44_DEVCTRL) & DEVCTRL_IPP)) {
1117 bw32(B44_ENET_CTRL, ENET_CTRL_EPSEL);
1118 br32(B44_ENET_CTRL);
1119 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1120 } else {
1121 u32 val = br32(B44_DEVCTRL);
1122
1123 if (val & DEVCTRL_EPR) {
1124 bw32(B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1125 br32(B44_DEVCTRL);
1126 udelay(100);
1127 }
1128 bp->flags |= B44_FLAG_INTERNAL_PHY;
1129 }
1130}
1131
1132
1133static void b44_halt(struct b44 *bp)
1134{
1135 b44_disable_ints(bp);
1136 b44_chip_reset(bp);
1137}
1138
1139
1140static void __b44_set_mac_addr(struct b44 *bp)
1141{
1142 bw32(B44_CAM_CTRL, 0);
1143 if (!(bp->dev->flags & IFF_PROMISC)) {
1144 u32 val;
1145
1146 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1147 val = br32(B44_CAM_CTRL);
1148 bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1149 }
1150}
1151
1152static int b44_set_mac_addr(struct net_device *dev, void *p)
1153{
1154 struct b44 *bp = dev->priv;
1155 struct sockaddr *addr = p;
1156
1157 if (netif_running(dev))
1158 return -EBUSY;
1159
1160 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1161
1162 spin_lock_irq(&bp->lock);
1163 __b44_set_mac_addr(bp);
1164 spin_unlock_irq(&bp->lock);
1165
1166 return 0;
1167}
1168
1169
1170
1171
1172static void __b44_set_rx_mode(struct net_device *);
1173static int b44_init_hw(struct b44 *bp)
1174{
1175 u32 val;
1176
1177 b44_disable_ints(bp);
1178 b44_chip_reset(bp);
1179 b44_phy_reset(bp);
1180 b44_setup_phy(bp);
1181 val = br32(B44_MAC_CTRL);
1182 bw32(B44_MAC_CTRL, val | MAC_CTRL_CRC32_ENAB);
1183 bw32(B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1184
1185
1186 __b44_set_rx_mode(bp->dev);
1187
1188
1189 bw32(B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1190 bw32(B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1191
1192 bw32(B44_TX_WMARK, 56);
1193 bw32(B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1194 bw32(B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1195 bw32(B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1196 (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1197 bw32(B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1198
1199 bw32(B44_DMARX_PTR, bp->rx_pending);
1200 bp->rx_prod = bp->rx_pending;
1201
1202 bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1203
1204 val = br32(B44_ENET_CTRL);
1205 bw32(B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1206
1207 return 0;
1208}
1209
1210static int b44_open(struct net_device *dev)
1211{
1212 struct b44 *bp = dev->priv;
1213 int err;
1214
1215 err = b44_alloc_consistent(bp);
1216 if (err)
1217 return err;
1218
1219 err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1220 if (err)
1221 goto err_out_free;
1222
1223 spin_lock_irq(&bp->lock);
1224
1225 b44_init_rings(bp);
1226 err = b44_init_hw(bp);
1227 if (err)
1228 goto err_out_noinit;
1229 bp->flags |= B44_FLAG_INIT_COMPLETE;
1230
1231 spin_unlock_irq(&bp->lock);
1232
1233 init_timer(&bp->timer);
1234 bp->timer.expires = jiffies + HZ;
1235 bp->timer.data = (unsigned long) bp;
1236 bp->timer.function = b44_timer;
1237 add_timer(&bp->timer);
1238
1239 b44_enable_ints(bp);
1240
1241 return 0;
1242
1243err_out_noinit:
1244 b44_halt(bp);
1245 b44_free_rings(bp);
1246 spin_unlock_irq(&bp->lock);
1247 free_irq(dev->irq, dev);
1248err_out_free:
1249 b44_free_consistent(bp);
1250 return err;
1251}
1252
1253#if 0
1254 void b44_dump_state(struct b44 *bp)
1255{
1256 u32 val32, val32_2, val32_3, val32_4, val32_5;
1257 u16 val16;
1258
1259 pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1260 printk("DEBUG: PCI status [%04x] \n", val16);
1261
1262}
1263#endif
1264
1265static int b44_close(struct net_device *dev)
1266{
1267 struct b44 *bp = dev->priv;
1268
1269 netif_stop_queue(dev);
1270
1271 del_timer_sync(&bp->timer);
1272
1273 spin_lock_irq(&bp->lock);
1274
1275#if 0
1276 b44_dump_state(bp);
1277#endif
1278 b44_halt(bp);
1279 b44_free_rings(bp);
1280 bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1281 netif_carrier_off(bp->dev);
1282
1283 spin_unlock_irq(&bp->lock);
1284
1285 free_irq(dev->irq, dev);
1286
1287 b44_free_consistent(bp);
1288
1289 return 0;
1290}
1291
1292static struct net_device_stats *b44_get_stats(struct net_device *dev)
1293{
1294 struct b44 *bp = dev->priv;
1295 struct net_device_stats *nstat = &bp->stats;
1296 struct b44_hw_stats *hwstat = &bp->hw_stats;
1297
1298
1299 nstat->rx_packets = hwstat->rx_pkts;
1300 nstat->tx_packets = hwstat->tx_pkts;
1301 nstat->rx_bytes = hwstat->rx_octets;
1302 nstat->tx_bytes = hwstat->tx_octets;
1303 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1304 hwstat->tx_oversize_pkts +
1305 hwstat->tx_underruns +
1306 hwstat->tx_excessive_cols +
1307 hwstat->tx_late_cols);
1308 nstat->multicast = hwstat->tx_multicast_pkts;
1309 nstat->collisions = hwstat->tx_total_cols;
1310
1311 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1312 hwstat->rx_undersize);
1313 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1314 nstat->rx_frame_errors = hwstat->rx_align_errs;
1315 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1316 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1317 hwstat->rx_oversize_pkts +
1318 hwstat->rx_missed_pkts +
1319 hwstat->rx_crc_align_errs +
1320 hwstat->rx_undersize +
1321 hwstat->rx_crc_errs +
1322 hwstat->rx_align_errs +
1323 hwstat->rx_symbol_errs);
1324
1325 nstat->tx_aborted_errors = hwstat->tx_underruns;
1326 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1327
1328 return nstat;
1329}
1330
1331static void __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1332{
1333 struct dev_mc_list *mclist;
1334 int i, num_ents;
1335
1336 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1337 mclist = dev->mc_list;
1338 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1339 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1340 }
1341}
1342
1343static void __b44_set_rx_mode(struct net_device *dev)
1344{
1345 struct b44 *bp = dev->priv;
1346 u32 val;
1347
1348 val = br32(B44_RXCONFIG);
1349 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1350 if (dev->flags & IFF_PROMISC) {
1351 val |= RXCONFIG_PROMISC;
1352 bw32(B44_RXCONFIG, val);
1353 } else {
1354 __b44_set_mac_addr(bp);
1355
1356 if (dev->flags & IFF_ALLMULTI)
1357 val |= RXCONFIG_ALLMULTI;
1358 else
1359 __b44_load_mcast(bp, dev);
1360
1361 bw32(B44_RXCONFIG, val);
1362 val = br32(B44_CAM_CTRL);
1363 bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1364 }
1365}
1366
1367static void b44_set_rx_mode(struct net_device *dev)
1368{
1369 struct b44 *bp = dev->priv;
1370
1371 spin_lock_irq(&bp->lock);
1372 __b44_set_rx_mode(dev);
1373 spin_unlock_irq(&bp->lock);
1374}
1375
1376static int b44_ethtool_ioctl (struct net_device *dev, void *useraddr)
1377{
1378 struct b44 *bp = dev->priv;
1379 struct pci_dev *pci_dev = bp->pdev;
1380 u32 ethcmd;
1381
1382 if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd)))
1383 return -EFAULT;
1384
1385 switch (ethcmd) {
1386 case ETHTOOL_GDRVINFO:{
1387 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1388 strcpy (info.driver, DRV_MODULE_NAME);
1389 strcpy (info.version, DRV_MODULE_VERSION);
1390 memset(&info.fw_version, 0, sizeof(info.fw_version));
1391 strcpy (info.bus_info, pci_name(pci_dev));
1392 info.eedump_len = 0;
1393 info.regdump_len = 0;
1394 if (copy_to_user (useraddr, &info, sizeof (info)))
1395 return -EFAULT;
1396 return 0;
1397 }
1398
1399 case ETHTOOL_GSET: {
1400 struct ethtool_cmd cmd = { ETHTOOL_GSET };
1401
1402 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1403 return -EAGAIN;
1404 cmd.supported = (SUPPORTED_Autoneg);
1405 cmd.supported |= (SUPPORTED_100baseT_Half |
1406 SUPPORTED_100baseT_Full |
1407 SUPPORTED_10baseT_Half |
1408 SUPPORTED_10baseT_Full |
1409 SUPPORTED_MII);
1410
1411 cmd.advertising = 0;
1412 if (bp->flags & B44_FLAG_ADV_10HALF)
1413 cmd.advertising |= ADVERTISE_10HALF;
1414 if (bp->flags & B44_FLAG_ADV_10FULL)
1415 cmd.advertising |= ADVERTISE_10FULL;
1416 if (bp->flags & B44_FLAG_ADV_100HALF)
1417 cmd.advertising |= ADVERTISE_100HALF;
1418 if (bp->flags & B44_FLAG_ADV_100FULL)
1419 cmd.advertising |= ADVERTISE_100FULL;
1420 cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1421 cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1422 SPEED_100 : SPEED_10;
1423 cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1424 DUPLEX_FULL : DUPLEX_HALF;
1425 cmd.port = 0;
1426 cmd.phy_address = bp->phy_addr;
1427 cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1428 XCVR_INTERNAL : XCVR_EXTERNAL;
1429 cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1430 AUTONEG_DISABLE : AUTONEG_ENABLE;
1431 cmd.maxtxpkt = 0;
1432 cmd.maxrxpkt = 0;
1433 if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
1434 return -EFAULT;
1435 return 0;
1436 }
1437 case ETHTOOL_SSET: {
1438 struct ethtool_cmd cmd;
1439
1440 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1441 return -EAGAIN;
1442
1443 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
1444 return -EFAULT;
1445
1446
1447 if (cmd.autoneg == AUTONEG_ENABLE) {
1448 if (cmd.advertising &
1449 (ADVERTISED_1000baseT_Half |
1450 ADVERTISED_1000baseT_Full))
1451 return -EINVAL;
1452 } else if ((cmd.speed != SPEED_100 &&
1453 cmd.speed != SPEED_10) ||
1454 (cmd.duplex != DUPLEX_HALF &&
1455 cmd.duplex != DUPLEX_FULL)) {
1456 return -EINVAL;
1457 }
1458
1459 spin_lock_irq(&bp->lock);
1460
1461 if (cmd.autoneg == AUTONEG_ENABLE) {
1462 bp->flags &= ~B44_FLAG_FORCE_LINK;
1463 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1464 B44_FLAG_ADV_10FULL |
1465 B44_FLAG_ADV_100HALF |
1466 B44_FLAG_ADV_100FULL);
1467 if (cmd.advertising & ADVERTISE_10HALF)
1468 bp->flags |= B44_FLAG_ADV_10HALF;
1469 if (cmd.advertising & ADVERTISE_10FULL)
1470 bp->flags |= B44_FLAG_ADV_10FULL;
1471 if (cmd.advertising & ADVERTISE_100HALF)
1472 bp->flags |= B44_FLAG_ADV_100HALF;
1473 if (cmd.advertising & ADVERTISE_100FULL)
1474 bp->flags |= B44_FLAG_ADV_100FULL;
1475 } else {
1476 bp->flags |= B44_FLAG_FORCE_LINK;
1477 if (cmd.speed == SPEED_100)
1478 bp->flags |= B44_FLAG_100_BASE_T;
1479 if (cmd.duplex == DUPLEX_FULL)
1480 bp->flags |= B44_FLAG_FULL_DUPLEX;
1481 }
1482
1483 b44_setup_phy(bp);
1484
1485 spin_unlock_irq(&bp->lock);
1486
1487 return 0;
1488 }
1489
1490 case ETHTOOL_GMSGLVL: {
1491 struct ethtool_value edata = { ETHTOOL_GMSGLVL };
1492 edata.data = bp->msg_enable;
1493 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1494 return -EFAULT;
1495 return 0;
1496 }
1497 case ETHTOOL_SMSGLVL: {
1498 struct ethtool_value edata;
1499 if (copy_from_user(&edata, useraddr, sizeof(edata)))
1500 return -EFAULT;
1501 bp->msg_enable = edata.data;
1502 return 0;
1503 }
1504 case ETHTOOL_NWAY_RST: {
1505 u32 bmcr;
1506 int r;
1507
1508 spin_lock_irq(&bp->lock);
1509 b44_readphy(bp, MII_BMCR, &bmcr);
1510 b44_readphy(bp, MII_BMCR, &bmcr);
1511 r = -EINVAL;
1512 if (bmcr & BMCR_ANENABLE) {
1513 b44_writephy(bp, MII_BMCR,
1514 bmcr | BMCR_ANRESTART);
1515 r = 0;
1516 }
1517 spin_unlock_irq(&bp->lock);
1518
1519 return r;
1520 }
1521 case ETHTOOL_GLINK: {
1522 struct ethtool_value edata = { ETHTOOL_GLINK };
1523 edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
1524 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1525 return -EFAULT;
1526 return 0;
1527 }
1528 case ETHTOOL_GRINGPARAM: {
1529 struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
1530
1531 ering.rx_max_pending = B44_RX_RING_SIZE - 1;
1532 ering.rx_pending = bp->rx_pending;
1533
1534
1535
1536 if (copy_to_user(useraddr, &ering, sizeof(ering)))
1537 return -EFAULT;
1538 return 0;
1539 }
1540 case ETHTOOL_SRINGPARAM: {
1541 struct ethtool_ringparam ering;
1542
1543 if (copy_from_user(&ering, useraddr, sizeof(ering)))
1544 return -EFAULT;
1545
1546 if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
1547 (ering.rx_mini_pending != 0) ||
1548 (ering.rx_jumbo_pending != 0) ||
1549 (ering.tx_pending > B44_TX_RING_SIZE - 1))
1550 return -EINVAL;
1551
1552 spin_lock_irq(&bp->lock);
1553
1554 bp->rx_pending = ering.rx_pending;
1555 bp->tx_pending = ering.tx_pending;
1556
1557 b44_halt(bp);
1558 b44_init_rings(bp);
1559 b44_init_hw(bp);
1560 netif_wake_queue(bp->dev);
1561 spin_unlock_irq(&bp->lock);
1562
1563 b44_enable_ints(bp);
1564
1565 return 0;
1566 }
1567 case ETHTOOL_GPAUSEPARAM: {
1568 struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
1569
1570 epause.autoneg =
1571 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1572 epause.rx_pause =
1573 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1574 epause.tx_pause =
1575 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1576 if (copy_to_user(useraddr, &epause, sizeof(epause)))
1577 return -EFAULT;
1578 return 0;
1579 }
1580 case ETHTOOL_SPAUSEPARAM: {
1581 struct ethtool_pauseparam epause;
1582
1583 if (copy_from_user(&epause, useraddr, sizeof(epause)))
1584 return -EFAULT;
1585
1586 spin_lock_irq(&bp->lock);
1587 if (epause.autoneg)
1588 bp->flags |= B44_FLAG_PAUSE_AUTO;
1589 else
1590 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1591 if (epause.rx_pause)
1592 bp->flags |= B44_FLAG_RX_PAUSE;
1593 else
1594 bp->flags &= ~B44_FLAG_RX_PAUSE;
1595 if (epause.tx_pause)
1596 bp->flags |= B44_FLAG_TX_PAUSE;
1597 else
1598 bp->flags &= ~B44_FLAG_TX_PAUSE;
1599 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1600 b44_halt(bp);
1601 b44_init_rings(bp);
1602 b44_init_hw(bp);
1603 } else {
1604 __b44_set_flow_ctrl(bp, bp->flags);
1605 }
1606 spin_unlock_irq(&bp->lock);
1607
1608 b44_enable_ints(bp);
1609
1610 return 0;
1611 }
1612 };
1613
1614 return -EOPNOTSUPP;
1615}
1616
1617static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1618{
1619 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data;
1620 struct b44 *bp = dev->priv;
1621 int err;
1622
1623 switch (cmd) {
1624 case SIOCETHTOOL:
1625 return b44_ethtool_ioctl(dev, (void *) ifr->ifr_data);
1626
1627 case SIOCGMIIPHY:
1628 data->phy_id = bp->phy_addr;
1629
1630
1631 case SIOCGMIIREG: {
1632 u32 mii_regval;
1633
1634 spin_lock_irq(&bp->lock);
1635 err = b44_readphy(bp, data->reg_num & 0x1f, &mii_regval);
1636 spin_unlock_irq(&bp->lock);
1637
1638 data->val_out = mii_regval;
1639
1640 return err;
1641 }
1642
1643 case SIOCSMIIREG:
1644 if (!capable(CAP_NET_ADMIN))
1645 return -EPERM;
1646
1647 spin_lock_irq(&bp->lock);
1648 err = b44_writephy(bp, data->reg_num & 0x1f, data->val_in);
1649 spin_unlock_irq(&bp->lock);
1650
1651 return err;
1652
1653 default:
1654
1655 break;
1656 };
1657 return -EOPNOTSUPP;
1658}
1659
1660
1661static int b44_read_eeprom(struct b44 *bp, u8 *data)
1662{
1663 long i;
1664 u16 *ptr = (u16 *) data;
1665
1666 for (i = 0; i < 128; i += 2)
1667 ptr[i / 2] = readw(bp->regs + 4096 + i);
1668
1669 return 0;
1670}
1671
1672static int __devinit b44_get_invariants(struct b44 *bp)
1673{
1674 u8 eeprom[128];
1675 int err;
1676
1677 err = b44_read_eeprom(bp, &eeprom[0]);
1678 if (err)
1679 goto out;
1680
1681 bp->dev->dev_addr[0] = eeprom[79];
1682 bp->dev->dev_addr[1] = eeprom[78];
1683 bp->dev->dev_addr[2] = eeprom[81];
1684 bp->dev->dev_addr[3] = eeprom[80];
1685 bp->dev->dev_addr[4] = eeprom[83];
1686 bp->dev->dev_addr[5] = eeprom[82];
1687
1688 bp->phy_addr = eeprom[90] & 0x1f;
1689 bp->mdc_port = (eeprom[90] >> 14) & 0x1;
1690
1691
1692
1693
1694 bp->rx_offset = 30;
1695
1696 bp->imask = IMASK_DEF;
1697
1698 bp->core_unit = ssb_core_unit(bp);
1699 bp->dma_offset = ssb_get_addr(bp, SBID_PCI_DMA, 0);
1700
1701
1702
1703
1704out:
1705 return err;
1706}
1707
1708static int __devinit b44_init_one(struct pci_dev *pdev,
1709 const struct pci_device_id *ent)
1710{
1711 static int b44_version_printed = 0;
1712 unsigned long b44reg_base, b44reg_len;
1713 struct net_device *dev;
1714 struct b44 *bp;
1715 int err, i;
1716
1717 if (b44_version_printed++ == 0)
1718 printk(KERN_INFO "%s", version);
1719
1720 err = pci_enable_device(pdev);
1721 if (err) {
1722 printk(KERN_ERR PFX "Cannot enable PCI device, "
1723 "aborting.\n");
1724 return err;
1725 }
1726
1727 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1728 printk(KERN_ERR PFX "Cannot find proper PCI device "
1729 "base address, aborting.\n");
1730 err = -ENODEV;
1731 goto err_out_disable_pdev;
1732 }
1733
1734 err = pci_request_regions(pdev, DRV_MODULE_NAME);
1735 if (err) {
1736 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1737 "aborting.\n");
1738 goto err_out_disable_pdev;
1739 }
1740
1741 pci_set_master(pdev);
1742
1743 err = pci_set_dma_mask(pdev, (u64) 0xffffffff);
1744 if (err) {
1745 printk(KERN_ERR PFX "No usable DMA configuration, "
1746 "aborting.\n");
1747 goto err_out_free_res;
1748 }
1749
1750 b44reg_base = pci_resource_start(pdev, 0);
1751 b44reg_len = pci_resource_len(pdev, 0);
1752
1753 dev = alloc_etherdev(sizeof(*bp));
1754 if (!dev) {
1755 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1756 err = -ENOMEM;
1757 goto err_out_free_res;
1758 }
1759
1760 SET_MODULE_OWNER(dev);
1761 SET_NETDEV_DEV(dev,&pdev->dev);
1762
1763
1764 dev->features |= 0;
1765
1766 bp = dev->priv;
1767 bp->pdev = pdev;
1768 bp->dev = dev;
1769 if (b44_debug >= 0)
1770 bp->msg_enable = (1 << b44_debug) - 1;
1771 else
1772 bp->msg_enable = B44_DEF_MSG_ENABLE;
1773
1774 spin_lock_init(&bp->lock);
1775
1776 bp->regs = (unsigned long) ioremap(b44reg_base, b44reg_len);
1777 if (bp->regs == 0UL) {
1778 printk(KERN_ERR PFX "Cannot map device registers, "
1779 "aborting.\n");
1780 err = -ENOMEM;
1781 goto err_out_free_dev;
1782 }
1783
1784 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1785 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1786
1787 dev->open = b44_open;
1788 dev->stop = b44_close;
1789 dev->hard_start_xmit = b44_start_xmit;
1790 dev->get_stats = b44_get_stats;
1791 dev->set_multicast_list = b44_set_rx_mode;
1792 dev->set_mac_address = b44_set_mac_addr;
1793 dev->do_ioctl = b44_ioctl;
1794 dev->tx_timeout = b44_tx_timeout;
1795 dev->poll = b44_poll;
1796 dev->weight = 64;
1797 dev->watchdog_timeo = B44_TX_TIMEOUT;
1798 dev->change_mtu = b44_change_mtu;
1799 dev->irq = pdev->irq;
1800
1801 err = b44_get_invariants(bp);
1802 if (err) {
1803 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1804 "aborting.\n");
1805 goto err_out_iounmap;
1806 }
1807
1808
1809 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
1810 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
1811
1812
1813 bp->flags |= B44_FLAG_PAUSE_AUTO;
1814
1815 err = register_netdev(dev);
1816 if (err) {
1817 printk(KERN_ERR PFX "Cannot register net device, "
1818 "aborting.\n");
1819 goto err_out_iounmap;
1820 }
1821
1822 pci_set_drvdata(pdev, dev);
1823
1824 pci_save_state(bp->pdev, bp->pci_cfg_state);
1825
1826 printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1827 for (i = 0; i < 6; i++)
1828 printk("%2.2x%c", dev->dev_addr[i],
1829 i == 5 ? '\n' : ':');
1830
1831 return 0;
1832
1833err_out_iounmap:
1834 iounmap((void *) bp->regs);
1835
1836err_out_free_dev:
1837 free_netdev(dev);
1838
1839err_out_free_res:
1840 pci_release_regions(pdev);
1841
1842err_out_disable_pdev:
1843 pci_disable_device(pdev);
1844 pci_set_drvdata(pdev, NULL);
1845 return err;
1846}
1847
1848static void __devexit b44_remove_one(struct pci_dev *pdev)
1849{
1850 struct net_device *dev = pci_get_drvdata(pdev);
1851
1852 if (dev) {
1853 unregister_netdev(dev);
1854 iounmap((void *) ((struct b44 *)(dev->priv))->regs);
1855 free_netdev(dev);
1856 pci_release_regions(pdev);
1857 pci_disable_device(pdev);
1858 pci_set_drvdata(pdev, NULL);
1859 }
1860}
1861
1862static int b44_suspend(struct pci_dev *pdev, u32 state)
1863{
1864 struct net_device *dev = pci_get_drvdata(pdev);
1865 struct b44 *bp = dev->priv;
1866
1867 if (!netif_running(dev))
1868 return 0;
1869
1870 del_timer_sync(&bp->timer);
1871
1872 spin_lock_irq(&bp->lock);
1873
1874 b44_halt(bp);
1875 netif_carrier_off(bp->dev);
1876 netif_device_detach(bp->dev);
1877 b44_free_rings(bp);
1878
1879 spin_unlock_irq(&bp->lock);
1880 return 0;
1881}
1882
1883static int b44_resume(struct pci_dev *pdev)
1884{
1885 struct net_device *dev = pci_get_drvdata(pdev);
1886 struct b44 *bp = dev->priv;
1887
1888 if (!netif_running(dev))
1889 return 0;
1890
1891 spin_lock_irq(&bp->lock);
1892
1893 b44_init_rings(bp);
1894 b44_init_hw(bp);
1895 netif_device_attach(bp->dev);
1896 spin_unlock_irq(&bp->lock);
1897
1898 bp->timer.expires = jiffies + HZ;
1899 add_timer(&bp->timer);
1900
1901 b44_enable_ints(bp);
1902 return 0;
1903}
1904
1905static struct pci_driver b44_driver = {
1906 .name = DRV_MODULE_NAME,
1907 .id_table = b44_pci_tbl,
1908 .probe = b44_init_one,
1909 .remove = __devexit_p(b44_remove_one),
1910 .suspend = b44_suspend,
1911 .resume = b44_resume,
1912};
1913
1914static int __init b44_init(void)
1915{
1916 return pci_module_init(&b44_driver);
1917}
1918
1919static void __exit b44_cleanup(void)
1920{
1921 pci_unregister_driver(&b44_driver);
1922}
1923
1924module_init(b44_init);
1925module_exit(b44_cleanup);
1926
1927
