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53#include <linux/config.h>
54#include <linux/module.h>
55#include <linux/version.h>
56#include <linux/types.h>
57#include <linux/errno.h>
58#include <linux/ioport.h>
59#include <linux/pci.h>
60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
69
70#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
71#include <linux/if_vlan.h>
72#endif
73
74#ifdef SIOCETHTOOL
75#include <linux/ethtool.h>
76#endif
77
78#include <net/sock.h>
79#include <net/ip.h>
80
81#include <asm/system.h>
82#include <asm/io.h>
83#include <asm/irq.h>
84#include <asm/byteorder.h>
85#include <asm/uaccess.h>
86
87
88#undef INDEX_DEBUG
89
90#ifdef CONFIG_ACENIC_OMIT_TIGON_I
91#define ACE_IS_TIGON_I(ap) 0
92#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
93#else
94#define ACE_IS_TIGON_I(ap) (ap->version == 1)
95#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
96#endif
97
98#ifndef PCI_VENDOR_ID_ALTEON
99#define PCI_VENDOR_ID_ALTEON 0x12ae
100#endif
101#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
102#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
103#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
104#endif
105#ifndef PCI_DEVICE_ID_3COM_3C985
106#define PCI_DEVICE_ID_3COM_3C985 0x0001
107#endif
108#ifndef PCI_VENDOR_ID_NETGEAR
109#define PCI_VENDOR_ID_NETGEAR 0x1385
110#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
111#endif
112#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
113#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
114#endif
115
116
117
118
119
120
121#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
122#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
123#endif
124#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
125#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
126#endif
127#ifndef PCI_VENDOR_ID_SGI
128#define PCI_VENDOR_ID_SGI 0x10a9
129#endif
130#ifndef PCI_DEVICE_ID_SGI_ACENIC
131#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
132#endif
133
134#if LINUX_VERSION_CODE >= 0x20400
135static struct pci_device_id acenic_pci_tbl[] = {
136 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
137 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
138 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
139 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
140 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
141 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
142 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
143 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
144 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
145 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
146
147
148
149
150 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
151 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
152 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
153 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
154 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
155 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
156 { }
157};
158MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
159#endif
160
161
162#ifndef MODULE_LICENSE
163#define MODULE_LICENSE(a)
164#endif
165
166#ifndef wmb
167#define wmb() mb()
168#endif
169
170#ifndef __exit
171#define __exit
172#endif
173
174#ifndef __devinit
175#define __devinit __init
176#endif
177
178#ifndef SMP_CACHE_BYTES
179#define SMP_CACHE_BYTES L1_CACHE_BYTES
180#endif
181
182#ifndef SET_MODULE_OWNER
183#define SET_MODULE_OWNER(dev) do{} while(0)
184#define ACE_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
185#define ACE_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
186#else
187#define ACE_MOD_INC_USE_COUNT do{} while(0)
188#define ACE_MOD_DEC_USE_COUNT do{} while(0)
189#endif
190
191#ifndef SET_NETDEV_DEV
192#define SET_NETDEV_DEV(net, pdev) do{} while(0)
193#endif
194
195#if LINUX_VERSION_CODE >= 0x2051c
196#define ace_sync_irq(irq) synchronize_irq(irq)
197#else
198#define ace_sync_irq(irq) synchronize_irq()
199#endif
200
201#if LINUX_VERSION_CODE < 0x2051e
202#define local_irq_save(flags) do{__save_flags(flags) ; \
203 __cli();} while(0)
204#define local_irq_restore(flags) __restore_flags(flags)
205#endif
206
207#if (LINUX_VERSION_CODE < 0x02030d)
208#define pci_resource_start(dev, bar) dev->base_address[bar]
209#elif (LINUX_VERSION_CODE < 0x02032c)
210#define pci_resource_start(dev, bar) dev->resource[bar].start
211#endif
212
213#if (LINUX_VERSION_CODE < 0x02030e)
214#define net_device device
215#endif
216
217
218#if (LINUX_VERSION_CODE < 0x02032a)
219typedef u32 dma_addr_t;
220
221static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
222 dma_addr_t *dma_handle)
223{
224 void *virt_ptr;
225
226 virt_ptr = kmalloc(size, GFP_KERNEL);
227 if (!virt_ptr)
228 return NULL;
229 *dma_handle = virt_to_bus(virt_ptr);
230 return virt_ptr;
231}
232
233#define pci_free_consistent(cookie, size, ptr, dma_ptr) kfree(ptr)
234#define pci_map_page(cookie, page, off, size, dir) \
235 virt_to_bus(page_address(page)+(off))
236#define pci_unmap_page(cookie, address, size, dir)
237#define pci_set_dma_mask(dev, mask) \
238 (((u64)(mask) & 0xffffffff00000000) == 0 ? 0 : -EIO)
239#define pci_dma_supported(dev, mask) \
240 (((u64)(mask) & 0xffffffff00000000) == 0 ? 1 : 0)
241
242#elif (LINUX_VERSION_CODE < 0x02040d)
243
244
245
246
247
248
249
250
251static inline dma_addr_t
252pci_map_page(struct pci_dev *cookie, struct page *page, unsigned long off,
253 size_t size, int dir)
254{
255 void *page_virt;
256
257 page_virt = page_address(page);
258 if (!page_virt)
259 BUG();
260 return pci_map_single(cookie, (page_virt + off), size, dir);
261}
262#define pci_unmap_page(cookie, dma_addr, size, dir) \
263 pci_unmap_single(cookie, dma_addr, size, dir)
264#endif
265
266#if (LINUX_VERSION_CODE < 0x020412)
267#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
268#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
269#define pci_unmap_addr(PTR, ADDR_NAME) 0
270#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do{} while(0)
271#define pci_unmap_len(PTR, LEN_NAME) 0
272#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do{} while(0)
273#endif
274
275
276#if (LINUX_VERSION_CODE < 0x02032b)
277
278
279
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281
282
283
284
285
286
287#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
288#define netif_wake_queue(dev) clear_bit(0, &dev->tbusy)
289#define netif_stop_queue(dev) set_bit(0, &dev->tbusy)
290#define late_stop_netif_stop_queue(dev) do{} while(0)
291#define early_stop_netif_stop_queue(dev) test_and_set_bit(0,&dev->tbusy)
292#define early_stop_netif_wake_queue(dev) netif_wake_queue(dev)
293
294static inline void netif_start_queue(struct net_device *dev)
295{
296 dev->tbusy = 0;
297 dev->interrupt = 0;
298 dev->start = 1;
299}
300
301#define ace_mark_net_bh() mark_bh(NET_BH)
302#define netif_queue_stopped(dev) dev->tbusy
303#define netif_running(dev) dev->start
304#define ace_if_down(dev) do{dev->start = 0;} while(0)
305
306#define tasklet_struct tq_struct
307static inline void tasklet_schedule(struct tasklet_struct *tasklet)
308{
309 queue_task(tasklet, &tq_immediate);
310 mark_bh(IMMEDIATE_BH);
311}
312
313static inline void tasklet_init(struct tasklet_struct *tasklet,
314 void (*func)(unsigned long),
315 unsigned long data)
316{
317 tasklet->next = NULL;
318 tasklet->sync = 0;
319 tasklet->routine = (void (*)(void *))func;
320 tasklet->data = (void *)data;
321}
322#define tasklet_kill(tasklet) do{} while(0)
323#else
324#define late_stop_netif_stop_queue(dev) netif_stop_queue(dev)
325#define early_stop_netif_stop_queue(dev) 0
326#define early_stop_netif_wake_queue(dev) do{} while(0)
327#define ace_mark_net_bh() do{} while(0)
328#define ace_if_down(dev) do{} while(0)
329#endif
330
331#if (LINUX_VERSION_CODE >= 0x02031b)
332#define NEW_NETINIT
333#define ACE_PROBE_ARG void
334#else
335#define ACE_PROBE_ARG struct net_device *dev
336#endif
337
338#ifndef min_t
339#define min_t(type,a,b) (((a)<(b))?(a):(b))
340#endif
341
342#ifndef ARCH_HAS_PREFETCHW
343#ifndef prefetchw
344#define prefetchw(x) do{} while(0)
345#endif
346#endif
347
348#define ACE_MAX_MOD_PARMS 8
349#define BOARD_IDX_STATIC 0
350#define BOARD_IDX_OVERFLOW -1
351
352#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
353 defined(NETIF_F_HW_VLAN_RX)
354#define ACENIC_DO_VLAN 1
355#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
356#else
357#define ACENIC_DO_VLAN 0
358#define ACE_RCB_VLAN_FLAG 0
359#endif
360
361#include "acenic.h"
362
363
364
365
366#define MAX_TEXT_LEN 96*1024
367#define MAX_RODATA_LEN 8*1024
368#define MAX_DATA_LEN 2*1024
369
370#include "acenic_firmware.h"
371
372#ifndef tigon2FwReleaseLocal
373#define tigon2FwReleaseLocal 0
374#endif
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523
524#define RX_RING_SIZE 72
525#define RX_MINI_SIZE 64
526#define RX_JUMBO_SIZE 48
527
528#define RX_PANIC_STD_THRES 16
529#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
530#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
531#define RX_PANIC_MINI_THRES 12
532#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
533#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
534#define RX_PANIC_JUMBO_THRES 6
535#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
536#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
537
538
539
540
541
542
543#define ACE_MINI_SIZE 100
544
545#define ACE_MINI_BUFSIZE (ACE_MINI_SIZE + 2 + 16)
546#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 2+4+16)
547#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 2+4+16)
548
549
550
551
552
553
554
555
556
557#define DEF_TX_COAL 400
558#define DEF_TX_MAX_DESC 60
559#define DEF_RX_COAL 120
560#define DEF_RX_MAX_DESC 25
561#define DEF_TX_RATIO 21
562
563#define DEF_JUMBO_TX_COAL 20
564#define DEF_JUMBO_TX_MAX_DESC 60
565#define DEF_JUMBO_RX_COAL 30
566#define DEF_JUMBO_RX_MAX_DESC 6
567#define DEF_JUMBO_TX_RATIO 21
568
569#if tigon2FwReleaseLocal < 20001118
570
571
572
573
574
575
576
577#define TX_COAL_INTS_ONLY 1
578#else
579
580
581
582#define TX_COAL_INTS_ONLY 1
583#endif
584
585#define DEF_TRACE 0
586#define DEF_STAT (2 * TICKS_PER_SEC)
587
588
589static int link[ACE_MAX_MOD_PARMS];
590static int trace[ACE_MAX_MOD_PARMS];
591static int tx_coal_tick[ACE_MAX_MOD_PARMS];
592static int rx_coal_tick[ACE_MAX_MOD_PARMS];
593static int max_tx_desc[ACE_MAX_MOD_PARMS];
594static int max_rx_desc[ACE_MAX_MOD_PARMS];
595static int tx_ratio[ACE_MAX_MOD_PARMS];
596static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
597
598static char version[] __initdata =
599 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
600 " http://home.cern.ch/~jes/gige/acenic.html\n";
601
602static struct net_device *root_dev;
603
604static int probed __initdata = 0;
605
606
607int __devinit acenic_probe (ACE_PROBE_ARG)
608{
609#ifdef NEW_NETINIT
610 struct net_device *dev;
611#endif
612 struct ace_private *ap;
613 struct pci_dev *pdev = NULL;
614 int boards_found = 0;
615 int version_disp;
616
617 if (probed)
618 return -ENODEV;
619 probed++;
620
621 version_disp = 0;
622
623 while ((pdev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET<<8, pdev))) {
624
625 if (!((pdev->vendor == PCI_VENDOR_ID_ALTEON) &&
626 ((pdev->device == PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE) ||
627 (pdev->device == PCI_DEVICE_ID_ALTEON_ACENIC_COPPER)))&&
628 !((pdev->vendor == PCI_VENDOR_ID_3COM) &&
629 (pdev->device == PCI_DEVICE_ID_3COM_3C985)) &&
630 !((pdev->vendor == PCI_VENDOR_ID_NETGEAR) &&
631 ((pdev->device == PCI_DEVICE_ID_NETGEAR_GA620) ||
632 (pdev->device == PCI_DEVICE_ID_NETGEAR_GA620T))) &&
633
634
635
636
637 !((pdev->vendor == PCI_VENDOR_ID_DEC) &&
638 (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX)) &&
639 !((pdev->vendor == PCI_VENDOR_ID_ALTEON) &&
640 (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T)) &&
641 !((pdev->vendor == PCI_VENDOR_ID_SGI) &&
642 (pdev->device == PCI_DEVICE_ID_SGI_ACENIC)))
643 continue;
644
645 dev = alloc_etherdev(sizeof(struct ace_private));
646 if (dev == NULL) {
647 printk(KERN_ERR "acenic: Unable to allocate "
648 "net_device structure!\n");
649 break;
650 }
651
652 SET_MODULE_OWNER(dev);
653 SET_NETDEV_DEV(dev, &pdev->dev);
654
655 ap = dev->priv;
656 ap->pdev = pdev;
657
658 dev->open = &ace_open;
659 dev->hard_start_xmit = &ace_start_xmit;
660 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
661#if ACENIC_DO_VLAN
662 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
663 dev->vlan_rx_register = ace_vlan_rx_register;
664 dev->vlan_rx_kill_vid = ace_vlan_rx_kill_vid;
665#endif
666 if (1) {
667 static void ace_watchdog(struct net_device *dev);
668 dev->tx_timeout = &ace_watchdog;
669 dev->watchdog_timeo = 5*HZ;
670 }
671 dev->stop = &ace_close;
672 dev->get_stats = &ace_get_stats;
673 dev->set_multicast_list = &ace_set_multicast_list;
674 dev->do_ioctl = &ace_ioctl;
675 dev->set_mac_address = &ace_set_mac_addr;
676 dev->change_mtu = &ace_change_mtu;
677
678
679 if (!version_disp)
680 {
681
682
683 version_disp = 1;
684 printk(version);
685 }
686
687 if (pci_enable_device(pdev)) {
688 free_netdev(dev);
689 continue;
690 }
691
692
693
694
695
696
697 pci_set_master(pdev);
698
699 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
700
701
702 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
703 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
704 "access - was not enabled by BIOS/Firmware\n",
705 dev->name);
706 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
707 pci_write_config_word(ap->pdev, PCI_COMMAND,
708 ap->pci_command);
709 wmb();
710 }
711
712 pci_read_config_byte(pdev, PCI_LATENCY_TIMER,
713 &ap->pci_latency);
714 if (ap->pci_latency <= 0x40) {
715 ap->pci_latency = 0x40;
716 pci_write_config_byte(pdev, PCI_LATENCY_TIMER,
717 ap->pci_latency);
718 }
719
720
721
722
723
724
725 dev->base_addr = pci_resource_start(pdev, 0);
726 ap->regs = (struct ace_regs *)ioremap(dev->base_addr, 0x4000);
727 if (!ap->regs) {
728 printk(KERN_ERR "%s: Unable to map I/O register, "
729 "AceNIC %i will be disabled.\n",
730 dev->name, boards_found);
731 break;
732 }
733
734 if (register_netdev(dev)) {
735 printk(KERN_ERR "acenic: device registration failed\n");
736 free_netdev(dev);
737 continue;
738 }
739
740 switch(pdev->vendor) {
741 case PCI_VENDOR_ID_ALTEON:
742 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
743 strncpy(ap->name, "Farallon PN9100-T "
744 "Gigabit Ethernet", sizeof (ap->name));
745 printk(KERN_INFO "%s: Farallon PN9100-T ",
746 dev->name);
747 } else {
748 strncpy(ap->name, "AceNIC Gigabit Ethernet",
749 sizeof (ap->name));
750 printk(KERN_INFO "%s: Alteon AceNIC ",
751 dev->name);
752 }
753 break;
754 case PCI_VENDOR_ID_3COM:
755 strncpy(ap->name, "3Com 3C985 Gigabit Ethernet",
756 sizeof (ap->name));
757 printk(KERN_INFO "%s: 3Com 3C985 ", dev->name);
758 break;
759 case PCI_VENDOR_ID_NETGEAR:
760 strncpy(ap->name, "NetGear GA620 Gigabit Ethernet",
761 sizeof (ap->name));
762 printk(KERN_INFO "%s: NetGear GA620 ", dev->name);
763 break;
764 case PCI_VENDOR_ID_DEC:
765 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
766 strncpy(ap->name, "Farallon PN9000-SX "
767 "Gigabit Ethernet", sizeof (ap->name));
768 printk(KERN_INFO "%s: Farallon PN9000-SX ",
769 dev->name);
770 break;
771 }
772 case PCI_VENDOR_ID_SGI:
773 strncpy(ap->name, "SGI AceNIC Gigabit Ethernet",
774 sizeof (ap->name));
775 printk(KERN_INFO "%s: SGI AceNIC ", dev->name);
776 break;
777 default:
778 strncpy(ap->name, "Unknown AceNIC based Gigabit "
779 "Ethernet", sizeof (ap->name));
780 printk(KERN_INFO "%s: Unknown AceNIC ", dev->name);
781 break;
782 }
783 ap->name [sizeof (ap->name) - 1] = '\0';
784 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
785#ifdef __sparc__
786 printk("irq %s\n", __irq_itoa(pdev->irq));
787#else
788 printk("irq %i\n", pdev->irq);
789#endif
790
791#ifdef CONFIG_ACENIC_OMIT_TIGON_I
792 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
793 printk(KERN_ERR "%s: Driver compiled without Tigon I"
794 " support - NIC disabled\n", dev->name);
795 ace_init_cleanup(dev);
796 free_netdev(dev);
797 continue;
798 }
799#endif
800
801 if (ace_allocate_descriptors(dev)) {
802
803
804
805
806 free_netdev(dev);
807 continue;
808 }
809
810#ifdef MODULE
811 if (boards_found >= ACE_MAX_MOD_PARMS)
812 ap->board_idx = BOARD_IDX_OVERFLOW;
813 else
814 ap->board_idx = boards_found;
815#else
816 ap->board_idx = BOARD_IDX_STATIC;
817#endif
818
819 if (ace_init(dev)) {
820
821
822
823 free_netdev(dev);
824 continue;
825 }
826
827 if (ap->pci_using_dac)
828 dev->features |= NETIF_F_HIGHDMA;
829
830 boards_found++;
831 }
832
833
834
835
836
837
838
839 if (boards_found > 0)
840 return 0;
841 else
842 return -ENODEV;
843}
844
845
846#ifdef MODULE
847MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
848MODULE_LICENSE("GPL");
849MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
850MODULE_PARM(link, "1-" __MODULE_STRING(8) "i");
851MODULE_PARM(trace, "1-" __MODULE_STRING(8) "i");
852MODULE_PARM(tx_coal_tick, "1-" __MODULE_STRING(8) "i");
853MODULE_PARM(max_tx_desc, "1-" __MODULE_STRING(8) "i");
854MODULE_PARM(rx_coal_tick, "1-" __MODULE_STRING(8) "i");
855MODULE_PARM(max_rx_desc, "1-" __MODULE_STRING(8) "i");
856MODULE_PARM(tx_ratio, "1-" __MODULE_STRING(8) "i");
857MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
858MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
859MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
860MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
861MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
862MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
863MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
864#endif
865
866
867static void __exit ace_module_cleanup(void)
868{
869 struct ace_private *ap;
870 struct ace_regs *regs;
871 struct net_device *next;
872 short i;
873
874 while (root_dev) {
875 ap = root_dev->priv;
876 next = ap->next;
877
878 regs = ap->regs;
879
880 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
881 if (ap->version >= 2)
882 writel(readl(®s->CpuBCtrl) | CPU_HALT,
883 ®s->CpuBCtrl);
884
885
886
887 writel(1, ®s->Mb0Lo);
888 readl(®s->CpuCtrl);
889
890
891
892
893
894
895
896
897
898
899 ace_sync_irq(root_dev->irq);
900
901 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
902 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
903
904 if (skb) {
905 struct ring_info *ringp;
906 dma_addr_t mapping;
907
908 ringp = &ap->skb->rx_std_skbuff[i];
909 mapping = pci_unmap_addr(ringp, mapping);
910 pci_unmap_page(ap->pdev, mapping,
911 ACE_STD_BUFSIZE - (2 + 16),
912 PCI_DMA_FROMDEVICE);
913
914 ap->rx_std_ring[i].size = 0;
915 ap->skb->rx_std_skbuff[i].skb = NULL;
916 dev_kfree_skb(skb);
917 }
918 }
919 if (ap->version >= 2) {
920 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
921 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
922
923 if (skb) {
924 struct ring_info *ringp;
925 dma_addr_t mapping;
926
927 ringp = &ap->skb->rx_mini_skbuff[i];
928 mapping = pci_unmap_addr(ringp,mapping);
929 pci_unmap_page(ap->pdev, mapping,
930 ACE_MINI_BUFSIZE - (2 + 16),
931 PCI_DMA_FROMDEVICE);
932
933 ap->rx_mini_ring[i].size = 0;
934 ap->skb->rx_mini_skbuff[i].skb = NULL;
935 dev_kfree_skb(skb);
936 }
937 }
938 }
939 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
940 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
941 if (skb) {
942 struct ring_info *ringp;
943 dma_addr_t mapping;
944
945 ringp = &ap->skb->rx_jumbo_skbuff[i];
946 mapping = pci_unmap_addr(ringp, mapping);
947 pci_unmap_page(ap->pdev, mapping,
948 ACE_JUMBO_BUFSIZE - (2 + 16),
949 PCI_DMA_FROMDEVICE);
950
951 ap->rx_jumbo_ring[i].size = 0;
952 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
953 dev_kfree_skb(skb);
954 }
955 }
956
957 ace_init_cleanup(root_dev);
958 free_netdev(root_dev);
959 root_dev = next;
960 }
961}
962
963
964int __init ace_module_init(void)
965{
966 int status;
967
968 root_dev = NULL;
969
970#ifdef NEW_NETINIT
971 status = acenic_probe();
972#else
973 status = acenic_probe(NULL);
974#endif
975 return status;
976}
977
978
979#if (LINUX_VERSION_CODE < 0x02032a)
980#ifdef MODULE
981int init_module(void)
982{
983 return ace_module_init();
984}
985
986
987void cleanup_module(void)
988{
989 ace_module_cleanup();
990}
991#endif
992#else
993module_init(ace_module_init);
994module_exit(ace_module_cleanup);
995#endif
996
997
998static void ace_free_descriptors(struct net_device *dev)
999{
1000 struct ace_private *ap = dev->priv;
1001 int size;
1002
1003 if (ap->rx_std_ring != NULL) {
1004 size = (sizeof(struct rx_desc) *
1005 (RX_STD_RING_ENTRIES +
1006 RX_JUMBO_RING_ENTRIES +
1007 RX_MINI_RING_ENTRIES +
1008 RX_RETURN_RING_ENTRIES));
1009 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
1010 ap->rx_ring_base_dma);
1011 ap->rx_std_ring = NULL;
1012 ap->rx_jumbo_ring = NULL;
1013 ap->rx_mini_ring = NULL;
1014 ap->rx_return_ring = NULL;
1015 }
1016 if (ap->evt_ring != NULL) {
1017 size = (sizeof(struct event) * EVT_RING_ENTRIES);
1018 pci_free_consistent(ap->pdev, size, ap->evt_ring,
1019 ap->evt_ring_dma);
1020 ap->evt_ring = NULL;
1021 }
1022 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
1023 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
1024 pci_free_consistent(ap->pdev, size, ap->tx_ring,
1025 ap->tx_ring_dma);
1026 }
1027 ap->tx_ring = NULL;
1028
1029 if (ap->evt_prd != NULL) {
1030 pci_free_consistent(ap->pdev, sizeof(u32),
1031 (void *)ap->evt_prd, ap->evt_prd_dma);
1032 ap->evt_prd = NULL;
1033 }
1034 if (ap->rx_ret_prd != NULL) {
1035 pci_free_consistent(ap->pdev, sizeof(u32),
1036 (void *)ap->rx_ret_prd,
1037 ap->rx_ret_prd_dma);
1038 ap->rx_ret_prd = NULL;
1039 }
1040 if (ap->tx_csm != NULL) {
1041 pci_free_consistent(ap->pdev, sizeof(u32),
1042 (void *)ap->tx_csm, ap->tx_csm_dma);
1043 ap->tx_csm = NULL;
1044 }
1045}
1046
1047
1048static int ace_allocate_descriptors(struct net_device *dev)
1049{
1050 struct ace_private *ap = dev->priv;
1051 int size;
1052
1053 size = (sizeof(struct rx_desc) *
1054 (RX_STD_RING_ENTRIES +
1055 RX_JUMBO_RING_ENTRIES +
1056 RX_MINI_RING_ENTRIES +
1057 RX_RETURN_RING_ENTRIES));
1058
1059 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
1060 &ap->rx_ring_base_dma);
1061 if (ap->rx_std_ring == NULL)
1062 goto fail;
1063
1064 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
1065 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
1066 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
1067
1068 size = (sizeof(struct event) * EVT_RING_ENTRIES);
1069
1070 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
1071
1072 if (ap->evt_ring == NULL)
1073 goto fail;
1074
1075
1076
1077
1078
1079 if (!ACE_IS_TIGON_I(ap)) {
1080 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
1081
1082 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
1083 &ap->tx_ring_dma);
1084
1085 if (ap->tx_ring == NULL)
1086 goto fail;
1087 }
1088
1089 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
1090 &ap->evt_prd_dma);
1091 if (ap->evt_prd == NULL)
1092 goto fail;
1093
1094 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
1095 &ap->rx_ret_prd_dma);
1096 if (ap->rx_ret_prd == NULL)
1097 goto fail;
1098
1099 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
1100 &ap->tx_csm_dma);
1101 if (ap->tx_csm == NULL)
1102 goto fail;
1103
1104 return 0;
1105
1106fail:
1107
1108 ace_init_cleanup(dev);
1109 return 1;
1110}
1111
1112
1113
1114
1115
1116
1117static void ace_init_cleanup(struct net_device *dev)
1118{
1119 struct ace_private *ap;
1120
1121 ap = dev->priv;
1122
1123 ace_free_descriptors(dev);
1124
1125 if (ap->info)
1126 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
1127 ap->info, ap->info_dma);
1128 if (ap->skb)
1129 kfree(ap->skb);
1130 if (ap->trace_buf)
1131 kfree(ap->trace_buf);
1132
1133 if (dev->irq)
1134 free_irq(dev->irq, dev);
1135
1136 unregister_netdev(dev);
1137 iounmap(ap->regs);
1138}
1139
1140
1141
1142
1143
1144static inline void ace_issue_cmd(struct ace_regs *regs, struct cmd *cmd)
1145{
1146 u32 idx;
1147
1148 idx = readl(®s->CmdPrd);
1149
1150 writel(*(u32 *)(cmd), ®s->CmdRng[idx]);
1151 idx = (idx + 1) % CMD_RING_ENTRIES;
1152
1153 writel(idx, ®s->CmdPrd);
1154}
1155
1156
1157static int __init ace_init(struct net_device *dev)
1158{
1159 struct ace_private *ap;
1160 struct ace_regs *regs;
1161 struct ace_info *info = NULL;
1162 struct pci_dev *pdev;
1163 unsigned long myjif;
1164 u64 tmp_ptr;
1165 u32 tig_ver, mac1, mac2, tmp, pci_state;
1166 int board_idx, ecode = 0;
1167 short i;
1168 unsigned char cache_size;
1169
1170 ap = dev->priv;
1171 regs = ap->regs;
1172
1173 board_idx = ap->board_idx;
1174
1175
1176
1177
1178
1179
1180 writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl);
1181 readl(®s->HostCtrl);
1182 udelay(5);
1183
1184
1185
1186
1187#ifdef __BIG_ENDIAN
1188
1189
1190
1191
1192 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
1193 ®s->HostCtrl);
1194#else
1195 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
1196 ®s->HostCtrl);
1197#endif
1198 readl(®s->HostCtrl);
1199
1200
1201
1202
1203 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
1204 readl(®s->CpuCtrl);
1205 writel(0, ®s->Mb0Lo);
1206
1207 tig_ver = readl(®s->HostCtrl) >> 28;
1208
1209 switch(tig_ver){
1210#ifndef CONFIG_ACENIC_OMIT_TIGON_I
1211 case 4:
1212 printk(KERN_INFO " Tigon I (Rev. 4), Firmware: %i.%i.%i, ",
1213 tigonFwReleaseMajor, tigonFwReleaseMinor,
1214 tigonFwReleaseFix);
1215 writel(0, ®s->LocalCtrl);
1216 ap->version = 1;
1217 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
1218 break;
1219#endif
1220 case 6:
1221 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
1222 tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
1223 tigon2FwReleaseFix);
1224 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl);
1225 readl(®s->CpuBCtrl);
1226
1227
1228
1229
1230
1231 writel(SRAM_BANK_512K, ®s->LocalCtrl);
1232 writel(SYNC_SRAM_TIMING, ®s->MiscCfg);
1233 ap->version = 2;
1234 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
1235 break;
1236 default:
1237 printk(KERN_WARNING " Unsupported Tigon version detected "
1238 "(%i), ", tig_ver);
1239 ecode = -ENODEV;
1240 goto init_error;
1241 }
1242
1243
1244
1245
1246
1247
1248
1249
1250#ifdef __BIG_ENDIAN
1251 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
1252 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat);
1253#else
1254 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
1255 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat);
1256#endif
1257 readl(®s->ModeStat);
1258
1259 mac1 = 0;
1260 for(i = 0; i < 4; i++) {
1261 mac1 = mac1 << 8;
1262 tmp = read_eeprom_byte(dev, 0x8c+i);
1263 if (tmp < 0) {
1264 ecode = -EIO;
1265 goto init_error;
1266 } else
1267 mac1 |= (tmp & 0xff);
1268 }
1269 mac2 = 0;
1270 for(i = 4; i < 8; i++) {
1271 mac2 = mac2 << 8;
1272 tmp = read_eeprom_byte(dev, 0x8c+i);
1273 if (tmp < 0) {
1274 ecode = -EIO;
1275 goto init_error;
1276 } else
1277 mac2 |= (tmp & 0xff);
1278 }
1279
1280 writel(mac1, ®s->MacAddrHi);
1281 writel(mac2, ®s->MacAddrLo);
1282
1283 printk("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
1284 (mac1 >> 8) & 0xff, mac1 & 0xff, (mac2 >> 24) &0xff,
1285 (mac2 >> 16) & 0xff, (mac2 >> 8) & 0xff, mac2 & 0xff);
1286
1287 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1288 dev->dev_addr[1] = mac1 & 0xff;
1289 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1290 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1291 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1292 dev->dev_addr[5] = mac2 & 0xff;
1293
1294
1295
1296
1297
1298
1299
1300 pdev = ap->pdev;
1301 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1302 cache_size <<= 2;
1303 if (cache_size != SMP_CACHE_BYTES) {
1304 printk(KERN_INFO " PCI cache line size set incorrectly "
1305 "(%i bytes) by BIOS/FW, ", cache_size);
1306 if (cache_size > SMP_CACHE_BYTES)
1307 printk("expecting %i\n", SMP_CACHE_BYTES);
1308 else {
1309 printk("correcting to %i\n", SMP_CACHE_BYTES);
1310 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1311 SMP_CACHE_BYTES >> 2);
1312 }
1313 }
1314
1315 pci_state = readl(®s->PciState);
1316 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1317 "latency: %i clks\n",
1318 (pci_state & PCI_32BIT) ? 32 : 64,
1319 (pci_state & PCI_66MHZ) ? 66 : 33,
1320 ap->pci_latency);
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1333 if (ap->version >= 2) {
1334 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1335
1336
1337
1338 if (board_idx == BOARD_IDX_OVERFLOW ||
1339 dis_pci_mem_inval[board_idx]) {
1340 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1341 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1342 pci_write_config_word(pdev, PCI_COMMAND,
1343 ap->pci_command);
1344 printk(KERN_INFO " Disabling PCI memory "
1345 "write and invalidate\n");
1346 }
1347 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1348 printk(KERN_INFO " PCI memory write & invalidate "
1349 "enabled by BIOS, enabling counter measures\n");
1350
1351 switch(SMP_CACHE_BYTES) {
1352 case 16:
1353 tmp |= DMA_WRITE_MAX_16;
1354 break;
1355 case 32:
1356 tmp |= DMA_WRITE_MAX_32;
1357 break;
1358 case 64:
1359 tmp |= DMA_WRITE_MAX_64;
1360 break;
1361 case 128:
1362 tmp |= DMA_WRITE_MAX_128;
1363 break;
1364 default:
1365 printk(KERN_INFO " Cache line size %i not "
1366 "supported, PCI write and invalidate "
1367 "disabled\n", SMP_CACHE_BYTES);
1368 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1369 pci_write_config_word(pdev, PCI_COMMAND,
1370 ap->pci_command);
1371 }
1372 }
1373 }
1374
1375#ifdef __sparc__
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387 tmp &= ~DMA_READ_WRITE_MASK;
1388 tmp |= DMA_READ_MAX_64;
1389 tmp |= DMA_WRITE_MAX_64;
1390#endif
1391#ifdef __alpha__
1392 tmp &= ~DMA_READ_WRITE_MASK;
1393 tmp |= DMA_READ_MAX_128;
1394
1395
1396
1397
1398
1399 tmp |= DMA_WRITE_MAX_128;
1400#endif
1401 writel(tmp, ®s->PciState);
1402
1403#if 0
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1416 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1417 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1418 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1419 }
1420#endif
1421
1422
1423
1424
1425 if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
1426 ap->pci_using_dac = 1;
1427 } else if (!pci_set_dma_mask(pdev, 0xffffffffULL)) {
1428 ap->pci_using_dac = 0;
1429 } else {
1430 ecode = -ENODEV;
1431 goto init_error;
1432 }
1433
1434
1435
1436
1437
1438
1439 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1440 &ap->info_dma))) {
1441 ecode = -EAGAIN;
1442 goto init_error;
1443 }
1444 ap->info = info;
1445
1446
1447
1448
1449 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1450 ecode = -EAGAIN;
1451 goto init_error;
1452 }
1453
1454 ecode = request_irq(pdev->irq, ace_interrupt, SA_SHIRQ,
1455 dev->name, dev);
1456 if (ecode) {
1457 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1458 dev->name, pdev->irq);
1459 goto init_error;
1460 } else
1461 dev->irq = pdev->irq;
1462
1463
1464
1465
1466
1467 ap->next = root_dev;
1468 root_dev = dev;
1469
1470#ifdef INDEX_DEBUG
1471 spin_lock_init(&ap->debug_lock);
1472 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1473 ap->last_std_rx = 0;
1474 ap->last_mini_rx = 0;
1475#endif
1476
1477 memset(ap->info, 0, sizeof(struct ace_info));
1478 memset(ap->skb, 0, sizeof(struct ace_skb));
1479
1480 ace_load_firmware(dev);
1481 ap->fw_running = 0;
1482
1483 tmp_ptr = ap->info_dma;
1484 writel(tmp_ptr >> 32, ®s->InfoPtrHi);
1485 writel(tmp_ptr & 0xffffffff, ®s->InfoPtrLo);
1486
1487 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1488
1489 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1490 info->evt_ctrl.flags = 0;
1491
1492 *(ap->evt_prd) = 0;
1493 wmb();
1494 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1495 writel(0, ®s->EvtCsm);
1496
1497 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1498 info->cmd_ctrl.flags = 0;
1499 info->cmd_ctrl.max_len = 0;
1500
1501 for (i = 0; i < CMD_RING_ENTRIES; i++)
1502 writel(0, ®s->CmdRng[i]);
1503
1504 writel(0, ®s->CmdPrd);
1505 writel(0, ®s->CmdCsm);
1506
1507 tmp_ptr = ap->info_dma;
1508 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1509 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1510
1511 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1512 info->rx_std_ctrl.max_len = ACE_STD_MTU + ETH_HLEN + 4;
1513 info->rx_std_ctrl.flags =
1514 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1515
1516 memset(ap->rx_std_ring, 0,
1517 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1518
1519 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1520 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1521
1522 ap->rx_std_skbprd = 0;
1523 atomic_set(&ap->cur_rx_bufs, 0);
1524
1525 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1526 (ap->rx_ring_base_dma +
1527 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1528 info->rx_jumbo_ctrl.max_len = 0;
1529 info->rx_jumbo_ctrl.flags =
1530 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1531
1532 memset(ap->rx_jumbo_ring, 0,
1533 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1534
1535 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1536 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1537
1538 ap->rx_jumbo_skbprd = 0;
1539 atomic_set(&ap->cur_jumbo_bufs, 0);
1540
1541 memset(ap->rx_mini_ring, 0,
1542 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1543
1544 if (ap->version >= 2) {
1545 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1546 (ap->rx_ring_base_dma +
1547 (sizeof(struct rx_desc) *
1548 (RX_STD_RING_ENTRIES +
1549 RX_JUMBO_RING_ENTRIES))));
1550 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
1551 info->rx_mini_ctrl.flags =
1552 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1553
1554 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1555 ap->rx_mini_ring[i].flags =
1556 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1557 } else {
1558 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1559 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1560 info->rx_mini_ctrl.max_len = 0;
1561 }
1562
1563 ap->rx_mini_skbprd = 0;
1564 atomic_set(&ap->cur_mini_bufs, 0);
1565
1566 set_aceaddr(&info->rx_return_ctrl.rngptr,
1567 (ap->rx_ring_base_dma +
1568 (sizeof(struct rx_desc) *
1569 (RX_STD_RING_ENTRIES +
1570 RX_JUMBO_RING_ENTRIES +
1571 RX_MINI_RING_ENTRIES))));
1572 info->rx_return_ctrl.flags = 0;
1573 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1574
1575 memset(ap->rx_return_ring, 0,
1576 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1577
1578 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1579 *(ap->rx_ret_prd) = 0;
1580
1581 writel(TX_RING_BASE, ®s->WinBase);
1582
1583 if (ACE_IS_TIGON_I(ap)) {
1584 ap->tx_ring = (struct tx_desc *)regs->Window;
1585 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES *
1586 sizeof(struct tx_desc) / 4); i++) {
1587 writel(0, (unsigned long)ap->tx_ring + i * 4);
1588 }
1589
1590 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1591 } else {
1592 memset(ap->tx_ring, 0,
1593 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1594
1595 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1596 }
1597
1598 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1599 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1600
1601
1602
1603
1604 if (!ACE_IS_TIGON_I(ap))
1605 tmp |= RCB_FLG_TX_HOST_RING;
1606#if TX_COAL_INTS_ONLY
1607 tmp |= RCB_FLG_COAL_INT_ONLY;
1608#endif
1609 info->tx_ctrl.flags = tmp;
1610
1611 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1612
1613
1614
1615
1616#if 0
1617 writel(DMA_THRESH_16W, ®s->DmaReadCfg);
1618 writel(DMA_THRESH_16W, ®s->DmaWriteCfg);
1619#else
1620 writel(DMA_THRESH_8W, ®s->DmaReadCfg);
1621 writel(DMA_THRESH_8W, ®s->DmaWriteCfg);
1622#endif
1623
1624 writel(0, ®s->MaskInt);
1625 writel(1, ®s->IfIdx);
1626#if 0
1627
1628
1629
1630
1631 writel(1, ®s->AssistState);
1632#endif
1633
1634 writel(DEF_STAT, ®s->TuneStatTicks);
1635 writel(DEF_TRACE, ®s->TuneTrace);
1636
1637 ace_set_rxtx_parms(dev, 0);
1638
1639 if (board_idx == BOARD_IDX_OVERFLOW) {
1640 printk(KERN_WARNING "%s: more than %i NICs detected, "
1641 "ignoring module parameters!\n",
1642 dev->name, ACE_MAX_MOD_PARMS);
1643 } else if (board_idx >= 0) {
1644 if (tx_coal_tick[board_idx])
1645 writel(tx_coal_tick[board_idx],
1646 ®s->TuneTxCoalTicks);
1647 if (max_tx_desc[board_idx])
1648 writel(max_tx_desc[board_idx], ®s->TuneMaxTxDesc);
1649
1650 if (rx_coal_tick[board_idx])
1651 writel(rx_coal_tick[board_idx],
1652 ®s->TuneRxCoalTicks);
1653 if (max_rx_desc[board_idx])
1654 writel(max_rx_desc[board_idx], ®s->TuneMaxRxDesc);
1655
1656 if (trace[board_idx])
1657 writel(trace[board_idx], ®s->TuneTrace);
1658
1659 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1660 writel(tx_ratio[board_idx], ®s->TxBufRat);
1661 }
1662
1663
1664
1665
1666 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1667 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1668 if(ap->version >= 2)
1669 tmp |= LNK_TX_FLOW_CTL_Y;
1670
1671
1672
1673
1674 if ((board_idx >= 0) && link[board_idx]) {
1675 int option = link[board_idx];
1676
1677 tmp = LNK_ENABLE;
1678
1679 if (option & 0x01) {
1680 printk(KERN_INFO "%s: Setting half duplex link\n",
1681 dev->name);
1682 tmp &= ~LNK_FULL_DUPLEX;
1683 }
1684 if (option & 0x02)
1685 tmp &= ~LNK_NEGOTIATE;
1686 if (option & 0x10)
1687 tmp |= LNK_10MB;
1688 if (option & 0x20)
1689 tmp |= LNK_100MB;
1690 if (option & 0x40)
1691 tmp |= LNK_1000MB;
1692 if ((option & 0x70) == 0) {
1693 printk(KERN_WARNING "%s: No media speed specified, "
1694 "forcing auto negotiation\n", dev->name);
1695 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1696 LNK_100MB | LNK_10MB;
1697 }
1698 if ((option & 0x100) == 0)
1699 tmp |= LNK_NEG_FCTL;
1700 else
1701 printk(KERN_INFO "%s: Disabling flow control "
1702 "negotiation\n", dev->name);
1703 if (option & 0x200)
1704 tmp |= LNK_RX_FLOW_CTL_Y;
1705 if ((option & 0x400) && (ap->version >= 2)) {
1706 printk(KERN_INFO "%s: Enabling TX flow control\n",
1707 dev->name);
1708 tmp |= LNK_TX_FLOW_CTL_Y;
1709 }
1710 }
1711
1712 ap->link = tmp;
1713 writel(tmp, ®s->TuneLink);
1714 if (ap->version >= 2)
1715 writel(tmp, ®s->TuneFastLink);
1716
1717 if (ACE_IS_TIGON_I(ap))
1718 writel(tigonFwStartAddr, ®s->Pc);
1719 if (ap->version == 2)
1720 writel(tigon2FwStartAddr, ®s->Pc);
1721
1722 writel(0, ®s->Mb0Lo);
1723
1724
1725
1726
1727
1728
1729
1730 ap->cur_rx = 0;
1731 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1732
1733 wmb();
1734 ace_set_txprd(regs, ap, 0);
1735 writel(0, ®s->RxRetCsm);
1736
1737
1738
1739
1740 memset(&ap->stats, 0, sizeof(ap->stats));
1741
1742
1743
1744
1745
1746
1747
1748 writel(1, ®s->AssistState);
1749
1750
1751
1752
1753 writel(readl(®s->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), ®s->CpuCtrl);
1754 readl(®s->CpuCtrl);
1755
1756
1757
1758
1759 myjif = jiffies + 3 * HZ;
1760 while (time_before(jiffies, myjif) && !ap->fw_running)
1761 cpu_relax();
1762
1763 if (!ap->fw_running) {
1764 printk(KERN_ERR "%s: Firmware NOT running!\n", dev->name);
1765
1766 ace_dump_trace(ap);
1767 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
1768 readl(®s->CpuCtrl);
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779 if (ap->version >= 2)
1780 writel(readl(®s->CpuBCtrl) | CPU_HALT,
1781 ®s->CpuBCtrl);
1782 writel(0, ®s->Mb0Lo);
1783 readl(®s->Mb0Lo);
1784
1785 ecode = -EBUSY;
1786 goto init_error;
1787 }
1788
1789
1790
1791
1792
1793 if (!test_and_set_bit(0, &ap->std_refill_busy))
1794 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1795 else
1796 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1797 dev->name);
1798 if (ap->version >= 2) {
1799 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1800 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1801 else
1802 printk(KERN_ERR "%s: Someone is busy refilling "
1803 "the RX mini ring\n", dev->name);
1804 }
1805 return 0;
1806
1807 init_error:
1808 ace_init_cleanup(dev);
1809 return ecode;
1810}
1811
1812
1813static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1814{
1815 struct ace_private *ap;
1816 struct ace_regs *regs;
1817 int board_idx;
1818
1819 ap = dev->priv;
1820 regs = ap->regs;
1821
1822 board_idx = ap->board_idx;
1823
1824 if (board_idx >= 0) {
1825 if (!jumbo) {
1826 if (!tx_coal_tick[board_idx])
1827 writel(DEF_TX_COAL, ®s->TuneTxCoalTicks);
1828 if (!max_tx_desc[board_idx])
1829 writel(DEF_TX_MAX_DESC, ®s->TuneMaxTxDesc);
1830 if (!rx_coal_tick[board_idx])
1831 writel(DEF_RX_COAL, ®s->TuneRxCoalTicks);
1832 if (!max_rx_desc[board_idx])
1833 writel(DEF_RX_MAX_DESC, ®s->TuneMaxRxDesc);
1834 if (!tx_ratio[board_idx])
1835 writel(DEF_TX_RATIO, ®s->TxBufRat);
1836 } else {
1837 if (!tx_coal_tick[board_idx])
1838 writel(DEF_JUMBO_TX_COAL,
1839 ®s->TuneTxCoalTicks);
1840 if (!max_tx_desc[board_idx])
1841 writel(DEF_JUMBO_TX_MAX_DESC,
1842 ®s->TuneMaxTxDesc);
1843 if (!rx_coal_tick[board_idx])
1844 writel(DEF_JUMBO_RX_COAL,
1845 ®s->TuneRxCoalTicks);
1846 if (!max_rx_desc[board_idx])
1847 writel(DEF_JUMBO_RX_MAX_DESC,
1848 ®s->TuneMaxRxDesc);
1849 if (!tx_ratio[board_idx])
1850 writel(DEF_JUMBO_TX_RATIO, ®s->TxBufRat);
1851 }
1852 }
1853}
1854
1855
1856static void ace_watchdog(struct net_device *data)
1857{
1858 struct net_device *dev = data;
1859 struct ace_private *ap = dev->priv;
1860 struct ace_regs *regs = ap->regs;
1861
1862
1863
1864
1865
1866
1867 if (*ap->tx_csm != ap->tx_ret_csm) {
1868 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1869 dev->name, (unsigned int)readl(®s->HostCtrl));
1870
1871 } else {
1872 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1873 dev->name);
1874#if 0
1875 netif_wake_queue(dev);
1876#endif
1877 }
1878}
1879
1880
1881static void ace_tasklet(unsigned long dev)
1882{
1883 struct ace_private *ap = ((struct net_device *)dev)->priv;
1884 int cur_size;
1885
1886 cur_size = atomic_read(&ap->cur_rx_bufs);
1887 if ((cur_size < RX_LOW_STD_THRES) &&
1888 !test_and_set_bit(0, &ap->std_refill_busy)) {
1889#if DEBUG
1890 printk("refilling buffers (current %i)\n", cur_size);
1891#endif
1892 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1893 }
1894
1895 if (ap->version >= 2) {
1896 cur_size = atomic_read(&ap->cur_mini_bufs);
1897 if ((cur_size < RX_LOW_MINI_THRES) &&
1898 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1899#if DEBUG
1900 printk("refilling mini buffers (current %i)\n",
1901 cur_size);
1902#endif
1903 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1904 }
1905 }
1906
1907 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1908 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1909 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1910#if DEBUG
1911 printk("refilling jumbo buffers (current %i)\n", cur_size);
1912#endif
1913 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1914 }
1915 ap->tasklet_pending = 0;
1916}
1917
1918
1919
1920
1921
1922static void ace_dump_trace(struct ace_private *ap)
1923{
1924#if 0
1925 if (!ap->trace_buf)
1926 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1927 return;
1928#endif
1929}
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1940{
1941 struct ace_regs *regs;
1942 short i, idx;
1943
1944 regs = ap->regs;
1945
1946 prefetchw(&ap->cur_rx_bufs);
1947
1948 idx = ap->rx_std_skbprd;
1949
1950 for (i = 0; i < nr_bufs; i++) {
1951 struct sk_buff *skb;
1952 struct rx_desc *rd;
1953 dma_addr_t mapping;
1954
1955 skb = alloc_skb(ACE_STD_BUFSIZE, GFP_ATOMIC);
1956 if (!skb)
1957 break;
1958
1959
1960
1961
1962 skb_reserve(skb, 2 + 16);
1963 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1964 offset_in_page(skb->data),
1965 ACE_STD_BUFSIZE - (2 + 16),
1966 PCI_DMA_FROMDEVICE);
1967 ap->skb->rx_std_skbuff[idx].skb = skb;
1968 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1969 mapping, mapping);
1970
1971 rd = &ap->rx_std_ring[idx];
1972 set_aceaddr(&rd->addr, mapping);
1973 rd->size = ACE_STD_MTU + ETH_HLEN + 4;
1974 rd->idx = idx;
1975 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1976 }
1977
1978 if (!i)
1979 goto error_out;
1980
1981 atomic_add(i, &ap->cur_rx_bufs);
1982 ap->rx_std_skbprd = idx;
1983
1984 if (ACE_IS_TIGON_I(ap)) {
1985 struct cmd cmd;
1986 cmd.evt = C_SET_RX_PRD_IDX;
1987 cmd.code = 0;
1988 cmd.idx = ap->rx_std_skbprd;
1989 ace_issue_cmd(regs, &cmd);
1990 } else {
1991 writel(idx, ®s->RxStdPrd);
1992 wmb();
1993 }
1994
1995 out:
1996 clear_bit(0, &ap->std_refill_busy);
1997 return;
1998
1999 error_out:
2000 printk(KERN_INFO "Out of memory when allocating "
2001 "standard receive buffers\n");
2002 goto out;
2003}
2004
2005
2006static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
2007{
2008 struct ace_regs *regs;
2009 short i, idx;
2010
2011 regs = ap->regs;
2012
2013 prefetchw(&ap->cur_mini_bufs);
2014
2015 idx = ap->rx_mini_skbprd;
2016 for (i = 0; i < nr_bufs; i++) {
2017 struct sk_buff *skb;
2018 struct rx_desc *rd;
2019 dma_addr_t mapping;
2020
2021 skb = alloc_skb(ACE_MINI_BUFSIZE, GFP_ATOMIC);
2022 if (!skb)
2023 break;
2024
2025
2026
2027
2028 skb_reserve(skb, 2 + 16);
2029 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2030 offset_in_page(skb->data),
2031 ACE_MINI_BUFSIZE - (2 + 16),
2032 PCI_DMA_FROMDEVICE);
2033 ap->skb->rx_mini_skbuff[idx].skb = skb;
2034 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
2035 mapping, mapping);
2036
2037 rd = &ap->rx_mini_ring[idx];
2038 set_aceaddr(&rd->addr, mapping);
2039 rd->size = ACE_MINI_SIZE;
2040 rd->idx = idx;
2041 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
2042 }
2043
2044 if (!i)
2045 goto error_out;
2046
2047 atomic_add(i, &ap->cur_mini_bufs);
2048
2049 ap->rx_mini_skbprd = idx;
2050
2051 writel(idx, ®s->RxMiniPrd);
2052 wmb();
2053
2054 out:
2055 clear_bit(0, &ap->mini_refill_busy);
2056 return;
2057 error_out:
2058 printk(KERN_INFO "Out of memory when allocating "
2059 "mini receive buffers\n");
2060 goto out;
2061}
2062
2063
2064
2065
2066
2067
2068static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
2069{
2070 struct ace_regs *regs;
2071 short i, idx;
2072
2073 regs = ap->regs;
2074
2075 idx = ap->rx_jumbo_skbprd;
2076
2077 for (i = 0; i < nr_bufs; i++) {
2078 struct sk_buff *skb;
2079 struct rx_desc *rd;
2080 dma_addr_t mapping;
2081
2082 skb = alloc_skb(ACE_JUMBO_BUFSIZE, GFP_ATOMIC);
2083 if (!skb)
2084 break;
2085
2086
2087
2088
2089 skb_reserve(skb, 2 + 16);
2090 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2091 offset_in_page(skb->data),
2092 ACE_JUMBO_BUFSIZE - (2 + 16),
2093 PCI_DMA_FROMDEVICE);
2094 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
2095 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
2096 mapping, mapping);
2097
2098 rd = &ap->rx_jumbo_ring[idx];
2099 set_aceaddr(&rd->addr, mapping);
2100 rd->size = ACE_JUMBO_MTU + ETH_HLEN + 4;
2101 rd->idx = idx;
2102 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
2103 }
2104
2105 if (!i)
2106 goto error_out;
2107
2108 atomic_add(i, &ap->cur_jumbo_bufs);
2109 ap->rx_jumbo_skbprd = idx;
2110
2111 if (ACE_IS_TIGON_I(ap)) {
2112 struct cmd cmd;
2113 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
2114 cmd.code = 0;
2115 cmd.idx = ap->rx_jumbo_skbprd;
2116 ace_issue_cmd(regs, &cmd);
2117 } else {
2118 writel(idx, ®s->RxJumboPrd);
2119 wmb();
2120 }
2121
2122 out:
2123 clear_bit(0, &ap->jumbo_refill_busy);
2124 return;
2125 error_out:
2126 if (net_ratelimit())
2127 printk(KERN_INFO "Out of memory when allocating "
2128 "jumbo receive buffers\n");
2129 goto out;
2130}
2131
2132
2133
2134
2135
2136
2137
2138static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
2139{
2140 struct ace_private *ap;
2141
2142 ap = dev->priv;
2143
2144 while (evtcsm != evtprd) {
2145 switch (ap->evt_ring[evtcsm].evt) {
2146 case E_FW_RUNNING:
2147 printk(KERN_INFO "%s: Firmware up and running\n",
2148 dev->name);
2149 ap->fw_running = 1;
2150 wmb();
2151 break;
2152 case E_STATS_UPDATED:
2153 break;
2154 case E_LNK_STATE:
2155 {
2156 u16 code = ap->evt_ring[evtcsm].code;
2157 switch (code) {
2158 case E_C_LINK_UP:
2159 {
2160 u32 state = readl(&ap->regs->GigLnkState);
2161 printk(KERN_WARNING "%s: Optical link UP "
2162 "(%s Duplex, Flow Control: %s%s)\n",
2163 dev->name,
2164 state & LNK_FULL_DUPLEX ? "Full":"Half",
2165 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
2166 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
2167 break;
2168 }
2169 case E_C_LINK_DOWN:
2170 printk(KERN_WARNING "%s: Optical link DOWN\n",
2171 dev->name);
2172 break;
2173 case E_C_LINK_10_100:
2174 printk(KERN_WARNING "%s: 10/100BaseT link "
2175 "UP\n", dev->name);
2176 break;
2177 default:
2178 printk(KERN_ERR "%s: Unknown optical link "
2179 "state %02x\n", dev->name, code);
2180 }
2181 break;
2182 }
2183 case E_ERROR:
2184 switch(ap->evt_ring[evtcsm].code) {
2185 case E_C_ERR_INVAL_CMD:
2186 printk(KERN_ERR "%s: invalid command error\n",
2187 dev->name);
2188 break;
2189 case E_C_ERR_UNIMP_CMD:
2190 printk(KERN_ERR "%s: unimplemented command "
2191 "error\n", dev->name);
2192 break;
2193 case E_C_ERR_BAD_CFG:
2194 printk(KERN_ERR "%s: bad config error\n",
2195 dev->name);
2196 break;
2197 default:
2198 printk(KERN_ERR "%s: unknown error %02x\n",
2199 dev->name, ap->evt_ring[evtcsm].code);
2200 }
2201 break;
2202 case E_RESET_JUMBO_RNG:
2203 {
2204 int i;
2205 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
2206 if (ap->skb->rx_jumbo_skbuff[i].skb) {
2207 ap->rx_jumbo_ring[i].size = 0;
2208 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
2209 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
2210 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
2211 }
2212 }
2213
2214 if (ACE_IS_TIGON_I(ap)) {
2215 struct cmd cmd;
2216 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
2217 cmd.code = 0;
2218 cmd.idx = 0;
2219 ace_issue_cmd(ap->regs, &cmd);
2220 } else {
2221 writel(0, &((ap->regs)->RxJumboPrd));
2222 wmb();
2223 }
2224
2225 ap->jumbo = 0;
2226 ap->rx_jumbo_skbprd = 0;
2227 printk(KERN_INFO "%s: Jumbo ring flushed\n",
2228 dev->name);
2229 clear_bit(0, &ap->jumbo_refill_busy);
2230 break;
2231 }
2232 default:
2233 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
2234 dev->name, ap->evt_ring[evtcsm].evt);
2235 }
2236 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
2237 }
2238
2239 return evtcsm;
2240}
2241
2242
2243static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
2244{
2245 struct ace_private *ap = dev->priv;
2246 u32 idx;
2247 int mini_count = 0, std_count = 0;
2248
2249 idx = rxretcsm;
2250
2251 prefetchw(&ap->cur_rx_bufs);
2252 prefetchw(&ap->cur_mini_bufs);
2253
2254 while (idx != rxretprd) {
2255 struct ring_info *rip;
2256 struct sk_buff *skb;
2257 struct rx_desc *rxdesc, *retdesc;
2258 u32 skbidx;
2259 int bd_flags, desc_type, mapsize;
2260 u16 csum;
2261
2262 retdesc = &ap->rx_return_ring[idx];
2263 skbidx = retdesc->idx;
2264 bd_flags = retdesc->flags;
2265 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
2266
2267 switch(desc_type) {
2268
2269
2270
2271
2272
2273
2274
2275 case 0:
2276 rip = &ap->skb->rx_std_skbuff[skbidx];
2277 mapsize = ACE_STD_BUFSIZE - (2 + 16);
2278 rxdesc = &ap->rx_std_ring[skbidx];
2279 std_count++;
2280 break;
2281 case BD_FLG_JUMBO:
2282 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
2283 mapsize = ACE_JUMBO_BUFSIZE - (2 + 16);
2284 rxdesc = &ap->rx_jumbo_ring[skbidx];
2285 atomic_dec(&ap->cur_jumbo_bufs);
2286 break;
2287 case BD_FLG_MINI:
2288 rip = &ap->skb->rx_mini_skbuff[skbidx];
2289 mapsize = ACE_MINI_BUFSIZE - (2 + 16);
2290 rxdesc = &ap->rx_mini_ring[skbidx];
2291 mini_count++;
2292 break;
2293 default:
2294 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2295 "returned by NIC\n", dev->name,
2296 retdesc->flags);
2297 goto error;
2298 }
2299
2300 skb = rip->skb;
2301 rip->skb = NULL;
2302 pci_unmap_page(ap->pdev,
2303 pci_unmap_addr(rip, mapping),
2304 mapsize,
2305 PCI_DMA_FROMDEVICE);
2306 skb_put(skb, retdesc->size);
2307
2308
2309
2310
2311 csum = retdesc->tcp_udp_csum;
2312
2313 skb->dev = dev;
2314 skb->protocol = eth_type_trans(skb, dev);
2315
2316
2317
2318
2319
2320 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2321 skb->csum = htons(csum);
2322 skb->ip_summed = CHECKSUM_HW;
2323 } else {
2324 skb->ip_summed = CHECKSUM_NONE;
2325 }
2326
2327
2328#if ACENIC_DO_VLAN
2329 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2330 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2331 } else
2332#endif
2333 netif_rx(skb);
2334
2335 dev->last_rx = jiffies;
2336 ap->stats.rx_packets++;
2337 ap->stats.rx_bytes += retdesc->size;
2338
2339 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2340 }
2341
2342 atomic_sub(std_count, &ap->cur_rx_bufs);
2343 if (!ACE_IS_TIGON_I(ap))
2344 atomic_sub(mini_count, &ap->cur_mini_bufs);
2345
2346 out:
2347
2348
2349
2350
2351 if (ACE_IS_TIGON_I(ap)) {
2352 struct ace_regs *regs = ap->regs;
2353 writel(idx, ®s->RxRetCsm);
2354 }
2355 ap->cur_rx = idx;
2356
2357 return;
2358 error:
2359 idx = rxretprd;
2360 goto out;
2361}
2362
2363
2364static inline void ace_tx_int(struct net_device *dev,
2365 u32 txcsm, u32 idx)
2366{
2367 struct ace_private *ap = dev->priv;
2368
2369 do {
2370 struct sk_buff *skb;
2371 dma_addr_t mapping;
2372 struct tx_ring_info *info;
2373
2374 info = ap->skb->tx_skbuff + idx;
2375 skb = info->skb;
2376 mapping = pci_unmap_addr(info, mapping);
2377
2378 if (mapping) {
2379 pci_unmap_page(ap->pdev, mapping,
2380 pci_unmap_len(info, maplen),
2381 PCI_DMA_TODEVICE);
2382 pci_unmap_addr_set(info, mapping, 0);
2383 }
2384
2385 if (skb) {
2386 ap->stats.tx_packets++;
2387 ap->stats.tx_bytes += skb->len;
2388 dev_kfree_skb_irq(skb);
2389 info->skb = NULL;
2390 }
2391
2392 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2393 } while (idx != txcsm);
2394
2395 if (netif_queue_stopped(dev))
2396 netif_wake_queue(dev);
2397
2398 wmb();
2399 ap->tx_ret_csm = txcsm;
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428}
2429
2430
2431static irqreturn_t ace_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
2432{
2433 struct ace_private *ap;
2434 struct ace_regs *regs;
2435 struct net_device *dev = (struct net_device *)dev_id;
2436 u32 idx;
2437 u32 txcsm, rxretcsm, rxretprd;
2438 u32 evtcsm, evtprd;
2439
2440 ap = dev->priv;
2441 regs = ap->regs;
2442
2443
2444
2445
2446
2447
2448 if (!(readl(®s->HostCtrl) & IN_INT))
2449 return IRQ_NONE;
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459 writel(0, ®s->Mb0Lo);
2460 readl(®s->Mb0Lo);
2461
2462
2463
2464
2465
2466
2467
2468
2469 rxretprd = *ap->rx_ret_prd;
2470 rxretcsm = ap->cur_rx;
2471
2472 if (rxretprd != rxretcsm)
2473 ace_rx_int(dev, rxretprd, rxretcsm);
2474
2475 txcsm = *ap->tx_csm;
2476 idx = ap->tx_ret_csm;
2477
2478 if (txcsm != idx) {
2479
2480
2481
2482
2483
2484
2485
2486 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2487 ace_tx_int(dev, txcsm, idx);
2488 }
2489
2490 evtcsm = readl(®s->EvtCsm);
2491 evtprd = *ap->evt_prd;
2492
2493 if (evtcsm != evtprd) {
2494 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2495 writel(evtcsm, ®s->EvtCsm);
2496 }
2497
2498
2499
2500
2501
2502 if (netif_running(dev)) {
2503 int cur_size;
2504 int run_tasklet = 0;
2505
2506 cur_size = atomic_read(&ap->cur_rx_bufs);
2507 if (cur_size < RX_LOW_STD_THRES) {
2508 if ((cur_size < RX_PANIC_STD_THRES) &&
2509 !test_and_set_bit(0, &ap->std_refill_busy)) {
2510#if DEBUG
2511 printk("low on std buffers %i\n", cur_size);
2512#endif
2513 ace_load_std_rx_ring(ap,
2514 RX_RING_SIZE - cur_size);
2515 } else
2516 run_tasklet = 1;
2517 }
2518
2519 if (!ACE_IS_TIGON_I(ap)) {
2520 cur_size = atomic_read(&ap->cur_mini_bufs);
2521 if (cur_size < RX_LOW_MINI_THRES) {
2522 if ((cur_size < RX_PANIC_MINI_THRES) &&
2523 !test_and_set_bit(0,
2524 &ap->mini_refill_busy)) {
2525#if DEBUG
2526 printk("low on mini buffers %i\n",
2527 cur_size);
2528#endif
2529 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2530 } else
2531 run_tasklet = 1;
2532 }
2533 }
2534
2535 if (ap->jumbo) {
2536 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2537 if (cur_size < RX_LOW_JUMBO_THRES) {
2538 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2539 !test_and_set_bit(0,
2540 &ap->jumbo_refill_busy)){
2541#if DEBUG
2542 printk("low on jumbo buffers %i\n",
2543 cur_size);
2544#endif
2545 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2546 } else
2547 run_tasklet = 1;
2548 }
2549 }
2550 if (run_tasklet && !ap->tasklet_pending) {
2551 ap->tasklet_pending = 1;
2552 tasklet_schedule(&ap->ace_tasklet);
2553 }
2554 }
2555
2556 return IRQ_HANDLED;
2557}
2558
2559
2560#if ACENIC_DO_VLAN
2561static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2562{
2563 struct ace_private *ap = dev->priv;
2564 unsigned long flags;
2565
2566 local_irq_save(flags);
2567 ace_mask_irq(dev);
2568
2569 ap->vlgrp = grp;
2570
2571 ace_unmask_irq(dev);
2572 local_irq_restore(flags);
2573}
2574
2575
2576static void ace_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
2577{
2578 struct ace_private *ap = dev->priv;
2579 unsigned long flags;
2580
2581 local_irq_save(flags);
2582 ace_mask_irq(dev);
2583
2584 if (ap->vlgrp)
2585 ap->vlgrp->vlan_devices[vid] = NULL;
2586
2587 ace_unmask_irq(dev);
2588 local_irq_restore(flags);
2589}
2590#endif
2591
2592
2593static int ace_open(struct net_device *dev)
2594{
2595 struct ace_private *ap;
2596 struct ace_regs *regs;
2597 struct cmd cmd;
2598
2599 ap = dev->priv;
2600 regs = ap->regs;
2601
2602 if (!(ap->fw_running)) {
2603 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2604 return -EBUSY;
2605 }
2606
2607 writel(dev->mtu + ETH_HLEN + 4, ®s->IfMtu);
2608
2609 cmd.evt = C_CLEAR_STATS;
2610 cmd.code = 0;
2611 cmd.idx = 0;
2612 ace_issue_cmd(regs, &cmd);
2613
2614 cmd.evt = C_HOST_STATE;
2615 cmd.code = C_C_STACK_UP;
2616 cmd.idx = 0;
2617 ace_issue_cmd(regs, &cmd);
2618
2619 if (ap->jumbo &&
2620 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2621 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2622
2623 if (dev->flags & IFF_PROMISC) {
2624 cmd.evt = C_SET_PROMISC_MODE;
2625 cmd.code = C_C_PROMISC_ENABLE;
2626 cmd.idx = 0;
2627 ace_issue_cmd(regs, &cmd);
2628
2629 ap->promisc = 1;
2630 }else
2631 ap->promisc = 0;
2632 ap->mcast_all = 0;
2633
2634#if 0
2635 cmd.evt = C_LNK_NEGOTIATION;
2636 cmd.code = 0;
2637 cmd.idx = 0;
2638 ace_issue_cmd(regs, &cmd);
2639#endif
2640
2641 netif_start_queue(dev);
2642
2643 ACE_MOD_INC_USE_COUNT;
2644
2645
2646
2647
2648 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2649 return 0;
2650}
2651
2652
2653static int ace_close(struct net_device *dev)
2654{
2655 struct ace_private *ap;
2656 struct ace_regs *regs;
2657 struct cmd cmd;
2658 unsigned long flags;
2659 short i;
2660
2661 ace_if_down(dev);
2662
2663
2664
2665
2666
2667
2668 netif_stop_queue(dev);
2669
2670 ap = dev->priv;
2671 regs = ap->regs;
2672
2673 if (ap->promisc) {
2674 cmd.evt = C_SET_PROMISC_MODE;
2675 cmd.code = C_C_PROMISC_DISABLE;
2676 cmd.idx = 0;
2677 ace_issue_cmd(regs, &cmd);
2678 ap->promisc = 0;
2679 }
2680
2681 cmd.evt = C_HOST_STATE;
2682 cmd.code = C_C_STACK_DOWN;
2683 cmd.idx = 0;
2684 ace_issue_cmd(regs, &cmd);
2685
2686 tasklet_kill(&ap->ace_tasklet);
2687
2688
2689
2690
2691
2692
2693 local_irq_save(flags);
2694 ace_mask_irq(dev);
2695
2696 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2697 struct sk_buff *skb;
2698 dma_addr_t mapping;
2699 struct tx_ring_info *info;
2700
2701 info = ap->skb->tx_skbuff + i;
2702 skb = info->skb;
2703 mapping = pci_unmap_addr(info, mapping);
2704
2705 if (mapping) {
2706 if (ACE_IS_TIGON_I(ap)) {
2707 writel(0, &ap->tx_ring[i].addr.addrhi);
2708 writel(0, &ap->tx_ring[i].addr.addrlo);
2709 writel(0, &ap->tx_ring[i].flagsize);
2710 } else
2711 memset(ap->tx_ring + i, 0,
2712 sizeof(struct tx_desc));
2713 pci_unmap_page(ap->pdev, mapping,
2714 pci_unmap_len(info, maplen),
2715 PCI_DMA_TODEVICE);
2716 pci_unmap_addr_set(info, mapping, 0);
2717 }
2718 if (skb) {
2719 dev_kfree_skb(skb);
2720 info->skb = NULL;
2721 }
2722 }
2723
2724 if (ap->jumbo) {
2725 cmd.evt = C_RESET_JUMBO_RNG;
2726 cmd.code = 0;
2727 cmd.idx = 0;
2728 ace_issue_cmd(regs, &cmd);
2729 }
2730
2731 ace_unmask_irq(dev);
2732 local_irq_restore(flags);
2733
2734 ACE_MOD_DEC_USE_COUNT;
2735 return 0;
2736}
2737
2738
2739static inline dma_addr_t
2740ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2741 struct sk_buff *tail, u32 idx)
2742{
2743 dma_addr_t mapping;
2744 struct tx_ring_info *info;
2745
2746 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2747 offset_in_page(skb->data),
2748 skb->len, PCI_DMA_TODEVICE);
2749
2750 info = ap->skb->tx_skbuff + idx;
2751 info->skb = tail;
2752 pci_unmap_addr_set(info, mapping, mapping);
2753 pci_unmap_len_set(info, maplen, skb->len);
2754 return mapping;
2755}
2756
2757
2758static inline void
2759ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2760 u32 flagsize, u32 vlan_tag)
2761{
2762#if !USE_TX_COAL_NOW
2763 flagsize &= ~BD_FLG_COAL_NOW;
2764#endif
2765
2766 if (ACE_IS_TIGON_I(ap)) {
2767 writel(addr >> 32, &desc->addr.addrhi);
2768 writel(addr & 0xffffffff, &desc->addr.addrlo);
2769 writel(flagsize, &desc->flagsize);
2770#if ACENIC_DO_VLAN
2771 writel(vlan_tag, &desc->vlanres);
2772#endif
2773 } else {
2774 desc->addr.addrhi = addr >> 32;
2775 desc->addr.addrlo = addr;
2776 desc->flagsize = flagsize;
2777#if ACENIC_DO_VLAN
2778 desc->vlanres = vlan_tag;
2779#endif
2780 }
2781}
2782
2783
2784static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
2785{
2786 struct ace_private *ap = dev->priv;
2787 struct ace_regs *regs = ap->regs;
2788 struct tx_desc *desc;
2789 u32 idx, flagsize;
2790
2791
2792
2793
2794 if (early_stop_netif_stop_queue(dev))
2795 return 1;
2796
2797restart:
2798 idx = ap->tx_prd;
2799
2800 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2801 goto overflow;
2802
2803#if MAX_SKB_FRAGS
2804 if (!skb_shinfo(skb)->nr_frags)
2805#endif
2806 {
2807 dma_addr_t mapping;
2808 u32 vlan_tag = 0;
2809
2810 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2811 flagsize = (skb->len << 16) | (BD_FLG_END);
2812 if (skb->ip_summed == CHECKSUM_HW)
2813 flagsize |= BD_FLG_TCP_UDP_SUM;
2814#if ACENIC_DO_VLAN
2815 if (vlan_tx_tag_present(skb)) {
2816 flagsize |= BD_FLG_VLAN_TAG;
2817 vlan_tag = vlan_tx_tag_get(skb);
2818 }
2819#endif
2820 desc = ap->tx_ring + idx;
2821 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2822
2823
2824 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2825 flagsize |= BD_FLG_COAL_NOW;
2826
2827 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2828 }
2829#if MAX_SKB_FRAGS
2830 else {
2831 dma_addr_t mapping;
2832 u32 vlan_tag = 0;
2833 int i, len = 0;
2834
2835 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2836 flagsize = (skb_headlen(skb) << 16);
2837 if (skb->ip_summed == CHECKSUM_HW)
2838 flagsize |= BD_FLG_TCP_UDP_SUM;
2839#if ACENIC_DO_VLAN
2840 if (vlan_tx_tag_present(skb)) {
2841 flagsize |= BD_FLG_VLAN_TAG;
2842 vlan_tag = vlan_tx_tag_get(skb);
2843 }
2844#endif
2845
2846 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2847
2848 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2849
2850 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2851 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2852 struct tx_ring_info *info;
2853
2854 len += frag->size;
2855 info = ap->skb->tx_skbuff + idx;
2856 desc = ap->tx_ring + idx;
2857
2858 mapping = pci_map_page(ap->pdev, frag->page,
2859 frag->page_offset, frag->size,
2860 PCI_DMA_TODEVICE);
2861
2862 flagsize = (frag->size << 16);
2863 if (skb->ip_summed == CHECKSUM_HW)
2864 flagsize |= BD_FLG_TCP_UDP_SUM;
2865 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2866
2867 if (i == skb_shinfo(skb)->nr_frags - 1) {
2868 flagsize |= BD_FLG_END;
2869 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2870 flagsize |= BD_FLG_COAL_NOW;
2871
2872
2873
2874
2875
2876 info->skb = skb;
2877 } else {
2878 info->skb = NULL;
2879 }
2880 pci_unmap_addr_set(info, mapping, mapping);
2881 pci_unmap_len_set(info, maplen, frag->size);
2882 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2883 }
2884 }
2885#endif
2886
2887 wmb();
2888 ap->tx_prd = idx;
2889 ace_set_txprd(regs, ap, idx);
2890
2891 if (flagsize & BD_FLG_COAL_NOW) {
2892 netif_stop_queue(dev);
2893
2894
2895
2896
2897
2898
2899
2900 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2901 netif_wake_queue(dev);
2902 }
2903
2904 dev->trans_start = jiffies;
2905 return 0;
2906
2907overflow:
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924 barrier();
2925 goto restart;
2926}
2927
2928
2929static int ace_change_mtu(struct net_device *dev, int new_mtu)
2930{
2931 struct ace_private *ap = dev->priv;
2932 struct ace_regs *regs = ap->regs;
2933
2934 if (new_mtu > ACE_JUMBO_MTU)
2935 return -EINVAL;
2936
2937 writel(new_mtu + ETH_HLEN + 4, ®s->IfMtu);
2938 dev->mtu = new_mtu;
2939
2940 if (new_mtu > ACE_STD_MTU) {
2941 if (!(ap->jumbo)) {
2942 printk(KERN_INFO "%s: Enabling Jumbo frame "
2943 "support\n", dev->name);
2944 ap->jumbo = 1;
2945 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2946 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2947 ace_set_rxtx_parms(dev, 1);
2948 }
2949 } else {
2950 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2951 ace_sync_irq(dev->irq);
2952 ace_set_rxtx_parms(dev, 0);
2953 if (ap->jumbo) {
2954 struct cmd cmd;
2955
2956 cmd.evt = C_RESET_JUMBO_RNG;
2957 cmd.code = 0;
2958 cmd.idx = 0;
2959 ace_issue_cmd(regs, &cmd);
2960 }
2961 }
2962
2963 return 0;
2964}
2965
2966
2967static int ace_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2968{
2969 struct ace_private *ap = dev->priv;
2970 struct ace_regs *regs = ap->regs;
2971#ifdef SIOCETHTOOL
2972 struct ethtool_cmd ecmd;
2973 u32 link, speed;
2974
2975 if (cmd != SIOCETHTOOL)
2976 return -EOPNOTSUPP;
2977 if (copy_from_user(&ecmd, ifr->ifr_data, sizeof(ecmd)))
2978 return -EFAULT;
2979 switch (ecmd.cmd) {
2980 case ETHTOOL_GSET:
2981 ecmd.supported =
2982 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2983 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2984 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2985 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2986
2987 ecmd.port = PORT_FIBRE;
2988 ecmd.transceiver = XCVR_INTERNAL;
2989 ecmd.phy_address = 0;
2990
2991 link = readl(®s->GigLnkState);
2992 if (link & LNK_1000MB)
2993 ecmd.speed = SPEED_1000;
2994 else {
2995 link = readl(®s->FastLnkState);
2996 if (link & LNK_100MB)
2997 ecmd.speed = SPEED_100;
2998 else if (link & LNK_100MB)
2999 ecmd.speed = SPEED_10;
3000 else
3001 ecmd.speed = 0;
3002 }
3003 if (link & LNK_FULL_DUPLEX)
3004 ecmd.duplex = DUPLEX_FULL;
3005 else
3006 ecmd.duplex = DUPLEX_HALF;
3007
3008 if (link & LNK_NEGOTIATE)
3009 ecmd.autoneg = AUTONEG_ENABLE;
3010 else
3011 ecmd.autoneg = AUTONEG_DISABLE;
3012
3013#if 0
3014
3015
3016
3017 ecmd.trace = readl(®s->TuneTrace);
3018
3019 ecmd.txcoal = readl(®s->TuneTxCoalTicks);
3020 ecmd.rxcoal = readl(®s->TuneRxCoalTicks);
3021#endif
3022 ecmd.maxtxpkt = readl(®s->TuneMaxTxDesc);
3023 ecmd.maxrxpkt = readl(®s->TuneMaxRxDesc);
3024
3025 if(copy_to_user(ifr->ifr_data, &ecmd, sizeof(ecmd)))
3026 return -EFAULT;
3027 return 0;
3028
3029 case ETHTOOL_SSET:
3030 link = readl(®s->GigLnkState);
3031 if (link & LNK_1000MB)
3032 speed = SPEED_1000;
3033 else {
3034 link = readl(®s->FastLnkState);
3035 if (link & LNK_100MB)
3036 speed = SPEED_100;
3037 else if (link & LNK_100MB)
3038 speed = SPEED_10;
3039 else
3040 speed = SPEED_100;
3041 }
3042
3043 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
3044 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
3045 if (!ACE_IS_TIGON_I(ap))
3046 link |= LNK_TX_FLOW_CTL_Y;
3047 if (ecmd.autoneg == AUTONEG_ENABLE)
3048 link |= LNK_NEGOTIATE;
3049 if (ecmd.speed != speed) {
3050 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
3051 switch (speed) {
3052 case SPEED_1000:
3053 link |= LNK_1000MB;
3054 break;
3055 case SPEED_100:
3056 link |= LNK_100MB;
3057 break;
3058 case SPEED_10:
3059 link |= LNK_10MB;
3060 break;
3061 }
3062 }
3063 if (ecmd.duplex == DUPLEX_FULL)
3064 link |= LNK_FULL_DUPLEX;
3065
3066 if (link != ap->link) {
3067 struct cmd cmd;
3068 printk(KERN_INFO "%s: Renegotiating link state\n",
3069 dev->name);
3070
3071 ap->link = link;
3072 writel(link, ®s->TuneLink);
3073 if (!ACE_IS_TIGON_I(ap))
3074 writel(link, ®s->TuneFastLink);
3075 wmb();
3076
3077 cmd.evt = C_LNK_NEGOTIATION;
3078 cmd.code = 0;
3079 cmd.idx = 0;
3080 ace_issue_cmd(regs, &cmd);
3081 }
3082 return 0;
3083
3084 case ETHTOOL_GDRVINFO: {
3085 struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO};
3086 strncpy(info.driver, "acenic", sizeof(info.driver) - 1);
3087 sprintf(info.fw_version, "%i.%i.%i",
3088 tigonFwReleaseMajor, tigonFwReleaseMinor,
3089 tigonFwReleaseFix);
3090 strncpy(info.version, version, sizeof(info.version) - 1);
3091 if (ap && ap->pdev)
3092 strcpy(info.bus_info, pci_name(ap->pdev));
3093 if (copy_to_user(ifr->ifr_data, &info, sizeof(info)))
3094 return -EFAULT;
3095 return 0;
3096 }
3097 default:
3098 break;
3099 }
3100
3101#endif
3102
3103 return -EOPNOTSUPP;
3104}
3105
3106
3107
3108
3109
3110static int ace_set_mac_addr(struct net_device *dev, void *p)
3111{
3112 struct sockaddr *addr=p;
3113 struct ace_regs *regs;
3114 u8 *da;
3115 struct cmd cmd;
3116
3117 if(netif_running(dev))
3118 return -EBUSY;
3119
3120 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
3121
3122 da = (u8 *)dev->dev_addr;
3123
3124 regs = ((struct ace_private *)dev->priv)->regs;
3125 writel(da[0] << 8 | da[1], ®s->MacAddrHi);
3126 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
3127 ®s->MacAddrLo);
3128
3129 cmd.evt = C_SET_MAC_ADDR;
3130 cmd.code = 0;
3131 cmd.idx = 0;
3132 ace_issue_cmd(regs, &cmd);
3133
3134 return 0;
3135}
3136
3137
3138static void ace_set_multicast_list(struct net_device *dev)
3139{
3140 struct ace_private *ap = dev->priv;
3141 struct ace_regs *regs = ap->regs;
3142 struct cmd cmd;
3143
3144 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
3145 cmd.evt = C_SET_MULTICAST_MODE;
3146 cmd.code = C_C_MCAST_ENABLE;
3147 cmd.idx = 0;
3148 ace_issue_cmd(regs, &cmd);
3149 ap->mcast_all = 1;
3150 } else if (ap->mcast_all) {
3151 cmd.evt = C_SET_MULTICAST_MODE;
3152 cmd.code = C_C_MCAST_DISABLE;
3153 cmd.idx = 0;
3154 ace_issue_cmd(regs, &cmd);
3155 ap->mcast_all = 0;
3156 }
3157
3158 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
3159 cmd.evt = C_SET_PROMISC_MODE;
3160 cmd.code = C_C_PROMISC_ENABLE;
3161 cmd.idx = 0;
3162 ace_issue_cmd(regs, &cmd);
3163 ap->promisc = 1;
3164 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
3165 cmd.evt = C_SET_PROMISC_MODE;
3166 cmd.code = C_C_PROMISC_DISABLE;
3167 cmd.idx = 0;
3168 ace_issue_cmd(regs, &cmd);
3169 ap->promisc = 0;
3170 }
3171
3172
3173
3174
3175
3176
3177
3178 if ((dev->mc_count) && !(ap->mcast_all)) {
3179 cmd.evt = C_SET_MULTICAST_MODE;
3180 cmd.code = C_C_MCAST_ENABLE;
3181 cmd.idx = 0;
3182 ace_issue_cmd(regs, &cmd);
3183 }else if (!ap->mcast_all) {
3184 cmd.evt = C_SET_MULTICAST_MODE;
3185 cmd.code = C_C_MCAST_DISABLE;
3186 cmd.idx = 0;
3187 ace_issue_cmd(regs, &cmd);
3188 }
3189}
3190
3191
3192static struct net_device_stats *ace_get_stats(struct net_device *dev)
3193{
3194 struct ace_private *ap = dev->priv;
3195 struct ace_mac_stats *mac_stats =
3196 (struct ace_mac_stats *)ap->regs->Stats;
3197
3198 ap->stats.rx_missed_errors = readl(&mac_stats->drop_space);
3199 ap->stats.multicast = readl(&mac_stats->kept_mc);
3200 ap->stats.collisions = readl(&mac_stats->coll);
3201
3202 return &ap->stats;
3203}
3204
3205
3206static void __init ace_copy(struct ace_regs *regs, void *src,
3207 u32 dest, int size)
3208{
3209 unsigned long tdest;
3210 u32 *wsrc;
3211 short tsize, i;
3212
3213 if (size <= 0)
3214 return;
3215
3216 while (size > 0) {
3217 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
3218 min_t(u32, size, ACE_WINDOW_SIZE));
3219 tdest = (unsigned long)®s->Window +
3220 (dest & (ACE_WINDOW_SIZE - 1));
3221 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
3222
3223
3224
3225
3226 wsrc = src;
3227 for (i = 0; i < (tsize / 4); i++) {
3228 writel(wsrc[i], tdest + i*4);
3229 }
3230 dest += tsize;
3231 src += tsize;
3232 size -= tsize;
3233 }
3234
3235 return;
3236}
3237
3238
3239static void __init ace_clear(struct ace_regs *regs, u32 dest, int size)
3240{
3241 unsigned long tdest;
3242 short tsize = 0, i;
3243
3244 if (size <= 0)
3245 return;
3246
3247 while (size > 0) {
3248 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
3249 min_t(u32, size, ACE_WINDOW_SIZE));
3250 tdest = (unsigned long)®s->Window +
3251 (dest & (ACE_WINDOW_SIZE - 1));
3252 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
3253
3254 for (i = 0; i < (tsize / 4); i++) {
3255 writel(0, tdest + i*4);
3256 }
3257
3258 dest += tsize;
3259 size -= tsize;
3260 }
3261
3262 return;
3263}
3264
3265
3266
3267
3268
3269
3270
3271
3272int __init ace_load_firmware(struct net_device *dev)
3273{
3274 struct ace_private *ap;
3275 struct ace_regs *regs;
3276
3277 ap = dev->priv;
3278 regs = ap->regs;
3279
3280 if (!(readl(®s->CpuCtrl) & CPU_HALTED)) {
3281 printk(KERN_ERR "%s: trying to download firmware while the "
3282 "CPU is running!\n", dev->name);
3283 return -EFAULT;
3284 }
3285
3286
3287
3288
3289
3290 ace_clear(regs, 0x2000, 0x80000-0x2000);
3291 if (ACE_IS_TIGON_I(ap)) {
3292 ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
3293 ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
3294 ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
3295 tigonFwRodataLen);
3296 ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
3297 ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
3298 }else if (ap->version == 2) {
3299 ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
3300 ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
3301 ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
3302 ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
3303 tigon2FwRodataLen);
3304 ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
3305 }
3306
3307 return 0;
3308}
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326static void __init eeprom_start(struct ace_regs *regs)
3327{
3328 u32 local;
3329
3330 readl(®s->LocalCtrl);
3331 udelay(ACE_SHORT_DELAY);
3332 local = readl(®s->LocalCtrl);
3333 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
3334 writel(local, ®s->LocalCtrl);
3335 readl(®s->LocalCtrl);
3336 mb();
3337 udelay(ACE_SHORT_DELAY);
3338 local |= EEPROM_CLK_OUT;
3339 writel(local, ®s->LocalCtrl);
3340 readl(®s->LocalCtrl);
3341 mb();
3342 udelay(ACE_SHORT_DELAY);
3343 local &= ~EEPROM_DATA_OUT;
3344 writel(local, ®s->LocalCtrl);
3345 readl(®s->LocalCtrl);
3346 mb();
3347 udelay(ACE_SHORT_DELAY);
3348 local &= ~EEPROM_CLK_OUT;
3349 writel(local, ®s->LocalCtrl);
3350 readl(®s->LocalCtrl);
3351 mb();
3352}
3353
3354
3355static void __init eeprom_prep(struct ace_regs *regs, u8 magic)
3356{
3357 short i;
3358 u32 local;
3359
3360 udelay(ACE_SHORT_DELAY);
3361 local = readl(®s->LocalCtrl);
3362 local &= ~EEPROM_DATA_OUT;
3363 local |= EEPROM_WRITE_ENABLE;
3364 writel(local, ®s->LocalCtrl);
3365 readl(®s->LocalCtrl);
3366 mb();
3367
3368 for (i = 0; i < 8; i++, magic <<= 1) {
3369 udelay(ACE_SHORT_DELAY);
3370 if (magic & 0x80)
3371 local |= EEPROM_DATA_OUT;
3372 else
3373 local &= ~EEPROM_DATA_OUT;
3374 writel(local, ®s->LocalCtrl);
3375 readl(®s->LocalCtrl);
3376 mb();
3377
3378 udelay(ACE_SHORT_DELAY);
3379 local |= EEPROM_CLK_OUT;
3380 writel(local, ®s->LocalCtrl);
3381 readl(®s->LocalCtrl);
3382 mb();
3383 udelay(ACE_SHORT_DELAY);
3384 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3385 writel(local, ®s->LocalCtrl);
3386 readl(®s->LocalCtrl);
3387 mb();
3388 }
3389}
3390
3391
3392static int __init eeprom_check_ack(struct ace_regs *regs)
3393{
3394 int state;
3395 u32 local;
3396
3397 local = readl(®s->LocalCtrl);
3398 local &= ~EEPROM_WRITE_ENABLE;
3399 writel(local, ®s->LocalCtrl);
3400 readl(®s->LocalCtrl);
3401 mb();
3402 udelay(ACE_LONG_DELAY);
3403 local |= EEPROM_CLK_OUT;
3404 writel(local, ®s->LocalCtrl);
3405 readl(®s->LocalCtrl);
3406 mb();
3407 udelay(ACE_SHORT_DELAY);
3408
3409 state = (readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0;
3410 udelay(ACE_SHORT_DELAY);
3411 mb();
3412 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl);
3413 readl(®s->LocalCtrl);
3414 mb();
3415
3416 return state;
3417}
3418
3419
3420static void __init eeprom_stop(struct ace_regs *regs)
3421{
3422 u32 local;
3423
3424 udelay(ACE_SHORT_DELAY);
3425 local = readl(®s->LocalCtrl);
3426 local |= EEPROM_WRITE_ENABLE;
3427 writel(local, ®s->LocalCtrl);
3428 readl(®s->LocalCtrl);
3429 mb();
3430 udelay(ACE_SHORT_DELAY);
3431 local &= ~EEPROM_DATA_OUT;
3432 writel(local, ®s->LocalCtrl);
3433 readl(®s->LocalCtrl);
3434 mb();
3435 udelay(ACE_SHORT_DELAY);
3436 local |= EEPROM_CLK_OUT;
3437 writel(local, ®s->LocalCtrl);
3438 readl(®s->LocalCtrl);
3439 mb();
3440 udelay(ACE_SHORT_DELAY);
3441 local |= EEPROM_DATA_OUT;
3442 writel(local, ®s->LocalCtrl);
3443 readl(®s->LocalCtrl);
3444 mb();
3445 udelay(ACE_LONG_DELAY);
3446 local &= ~EEPROM_CLK_OUT;
3447 writel(local, ®s->LocalCtrl);
3448 mb();
3449}
3450
3451
3452
3453
3454
3455static int __init read_eeprom_byte(struct net_device *dev,
3456 unsigned long offset)
3457{
3458 struct ace_regs *regs;
3459 unsigned long flags;
3460 u32 local;
3461 int result = 0;
3462 short i;
3463
3464 if (!dev) {
3465 printk(KERN_ERR "No device!\n");
3466 result = -ENODEV;
3467 goto eeprom_read_error;
3468 }
3469
3470 regs = ((struct ace_private *)dev->priv)->regs;
3471
3472
3473
3474
3475
3476 local_irq_save(flags);
3477
3478 eeprom_start(regs);
3479
3480 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3481 if (eeprom_check_ack(regs)) {
3482 local_irq_restore(flags);
3483 printk(KERN_ERR "%s: Unable to sync eeprom\n", dev->name);
3484 result = -EIO;
3485 goto eeprom_read_error;
3486 }
3487
3488 eeprom_prep(regs, (offset >> 8) & 0xff);
3489 if (eeprom_check_ack(regs)) {
3490 local_irq_restore(flags);
3491 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3492 dev->name);
3493 result = -EIO;
3494 goto eeprom_read_error;
3495 }
3496
3497 eeprom_prep(regs, offset & 0xff);
3498 if (eeprom_check_ack(regs)) {
3499 local_irq_restore(flags);
3500 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3501 dev->name);
3502 result = -EIO;
3503 goto eeprom_read_error;
3504 }
3505
3506 eeprom_start(regs);
3507 eeprom_prep(regs, EEPROM_READ_SELECT);
3508 if (eeprom_check_ack(regs)) {
3509 local_irq_restore(flags);
3510 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3511 dev->name);
3512 result = -EIO;
3513 goto eeprom_read_error;
3514 }
3515
3516 for (i = 0; i < 8; i++) {
3517 local = readl(®s->LocalCtrl);
3518 local &= ~EEPROM_WRITE_ENABLE;
3519 writel(local, ®s->LocalCtrl);
3520 readl(®s->LocalCtrl);
3521 udelay(ACE_LONG_DELAY);
3522 mb();
3523 local |= EEPROM_CLK_OUT;
3524 writel(local, ®s->LocalCtrl);
3525 readl(®s->LocalCtrl);
3526 mb();
3527 udelay(ACE_SHORT_DELAY);
3528
3529 result = (result << 1) |
3530 ((readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0);
3531 udelay(ACE_SHORT_DELAY);
3532 mb();
3533 local = readl(®s->LocalCtrl);
3534 local &= ~EEPROM_CLK_OUT;
3535 writel(local, ®s->LocalCtrl);
3536 readl(®s->LocalCtrl);
3537 udelay(ACE_SHORT_DELAY);
3538 mb();
3539 if (i == 7) {
3540 local |= EEPROM_WRITE_ENABLE;
3541 writel(local, ®s->LocalCtrl);
3542 readl(®s->LocalCtrl);
3543 mb();
3544 udelay(ACE_SHORT_DELAY);
3545 }
3546 }
3547
3548 local |= EEPROM_DATA_OUT;
3549 writel(local, ®s->LocalCtrl);
3550 readl(®s->LocalCtrl);
3551 mb();
3552 udelay(ACE_SHORT_DELAY);
3553 writel(readl(®s->LocalCtrl) | EEPROM_CLK_OUT, ®s->LocalCtrl);
3554 readl(®s->LocalCtrl);
3555 udelay(ACE_LONG_DELAY);
3556 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl);
3557 readl(®s->LocalCtrl);
3558 mb();
3559 udelay(ACE_SHORT_DELAY);
3560 eeprom_stop(regs);
3561
3562 local_irq_restore(flags);
3563 out:
3564 return result;
3565
3566 eeprom_read_error:
3567 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3568 dev->name, offset);
3569 goto out;
3570}
3571
3572
3573
3574
3575
3576
3577
3578