1/* 2 * 7990.h -- LANCE ethernet IC generic routines. 3 * This is an attempt to separate out the bits of various ethernet 4 * drivers that are common because they all use the AMD 7990 LANCE 5 * (Local Area Network Controller for Ethernet) chip. 6 * 7 * Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk> 8 * 9 * Most of this stuff was obtained by looking at other LANCE drivers, 10 * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful. 11 */ 12 13#ifndef _7990_H 14#define _7990_H 15 16/* The lance only has two register locations. We communicate mostly via memory. */ 17struct lance_regs 18{ 19 unsigned short rdp; /* Register Data Port */ 20 unsigned short rap; /* Register Address Port */ 21}; 22 23/* Transmit/receive ring definitions. 24 * We allow the specific drivers to override these defaults if they want to. 25 * NB: according to lance.c, increasing the number of buffers is a waste 26 * of space and reduces the chance that an upper layer will be able to 27 * reorder queued Tx packets based on priority. [Clearly there is a minimum 28 * limit too: too small and we drop rx packets and can't tx at full speed.] 29 * 4+4 seems to be the usual setting; the atarilance driver uses 3 and 5. 30 */ 31 32/* Blast! This won't work. The problem is that we can't specify a default 33 * setting because that would cause the lance_init_block struct to be 34 * too long (and overflow the RAM on shared-memory cards like the HP LANCE. 35 */ 36#ifndef LANCE_LOG_TX_BUFFERS 37#define LANCE_LOG_TX_BUFFERS 1 38#define LANCE_LOG_RX_BUFFERS 3 39#endif 40 41#define TX_RING_SIZE (1<<LANCE_LOG_TX_BUFFERS) 42#define RX_RING_SIZE (1<<LANCE_LOG_RX_BUFFERS) 43#define TX_RING_MOD_MASK (TX_RING_SIZE - 1) 44#define RX_RING_MOD_MASK (RX_RING_SIZE - 1) 45#define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29) 46#define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29) 47#define PKT_BUFF_SIZE (1544) 48#define RX_BUFF_SIZE PKT_BUFF_SIZE 49#define TX_BUFF_SIZE PKT_BUFF_SIZE 50 51/* Each receive buffer is described by a receive message descriptor (RMD) */ 52struct lance_rx_desc { 53 volatile unsigned short rmd0; /* low address of packet */ 54 volatile unsigned char rmd1_bits; /* descriptor bits */ 55 volatile unsigned char rmd1_hadr; /* high address of packet */ 56 volatile short length; /* This length is 2s complement (negative)! 57 * Buffer length 58 */ 59 volatile unsigned short mblength; /* Actual number of bytes received */ 60}; 61 62/* Ditto for TMD: */ 63struct lance_tx_desc { 64 volatile unsigned short tmd0; /* low address of packet */ 65 volatile unsigned char tmd1_bits; /* descriptor bits */ 66 volatile unsigned char tmd1_hadr; /* high address of packet */ 67 volatile short length; /* Length is 2s complement (negative)! */ 68 volatile unsigned short misc; 69}; 70 71/* There are three memory structures accessed by the LANCE: 72 * the initialization block, the receive and transmit descriptor rings, 73 * and the data buffers themselves. In fact we might as well put the 74 * init block,the Tx and Rx rings and the buffers together in memory: 75 */ 76struct lance_init_block { 77 volatile unsigned short mode; /* Pre-set mode (reg. 15) */ 78 volatile unsigned char phys_addr[6]; /* Physical ethernet address */ 79 volatile unsigned filter[2]; /* Multicast filter (64 bits) */ 80 81 /* Receive and transmit ring base, along with extra bits. */ 82 volatile unsigned short rx_ptr; /* receive descriptor addr */ 83 volatile unsigned short rx_len; /* receive len and high addr */ 84 volatile unsigned short tx_ptr; /* transmit descriptor addr */ 85 volatile unsigned short tx_len; /* transmit len and high addr */ 86 87 /* The Tx and Rx ring entries must be aligned on 8-byte boundaries. 88 * This will be true if this whole struct is 8-byte aligned. 89 */ 90 volatile struct lance_tx_desc btx_ring[TX_RING_SIZE]; 91 volatile struct lance_rx_desc brx_ring[RX_RING_SIZE]; 92 93 volatile char tx_buf [TX_RING_SIZE][TX_BUFF_SIZE]; 94 volatile char rx_buf [RX_RING_SIZE][RX_BUFF_SIZE]; 95 /* we use this just to make the struct big enough that we can move its startaddr 96 * in order to force alignment to an eight byte boundary. 97 */ 98}; 99 100/* This is where we keep all the stuff the driver needs to know about. 101 * I'm definitely unhappy about the mechanism for allowing specific 102 * drivers to add things... 103 */ 104struct lance_private 105{ 106 char *name; 107 volatile struct lance_regs *ll; 108 volatile struct lance_init_block *init_block; /* CPU address of RAM */ 109 volatile struct lance_init_block *lance_init_block; /* LANCE address of RAM */ 110 111 int rx_new, tx_new; 112 int rx_old, tx_old; 113 114 int lance_log_rx_bufs, lance_log_tx_bufs; 115 int rx_ring_mod_mask, tx_ring_mod_mask; 116 117 struct net_device_stats stats; 118 int tpe; /* TPE is selected */ 119 int auto_select; /* cable-selection is by carrier */ 120 unsigned short busmaster_regval; 121 122 unsigned int irq; /* IRQ to register */ 123 124 /* This is because the HP LANCE is disgusting and you have to check 125 * a DIO-specific register every time you read/write the LANCE regs :-< 126 * [could we get away with making these some sort of macro?] 127 */ 128 void (*writerap)(void *, unsigned short); 129 void (*writerdp)(void *, unsigned short); 130 unsigned short (*readrdp)(void *); 131 spinlock_t devlock; 132 char tx_full; 133}; 134 135/* 136 * Am7990 Control and Status Registers 137 */ 138#define LE_CSR0 0x0000 /* LANCE Controller Status */ 139#define LE_CSR1 0x0001 /* IADR[15:0] (bit0==0 ie word aligned) */ 140#define LE_CSR2 0x0002 /* IADR[23:16] (high bits reserved) */ 141#define LE_CSR3 0x0003 /* Misc */ 142 143/* 144 * Bit definitions for CSR0 (LANCE Controller Status) 145 */ 146#define LE_C0_ERR 0x8000 /* Error = BABL | CERR | MISS | MERR */ 147#define LE_C0_BABL 0x4000 /* Babble: Transmitted too many bits */ 148#define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */ 149#define LE_C0_MISS 0x1000 /* Missed Frame (no rx buffer to put it in) */ 150#define LE_C0_MERR 0x0800 /* Memory Error */ 151#define LE_C0_RINT 0x0400 /* Receive Interrupt */ 152#define LE_C0_TINT 0x0200 /* Transmit Interrupt */ 153#define LE_C0_IDON 0x0100 /* Initialization Done */ 154#define LE_C0_INTR 0x0080 /* Interrupt Flag 155 = BABL | MISS | MERR | RINT | TINT | IDON */ 156#define LE_C0_INEA 0x0040 /* Interrupt Enable */ 157#define LE_C0_RXON 0x0020 /* Receive On */ 158#define LE_C0_TXON 0x0010 /* Transmit On */ 159#define LE_C0_TDMD 0x0008 /* Transmit Demand */ 160#define LE_C0_STOP 0x0004 /* Stop */ 161#define LE_C0_STRT 0x0002 /* Start */ 162#define LE_C0_INIT 0x0001 /* Initialize */ 163 164 165/* 166 * Bit definitions for CSR3 167 */ 168#define LE_C3_BSWP 0x0004 /* Byte Swap 169 (on for big endian byte order) */ 170#define LE_C3_ACON 0x0002 /* ALE Control 171 (on for active low ALE) */ 172#define LE_C3_BCON 0x0001 /* Byte Control */ 173 174 175/* 176 * Mode Flags 177 */ 178#define LE_MO_PROM 0x8000 /* Promiscuous Mode */ 179/* these next ones 0x4000 -- 0x0080 are not available on the LANCE 7990, 180 * but they are in NetBSD's am7990.h, presumably for backwards-compatible chips 181 */ 182#define LE_MO_DRCVBC 0x4000 /* disable receive broadcast */ 183#define LE_MO_DRCVPA 0x2000 /* disable physical address detection */ 184#define LE_MO_DLNKTST 0x1000 /* disable link status */ 185#define LE_MO_DAPC 0x0800 /* disable automatic polarity correction */ 186#define LE_MO_MENDECL 0x0400 /* MENDEC loopback mode */ 187#define LE_MO_LRTTSEL 0x0200 /* lower RX threshold / TX mode selection */ 188#define LE_MO_PSEL1 0x0100 /* port selection bit1 */ 189#define LE_MO_PSEL0 0x0080 /* port selection bit0 */ 190/* and this one is from the C-LANCE data sheet... */ 191#define LE_MO_EMBA 0x0080 /* Enable Modified Backoff Algorithm 192 (C-LANCE, not original LANCE) */ 193#define LE_MO_INTL 0x0040 /* Internal Loopback */ 194#define LE_MO_DRTY 0x0020 /* Disable Retry */ 195#define LE_MO_FCOLL 0x0010 /* Force Collision */ 196#define LE_MO_DXMTFCS 0x0008 /* Disable Transmit CRC */ 197#define LE_MO_LOOP 0x0004 /* Loopback Enable */ 198#define LE_MO_DTX 0x0002 /* Disable Transmitter */ 199#define LE_MO_DRX 0x0001 /* Disable Receiver */ 200 201 202/* 203 * Receive Flags 204 */ 205#define LE_R1_OWN 0x80 /* LANCE owns the descriptor */ 206#define LE_R1_ERR 0x40 /* Error */ 207#define LE_R1_FRA 0x20 /* Framing Error */ 208#define LE_R1_OFL 0x10 /* Overflow Error */ 209#define LE_R1_CRC 0x08 /* CRC Error */ 210#define LE_R1_BUF 0x04 /* Buffer Error */ 211#define LE_R1_SOP 0x02 /* Start of Packet */ 212#define LE_R1_EOP 0x01 /* End of Packet */ 213#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */ 214 215 216/* 217 * Transmit Flags 218 */ 219#define LE_T1_OWN 0x80 /* LANCE owns the descriptor */ 220#define LE_T1_ERR 0x40 /* Error */ 221#define LE_T1_RES 0x20 /* Reserved, LANCE writes this with a zero */ 222#define LE_T1_EMORE 0x10 /* More than one retry needed */ 223#define LE_T1_EONE 0x08 /* One retry needed */ 224#define LE_T1_EDEF 0x04 /* Deferred */ 225#define LE_T1_SOP 0x02 /* Start of Packet */ 226#define LE_T1_EOP 0x01 /* End of Packet */ 227#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */ 228 229/* 230 * Error Flags 231 */ 232#define LE_T3_BUF 0x8000 /* Buffer Error */ 233#define LE_T3_UFL 0x4000 /* Underflow Error */ 234#define LE_T3_LCOL 0x1000 /* Late Collision */ 235#define LE_T3_CLOS 0x0800 /* Loss of Carrier */ 236#define LE_T3_RTY 0x0400 /* Retry Error */ 237#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry */ 238 239/* Miscellaneous useful macros */ 240 241#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\ 242 lp->tx_old+lp->tx_ring_mod_mask-lp->tx_new:\ 243 lp->tx_old - lp->tx_new-1) 244 245/* The LANCE only uses 24 bit addresses. This does the obvious thing. */ 246#define LANCE_ADDR(x) ((int)(x) & ~0xff000000) 247 248/* Now the prototypes we export */ 249extern int lance_open(struct net_device *dev); 250extern int lance_close (struct net_device *dev); 251extern int lance_start_xmit (struct sk_buff *skb, struct net_device *dev); 252extern struct net_device_stats *lance_get_stats (struct net_device *dev); 253extern void lance_set_multicast (struct net_device *dev); 254extern void lance_tx_timeout(struct net_device *dev); 255 256#endif /* ndef _7990_H */ 257