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53#include <linux/config.h>
54#include <linux/module.h>
55#include <linux/version.h>
56#include <linux/types.h>
57#include <linux/errno.h>
58#include <linux/ioport.h>
59#include <linux/pci.h>
60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
69
70#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
71#include <linux/if_vlan.h>
72#endif
73
74#ifdef SIOCETHTOOL
75#include <linux/ethtool.h>
76#endif
77
78#include <net/sock.h>
79#include <net/ip.h>
80
81#include <asm/system.h>
82#include <asm/io.h>
83#include <asm/irq.h>
84#include <asm/byteorder.h>
85#include <asm/uaccess.h>
86
87
88#undef INDEX_DEBUG
89
90#ifdef CONFIG_ACENIC_OMIT_TIGON_I
91#define ACE_IS_TIGON_I(ap) 0
92#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
93#else
94#define ACE_IS_TIGON_I(ap) (ap->version == 1)
95#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
96#endif
97
98#ifndef PCI_VENDOR_ID_ALTEON
99#define PCI_VENDOR_ID_ALTEON 0x12ae
100#endif
101#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
102#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
103#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
104#endif
105#ifndef PCI_DEVICE_ID_3COM_3C985
106#define PCI_DEVICE_ID_3COM_3C985 0x0001
107#endif
108#ifndef PCI_VENDOR_ID_NETGEAR
109#define PCI_VENDOR_ID_NETGEAR 0x1385
110#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
111#endif
112#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
113#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
114#endif
115
116
117
118
119
120
121#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
122#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
123#endif
124#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
125#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
126#endif
127#ifndef PCI_VENDOR_ID_SGI
128#define PCI_VENDOR_ID_SGI 0x10a9
129#endif
130#ifndef PCI_DEVICE_ID_SGI_ACENIC
131#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
132#endif
133
134#if LINUX_VERSION_CODE >= 0x20400
135static struct pci_device_id acenic_pci_tbl[] __initdata = {
136 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
137 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
138 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
139 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
140 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
141 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
142 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
143 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
144 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
145 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
146
147
148
149
150 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
151 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
152 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
153 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
154 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
155 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
156 { }
157};
158MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
159#endif
160
161
162#ifndef MODULE_LICENSE
163#define MODULE_LICENSE(a)
164#endif
165
166#ifndef wmb
167#define wmb() mb()
168#endif
169
170#ifndef __exit
171#define __exit
172#endif
173
174#ifndef __devinit
175#define __devinit __init
176#endif
177
178#ifndef SMP_CACHE_BYTES
179#define SMP_CACHE_BYTES L1_CACHE_BYTES
180#endif
181
182#ifndef SET_MODULE_OWNER
183#define SET_MODULE_OWNER(dev) do{} while(0)
184#define ACE_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
185#define ACE_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
186#else
187#define ACE_MOD_INC_USE_COUNT do{} while(0)
188#define ACE_MOD_DEC_USE_COUNT do{} while(0)
189#endif
190
191
192#if LINUX_VERSION_CODE >= 0x2051c
193#define ace_sync_irq(irq) synchronize_irq(irq)
194#else
195#define ace_sync_irq(irq) synchronize_irq()
196#endif
197
198#if LINUX_VERSION_CODE < 0x2051e
199#define local_irq_save(flags) do{__save_flags(flags) ; \
200 __cli();} while(0)
201#define local_irq_restore(flags) __restore_flags(flags)
202#endif
203
204#if (LINUX_VERSION_CODE < 0x02030d)
205#define pci_resource_start(dev, bar) dev->base_address[bar]
206#elif (LINUX_VERSION_CODE < 0x02032c)
207#define pci_resource_start(dev, bar) dev->resource[bar].start
208#endif
209
210#if (LINUX_VERSION_CODE < 0x02030e)
211#define net_device device
212#endif
213
214
215#if (LINUX_VERSION_CODE < 0x02032a)
216typedef u32 dma_addr_t;
217
218static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
219 dma_addr_t *dma_handle)
220{
221 void *virt_ptr;
222
223 virt_ptr = kmalloc(size, GFP_KERNEL);
224 if (!virt_ptr)
225 return NULL;
226 *dma_handle = virt_to_bus(virt_ptr);
227 return virt_ptr;
228}
229
230#define pci_free_consistent(cookie, size, ptr, dma_ptr) kfree(ptr)
231#define pci_map_page(cookie, page, off, size, dir) \
232 virt_to_bus(page_address(page)+(off))
233#define pci_unmap_page(cookie, address, size, dir)
234#define pci_set_dma_mask(dev, mask) \
235 (((u64)(mask) & 0xffffffff00000000) == 0 ? 0 : -EIO)
236#define pci_dma_supported(dev, mask) \
237 (((u64)(mask) & 0xffffffff00000000) == 0 ? 1 : 0)
238
239#elif (LINUX_VERSION_CODE < 0x02040d)
240
241
242
243
244
245
246
247
248static inline dma_addr_t
249pci_map_page(struct pci_dev *cookie, struct page *page, unsigned long off,
250 size_t size, int dir)
251{
252 void *page_virt;
253
254 page_virt = page_address(page);
255 if (!page_virt)
256 BUG();
257 return pci_map_single(cookie, (page_virt + off), size, dir);
258}
259#define pci_unmap_page(cookie, dma_addr, size, dir) \
260 pci_unmap_single(cookie, dma_addr, size, dir)
261#endif
262
263#if (LINUX_VERSION_CODE < 0x020412)
264#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
265#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
266#define pci_unmap_addr(PTR, ADDR_NAME) 0
267#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do{} while(0)
268#define pci_unmap_len(PTR, LEN_NAME) 0
269#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do{} while(0)
270#endif
271
272
273#if (LINUX_VERSION_CODE < 0x02032b)
274
275
276
277
278
279
280
281
282
283
284#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
285#define netif_wake_queue(dev) clear_bit(0, &dev->tbusy)
286#define netif_stop_queue(dev) set_bit(0, &dev->tbusy)
287#define late_stop_netif_stop_queue(dev) do{} while(0)
288#define early_stop_netif_stop_queue(dev) test_and_set_bit(0,&dev->tbusy)
289#define early_stop_netif_wake_queue(dev) netif_wake_queue(dev)
290
291static inline void netif_start_queue(struct net_device *dev)
292{
293 dev->tbusy = 0;
294 dev->interrupt = 0;
295 dev->start = 1;
296}
297
298#define ace_mark_net_bh() mark_bh(NET_BH)
299#define netif_queue_stopped(dev) dev->tbusy
300#define netif_running(dev) dev->start
301#define ace_if_down(dev) do{dev->start = 0;} while(0)
302
303#define tasklet_struct tq_struct
304static inline void tasklet_schedule(struct tasklet_struct *tasklet)
305{
306 queue_task(tasklet, &tq_immediate);
307 mark_bh(IMMEDIATE_BH);
308}
309
310static inline void tasklet_init(struct tasklet_struct *tasklet,
311 void (*func)(unsigned long),
312 unsigned long data)
313{
314 tasklet->next = NULL;
315 tasklet->sync = 0;
316 tasklet->routine = (void (*)(void *))func;
317 tasklet->data = (void *)data;
318}
319#define tasklet_kill(tasklet) do{} while(0)
320#else
321#define late_stop_netif_stop_queue(dev) netif_stop_queue(dev)
322#define early_stop_netif_stop_queue(dev) 0
323#define early_stop_netif_wake_queue(dev) do{} while(0)
324#define ace_mark_net_bh() do{} while(0)
325#define ace_if_down(dev) do{} while(0)
326#endif
327
328#if (LINUX_VERSION_CODE >= 0x02031b)
329#define NEW_NETINIT
330#define ACE_PROBE_ARG void
331#else
332#define ACE_PROBE_ARG struct net_device *dev
333#endif
334
335#ifndef min_t
336#define min_t(type,a,b) (((a)<(b))?(a):(b))
337#endif
338
339#ifndef ARCH_HAS_PREFETCHW
340#ifndef prefetchw
341#define prefetchw(x) do{} while(0)
342#endif
343#endif
344
345#define ACE_MAX_MOD_PARMS 8
346#define BOARD_IDX_STATIC 0
347#define BOARD_IDX_OVERFLOW -1
348
349#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
350 defined(NETIF_F_HW_VLAN_RX)
351#define ACENIC_DO_VLAN 1
352#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
353#else
354#define ACENIC_DO_VLAN 0
355#define ACE_RCB_VLAN_FLAG 0
356#endif
357
358#include "acenic.h"
359
360
361
362
363#define MAX_TEXT_LEN 96*1024
364#define MAX_RODATA_LEN 8*1024
365#define MAX_DATA_LEN 2*1024
366
367#include "acenic_firmware.h"
368
369#ifndef tigon2FwReleaseLocal
370#define tigon2FwReleaseLocal 0
371#endif
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520
521#define RX_RING_SIZE 72
522#define RX_MINI_SIZE 64
523#define RX_JUMBO_SIZE 48
524
525#define RX_PANIC_STD_THRES 16
526#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
527#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
528#define RX_PANIC_MINI_THRES 12
529#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
530#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
531#define RX_PANIC_JUMBO_THRES 6
532#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
533#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
534
535
536
537
538
539
540#define ACE_MINI_SIZE 100
541
542#define ACE_MINI_BUFSIZE (ACE_MINI_SIZE + 2 + 16)
543#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 2+4+16)
544#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 2+4+16)
545
546
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549
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551
552
553
554#define DEF_TX_COAL 400
555#define DEF_TX_MAX_DESC 60
556#define DEF_RX_COAL 120
557#define DEF_RX_MAX_DESC 25
558#define DEF_TX_RATIO 21
559
560#define DEF_JUMBO_TX_COAL 20
561#define DEF_JUMBO_TX_MAX_DESC 60
562#define DEF_JUMBO_RX_COAL 30
563#define DEF_JUMBO_RX_MAX_DESC 6
564#define DEF_JUMBO_TX_RATIO 21
565
566#if tigon2FwReleaseLocal < 20001118
567
568
569
570
571
572
573
574#define TX_COAL_INTS_ONLY 1
575#else
576
577
578
579#define TX_COAL_INTS_ONLY 1
580#endif
581
582#define DEF_TRACE 0
583#define DEF_STAT (2 * TICKS_PER_SEC)
584
585
586static int link[ACE_MAX_MOD_PARMS];
587static int trace[ACE_MAX_MOD_PARMS];
588static int tx_coal_tick[ACE_MAX_MOD_PARMS];
589static int rx_coal_tick[ACE_MAX_MOD_PARMS];
590static int max_tx_desc[ACE_MAX_MOD_PARMS];
591static int max_rx_desc[ACE_MAX_MOD_PARMS];
592static int tx_ratio[ACE_MAX_MOD_PARMS];
593static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
594
595static char version[] __initdata =
596 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
597 " http://home.cern.ch/~jes/gige/acenic.html\n";
598
599static struct net_device *root_dev;
600
601static int probed __initdata = 0;
602
603
604int __devinit acenic_probe (ACE_PROBE_ARG)
605{
606#ifdef NEW_NETINIT
607 struct net_device *dev;
608#endif
609 struct ace_private *ap;
610 struct pci_dev *pdev = NULL;
611 int boards_found = 0;
612 int version_disp;
613
614 if (probed)
615 return -ENODEV;
616 probed++;
617
618 if (!pci_present())
619 return -ENODEV;
620
621 version_disp = 0;
622
623 while ((pdev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET<<8, pdev))) {
624
625 if (!((pdev->vendor == PCI_VENDOR_ID_ALTEON) &&
626 ((pdev->device == PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE) ||
627 (pdev->device == PCI_DEVICE_ID_ALTEON_ACENIC_COPPER)))&&
628 !((pdev->vendor == PCI_VENDOR_ID_3COM) &&
629 (pdev->device == PCI_DEVICE_ID_3COM_3C985)) &&
630 !((pdev->vendor == PCI_VENDOR_ID_NETGEAR) &&
631 ((pdev->device == PCI_DEVICE_ID_NETGEAR_GA620) ||
632 (pdev->device == PCI_DEVICE_ID_NETGEAR_GA620T))) &&
633
634
635
636
637 !((pdev->vendor == PCI_VENDOR_ID_DEC) &&
638 (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX)) &&
639 !((pdev->vendor == PCI_VENDOR_ID_ALTEON) &&
640 (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T)) &&
641 !((pdev->vendor == PCI_VENDOR_ID_SGI) &&
642 (pdev->device == PCI_DEVICE_ID_SGI_ACENIC)))
643 continue;
644
645 dev = init_etherdev(NULL, sizeof(struct ace_private));
646
647 if (dev == NULL) {
648 printk(KERN_ERR "acenic: Unable to allocate "
649 "net_device structure!\n");
650 break;
651 }
652
653 SET_MODULE_OWNER(dev);
654
655 if (!dev->priv)
656 dev->priv = kmalloc(sizeof(*ap), GFP_KERNEL);
657 if (!dev->priv) {
658 printk(KERN_ERR "acenic: Unable to allocate memory\n");
659 return -ENOMEM;
660 }
661
662 ap = dev->priv;
663 ap->pdev = pdev;
664
665 dev->open = &ace_open;
666 dev->hard_start_xmit = &ace_start_xmit;
667 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
668#if ACENIC_DO_VLAN
669 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
670 dev->vlan_rx_register = ace_vlan_rx_register;
671 dev->vlan_rx_kill_vid = ace_vlan_rx_kill_vid;
672#endif
673 if (1) {
674 static void ace_watchdog(struct net_device *dev);
675 dev->tx_timeout = &ace_watchdog;
676 dev->watchdog_timeo = 5*HZ;
677 }
678 dev->stop = &ace_close;
679 dev->get_stats = &ace_get_stats;
680 dev->set_multicast_list = &ace_set_multicast_list;
681 dev->do_ioctl = &ace_ioctl;
682 dev->set_mac_address = &ace_set_mac_addr;
683 dev->change_mtu = &ace_change_mtu;
684
685
686 if (!version_disp)
687 {
688
689
690 version_disp = 1;
691 printk(version);
692 }
693
694 if (pci_enable_device(pdev)) {
695 kfree(dev);
696 continue;
697 }
698
699
700
701
702
703
704 pci_set_master(pdev);
705
706 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
707
708
709 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
710 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
711 "access - was not enabled by BIOS/Firmware\n",
712 dev->name);
713 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
714 pci_write_config_word(ap->pdev, PCI_COMMAND,
715 ap->pci_command);
716 wmb();
717 }
718
719 pci_read_config_byte(pdev, PCI_LATENCY_TIMER,
720 &ap->pci_latency);
721 if (ap->pci_latency <= 0x40) {
722 ap->pci_latency = 0x40;
723 pci_write_config_byte(pdev, PCI_LATENCY_TIMER,
724 ap->pci_latency);
725 }
726
727
728
729
730
731
732 dev->base_addr = pci_resource_start(pdev, 0);
733 ap->regs = (struct ace_regs *)ioremap(dev->base_addr, 0x4000);
734 if (!ap->regs) {
735 printk(KERN_ERR "%s: Unable to map I/O register, "
736 "AceNIC %i will be disabled.\n",
737 dev->name, boards_found);
738 break;
739 }
740
741 switch(pdev->vendor) {
742 case PCI_VENDOR_ID_ALTEON:
743 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
744 strncpy(ap->name, "Farallon PN9100-T "
745 "Gigabit Ethernet", sizeof (ap->name));
746 printk(KERN_INFO "%s: Farallon PN9100-T ",
747 dev->name);
748 } else {
749 strncpy(ap->name, "AceNIC Gigabit Ethernet",
750 sizeof (ap->name));
751 printk(KERN_INFO "%s: Alteon AceNIC ",
752 dev->name);
753 }
754 break;
755 case PCI_VENDOR_ID_3COM:
756 strncpy(ap->name, "3Com 3C985 Gigabit Ethernet",
757 sizeof (ap->name));
758 printk(KERN_INFO "%s: 3Com 3C985 ", dev->name);
759 break;
760 case PCI_VENDOR_ID_NETGEAR:
761 strncpy(ap->name, "NetGear GA620 Gigabit Ethernet",
762 sizeof (ap->name));
763 printk(KERN_INFO "%s: NetGear GA620 ", dev->name);
764 break;
765 case PCI_VENDOR_ID_DEC:
766 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
767 strncpy(ap->name, "Farallon PN9000-SX "
768 "Gigabit Ethernet", sizeof (ap->name));
769 printk(KERN_INFO "%s: Farallon PN9000-SX ",
770 dev->name);
771 break;
772 }
773 case PCI_VENDOR_ID_SGI:
774 strncpy(ap->name, "SGI AceNIC Gigabit Ethernet",
775 sizeof (ap->name));
776 printk(KERN_INFO "%s: SGI AceNIC ", dev->name);
777 break;
778 default:
779 strncpy(ap->name, "Unknown AceNIC based Gigabit "
780 "Ethernet", sizeof (ap->name));
781 printk(KERN_INFO "%s: Unknown AceNIC ", dev->name);
782 break;
783 }
784 ap->name [sizeof (ap->name) - 1] = '\0';
785 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
786#ifdef __sparc__
787 printk("irq %s\n", __irq_itoa(pdev->irq));
788#else
789 printk("irq %i\n", pdev->irq);
790#endif
791
792#ifdef CONFIG_ACENIC_OMIT_TIGON_I
793 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
794 printk(KERN_ERR "%s: Driver compiled without Tigon I"
795 " support - NIC disabled\n", dev->name);
796 ace_init_cleanup(dev);
797 kfree(dev);
798 continue;
799 }
800#endif
801
802 if (ace_allocate_descriptors(dev)) {
803
804
805
806
807 kfree(dev);
808 continue;
809 }
810
811#ifdef MODULE
812 if (boards_found >= ACE_MAX_MOD_PARMS)
813 ap->board_idx = BOARD_IDX_OVERFLOW;
814 else
815 ap->board_idx = boards_found;
816#else
817 ap->board_idx = BOARD_IDX_STATIC;
818#endif
819
820 if (ace_init(dev)) {
821
822
823
824 kfree(dev);
825 continue;
826 }
827
828 if (ap->pci_using_dac)
829 dev->features |= NETIF_F_HIGHDMA;
830
831 boards_found++;
832 }
833
834
835
836
837
838
839
840 if (boards_found > 0)
841 return 0;
842 else
843 return -ENODEV;
844}
845
846
847#ifdef MODULE
848MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
849MODULE_LICENSE("GPL");
850MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
851MODULE_PARM(link, "1-" __MODULE_STRING(8) "i");
852MODULE_PARM(trace, "1-" __MODULE_STRING(8) "i");
853MODULE_PARM(tx_coal_tick, "1-" __MODULE_STRING(8) "i");
854MODULE_PARM(max_tx_desc, "1-" __MODULE_STRING(8) "i");
855MODULE_PARM(rx_coal_tick, "1-" __MODULE_STRING(8) "i");
856MODULE_PARM(max_rx_desc, "1-" __MODULE_STRING(8) "i");
857MODULE_PARM(tx_ratio, "1-" __MODULE_STRING(8) "i");
858MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
859MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
860MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
861MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
862MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
863MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
864MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
865#endif
866
867
868static void __exit ace_module_cleanup(void)
869{
870 struct ace_private *ap;
871 struct ace_regs *regs;
872 struct net_device *next;
873 short i;
874
875 while (root_dev) {
876 ap = root_dev->priv;
877 next = ap->next;
878
879 regs = ap->regs;
880
881 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
882 if (ap->version >= 2)
883 writel(readl(®s->CpuBCtrl) | CPU_HALT,
884 ®s->CpuBCtrl);
885
886
887
888 writel(1, ®s->Mb0Lo);
889 readl(®s->CpuCtrl);
890
891
892
893
894
895
896
897
898
899
900 ace_sync_irq(root_dev->irq);
901
902 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
903 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
904
905 if (skb) {
906 struct ring_info *ringp;
907 dma_addr_t mapping;
908
909 ringp = &ap->skb->rx_std_skbuff[i];
910 mapping = pci_unmap_addr(ringp, mapping);
911 pci_unmap_page(ap->pdev, mapping,
912 ACE_STD_BUFSIZE - (2 + 16),
913 PCI_DMA_FROMDEVICE);
914
915 ap->rx_std_ring[i].size = 0;
916 ap->skb->rx_std_skbuff[i].skb = NULL;
917 dev_kfree_skb(skb);
918 }
919 }
920 if (ap->version >= 2) {
921 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
922 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
923
924 if (skb) {
925 struct ring_info *ringp;
926 dma_addr_t mapping;
927
928 ringp = &ap->skb->rx_mini_skbuff[i];
929 mapping = pci_unmap_addr(ringp,mapping);
930 pci_unmap_page(ap->pdev, mapping,
931 ACE_MINI_BUFSIZE - (2 + 16),
932 PCI_DMA_FROMDEVICE);
933
934 ap->rx_mini_ring[i].size = 0;
935 ap->skb->rx_mini_skbuff[i].skb = NULL;
936 dev_kfree_skb(skb);
937 }
938 }
939 }
940 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
941 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
942 if (skb) {
943 struct ring_info *ringp;
944 dma_addr_t mapping;
945
946 ringp = &ap->skb->rx_jumbo_skbuff[i];
947 mapping = pci_unmap_addr(ringp, mapping);
948 pci_unmap_page(ap->pdev, mapping,
949 ACE_JUMBO_BUFSIZE - (2 + 16),
950 PCI_DMA_FROMDEVICE);
951
952 ap->rx_jumbo_ring[i].size = 0;
953 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
954 dev_kfree_skb(skb);
955 }
956 }
957
958 ace_init_cleanup(root_dev);
959 kfree(root_dev);
960 root_dev = next;
961 }
962}
963
964
965int __init ace_module_init(void)
966{
967 int status;
968
969 root_dev = NULL;
970
971#ifdef NEW_NETINIT
972 status = acenic_probe();
973#else
974 status = acenic_probe(NULL);
975#endif
976 return status;
977}
978
979
980#if (LINUX_VERSION_CODE < 0x02032a)
981#ifdef MODULE
982int init_module(void)
983{
984 return ace_module_init();
985}
986
987
988void cleanup_module(void)
989{
990 ace_module_cleanup();
991}
992#endif
993#else
994module_init(ace_module_init);
995module_exit(ace_module_cleanup);
996#endif
997
998
999static void ace_free_descriptors(struct net_device *dev)
1000{
1001 struct ace_private *ap = dev->priv;
1002 int size;
1003
1004 if (ap->rx_std_ring != NULL) {
1005 size = (sizeof(struct rx_desc) *
1006 (RX_STD_RING_ENTRIES +
1007 RX_JUMBO_RING_ENTRIES +
1008 RX_MINI_RING_ENTRIES +
1009 RX_RETURN_RING_ENTRIES));
1010 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
1011 ap->rx_ring_base_dma);
1012 ap->rx_std_ring = NULL;
1013 ap->rx_jumbo_ring = NULL;
1014 ap->rx_mini_ring = NULL;
1015 ap->rx_return_ring = NULL;
1016 }
1017 if (ap->evt_ring != NULL) {
1018 size = (sizeof(struct event) * EVT_RING_ENTRIES);
1019 pci_free_consistent(ap->pdev, size, ap->evt_ring,
1020 ap->evt_ring_dma);
1021 ap->evt_ring = NULL;
1022 }
1023 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
1024 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
1025 pci_free_consistent(ap->pdev, size, ap->tx_ring,
1026 ap->tx_ring_dma);
1027 }
1028 ap->tx_ring = NULL;
1029
1030 if (ap->evt_prd != NULL) {
1031 pci_free_consistent(ap->pdev, sizeof(u32),
1032 (void *)ap->evt_prd, ap->evt_prd_dma);
1033 ap->evt_prd = NULL;
1034 }
1035 if (ap->rx_ret_prd != NULL) {
1036 pci_free_consistent(ap->pdev, sizeof(u32),
1037 (void *)ap->rx_ret_prd,
1038 ap->rx_ret_prd_dma);
1039 ap->rx_ret_prd = NULL;
1040 }
1041 if (ap->tx_csm != NULL) {
1042 pci_free_consistent(ap->pdev, sizeof(u32),
1043 (void *)ap->tx_csm, ap->tx_csm_dma);
1044 ap->tx_csm = NULL;
1045 }
1046}
1047
1048
1049static int ace_allocate_descriptors(struct net_device *dev)
1050{
1051 struct ace_private *ap = dev->priv;
1052 int size;
1053
1054 size = (sizeof(struct rx_desc) *
1055 (RX_STD_RING_ENTRIES +
1056 RX_JUMBO_RING_ENTRIES +
1057 RX_MINI_RING_ENTRIES +
1058 RX_RETURN_RING_ENTRIES));
1059
1060 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
1061 &ap->rx_ring_base_dma);
1062 if (ap->rx_std_ring == NULL)
1063 goto fail;
1064
1065 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
1066 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
1067 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
1068
1069 size = (sizeof(struct event) * EVT_RING_ENTRIES);
1070
1071 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
1072
1073 if (ap->evt_ring == NULL)
1074 goto fail;
1075
1076
1077
1078
1079
1080 if (!ACE_IS_TIGON_I(ap)) {
1081 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
1082
1083 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
1084 &ap->tx_ring_dma);
1085
1086 if (ap->tx_ring == NULL)
1087 goto fail;
1088 }
1089
1090 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
1091 &ap->evt_prd_dma);
1092 if (ap->evt_prd == NULL)
1093 goto fail;
1094
1095 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
1096 &ap->rx_ret_prd_dma);
1097 if (ap->rx_ret_prd == NULL)
1098 goto fail;
1099
1100 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
1101 &ap->tx_csm_dma);
1102 if (ap->tx_csm == NULL)
1103 goto fail;
1104
1105 return 0;
1106
1107fail:
1108
1109 ace_init_cleanup(dev);
1110 return 1;
1111}
1112
1113
1114
1115
1116
1117
1118static void ace_init_cleanup(struct net_device *dev)
1119{
1120 struct ace_private *ap;
1121
1122 ap = dev->priv;
1123
1124 ace_free_descriptors(dev);
1125
1126 if (ap->info)
1127 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
1128 ap->info, ap->info_dma);
1129 if (ap->skb)
1130 kfree(ap->skb);
1131 if (ap->trace_buf)
1132 kfree(ap->trace_buf);
1133
1134 if (dev->irq)
1135 free_irq(dev->irq, dev);
1136
1137 unregister_netdev(dev);
1138 iounmap(ap->regs);
1139}
1140
1141
1142
1143
1144
1145static inline void ace_issue_cmd(struct ace_regs *regs, struct cmd *cmd)
1146{
1147 u32 idx;
1148
1149 idx = readl(®s->CmdPrd);
1150
1151 writel(*(u32 *)(cmd), ®s->CmdRng[idx]);
1152 idx = (idx + 1) % CMD_RING_ENTRIES;
1153
1154 writel(idx, ®s->CmdPrd);
1155}
1156
1157
1158static int __init ace_init(struct net_device *dev)
1159{
1160 struct ace_private *ap;
1161 struct ace_regs *regs;
1162 struct ace_info *info = NULL;
1163 struct pci_dev *pdev;
1164 unsigned long myjif;
1165 u64 tmp_ptr;
1166 u32 tig_ver, mac1, mac2, tmp, pci_state;
1167 int board_idx, ecode = 0;
1168 short i;
1169 unsigned char cache_size;
1170
1171 ap = dev->priv;
1172 regs = ap->regs;
1173
1174 board_idx = ap->board_idx;
1175
1176
1177
1178
1179
1180
1181 writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl);
1182 readl(®s->HostCtrl);
1183 udelay(5);
1184
1185
1186
1187
1188#ifdef __BIG_ENDIAN
1189
1190
1191
1192
1193 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
1194 ®s->HostCtrl);
1195#else
1196 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
1197 ®s->HostCtrl);
1198#endif
1199 readl(®s->HostCtrl);
1200
1201
1202
1203
1204 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
1205 readl(®s->CpuCtrl);
1206 writel(0, ®s->Mb0Lo);
1207
1208 tig_ver = readl(®s->HostCtrl) >> 28;
1209
1210 switch(tig_ver){
1211#ifndef CONFIG_ACENIC_OMIT_TIGON_I
1212 case 4:
1213 printk(KERN_INFO " Tigon I (Rev. 4), Firmware: %i.%i.%i, ",
1214 tigonFwReleaseMajor, tigonFwReleaseMinor,
1215 tigonFwReleaseFix);
1216 writel(0, ®s->LocalCtrl);
1217 ap->version = 1;
1218 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
1219 break;
1220#endif
1221 case 6:
1222 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
1223 tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
1224 tigon2FwReleaseFix);
1225 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl);
1226 readl(®s->CpuBCtrl);
1227
1228
1229
1230
1231
1232 writel(SRAM_BANK_512K, ®s->LocalCtrl);
1233 writel(SYNC_SRAM_TIMING, ®s->MiscCfg);
1234 ap->version = 2;
1235 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
1236 break;
1237 default:
1238 printk(KERN_WARNING " Unsupported Tigon version detected "
1239 "(%i), ", tig_ver);
1240 ecode = -ENODEV;
1241 goto init_error;
1242 }
1243
1244
1245
1246
1247
1248
1249
1250
1251#ifdef __BIG_ENDIAN
1252 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
1253 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat);
1254#else
1255 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
1256 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat);
1257#endif
1258 readl(®s->ModeStat);
1259
1260 mac1 = 0;
1261 for(i = 0; i < 4; i++) {
1262 mac1 = mac1 << 8;
1263 tmp = read_eeprom_byte(dev, 0x8c+i);
1264 if (tmp < 0) {
1265 ecode = -EIO;
1266 goto init_error;
1267 } else
1268 mac1 |= (tmp & 0xff);
1269 }
1270 mac2 = 0;
1271 for(i = 4; i < 8; i++) {
1272 mac2 = mac2 << 8;
1273 tmp = read_eeprom_byte(dev, 0x8c+i);
1274 if (tmp < 0) {
1275 ecode = -EIO;
1276 goto init_error;
1277 } else
1278 mac2 |= (tmp & 0xff);
1279 }
1280
1281 writel(mac1, ®s->MacAddrHi);
1282 writel(mac2, ®s->MacAddrLo);
1283
1284 printk("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
1285 (mac1 >> 8) & 0xff, mac1 & 0xff, (mac2 >> 24) &0xff,
1286 (mac2 >> 16) & 0xff, (mac2 >> 8) & 0xff, mac2 & 0xff);
1287
1288 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1289 dev->dev_addr[1] = mac1 & 0xff;
1290 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1291 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1292 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1293 dev->dev_addr[5] = mac2 & 0xff;
1294
1295
1296
1297
1298
1299
1300
1301 pdev = ap->pdev;
1302 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1303 cache_size <<= 2;
1304 if (cache_size != SMP_CACHE_BYTES) {
1305 printk(KERN_INFO " PCI cache line size set incorrectly "
1306 "(%i bytes) by BIOS/FW, ", cache_size);
1307 if (cache_size > SMP_CACHE_BYTES)
1308 printk("expecting %i\n", SMP_CACHE_BYTES);
1309 else {
1310 printk("correcting to %i\n", SMP_CACHE_BYTES);
1311 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1312 SMP_CACHE_BYTES >> 2);
1313 }
1314 }
1315
1316 pci_state = readl(®s->PciState);
1317 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1318 "latency: %i clks\n",
1319 (pci_state & PCI_32BIT) ? 32 : 64,
1320 (pci_state & PCI_66MHZ) ? 66 : 33,
1321 ap->pci_latency);
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1334 if (ap->version >= 2) {
1335 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1336
1337
1338
1339 if (board_idx == BOARD_IDX_OVERFLOW ||
1340 dis_pci_mem_inval[board_idx]) {
1341 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1342 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1343 pci_write_config_word(pdev, PCI_COMMAND,
1344 ap->pci_command);
1345 printk(KERN_INFO " Disabling PCI memory "
1346 "write and invalidate\n");
1347 }
1348 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1349 printk(KERN_INFO " PCI memory write & invalidate "
1350 "enabled by BIOS, enabling counter measures\n");
1351
1352 switch(SMP_CACHE_BYTES) {
1353 case 16:
1354 tmp |= DMA_WRITE_MAX_16;
1355 break;
1356 case 32:
1357 tmp |= DMA_WRITE_MAX_32;
1358 break;
1359 case 64:
1360 tmp |= DMA_WRITE_MAX_64;
1361 break;
1362 case 128:
1363 tmp |= DMA_WRITE_MAX_128;
1364 break;
1365 default:
1366 printk(KERN_INFO " Cache line size %i not "
1367 "supported, PCI write and invalidate "
1368 "disabled\n", SMP_CACHE_BYTES);
1369 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1370 pci_write_config_word(pdev, PCI_COMMAND,
1371 ap->pci_command);
1372 }
1373 }
1374 }
1375
1376#ifdef __sparc__
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388 tmp &= ~DMA_READ_WRITE_MASK;
1389 tmp |= DMA_READ_MAX_64;
1390 tmp |= DMA_WRITE_MAX_64;
1391#endif
1392#ifdef __alpha__
1393 tmp &= ~DMA_READ_WRITE_MASK;
1394 tmp |= DMA_READ_MAX_128;
1395
1396
1397
1398
1399
1400 tmp |= DMA_WRITE_MAX_128;
1401#endif
1402 writel(tmp, ®s->PciState);
1403
1404#if 0
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1417 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1418 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1419 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1420 }
1421#endif
1422
1423
1424
1425
1426 if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
1427 ap->pci_using_dac = 1;
1428 } else if (!pci_set_dma_mask(pdev, 0xffffffffULL)) {
1429 ap->pci_using_dac = 0;
1430 } else {
1431 ecode = -ENODEV;
1432 goto init_error;
1433 }
1434
1435
1436
1437
1438
1439
1440 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1441 &ap->info_dma))) {
1442 ecode = -EAGAIN;
1443 goto init_error;
1444 }
1445 ap->info = info;
1446
1447
1448
1449
1450 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1451 ecode = -EAGAIN;
1452 goto init_error;
1453 }
1454
1455 ecode = request_irq(pdev->irq, ace_interrupt, SA_SHIRQ,
1456 dev->name, dev);
1457 if (ecode) {
1458 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1459 dev->name, pdev->irq);
1460 goto init_error;
1461 } else
1462 dev->irq = pdev->irq;
1463
1464
1465
1466
1467
1468 ap->next = root_dev;
1469 root_dev = dev;
1470
1471#ifdef INDEX_DEBUG
1472 spin_lock_init(&ap->debug_lock);
1473 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1474 ap->last_std_rx = 0;
1475 ap->last_mini_rx = 0;
1476#endif
1477
1478 memset(ap->info, 0, sizeof(struct ace_info));
1479 memset(ap->skb, 0, sizeof(struct ace_skb));
1480
1481 ace_load_firmware(dev);
1482 ap->fw_running = 0;
1483
1484 tmp_ptr = ap->info_dma;
1485 writel(tmp_ptr >> 32, ®s->InfoPtrHi);
1486 writel(tmp_ptr & 0xffffffff, ®s->InfoPtrLo);
1487
1488 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1489
1490 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1491 info->evt_ctrl.flags = 0;
1492
1493 *(ap->evt_prd) = 0;
1494 wmb();
1495 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1496 writel(0, ®s->EvtCsm);
1497
1498 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1499 info->cmd_ctrl.flags = 0;
1500 info->cmd_ctrl.max_len = 0;
1501
1502 for (i = 0; i < CMD_RING_ENTRIES; i++)
1503 writel(0, ®s->CmdRng[i]);
1504
1505 writel(0, ®s->CmdPrd);
1506 writel(0, ®s->CmdCsm);
1507
1508 tmp_ptr = ap->info_dma;
1509 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1510 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1511
1512 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1513 info->rx_std_ctrl.max_len = ACE_STD_MTU + ETH_HLEN + 4;
1514 info->rx_std_ctrl.flags =
1515 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1516
1517 memset(ap->rx_std_ring, 0,
1518 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1519
1520 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1521 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1522
1523 ap->rx_std_skbprd = 0;
1524 atomic_set(&ap->cur_rx_bufs, 0);
1525
1526 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1527 (ap->rx_ring_base_dma +
1528 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1529 info->rx_jumbo_ctrl.max_len = 0;
1530 info->rx_jumbo_ctrl.flags =
1531 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1532
1533 memset(ap->rx_jumbo_ring, 0,
1534 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1535
1536 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1537 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1538
1539 ap->rx_jumbo_skbprd = 0;
1540 atomic_set(&ap->cur_jumbo_bufs, 0);
1541
1542 memset(ap->rx_mini_ring, 0,
1543 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1544
1545 if (ap->version >= 2) {
1546 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1547 (ap->rx_ring_base_dma +
1548 (sizeof(struct rx_desc) *
1549 (RX_STD_RING_ENTRIES +
1550 RX_JUMBO_RING_ENTRIES))));
1551 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
1552 info->rx_mini_ctrl.flags =
1553 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1554
1555 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1556 ap->rx_mini_ring[i].flags =
1557 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1558 } else {
1559 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1560 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1561 info->rx_mini_ctrl.max_len = 0;
1562 }
1563
1564 ap->rx_mini_skbprd = 0;
1565 atomic_set(&ap->cur_mini_bufs, 0);
1566
1567 set_aceaddr(&info->rx_return_ctrl.rngptr,
1568 (ap->rx_ring_base_dma +
1569 (sizeof(struct rx_desc) *
1570 (RX_STD_RING_ENTRIES +
1571 RX_JUMBO_RING_ENTRIES +
1572 RX_MINI_RING_ENTRIES))));
1573 info->rx_return_ctrl.flags = 0;
1574 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1575
1576 memset(ap->rx_return_ring, 0,
1577 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1578
1579 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1580 *(ap->rx_ret_prd) = 0;
1581
1582 writel(TX_RING_BASE, ®s->WinBase);
1583
1584 if (ACE_IS_TIGON_I(ap)) {
1585 ap->tx_ring = (struct tx_desc *)regs->Window;
1586 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES *
1587 sizeof(struct tx_desc) / 4); i++) {
1588 writel(0, (unsigned long)ap->tx_ring + i * 4);
1589 }
1590
1591 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1592 } else {
1593 memset(ap->tx_ring, 0,
1594 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1595
1596 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1597 }
1598
1599 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1600 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1601
1602
1603
1604
1605 if (!ACE_IS_TIGON_I(ap))
1606 tmp |= RCB_FLG_TX_HOST_RING;
1607#if TX_COAL_INTS_ONLY
1608 tmp |= RCB_FLG_COAL_INT_ONLY;
1609#endif
1610 info->tx_ctrl.flags = tmp;
1611
1612 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1613
1614
1615
1616
1617#if 0
1618 writel(DMA_THRESH_16W, ®s->DmaReadCfg);
1619 writel(DMA_THRESH_16W, ®s->DmaWriteCfg);
1620#else
1621 writel(DMA_THRESH_8W, ®s->DmaReadCfg);
1622 writel(DMA_THRESH_8W, ®s->DmaWriteCfg);
1623#endif
1624
1625 writel(0, ®s->MaskInt);
1626 writel(1, ®s->IfIdx);
1627#if 0
1628
1629
1630
1631
1632 writel(1, ®s->AssistState);
1633#endif
1634
1635 writel(DEF_STAT, ®s->TuneStatTicks);
1636 writel(DEF_TRACE, ®s->TuneTrace);
1637
1638 ace_set_rxtx_parms(dev, 0);
1639
1640 if (board_idx == BOARD_IDX_OVERFLOW) {
1641 printk(KERN_WARNING "%s: more than %i NICs detected, "
1642 "ignoring module parameters!\n",
1643 dev->name, ACE_MAX_MOD_PARMS);
1644 } else if (board_idx >= 0) {
1645 if (tx_coal_tick[board_idx])
1646 writel(tx_coal_tick[board_idx],
1647 ®s->TuneTxCoalTicks);
1648 if (max_tx_desc[board_idx])
1649 writel(max_tx_desc[board_idx], ®s->TuneMaxTxDesc);
1650
1651 if (rx_coal_tick[board_idx])
1652 writel(rx_coal_tick[board_idx],
1653 ®s->TuneRxCoalTicks);
1654 if (max_rx_desc[board_idx])
1655 writel(max_rx_desc[board_idx], ®s->TuneMaxRxDesc);
1656
1657 if (trace[board_idx])
1658 writel(trace[board_idx], ®s->TuneTrace);
1659
1660 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1661 writel(tx_ratio[board_idx], ®s->TxBufRat);
1662 }
1663
1664
1665
1666
1667 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1668 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1669 if(ap->version >= 2)
1670 tmp |= LNK_TX_FLOW_CTL_Y;
1671
1672
1673
1674
1675 if ((board_idx >= 0) && link[board_idx]) {
1676 int option = link[board_idx];
1677
1678 tmp = LNK_ENABLE;
1679
1680 if (option & 0x01) {
1681 printk(KERN_INFO "%s: Setting half duplex link\n",
1682 dev->name);
1683 tmp &= ~LNK_FULL_DUPLEX;
1684 }
1685 if (option & 0x02)
1686 tmp &= ~LNK_NEGOTIATE;
1687 if (option & 0x10)
1688 tmp |= LNK_10MB;
1689 if (option & 0x20)
1690 tmp |= LNK_100MB;
1691 if (option & 0x40)
1692 tmp |= LNK_1000MB;
1693 if ((option & 0x70) == 0) {
1694 printk(KERN_WARNING "%s: No media speed specified, "
1695 "forcing auto negotiation\n", dev->name);
1696 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1697 LNK_100MB | LNK_10MB;
1698 }
1699 if ((option & 0x100) == 0)
1700 tmp |= LNK_NEG_FCTL;
1701 else
1702 printk(KERN_INFO "%s: Disabling flow control "
1703 "negotiation\n", dev->name);
1704 if (option & 0x200)
1705 tmp |= LNK_RX_FLOW_CTL_Y;
1706 if ((option & 0x400) && (ap->version >= 2)) {
1707 printk(KERN_INFO "%s: Enabling TX flow control\n",
1708 dev->name);
1709 tmp |= LNK_TX_FLOW_CTL_Y;
1710 }
1711 }
1712
1713 ap->link = tmp;
1714 writel(tmp, ®s->TuneLink);
1715 if (ap->version >= 2)
1716 writel(tmp, ®s->TuneFastLink);
1717
1718 if (ACE_IS_TIGON_I(ap))
1719 writel(tigonFwStartAddr, ®s->Pc);
1720 if (ap->version == 2)
1721 writel(tigon2FwStartAddr, ®s->Pc);
1722
1723 writel(0, ®s->Mb0Lo);
1724
1725
1726
1727
1728
1729
1730
1731 ap->cur_rx = 0;
1732 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1733
1734 wmb();
1735 ace_set_txprd(regs, ap, 0);
1736 writel(0, ®s->RxRetCsm);
1737
1738
1739
1740
1741 memset(&ap->stats, 0, sizeof(ap->stats));
1742
1743
1744
1745
1746
1747
1748
1749 writel(1, ®s->AssistState);
1750
1751
1752
1753
1754 writel(readl(®s->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), ®s->CpuCtrl);
1755 readl(®s->CpuCtrl);
1756
1757
1758
1759
1760 myjif = jiffies + 3 * HZ;
1761 while (time_before(jiffies, myjif) && !ap->fw_running);
1762
1763 if (!ap->fw_running) {
1764 printk(KERN_ERR "%s: Firmware NOT running!\n", dev->name);
1765
1766 ace_dump_trace(ap);
1767 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
1768 readl(®s->CpuCtrl);
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779 if (ap->version >= 2)
1780 writel(readl(®s->CpuBCtrl) | CPU_HALT,
1781 ®s->CpuBCtrl);
1782 writel(0, ®s->Mb0Lo);
1783 readl(®s->Mb0Lo);
1784
1785 ecode = -EBUSY;
1786 goto init_error;
1787 }
1788
1789
1790
1791
1792
1793 if (!test_and_set_bit(0, &ap->std_refill_busy))
1794 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1795 else
1796 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1797 dev->name);
1798 if (ap->version >= 2) {
1799 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1800 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1801 else
1802 printk(KERN_ERR "%s: Someone is busy refilling "
1803 "the RX mini ring\n", dev->name);
1804 }
1805 return 0;
1806
1807 init_error:
1808 ace_init_cleanup(dev);
1809 return ecode;
1810}
1811
1812
1813static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1814{
1815 struct ace_private *ap;
1816 struct ace_regs *regs;
1817 int board_idx;
1818
1819 ap = dev->priv;
1820 regs = ap->regs;
1821
1822 board_idx = ap->board_idx;
1823
1824 if (board_idx >= 0) {
1825 if (!jumbo) {
1826 if (!tx_coal_tick[board_idx])
1827 writel(DEF_TX_COAL, ®s->TuneTxCoalTicks);
1828 if (!max_tx_desc[board_idx])
1829 writel(DEF_TX_MAX_DESC, ®s->TuneMaxTxDesc);
1830 if (!rx_coal_tick[board_idx])
1831 writel(DEF_RX_COAL, ®s->TuneRxCoalTicks);
1832 if (!max_rx_desc[board_idx])
1833 writel(DEF_RX_MAX_DESC, ®s->TuneMaxRxDesc);
1834 if (!tx_ratio[board_idx])
1835 writel(DEF_TX_RATIO, ®s->TxBufRat);
1836 } else {
1837 if (!tx_coal_tick[board_idx])
1838 writel(DEF_JUMBO_TX_COAL,
1839 ®s->TuneTxCoalTicks);
1840 if (!max_tx_desc[board_idx])
1841 writel(DEF_JUMBO_TX_MAX_DESC,
1842 ®s->TuneMaxTxDesc);
1843 if (!rx_coal_tick[board_idx])
1844 writel(DEF_JUMBO_RX_COAL,
1845 ®s->TuneRxCoalTicks);
1846 if (!max_rx_desc[board_idx])
1847 writel(DEF_JUMBO_RX_MAX_DESC,
1848 ®s->TuneMaxRxDesc);
1849 if (!tx_ratio[board_idx])
1850 writel(DEF_JUMBO_TX_RATIO, ®s->TxBufRat);
1851 }
1852 }
1853}
1854
1855
1856static void ace_watchdog(struct net_device *data)
1857{
1858 struct net_device *dev = data;
1859 struct ace_private *ap = dev->priv;
1860 struct ace_regs *regs = ap->regs;
1861
1862
1863
1864
1865
1866
1867 if (*ap->tx_csm != ap->tx_ret_csm) {
1868 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1869 dev->name, (unsigned int)readl(®s->HostCtrl));
1870
1871 } else {
1872 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1873 dev->name);
1874 netif_wake_queue(dev);
1875 }
1876}
1877
1878
1879static void ace_tasklet(unsigned long dev)
1880{
1881 struct ace_private *ap = ((struct net_device *)dev)->priv;
1882 int cur_size;
1883
1884 cur_size = atomic_read(&ap->cur_rx_bufs);
1885 if ((cur_size < RX_LOW_STD_THRES) &&
1886 !test_and_set_bit(0, &ap->std_refill_busy)) {
1887#if DEBUG
1888 printk("refilling buffers (current %i)\n", cur_size);
1889#endif
1890 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1891 }
1892
1893 if (ap->version >= 2) {
1894 cur_size = atomic_read(&ap->cur_mini_bufs);
1895 if ((cur_size < RX_LOW_MINI_THRES) &&
1896 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1897#if DEBUG
1898 printk("refilling mini buffers (current %i)\n",
1899 cur_size);
1900#endif
1901 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1902 }
1903 }
1904
1905 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1906 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1907 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1908#if DEBUG
1909 printk("refilling jumbo buffers (current %i)\n", cur_size);
1910#endif
1911 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1912 }
1913 ap->tasklet_pending = 0;
1914}
1915
1916
1917
1918
1919
1920static void ace_dump_trace(struct ace_private *ap)
1921{
1922#if 0
1923 if (!ap->trace_buf)
1924 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1925 return;
1926#endif
1927}
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1938{
1939 struct ace_regs *regs;
1940 short i, idx;
1941
1942 regs = ap->regs;
1943
1944 prefetchw(&ap->cur_rx_bufs);
1945
1946 idx = ap->rx_std_skbprd;
1947
1948 for (i = 0; i < nr_bufs; i++) {
1949 struct sk_buff *skb;
1950 struct rx_desc *rd;
1951 dma_addr_t mapping;
1952
1953 skb = alloc_skb(ACE_STD_BUFSIZE, GFP_ATOMIC);
1954 if (!skb)
1955 break;
1956
1957
1958
1959
1960 skb_reserve(skb, 2 + 16);
1961 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1962 ((unsigned long)skb->data & ~PAGE_MASK),
1963 ACE_STD_BUFSIZE - (2 + 16),
1964 PCI_DMA_FROMDEVICE);
1965 ap->skb->rx_std_skbuff[idx].skb = skb;
1966 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1967 mapping, mapping);
1968
1969 rd = &ap->rx_std_ring[idx];
1970 set_aceaddr(&rd->addr, mapping);
1971 rd->size = ACE_STD_MTU + ETH_HLEN + 4;
1972 rd->idx = idx;
1973 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1974 }
1975
1976 if (!i)
1977 goto error_out;
1978
1979 atomic_add(i, &ap->cur_rx_bufs);
1980 ap->rx_std_skbprd = idx;
1981
1982 if (ACE_IS_TIGON_I(ap)) {
1983 struct cmd cmd;
1984 cmd.evt = C_SET_RX_PRD_IDX;
1985 cmd.code = 0;
1986 cmd.idx = ap->rx_std_skbprd;
1987 ace_issue_cmd(regs, &cmd);
1988 } else {
1989 writel(idx, ®s->RxStdPrd);
1990 wmb();
1991 }
1992
1993 out:
1994 clear_bit(0, &ap->std_refill_busy);
1995 return;
1996
1997 error_out:
1998 printk(KERN_INFO "Out of memory when allocating "
1999 "standard receive buffers\n");
2000 goto out;
2001}
2002
2003
2004static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
2005{
2006 struct ace_regs *regs;
2007 short i, idx;
2008
2009 regs = ap->regs;
2010
2011 prefetchw(&ap->cur_mini_bufs);
2012
2013 idx = ap->rx_mini_skbprd;
2014 for (i = 0; i < nr_bufs; i++) {
2015 struct sk_buff *skb;
2016 struct rx_desc *rd;
2017 dma_addr_t mapping;
2018
2019 skb = alloc_skb(ACE_MINI_BUFSIZE, GFP_ATOMIC);
2020 if (!skb)
2021 break;
2022
2023
2024
2025
2026 skb_reserve(skb, 2 + 16);
2027 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2028 ((unsigned long)skb->data & ~PAGE_MASK),
2029 ACE_MINI_BUFSIZE - (2 + 16),
2030 PCI_DMA_FROMDEVICE);
2031 ap->skb->rx_mini_skbuff[idx].skb = skb;
2032 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
2033 mapping, mapping);
2034
2035 rd = &ap->rx_mini_ring[idx];
2036 set_aceaddr(&rd->addr, mapping);
2037 rd->size = ACE_MINI_SIZE;
2038 rd->idx = idx;
2039 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
2040 }
2041
2042 if (!i)
2043 goto error_out;
2044
2045 atomic_add(i, &ap->cur_mini_bufs);
2046
2047 ap->rx_mini_skbprd = idx;
2048
2049 writel(idx, ®s->RxMiniPrd);
2050 wmb();
2051
2052 out:
2053 clear_bit(0, &ap->mini_refill_busy);
2054 return;
2055 error_out:
2056 printk(KERN_INFO "Out of memory when allocating "
2057 "mini receive buffers\n");
2058 goto out;
2059}
2060
2061
2062
2063
2064
2065
2066static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
2067{
2068 struct ace_regs *regs;
2069 short i, idx;
2070
2071 regs = ap->regs;
2072
2073 idx = ap->rx_jumbo_skbprd;
2074
2075 for (i = 0; i < nr_bufs; i++) {
2076 struct sk_buff *skb;
2077 struct rx_desc *rd;
2078 dma_addr_t mapping;
2079
2080 skb = alloc_skb(ACE_JUMBO_BUFSIZE, GFP_ATOMIC);
2081 if (!skb)
2082 break;
2083
2084
2085
2086
2087 skb_reserve(skb, 2 + 16);
2088 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2089 ((unsigned long)skb->data & ~PAGE_MASK),
2090 ACE_JUMBO_BUFSIZE - (2 + 16),
2091 PCI_DMA_FROMDEVICE);
2092 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
2093 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
2094 mapping, mapping);
2095
2096 rd = &ap->rx_jumbo_ring[idx];
2097 set_aceaddr(&rd->addr, mapping);
2098 rd->size = ACE_JUMBO_MTU + ETH_HLEN + 4;
2099 rd->idx = idx;
2100 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
2101 }
2102
2103 if (!i)
2104 goto error_out;
2105
2106 atomic_add(i, &ap->cur_jumbo_bufs);
2107 ap->rx_jumbo_skbprd = idx;
2108
2109 if (ACE_IS_TIGON_I(ap)) {
2110 struct cmd cmd;
2111 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
2112 cmd.code = 0;
2113 cmd.idx = ap->rx_jumbo_skbprd;
2114 ace_issue_cmd(regs, &cmd);
2115 } else {
2116 writel(idx, ®s->RxJumboPrd);
2117 wmb();
2118 }
2119
2120 out:
2121 clear_bit(0, &ap->jumbo_refill_busy);
2122 return;
2123 error_out:
2124 if (net_ratelimit())
2125 printk(KERN_INFO "Out of memory when allocating "
2126 "jumbo receive buffers\n");
2127 goto out;
2128}
2129
2130
2131
2132
2133
2134
2135
2136static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
2137{
2138 struct ace_private *ap;
2139
2140 ap = dev->priv;
2141
2142 while (evtcsm != evtprd) {
2143 switch (ap->evt_ring[evtcsm].evt) {
2144 case E_FW_RUNNING:
2145 printk(KERN_INFO "%s: Firmware up and running\n",
2146 dev->name);
2147 ap->fw_running = 1;
2148 wmb();
2149 break;
2150 case E_STATS_UPDATED:
2151 break;
2152 case E_LNK_STATE:
2153 {
2154 u16 code = ap->evt_ring[evtcsm].code;
2155 switch (code) {
2156 case E_C_LINK_UP:
2157 {
2158 u32 state = readl(&ap->regs->GigLnkState);
2159 printk(KERN_WARNING "%s: Optical link UP "
2160 "(%s Duplex, Flow Control: %s%s)\n",
2161 dev->name,
2162 state & LNK_FULL_DUPLEX ? "Full":"Half",
2163 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
2164 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
2165 break;
2166 }
2167 case E_C_LINK_DOWN:
2168 printk(KERN_WARNING "%s: Optical link DOWN\n",
2169 dev->name);
2170 break;
2171 case E_C_LINK_10_100:
2172 printk(KERN_WARNING "%s: 10/100BaseT link "
2173 "UP\n", dev->name);
2174 break;
2175 default:
2176 printk(KERN_ERR "%s: Unknown optical link "
2177 "state %02x\n", dev->name, code);
2178 }
2179 break;
2180 }
2181 case E_ERROR:
2182 switch(ap->evt_ring[evtcsm].code) {
2183 case E_C_ERR_INVAL_CMD:
2184 printk(KERN_ERR "%s: invalid command error\n",
2185 dev->name);
2186 break;
2187 case E_C_ERR_UNIMP_CMD:
2188 printk(KERN_ERR "%s: unimplemented command "
2189 "error\n", dev->name);
2190 break;
2191 case E_C_ERR_BAD_CFG:
2192 printk(KERN_ERR "%s: bad config error\n",
2193 dev->name);
2194 break;
2195 default:
2196 printk(KERN_ERR "%s: unknown error %02x\n",
2197 dev->name, ap->evt_ring[evtcsm].code);
2198 }
2199 break;
2200 case E_RESET_JUMBO_RNG:
2201 {
2202 int i;
2203 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
2204 if (ap->skb->rx_jumbo_skbuff[i].skb) {
2205 ap->rx_jumbo_ring[i].size = 0;
2206 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
2207 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
2208 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
2209 }
2210 }
2211
2212 if (ACE_IS_TIGON_I(ap)) {
2213 struct cmd cmd;
2214 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
2215 cmd.code = 0;
2216 cmd.idx = 0;
2217 ace_issue_cmd(ap->regs, &cmd);
2218 } else {
2219 writel(0, &((ap->regs)->RxJumboPrd));
2220 wmb();
2221 }
2222
2223 ap->jumbo = 0;
2224 ap->rx_jumbo_skbprd = 0;
2225 printk(KERN_INFO "%s: Jumbo ring flushed\n",
2226 dev->name);
2227 clear_bit(0, &ap->jumbo_refill_busy);
2228 break;
2229 }
2230 default:
2231 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
2232 dev->name, ap->evt_ring[evtcsm].evt);
2233 }
2234 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
2235 }
2236
2237 return evtcsm;
2238}
2239
2240
2241static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
2242{
2243 struct ace_private *ap = dev->priv;
2244 u32 idx;
2245 int mini_count = 0, std_count = 0;
2246
2247 idx = rxretcsm;
2248
2249 prefetchw(&ap->cur_rx_bufs);
2250 prefetchw(&ap->cur_mini_bufs);
2251
2252 while (idx != rxretprd) {
2253 struct ring_info *rip;
2254 struct sk_buff *skb;
2255 struct rx_desc *rxdesc, *retdesc;
2256 u32 skbidx;
2257 int bd_flags, desc_type, mapsize;
2258 u16 csum;
2259
2260 retdesc = &ap->rx_return_ring[idx];
2261 skbidx = retdesc->idx;
2262 bd_flags = retdesc->flags;
2263 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
2264
2265 switch(desc_type) {
2266
2267
2268
2269
2270
2271
2272
2273 case 0:
2274 rip = &ap->skb->rx_std_skbuff[skbidx];
2275 mapsize = ACE_STD_BUFSIZE - (2 + 16);
2276 rxdesc = &ap->rx_std_ring[skbidx];
2277 std_count++;
2278 break;
2279 case BD_FLG_JUMBO:
2280 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
2281 mapsize = ACE_JUMBO_BUFSIZE - (2 + 16);
2282 rxdesc = &ap->rx_jumbo_ring[skbidx];
2283 atomic_dec(&ap->cur_jumbo_bufs);
2284 break;
2285 case BD_FLG_MINI:
2286 rip = &ap->skb->rx_mini_skbuff[skbidx];
2287 mapsize = ACE_MINI_BUFSIZE - (2 + 16);
2288 rxdesc = &ap->rx_mini_ring[skbidx];
2289 mini_count++;
2290 break;
2291 default:
2292 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2293 "returned by NIC\n", dev->name,
2294 retdesc->flags);
2295 goto error;
2296 }
2297
2298 skb = rip->skb;
2299 rip->skb = NULL;
2300 pci_unmap_page(ap->pdev,
2301 pci_unmap_addr(rip, mapping),
2302 mapsize,
2303 PCI_DMA_FROMDEVICE);
2304 skb_put(skb, retdesc->size);
2305
2306
2307
2308
2309 csum = retdesc->tcp_udp_csum;
2310
2311 skb->dev = dev;
2312 skb->protocol = eth_type_trans(skb, dev);
2313
2314
2315
2316
2317
2318 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2319 skb->csum = htons(csum);
2320 skb->ip_summed = CHECKSUM_HW;
2321 } else {
2322 skb->ip_summed = CHECKSUM_NONE;
2323 }
2324
2325
2326#if ACENIC_DO_VLAN
2327 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2328 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2329 } else
2330#endif
2331 netif_rx(skb);
2332
2333 dev->last_rx = jiffies;
2334 ap->stats.rx_packets++;
2335 ap->stats.rx_bytes += retdesc->size;
2336
2337 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2338 }
2339
2340 atomic_sub(std_count, &ap->cur_rx_bufs);
2341 if (!ACE_IS_TIGON_I(ap))
2342 atomic_sub(mini_count, &ap->cur_mini_bufs);
2343
2344 out:
2345
2346
2347
2348
2349 if (ACE_IS_TIGON_I(ap)) {
2350 struct ace_regs *regs = ap->regs;
2351 writel(idx, ®s->RxRetCsm);
2352 }
2353 ap->cur_rx = idx;
2354
2355 return;
2356 error:
2357 idx = rxretprd;
2358 goto out;
2359}
2360
2361
2362static inline void ace_tx_int(struct net_device *dev,
2363 u32 txcsm, u32 idx)
2364{
2365 struct ace_private *ap = dev->priv;
2366
2367 do {
2368 struct sk_buff *skb;
2369 dma_addr_t mapping;
2370 struct tx_ring_info *info;
2371
2372 info = ap->skb->tx_skbuff + idx;
2373 skb = info->skb;
2374 mapping = pci_unmap_addr(info, mapping);
2375
2376 if (mapping) {
2377 pci_unmap_page(ap->pdev, mapping,
2378 pci_unmap_len(info, maplen),
2379 PCI_DMA_TODEVICE);
2380 pci_unmap_addr_set(info, mapping, 0);
2381 }
2382
2383 if (skb) {
2384 ap->stats.tx_packets++;
2385 ap->stats.tx_bytes += skb->len;
2386 dev_kfree_skb_irq(skb);
2387 info->skb = NULL;
2388 }
2389
2390 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2391 } while (idx != txcsm);
2392
2393 if (netif_queue_stopped(dev))
2394 netif_wake_queue(dev);
2395
2396 wmb();
2397 ap->tx_ret_csm = txcsm;
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426}
2427
2428
2429static void ace_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
2430{
2431 struct ace_private *ap;
2432 struct ace_regs *regs;
2433 struct net_device *dev = (struct net_device *)dev_id;
2434 u32 idx;
2435 u32 txcsm, rxretcsm, rxretprd;
2436 u32 evtcsm, evtprd;
2437
2438 ap = dev->priv;
2439 regs = ap->regs;
2440
2441
2442
2443
2444
2445
2446 if (!(readl(®s->HostCtrl) & IN_INT))
2447 return;
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457 writel(0, ®s->Mb0Lo);
2458 readl(®s->Mb0Lo);
2459
2460
2461
2462
2463
2464
2465
2466
2467 rxretprd = *ap->rx_ret_prd;
2468 rxretcsm = ap->cur_rx;
2469
2470 if (rxretprd != rxretcsm)
2471 ace_rx_int(dev, rxretprd, rxretcsm);
2472
2473 txcsm = *ap->tx_csm;
2474 idx = ap->tx_ret_csm;
2475
2476 if (txcsm != idx) {
2477
2478
2479
2480
2481
2482
2483
2484 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2485 ace_tx_int(dev, txcsm, idx);
2486 }
2487
2488 evtcsm = readl(®s->EvtCsm);
2489 evtprd = *ap->evt_prd;
2490
2491 if (evtcsm != evtprd) {
2492 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2493 writel(evtcsm, ®s->EvtCsm);
2494 }
2495
2496
2497
2498
2499
2500 if (netif_running(dev)) {
2501 int cur_size;
2502 int run_tasklet = 0;
2503
2504 cur_size = atomic_read(&ap->cur_rx_bufs);
2505 if (cur_size < RX_LOW_STD_THRES) {
2506 if ((cur_size < RX_PANIC_STD_THRES) &&
2507 !test_and_set_bit(0, &ap->std_refill_busy)) {
2508#if DEBUG
2509 printk("low on std buffers %i\n", cur_size);
2510#endif
2511 ace_load_std_rx_ring(ap,
2512 RX_RING_SIZE - cur_size);
2513 } else
2514 run_tasklet = 1;
2515 }
2516
2517 if (!ACE_IS_TIGON_I(ap)) {
2518 cur_size = atomic_read(&ap->cur_mini_bufs);
2519 if (cur_size < RX_LOW_MINI_THRES) {
2520 if ((cur_size < RX_PANIC_MINI_THRES) &&
2521 !test_and_set_bit(0,
2522 &ap->mini_refill_busy)) {
2523#if DEBUG
2524 printk("low on mini buffers %i\n",
2525 cur_size);
2526#endif
2527 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2528 } else
2529 run_tasklet = 1;
2530 }
2531 }
2532
2533 if (ap->jumbo) {
2534 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2535 if (cur_size < RX_LOW_JUMBO_THRES) {
2536 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2537 !test_and_set_bit(0,
2538 &ap->jumbo_refill_busy)){
2539#if DEBUG
2540 printk("low on jumbo buffers %i\n",
2541 cur_size);
2542#endif
2543 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2544 } else
2545 run_tasklet = 1;
2546 }
2547 }
2548 if (run_tasklet && !ap->tasklet_pending) {
2549 ap->tasklet_pending = 1;
2550 tasklet_schedule(&ap->ace_tasklet);
2551 }
2552 }
2553}
2554
2555
2556#if ACENIC_DO_VLAN
2557static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2558{
2559 struct ace_private *ap = dev->priv;
2560 unsigned long flags;
2561
2562 local_irq_save(flags);
2563 ace_mask_irq(dev);
2564
2565 ap->vlgrp = grp;
2566
2567 ace_unmask_irq(dev);
2568 local_irq_restore(flags);
2569}
2570
2571
2572static void ace_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
2573{
2574 struct ace_private *ap = dev->priv;
2575 unsigned long flags;
2576
2577 local_irq_save(flags);
2578 ace_mask_irq(dev);
2579
2580 if (ap->vlgrp)
2581 ap->vlgrp->vlan_devices[vid] = NULL;
2582
2583 ace_unmask_irq(dev);
2584 local_irq_restore(flags);
2585}
2586#endif
2587
2588
2589static int ace_open(struct net_device *dev)
2590{
2591 struct ace_private *ap;
2592 struct ace_regs *regs;
2593 struct cmd cmd;
2594
2595 ap = dev->priv;
2596 regs = ap->regs;
2597
2598 if (!(ap->fw_running)) {
2599 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2600 return -EBUSY;
2601 }
2602
2603 writel(dev->mtu + ETH_HLEN + 4, ®s->IfMtu);
2604
2605 cmd.evt = C_CLEAR_STATS;
2606 cmd.code = 0;
2607 cmd.idx = 0;
2608 ace_issue_cmd(regs, &cmd);
2609
2610 cmd.evt = C_HOST_STATE;
2611 cmd.code = C_C_STACK_UP;
2612 cmd.idx = 0;
2613 ace_issue_cmd(regs, &cmd);
2614
2615 if (ap->jumbo &&
2616 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2617 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2618
2619 if (dev->flags & IFF_PROMISC) {
2620 cmd.evt = C_SET_PROMISC_MODE;
2621 cmd.code = C_C_PROMISC_ENABLE;
2622 cmd.idx = 0;
2623 ace_issue_cmd(regs, &cmd);
2624
2625 ap->promisc = 1;
2626 }else
2627 ap->promisc = 0;
2628 ap->mcast_all = 0;
2629
2630#if 0
2631 cmd.evt = C_LNK_NEGOTIATION;
2632 cmd.code = 0;
2633 cmd.idx = 0;
2634 ace_issue_cmd(regs, &cmd);
2635#endif
2636
2637 netif_start_queue(dev);
2638
2639 ACE_MOD_INC_USE_COUNT;
2640
2641
2642
2643
2644 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2645 return 0;
2646}
2647
2648
2649static int ace_close(struct net_device *dev)
2650{
2651 struct ace_private *ap;
2652 struct ace_regs *regs;
2653 struct cmd cmd;
2654 unsigned long flags;
2655 short i;
2656
2657 ace_if_down(dev);
2658
2659
2660
2661
2662
2663
2664 netif_stop_queue(dev);
2665
2666 ap = dev->priv;
2667 regs = ap->regs;
2668
2669 if (ap->promisc) {
2670 cmd.evt = C_SET_PROMISC_MODE;
2671 cmd.code = C_C_PROMISC_DISABLE;
2672 cmd.idx = 0;
2673 ace_issue_cmd(regs, &cmd);
2674 ap->promisc = 0;
2675 }
2676
2677 cmd.evt = C_HOST_STATE;
2678 cmd.code = C_C_STACK_DOWN;
2679 cmd.idx = 0;
2680 ace_issue_cmd(regs, &cmd);
2681
2682 tasklet_kill(&ap->ace_tasklet);
2683
2684
2685
2686
2687
2688
2689 local_irq_save(flags);
2690 ace_mask_irq(dev);
2691
2692 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2693 struct sk_buff *skb;
2694 dma_addr_t mapping;
2695 struct tx_ring_info *info;
2696
2697 info = ap->skb->tx_skbuff + i;
2698 skb = info->skb;
2699 mapping = pci_unmap_addr(info, mapping);
2700
2701 if (mapping) {
2702 if (ACE_IS_TIGON_I(ap)) {
2703 writel(0, &ap->tx_ring[i].addr.addrhi);
2704 writel(0, &ap->tx_ring[i].addr.addrlo);
2705 writel(0, &ap->tx_ring[i].flagsize);
2706 } else
2707 memset(ap->tx_ring + i, 0,
2708 sizeof(struct tx_desc));
2709 pci_unmap_page(ap->pdev, mapping,
2710 pci_unmap_len(info, maplen),
2711 PCI_DMA_TODEVICE);
2712 pci_unmap_addr_set(info, mapping, 0);
2713 }
2714 if (skb) {
2715 dev_kfree_skb(skb);
2716 info->skb = NULL;
2717 }
2718 }
2719
2720 if (ap->jumbo) {
2721 cmd.evt = C_RESET_JUMBO_RNG;
2722 cmd.code = 0;
2723 cmd.idx = 0;
2724 ace_issue_cmd(regs, &cmd);
2725 }
2726
2727 ace_unmask_irq(dev);
2728 local_irq_restore(flags);
2729
2730 ACE_MOD_DEC_USE_COUNT;
2731 return 0;
2732}
2733
2734
2735static inline dma_addr_t
2736ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2737 struct sk_buff *tail, u32 idx)
2738{
2739 dma_addr_t mapping;
2740 struct tx_ring_info *info;
2741
2742 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2743 ((unsigned long) skb->data & ~PAGE_MASK),
2744 skb->len, PCI_DMA_TODEVICE);
2745
2746 info = ap->skb->tx_skbuff + idx;
2747 info->skb = tail;
2748 pci_unmap_addr_set(info, mapping, mapping);
2749 pci_unmap_len_set(info, maplen, skb->len);
2750 return mapping;
2751}
2752
2753
2754static inline void
2755ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2756 u32 flagsize, u32 vlan_tag)
2757{
2758#if !USE_TX_COAL_NOW
2759 flagsize &= ~BD_FLG_COAL_NOW;
2760#endif
2761
2762 if (ACE_IS_TIGON_I(ap)) {
2763 writel(addr >> 32, &desc->addr.addrhi);
2764 writel(addr & 0xffffffff, &desc->addr.addrlo);
2765 writel(flagsize, &desc->flagsize);
2766#if ACENIC_DO_VLAN
2767 writel(vlan_tag, &desc->vlanres);
2768#endif
2769 } else {
2770 desc->addr.addrhi = addr >> 32;
2771 desc->addr.addrlo = addr;
2772 desc->flagsize = flagsize;
2773#if ACENIC_DO_VLAN
2774 desc->vlanres = vlan_tag;
2775#endif
2776 }
2777}
2778
2779
2780static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
2781{
2782 struct ace_private *ap = dev->priv;
2783 struct ace_regs *regs = ap->regs;
2784 struct tx_desc *desc;
2785 u32 idx, flagsize;
2786
2787
2788
2789
2790 if (early_stop_netif_stop_queue(dev))
2791 return 1;
2792
2793restart:
2794 idx = ap->tx_prd;
2795
2796 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2797 goto overflow;
2798
2799#if MAX_SKB_FRAGS
2800 if (!skb_shinfo(skb)->nr_frags)
2801#endif
2802 {
2803 dma_addr_t mapping;
2804 u32 vlan_tag = 0;
2805
2806 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2807 flagsize = (skb->len << 16) | (BD_FLG_END);
2808 if (skb->ip_summed == CHECKSUM_HW)
2809 flagsize |= BD_FLG_TCP_UDP_SUM;
2810#if ACENIC_DO_VLAN
2811 if (vlan_tx_tag_present(skb)) {
2812 flagsize |= BD_FLG_VLAN_TAG;
2813 vlan_tag = vlan_tx_tag_get(skb);
2814 }
2815#endif
2816 desc = ap->tx_ring + idx;
2817 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2818
2819
2820 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2821 flagsize |= BD_FLG_COAL_NOW;
2822
2823 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2824 }
2825#if MAX_SKB_FRAGS
2826 else {
2827 dma_addr_t mapping;
2828 u32 vlan_tag = 0;
2829 int i, len = 0;
2830
2831 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2832 flagsize = ((skb->len - skb->data_len) << 16);
2833 if (skb->ip_summed == CHECKSUM_HW)
2834 flagsize |= BD_FLG_TCP_UDP_SUM;
2835#if ACENIC_DO_VLAN
2836 if (vlan_tx_tag_present(skb)) {
2837 flagsize |= BD_FLG_VLAN_TAG;
2838 vlan_tag = vlan_tx_tag_get(skb);
2839 }
2840#endif
2841
2842 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2843
2844 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2845
2846 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2847 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2848 struct tx_ring_info *info;
2849
2850 len += frag->size;
2851 info = ap->skb->tx_skbuff + idx;
2852 desc = ap->tx_ring + idx;
2853
2854 mapping = pci_map_page(ap->pdev, frag->page,
2855 frag->page_offset, frag->size,
2856 PCI_DMA_TODEVICE);
2857
2858 flagsize = (frag->size << 16);
2859 if (skb->ip_summed == CHECKSUM_HW)
2860 flagsize |= BD_FLG_TCP_UDP_SUM;
2861 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2862
2863 if (i == skb_shinfo(skb)->nr_frags - 1) {
2864 flagsize |= BD_FLG_END;
2865 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2866 flagsize |= BD_FLG_COAL_NOW;
2867
2868
2869
2870
2871
2872 info->skb = skb;
2873 } else {
2874 info->skb = NULL;
2875 }
2876 pci_unmap_addr_set(info, mapping, mapping);
2877 pci_unmap_len_set(info, maplen, frag->size);
2878 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2879 }
2880 }
2881#endif
2882
2883 wmb();
2884 ap->tx_prd = idx;
2885 ace_set_txprd(regs, ap, idx);
2886
2887 if (flagsize & BD_FLG_COAL_NOW) {
2888 netif_stop_queue(dev);
2889
2890
2891
2892
2893
2894
2895
2896 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2897 netif_wake_queue(dev);
2898 }
2899
2900 dev->trans_start = jiffies;
2901 return 0;
2902
2903overflow:
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920 barrier();
2921 goto restart;
2922}
2923
2924
2925static int ace_change_mtu(struct net_device *dev, int new_mtu)
2926{
2927 struct ace_private *ap = dev->priv;
2928 struct ace_regs *regs = ap->regs;
2929
2930 if (new_mtu > ACE_JUMBO_MTU)
2931 return -EINVAL;
2932
2933 writel(new_mtu + ETH_HLEN + 4, ®s->IfMtu);
2934 dev->mtu = new_mtu;
2935
2936 if (new_mtu > ACE_STD_MTU) {
2937 if (!(ap->jumbo)) {
2938 printk(KERN_INFO "%s: Enabling Jumbo frame "
2939 "support\n", dev->name);
2940 ap->jumbo = 1;
2941 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2942 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2943 ace_set_rxtx_parms(dev, 1);
2944 }
2945 } else {
2946 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2947 ace_sync_irq(dev->irq);
2948 ace_set_rxtx_parms(dev, 0);
2949 if (ap->jumbo) {
2950 struct cmd cmd;
2951
2952 cmd.evt = C_RESET_JUMBO_RNG;
2953 cmd.code = 0;
2954 cmd.idx = 0;
2955 ace_issue_cmd(regs, &cmd);
2956 }
2957 }
2958
2959 return 0;
2960}
2961
2962
2963static int ace_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2964{
2965 struct ace_private *ap = dev->priv;
2966 struct ace_regs *regs = ap->regs;
2967#ifdef SIOCETHTOOL
2968 struct ethtool_cmd ecmd;
2969 u32 link, speed;
2970
2971 if (cmd != SIOCETHTOOL)
2972 return -EOPNOTSUPP;
2973 if (copy_from_user(&ecmd, ifr->ifr_data, sizeof(ecmd)))
2974 return -EFAULT;
2975 switch (ecmd.cmd) {
2976 case ETHTOOL_GSET:
2977 ecmd.supported =
2978 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2979 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2980 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2981 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2982
2983 ecmd.port = PORT_FIBRE;
2984 ecmd.transceiver = XCVR_INTERNAL;
2985 ecmd.phy_address = 0;
2986
2987 link = readl(®s->GigLnkState);
2988 if (link & LNK_1000MB)
2989 ecmd.speed = SPEED_1000;
2990 else {
2991 link = readl(®s->FastLnkState);
2992 if (link & LNK_100MB)
2993 ecmd.speed = SPEED_100;
2994 else if (link & LNK_100MB)
2995 ecmd.speed = SPEED_10;
2996 else
2997 ecmd.speed = 0;
2998 }
2999 if (link & LNK_FULL_DUPLEX)
3000 ecmd.duplex = DUPLEX_FULL;
3001 else
3002 ecmd.duplex = DUPLEX_HALF;
3003
3004 if (link & LNK_NEGOTIATE)
3005 ecmd.autoneg = AUTONEG_ENABLE;
3006 else
3007 ecmd.autoneg = AUTONEG_DISABLE;
3008
3009#if 0
3010
3011
3012
3013 ecmd.trace = readl(®s->TuneTrace);
3014
3015 ecmd.txcoal = readl(®s->TuneTxCoalTicks);
3016 ecmd.rxcoal = readl(®s->TuneRxCoalTicks);
3017#endif
3018 ecmd.maxtxpkt = readl(®s->TuneMaxTxDesc);
3019 ecmd.maxrxpkt = readl(®s->TuneMaxRxDesc);
3020
3021 if(copy_to_user(ifr->ifr_data, &ecmd, sizeof(ecmd)))
3022 return -EFAULT;
3023 return 0;
3024
3025 case ETHTOOL_SSET:
3026 if(!capable(CAP_NET_ADMIN))
3027 return -EPERM;
3028
3029 link = readl(®s->GigLnkState);
3030 if (link & LNK_1000MB)
3031 speed = SPEED_1000;
3032 else {
3033 link = readl(®s->FastLnkState);
3034 if (link & LNK_100MB)
3035 speed = SPEED_100;
3036 else if (link & LNK_100MB)
3037 speed = SPEED_10;
3038 else
3039 speed = SPEED_100;
3040 }
3041
3042 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
3043 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
3044 if (!ACE_IS_TIGON_I(ap))
3045 link |= LNK_TX_FLOW_CTL_Y;
3046 if (ecmd.autoneg == AUTONEG_ENABLE)
3047 link |= LNK_NEGOTIATE;
3048 if (ecmd.speed != speed) {
3049 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
3050 switch (speed) {
3051 case SPEED_1000:
3052 link |= LNK_1000MB;
3053 break;
3054 case SPEED_100:
3055 link |= LNK_100MB;
3056 break;
3057 case SPEED_10:
3058 link |= LNK_10MB;
3059 break;
3060 }
3061 }
3062 if (ecmd.duplex == DUPLEX_FULL)
3063 link |= LNK_FULL_DUPLEX;
3064
3065 if (link != ap->link) {
3066 struct cmd cmd;
3067 printk(KERN_INFO "%s: Renegotiating link state\n",
3068 dev->name);
3069
3070 ap->link = link;
3071 writel(link, ®s->TuneLink);
3072 if (!ACE_IS_TIGON_I(ap))
3073 writel(link, ®s->TuneFastLink);
3074 wmb();
3075
3076 cmd.evt = C_LNK_NEGOTIATION;
3077 cmd.code = 0;
3078 cmd.idx = 0;
3079 ace_issue_cmd(regs, &cmd);
3080 }
3081 return 0;
3082
3083 case ETHTOOL_GDRVINFO: {
3084 struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO};
3085 strncpy(info.driver, "acenic", sizeof(info.driver) - 1);
3086 sprintf(info.fw_version, "%i.%i.%i",
3087 tigonFwReleaseMajor, tigonFwReleaseMinor,
3088 tigonFwReleaseFix);
3089 strncpy(info.version, version, sizeof(info.version) - 1);
3090 if (ap && ap->pdev)
3091 strcpy(info.bus_info, ap->pdev->slot_name);
3092 if (copy_to_user(ifr->ifr_data, &info, sizeof(info)))
3093 return -EFAULT;
3094 return 0;
3095 }
3096 default:
3097 break;
3098 }
3099
3100#endif
3101
3102 return -EOPNOTSUPP;
3103}
3104
3105
3106
3107
3108
3109static int ace_set_mac_addr(struct net_device *dev, void *p)
3110{
3111 struct sockaddr *addr=p;
3112 struct ace_regs *regs;
3113 u8 *da;
3114 struct cmd cmd;
3115
3116 if(netif_running(dev))
3117 return -EBUSY;
3118
3119 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
3120
3121 da = (u8 *)dev->dev_addr;
3122
3123 regs = ((struct ace_private *)dev->priv)->regs;
3124 writel(da[0] << 8 | da[1], ®s->MacAddrHi);
3125 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
3126 ®s->MacAddrLo);
3127
3128 cmd.evt = C_SET_MAC_ADDR;
3129 cmd.code = 0;
3130 cmd.idx = 0;
3131 ace_issue_cmd(regs, &cmd);
3132
3133 return 0;
3134}
3135
3136
3137static void ace_set_multicast_list(struct net_device *dev)
3138{
3139 struct ace_private *ap = dev->priv;
3140 struct ace_regs *regs = ap->regs;
3141 struct cmd cmd;
3142
3143 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
3144 cmd.evt = C_SET_MULTICAST_MODE;
3145 cmd.code = C_C_MCAST_ENABLE;
3146 cmd.idx = 0;
3147 ace_issue_cmd(regs, &cmd);
3148 ap->mcast_all = 1;
3149 } else if (ap->mcast_all) {
3150 cmd.evt = C_SET_MULTICAST_MODE;
3151 cmd.code = C_C_MCAST_DISABLE;
3152 cmd.idx = 0;
3153 ace_issue_cmd(regs, &cmd);
3154 ap->mcast_all = 0;
3155 }
3156
3157 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
3158 cmd.evt = C_SET_PROMISC_MODE;
3159 cmd.code = C_C_PROMISC_ENABLE;
3160 cmd.idx = 0;
3161 ace_issue_cmd(regs, &cmd);
3162 ap->promisc = 1;
3163 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
3164 cmd.evt = C_SET_PROMISC_MODE;
3165 cmd.code = C_C_PROMISC_DISABLE;
3166 cmd.idx = 0;
3167 ace_issue_cmd(regs, &cmd);
3168 ap->promisc = 0;
3169 }
3170
3171
3172
3173
3174
3175
3176
3177 if ((dev->mc_count) && !(ap->mcast_all)) {
3178 cmd.evt = C_SET_MULTICAST_MODE;
3179 cmd.code = C_C_MCAST_ENABLE;
3180 cmd.idx = 0;
3181 ace_issue_cmd(regs, &cmd);
3182 }else if (!ap->mcast_all) {
3183 cmd.evt = C_SET_MULTICAST_MODE;
3184 cmd.code = C_C_MCAST_DISABLE;
3185 cmd.idx = 0;
3186 ace_issue_cmd(regs, &cmd);
3187 }
3188}
3189
3190
3191static struct net_device_stats *ace_get_stats(struct net_device *dev)
3192{
3193 struct ace_private *ap = dev->priv;
3194 struct ace_mac_stats *mac_stats =
3195 (struct ace_mac_stats *)ap->regs->Stats;
3196
3197 ap->stats.rx_missed_errors = readl(&mac_stats->drop_space);
3198 ap->stats.multicast = readl(&mac_stats->kept_mc);
3199 ap->stats.collisions = readl(&mac_stats->coll);
3200
3201 return &ap->stats;
3202}
3203
3204
3205static void __init ace_copy(struct ace_regs *regs, void *src,
3206 u32 dest, int size)
3207{
3208 unsigned long tdest;
3209 u32 *wsrc;
3210 short tsize, i;
3211
3212 if (size <= 0)
3213 return;
3214
3215 while (size > 0) {
3216 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
3217 min_t(u32, size, ACE_WINDOW_SIZE));
3218 tdest = (unsigned long)®s->Window +
3219 (dest & (ACE_WINDOW_SIZE - 1));
3220 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
3221
3222
3223
3224
3225 wsrc = src;
3226 for (i = 0; i < (tsize / 4); i++) {
3227 writel(wsrc[i], tdest + i*4);
3228 }
3229 dest += tsize;
3230 src += tsize;
3231 size -= tsize;
3232 }
3233
3234 return;
3235}
3236
3237
3238static void __init ace_clear(struct ace_regs *regs, u32 dest, int size)
3239{
3240 unsigned long tdest;
3241 short tsize = 0, i;
3242
3243 if (size <= 0)
3244 return;
3245
3246 while (size > 0) {
3247 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
3248 min_t(u32, size, ACE_WINDOW_SIZE));
3249 tdest = (unsigned long)®s->Window +
3250 (dest & (ACE_WINDOW_SIZE - 1));
3251 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
3252
3253 for (i = 0; i < (tsize / 4); i++) {
3254 writel(0, tdest + i*4);
3255 }
3256
3257 dest += tsize;
3258 size -= tsize;
3259 }
3260
3261 return;
3262}
3263
3264
3265
3266
3267
3268
3269
3270
3271int __init ace_load_firmware(struct net_device *dev)
3272{
3273 struct ace_private *ap;
3274 struct ace_regs *regs;
3275
3276 ap = dev->priv;
3277 regs = ap->regs;
3278
3279 if (!(readl(®s->CpuCtrl) & CPU_HALTED)) {
3280 printk(KERN_ERR "%s: trying to download firmware while the "
3281 "CPU is running!\n", dev->name);
3282 return -EFAULT;
3283 }
3284
3285
3286
3287
3288
3289 ace_clear(regs, 0x2000, 0x80000-0x2000);
3290 if (ACE_IS_TIGON_I(ap)) {
3291 ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
3292 ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
3293 ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
3294 tigonFwRodataLen);
3295 ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
3296 ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
3297 }else if (ap->version == 2) {
3298 ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
3299 ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
3300 ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
3301 ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
3302 tigon2FwRodataLen);
3303 ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
3304 }
3305
3306 return 0;
3307}
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325static void __init eeprom_start(struct ace_regs *regs)
3326{
3327 u32 local;
3328
3329 readl(®s->LocalCtrl);
3330 udelay(ACE_SHORT_DELAY);
3331 local = readl(®s->LocalCtrl);
3332 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
3333 writel(local, ®s->LocalCtrl);
3334 readl(®s->LocalCtrl);
3335 mb();
3336 udelay(ACE_SHORT_DELAY);
3337 local |= EEPROM_CLK_OUT;
3338 writel(local, ®s->LocalCtrl);
3339 readl(®s->LocalCtrl);
3340 mb();
3341 udelay(ACE_SHORT_DELAY);
3342 local &= ~EEPROM_DATA_OUT;
3343 writel(local, ®s->LocalCtrl);
3344 readl(®s->LocalCtrl);
3345 mb();
3346 udelay(ACE_SHORT_DELAY);
3347 local &= ~EEPROM_CLK_OUT;
3348 writel(local, ®s->LocalCtrl);
3349 readl(®s->LocalCtrl);
3350 mb();
3351}
3352
3353
3354static void __init eeprom_prep(struct ace_regs *regs, u8 magic)
3355{
3356 short i;
3357 u32 local;
3358
3359 udelay(ACE_SHORT_DELAY);
3360 local = readl(®s->LocalCtrl);
3361 local &= ~EEPROM_DATA_OUT;
3362 local |= EEPROM_WRITE_ENABLE;
3363 writel(local, ®s->LocalCtrl);
3364 readl(®s->LocalCtrl);
3365 mb();
3366
3367 for (i = 0; i < 8; i++, magic <<= 1) {
3368 udelay(ACE_SHORT_DELAY);
3369 if (magic & 0x80)
3370 local |= EEPROM_DATA_OUT;
3371 else
3372 local &= ~EEPROM_DATA_OUT;
3373 writel(local, ®s->LocalCtrl);
3374 readl(®s->LocalCtrl);
3375 mb();
3376
3377 udelay(ACE_SHORT_DELAY);
3378 local |= EEPROM_CLK_OUT;
3379 writel(local, ®s->LocalCtrl);
3380 readl(®s->LocalCtrl);
3381 mb();
3382 udelay(ACE_SHORT_DELAY);
3383 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3384 writel(local, ®s->LocalCtrl);
3385 readl(®s->LocalCtrl);
3386 mb();
3387 }
3388}
3389
3390
3391static int __init eeprom_check_ack(struct ace_regs *regs)
3392{
3393 int state;
3394 u32 local;
3395
3396 local = readl(®s->LocalCtrl);
3397 local &= ~EEPROM_WRITE_ENABLE;
3398 writel(local, ®s->LocalCtrl);
3399 readl(®s->LocalCtrl);
3400 mb();
3401 udelay(ACE_LONG_DELAY);
3402 local |= EEPROM_CLK_OUT;
3403 writel(local, ®s->LocalCtrl);
3404 readl(®s->LocalCtrl);
3405 mb();
3406 udelay(ACE_SHORT_DELAY);
3407
3408 state = (readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0;
3409 udelay(ACE_SHORT_DELAY);
3410 mb();
3411 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl);
3412 readl(®s->LocalCtrl);
3413 mb();
3414
3415 return state;
3416}
3417
3418
3419static void __init eeprom_stop(struct ace_regs *regs)
3420{
3421 u32 local;
3422
3423 udelay(ACE_SHORT_DELAY);
3424 local = readl(®s->LocalCtrl);
3425 local |= EEPROM_WRITE_ENABLE;
3426 writel(local, ®s->LocalCtrl);
3427 readl(®s->LocalCtrl);
3428 mb();
3429 udelay(ACE_SHORT_DELAY);
3430 local &= ~EEPROM_DATA_OUT;
3431 writel(local, ®s->LocalCtrl);
3432 readl(®s->LocalCtrl);
3433 mb();
3434 udelay(ACE_SHORT_DELAY);
3435 local |= EEPROM_CLK_OUT;
3436 writel(local, ®s->LocalCtrl);
3437 readl(®s->LocalCtrl);
3438 mb();
3439 udelay(ACE_SHORT_DELAY);
3440 local |= EEPROM_DATA_OUT;
3441 writel(local, ®s->LocalCtrl);
3442 readl(®s->LocalCtrl);
3443 mb();
3444 udelay(ACE_LONG_DELAY);
3445 local &= ~EEPROM_CLK_OUT;
3446 writel(local, ®s->LocalCtrl);
3447 mb();
3448}
3449
3450
3451
3452
3453
3454static int __init read_eeprom_byte(struct net_device *dev,
3455 unsigned long offset)
3456{
3457 struct ace_regs *regs;
3458 unsigned long flags;
3459 u32 local;
3460 int result = 0;
3461 short i;
3462
3463 if (!dev) {
3464 printk(KERN_ERR "No device!\n");
3465 result = -ENODEV;
3466 goto eeprom_read_error;
3467 }
3468
3469 regs = ((struct ace_private *)dev->priv)->regs;
3470
3471
3472
3473
3474
3475 local_irq_save(flags);
3476
3477 eeprom_start(regs);
3478
3479 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3480 if (eeprom_check_ack(regs)) {
3481 local_irq_restore(flags);
3482 printk(KERN_ERR "%s: Unable to sync eeprom\n", dev->name);
3483 result = -EIO;
3484 goto eeprom_read_error;
3485 }
3486
3487 eeprom_prep(regs, (offset >> 8) & 0xff);
3488 if (eeprom_check_ack(regs)) {
3489 local_irq_restore(flags);
3490 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3491 dev->name);
3492 result = -EIO;
3493 goto eeprom_read_error;
3494 }
3495
3496 eeprom_prep(regs, offset & 0xff);
3497 if (eeprom_check_ack(regs)) {
3498 local_irq_restore(flags);
3499 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3500 dev->name);
3501 result = -EIO;
3502 goto eeprom_read_error;
3503 }
3504
3505 eeprom_start(regs);
3506 eeprom_prep(regs, EEPROM_READ_SELECT);
3507 if (eeprom_check_ack(regs)) {
3508 local_irq_restore(flags);
3509 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3510 dev->name);
3511 result = -EIO;
3512 goto eeprom_read_error;
3513 }
3514
3515 for (i = 0; i < 8; i++) {
3516 local = readl(®s->LocalCtrl);
3517 local &= ~EEPROM_WRITE_ENABLE;
3518 writel(local, ®s->LocalCtrl);
3519 readl(®s->LocalCtrl);
3520 udelay(ACE_LONG_DELAY);
3521 mb();
3522 local |= EEPROM_CLK_OUT;
3523 writel(local, ®s->LocalCtrl);
3524 readl(®s->LocalCtrl);
3525 mb();
3526 udelay(ACE_SHORT_DELAY);
3527
3528 result = (result << 1) |
3529 ((readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0);
3530 udelay(ACE_SHORT_DELAY);
3531 mb();
3532 local = readl(®s->LocalCtrl);
3533 local &= ~EEPROM_CLK_OUT;
3534 writel(local, ®s->LocalCtrl);
3535 readl(®s->LocalCtrl);
3536 udelay(ACE_SHORT_DELAY);
3537 mb();
3538 if (i == 7) {
3539 local |= EEPROM_WRITE_ENABLE;
3540 writel(local, ®s->LocalCtrl);
3541 readl(®s->LocalCtrl);
3542 mb();
3543 udelay(ACE_SHORT_DELAY);
3544 }
3545 }
3546
3547 local |= EEPROM_DATA_OUT;
3548 writel(local, ®s->LocalCtrl);
3549 readl(®s->LocalCtrl);
3550 mb();
3551 udelay(ACE_SHORT_DELAY);
3552 writel(readl(®s->LocalCtrl) | EEPROM_CLK_OUT, ®s->LocalCtrl);
3553 readl(®s->LocalCtrl);
3554 udelay(ACE_LONG_DELAY);
3555 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl);
3556 readl(®s->LocalCtrl);
3557 mb();
3558 udelay(ACE_SHORT_DELAY);
3559 eeprom_stop(regs);
3560
3561 local_irq_restore(flags);
3562 out:
3563 return result;
3564
3565 eeprom_read_error:
3566 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3567 dev->name, offset);
3568 goto out;
3569}
3570
3571
3572
3573
3574
3575
3576
3577