1/* 2 * 3 * Alchemy Semi Au1000 ethernet driver include file 4 * 5 * Author: Pete Popov <ppopov@mvista.com> 6 * 7 * Copyright 2001 MontaVista Software Inc. 8 * 9 * ######################################################################## 10 * 11 * This program is free software; you can distribute it and/or modify it 12 * under the terms of the GNU General Public License (Version 2) as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18 * for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, write to the Free Software Foundation, Inc., 22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 23 * 24 * ######################################################################## 25 * 26 * 27 */ 28 29 30#define NUM_INTERFACES 2 31#define MAC_IOSIZE 0x10000 32#define NUM_RX_DMA 4 /* Au1000 has 4 rx hardware descriptors */ 33#define NUM_TX_DMA 4 /* Au1000 has 4 tx hardware descriptors */ 34 35#define NUM_RX_BUFFS 4 36#define NUM_TX_BUFFS 4 37#define MAX_BUF_SIZE 2048 38 39#define ETH_TX_TIMEOUT HZ/4 40#define MAC_MIN_PKT_SIZE 64 41 42#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1500) 43#define PHY_ADDRESS 0 44#define PHY_CONTROL_DEFAULT 0x3000 45#define PHY_CONTROL_REG_ADDR 0 46#endif 47 48#define MULTICAST_FILTER_LIMIT 64 49 50/* FIXME 51 * The PHY defines should be in a separate file. 52 */ 53 54/* MII register offsets */ 55#define MII_CONTROL 0x0000 56#define MII_STATUS 0x0001 57#define MII_PHY_ID0 0x0002 58#define MII_PHY_ID1 0x0003 59#define MII_ANADV 0x0004 60#define MII_ANLPAR 0x0005 61#define MII_AEXP 0x0006 62#define MII_ANEXT 0x0007 63#define MII_LSI_CONFIG 0x0011 64#define MII_LSI_STAT 0x0012 65#define MII_AUX_CNTRL 0x0018 66 67/* mii registers specific to AMD 79C901 */ 68#define MII_STATUS_SUMMARY = 0x0018 69 70/* MII Control register bit definitions. */ 71#define MII_CNTL_FDX 0x0100 72#define MII_CNTL_RST_AUTO 0x0200 73#define MII_CNTL_ISOLATE 0x0400 74#define MII_CNTL_PWRDWN 0x0800 75#define MII_CNTL_AUTO 0x1000 76#define MII_CNTL_F100 0x2000 77#define MII_CNTL_LPBK 0x4000 78#define MII_CNTL_RESET 0x8000 79 80/* MII Status register bit */ 81#define MII_STAT_EXT 0x0001 82#define MII_STAT_JAB 0x0002 83#define MII_STAT_LINK 0x0004 84#define MII_STAT_CAN_AUTO 0x0008 85#define MII_STAT_FAULT 0x0010 86#define MII_STAT_AUTO_DONE 0x0020 87#define MII_STAT_CAN_T 0x0800 88#define MII_STAT_CAN_T_FDX 0x1000 89#define MII_STAT_CAN_TX 0x2000 90#define MII_STAT_CAN_TX_FDX 0x4000 91#define MII_STAT_CAN_T4 0x8000 92 93 94#define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */ 95#define MII_ID1_MODEL 0x03F0 /* model number */ 96#define MII_ID1_REV 0x000F /* model number */ 97 98/* MII NWAY Register Bits ... 99 valid for the ANAR (Auto-Negotiation Advertisement) and 100 ANLPAR (Auto-Negotiation Link Partner) registers */ 101#define MII_NWAY_NODE_SEL 0x001f 102#define MII_NWAY_CSMA_CD 0x0001 103#define MII_NWAY_T 0x0020 104#define MII_NWAY_T_FDX 0x0040 105#define MII_NWAY_TX 0x0080 106#define MII_NWAY_TX_FDX 0x0100 107#define MII_NWAY_T4 0x0200 108#define MII_NWAY_PAUSE 0x0400 109#define MII_NWAY_RF 0x2000 /* Remote Fault */ 110#define MII_NWAY_ACK 0x4000 /* Remote Acknowledge */ 111#define MII_NWAY_NP 0x8000 /* Next Page (Enable) */ 112 113/* mii stsout register bits */ 114#define MII_STSOUT_LINK_FAIL 0x4000 115#define MII_STSOUT_SPD 0x0080 116#define MII_STSOUT_DPLX 0x0040 117 118/* mii stsics register bits */ 119#define MII_STSICS_SPD 0x8000 120#define MII_STSICS_DPLX 0x4000 121#define MII_STSICS_LINKSTS 0x0001 122 123/* mii stssum register bits */ 124#define MII_STSSUM_LINK 0x0008 125#define MII_STSSUM_DPLX 0x0004 126#define MII_STSSUM_AUTO 0x0002 127#define MII_STSSUM_SPD 0x0001 128 129/* lsi status register */ 130 131#define MII_LSI_STAT_FDX 0x0008 132#define MII_LSI_STAT_SPD 0x0010 133 134/* Auxilliary Control/Status Register */ 135#define MII_AUX_FDX 0x0001 136#define MII_AUX_100 0x0002 137#define MII_AUX_F100 0x0004 138#define MII_AUX_ANEG 0x0008 139 140typedef struct mii_phy { 141 struct mii_phy * next; 142 struct mii_chip_info * chip_info; 143 int phy_addr; 144 u16 status; 145} mii_phy_t; 146 147struct phy_ops { 148 int (*phy_init) (struct net_device *, int); 149 int (*phy_reset) (struct net_device *, int); 150 int (*phy_status) (struct net_device *, int, u16 *, u16 *); 151}; 152 153/* 154 * Data Buffer Descriptor. Data buffers must be aligned on 32 byte 155 * boundary for both, receive and transmit. 156 */ 157typedef struct db_dest { 158 struct db_dest *pnext; 159 volatile u32 *vaddr; 160 dma_addr_t dma_addr; 161} db_dest_t; 162 163/* 164 * The transmit and receive descriptors are memory 165 * mapped registers. 166 */ 167typedef struct tx_dma { 168 u32 status; 169 u32 buff_stat; 170 u32 len; 171 u32 pad; 172} tx_dma_t; 173 174typedef struct rx_dma { 175 u32 status; 176 u32 buff_stat; 177 u32 pad[2]; 178} rx_dma_t; 179 180 181/* 182 * MAC control registers, memory mapped. 183 */ 184typedef struct mac_reg { 185 u32 control; 186 u32 mac_addr_high; 187 u32 mac_addr_low; 188 u32 multi_hash_high; 189 u32 multi_hash_low; 190 u32 mii_control; 191 u32 mii_data; 192 u32 flow_control; 193 u32 vlan1_tag; 194 u32 vlan2_tag; 195} mac_reg_t; 196 197 198struct au1000_private { 199 200 db_dest_t *pDBfree; 201 db_dest_t db[NUM_RX_BUFFS+NUM_TX_BUFFS]; 202 volatile rx_dma_t *rx_dma_ring[NUM_RX_DMA]; 203 volatile tx_dma_t *tx_dma_ring[NUM_TX_DMA]; 204 db_dest_t *rx_db_inuse[NUM_RX_DMA]; 205 db_dest_t *tx_db_inuse[NUM_TX_DMA]; 206 u32 rx_head; 207 u32 tx_head; 208 u32 tx_tail; 209 u32 tx_full; 210 211 mii_phy_t *mii; 212 struct phy_ops *phy_ops; 213 214 /* These variables are just for quick access to certain regs addresses. */ 215 volatile mac_reg_t *mac; /* mac registers */ 216 volatile u32 *enable; /* address of MAC Enable Register */ 217 218 u32 vaddr; /* virtual address of rx/tx buffers */ 219 dma_addr_t dma_addr; /* dma address of rx/tx buffers */ 220 221 u8 *hash_table; 222 u32 hash_mode; 223 u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */ 224 u32 phy_addr; /* PHY address */ 225 u32 options; /* User-settable misc. driver options. */ 226 u32 drv_flags; 227 struct net_device_stats stats; 228 struct timer_list timer; 229 spinlock_t lock; /* Serialise access to device */ 230}; 231