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29#ifndef __mips__
30#error This driver only works with MIPS architectures!
31#endif
32
33
34#include <linux/module.h>
35#include <linux/kernel.h>
36#include <linux/sched.h>
37#include <linux/string.h>
38#include <linux/timer.h>
39#include <linux/errno.h>
40#include <linux/in.h>
41#include <linux/ioport.h>
42#include <linux/slab.h>
43#include <linux/interrupt.h>
44#include <linux/pci.h>
45#include <linux/init.h>
46#include <linux/netdevice.h>
47#include <linux/etherdevice.h>
48#include <linux/skbuff.h>
49#include <linux/delay.h>
50#include <linux/crc32.h>
51#include <asm/mipsregs.h>
52#include <asm/irq.h>
53#include <asm/bitops.h>
54#include <asm/io.h>
55
56#include <asm/au1000.h>
57#include "au1000_eth.h"
58
59#ifdef AU1000_ETH_DEBUG
60static int au1000_debug = 10;
61#else
62static int au1000_debug = 3;
63#endif
64
65
66static void *dma_alloc(size_t, dma_addr_t *);
67static void dma_free(void *, size_t);
68static void hard_stop(struct net_device *);
69static void enable_rx_tx(struct net_device *dev);
70static int __init au1000_probe1(struct net_device *, long, int, int);
71static int au1000_init(struct net_device *);
72static int au1000_open(struct net_device *);
73static int au1000_close(struct net_device *);
74static int au1000_tx(struct sk_buff *, struct net_device *);
75static int au1000_rx(struct net_device *);
76static void au1000_interrupt(int, void *, struct pt_regs *);
77static void au1000_tx_timeout(struct net_device *);
78static int au1000_set_config(struct net_device *dev, struct ifmap *map);
79static void set_rx_mode(struct net_device *);
80static struct net_device_stats *au1000_get_stats(struct net_device *);
81static inline void update_tx_stats(struct net_device *, u32, u32);
82static inline void update_rx_stats(struct net_device *, u32);
83static void au1000_timer(unsigned long);
84static int au1000_ioctl(struct net_device *, struct ifreq *, int);
85static int mdio_read(struct net_device *, int, int);
86static void mdio_write(struct net_device *, int, int, u16);
87static void dump_mii(struct net_device *dev, int phy_id);
88
89
90extern void ack_rise_edge_irq(unsigned int);
91extern int get_ethernet_addr(char *ethernet_addr);
92extern inline void str2eaddr(unsigned char *ea, unsigned char *str);
93extern inline unsigned char str2hexnum(unsigned char c);
94extern char * __init prom_getcmdline(void);
95
96
97
98
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113
114
115static struct {
116 unsigned int port;
117 int irq;
118} au1000_iflist[NUM_INTERFACES] = {
119 {AU1000_ETH0_BASE, AU1000_ETH0_IRQ},
120 {AU1000_ETH1_BASE, AU1000_ETH1_IRQ}
121 },
122 au1500_iflist[NUM_INTERFACES] = {
123 {AU1500_ETH0_BASE, AU1000_ETH0_IRQ},
124 {AU1500_ETH1_BASE, AU1000_ETH1_IRQ}
125 };
126
127
128static char version[] __devinitdata =
129 "au1000eth.c:1.0 ppopov@mvista.com\n";
130
131
132
133
134
135static unsigned char au1000_mac_addr[6] __devinitdata = {
136 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
137};
138
139#define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0))
140#define RUN_AT(x) (jiffies + (x))
141
142
143#define cpu_to_dma32 cpu_to_be32
144#define dma32_to_cpu be32_to_cpu
145
146
147
148
149
150
151
152static char *phy_link[] =
153 {"unknown",
154 "10Base2", "10BaseT",
155 "AUI",
156 "100BaseT", "100BaseTX", "100BaseFX"
157 };
158
159int bcm_5201_init(struct net_device *dev, int phy_addr)
160{
161 s16 data;
162
163
164
165 data = mdio_read(dev, phy_addr, MII_CONTROL);
166 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
167
168
169
170 data = mdio_read(dev, phy_addr, MII_ANADV);
171 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
172 mdio_write(dev, phy_addr, MII_ANADV, data);
173
174
175 data = mdio_read(dev, phy_addr, MII_CONTROL);
176 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
177 mdio_write(dev, phy_addr, MII_CONTROL, data);
178
179 if (au1000_debug > 4) dump_mii(dev, phy_addr);
180 return 0;
181}
182
183int bcm_5201_reset(struct net_device *dev, int phy_addr)
184{
185 s16 mii_control, timeout;
186
187
188 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
189 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
190 mdelay(1);
191 for (timeout = 100; timeout > 0; --timeout) {
192 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
193 if ((mii_control & MII_CNTL_RESET) == 0)
194 break;
195 mdelay(1);
196 }
197 if (mii_control & MII_CNTL_RESET) {
198 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
199 return -1;
200 }
201 return 0;
202}
203
204int
205bcm_5201_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
206{
207 u16 mii_data;
208 struct au1000_private *aup;
209
210 if (!dev) {
211 printk(KERN_ERR "bcm_5201_status error: NULL dev\n");
212 return -1;
213 }
214 aup = (struct au1000_private *) dev->priv;
215
216 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
217 if (mii_data & MII_STAT_LINK) {
218 *link = 1;
219 mii_data = mdio_read(dev, aup->phy_addr, MII_AUX_CNTRL);
220 if (mii_data & MII_AUX_100) {
221 if (mii_data & MII_AUX_FDX) {
222 *speed = IF_PORT_100BASEFX;
223 dev->if_port = IF_PORT_100BASEFX;
224 }
225 else {
226 *speed = IF_PORT_100BASETX;
227 dev->if_port = IF_PORT_100BASETX;
228 }
229 }
230 else {
231 *speed = IF_PORT_10BASET;
232 dev->if_port = IF_PORT_10BASET;
233 }
234
235 }
236 else {
237 *link = 0;
238 *speed = 0;
239 dev->if_port = IF_PORT_UNKNOWN;
240 }
241 return 0;
242}
243
244int lsi_80227_init(struct net_device *dev, int phy_addr)
245{
246 if (au1000_debug > 4)
247 printk("lsi_80227_init\n");
248
249
250 mdio_write(dev, phy_addr, 0, 0x3200);
251
252
253 mdio_write(dev, phy_addr, 17, 0xffc0);
254
255 if (au1000_debug > 4)
256 dump_mii(dev, phy_addr);
257 return 0;
258}
259
260int lsi_80227_reset(struct net_device *dev, int phy_addr)
261{
262 s16 mii_control, timeout;
263
264 if (au1000_debug > 4) {
265 printk("lsi_80227_reset\n");
266 dump_mii(dev, phy_addr);
267 }
268
269 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
270 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
271 mdelay(1);
272 for (timeout = 100; timeout > 0; --timeout) {
273 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
274 if ((mii_control & MII_CNTL_RESET) == 0)
275 break;
276 mdelay(1);
277 }
278 if (mii_control & MII_CNTL_RESET) {
279 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
280 return -1;
281 }
282 return 0;
283}
284
285int
286lsi_80227_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
287{
288 u16 mii_data;
289 struct au1000_private *aup;
290
291 if (!dev) {
292 printk(KERN_ERR "lsi_80227_status error: NULL dev\n");
293 return -1;
294 }
295 aup = (struct au1000_private *) dev->priv;
296
297 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
298 if (mii_data & MII_STAT_LINK) {
299 *link = 1;
300 mii_data = mdio_read(dev, aup->phy_addr, MII_LSI_STAT);
301 if (mii_data & MII_LSI_STAT_SPD) {
302 if (mii_data & MII_LSI_STAT_FDX) {
303 *speed = IF_PORT_100BASEFX;
304 dev->if_port = IF_PORT_100BASEFX;
305 }
306 else {
307 *speed = IF_PORT_100BASETX;
308 dev->if_port = IF_PORT_100BASETX;
309 }
310 }
311 else {
312 *speed = IF_PORT_10BASET;
313 dev->if_port = IF_PORT_10BASET;
314 }
315
316 }
317 else {
318 *link = 0;
319 *speed = 0;
320 dev->if_port = IF_PORT_UNKNOWN;
321 }
322 return 0;
323}
324
325int am79c901_init(struct net_device *dev, int phy_addr)
326{
327 printk("am79c901_init\n");
328 return 0;
329}
330
331int am79c901_reset(struct net_device *dev, int phy_addr)
332{
333 printk("am79c901_reset\n");
334 return 0;
335}
336
337int
338am79c901_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
339{
340 return 0;
341}
342
343struct phy_ops bcm_5201_ops = {
344 bcm_5201_init,
345 bcm_5201_reset,
346 bcm_5201_status,
347};
348
349struct phy_ops am79c901_ops = {
350 am79c901_init,
351 am79c901_reset,
352 am79c901_status,
353};
354
355struct phy_ops lsi_80227_ops = {
356 lsi_80227_init,
357 lsi_80227_reset,
358 lsi_80227_status,
359};
360
361static struct mii_chip_info {
362 const char * name;
363 u16 phy_id0;
364 u16 phy_id1;
365 struct phy_ops *phy_ops;
366} mii_chip_table[] = {
367 {"Broadcom BCM5201 10/100 BaseT PHY", 0x0040, 0x6212, &bcm_5201_ops },
368 {"AMD 79C901 HomePNA PHY", 0x0000, 0x35c8, &am79c901_ops },
369 {"LSI 80227 10/100 BaseT PHY", 0x0016, 0xf840, &lsi_80227_ops },
370 {0,},
371};
372
373static int mdio_read(struct net_device *dev, int phy_id, int reg)
374{
375 struct au1000_private *aup = (struct au1000_private *) dev->priv;
376 u32 timedout = 20;
377 u32 mii_control;
378
379 while (aup->mac->mii_control & MAC_MII_BUSY) {
380 mdelay(1);
381 if (--timedout == 0) {
382 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
383 dev->name);
384 return -1;
385 }
386 }
387
388 mii_control = MAC_SET_MII_SELECT_REG(reg) |
389 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_READ;
390
391 aup->mac->mii_control = mii_control;
392
393 timedout = 20;
394 while (aup->mac->mii_control & MAC_MII_BUSY) {
395 mdelay(1);
396 if (--timedout == 0) {
397 printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
398 dev->name);
399 return -1;
400 }
401 }
402 return (int)aup->mac->mii_data;
403}
404
405static void mdio_write(struct net_device *dev, int phy_id, int reg, u16 value)
406{
407 struct au1000_private *aup = (struct au1000_private *) dev->priv;
408 u32 timedout = 20;
409 u32 mii_control;
410
411 while (aup->mac->mii_control & MAC_MII_BUSY) {
412 mdelay(1);
413 if (--timedout == 0) {
414 printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
415 dev->name);
416 return;
417 }
418 }
419
420 mii_control = MAC_SET_MII_SELECT_REG(reg) |
421 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_WRITE;
422
423 aup->mac->mii_data = value;
424 aup->mac->mii_control = mii_control;
425}
426
427
428static void dump_mii(struct net_device *dev, int phy_id)
429{
430 int i, val;
431
432 for (i = 0; i < 7; i++) {
433 if ((val = mdio_read(dev, phy_id, i)) >= 0)
434 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
435 }
436 for (i = 16; i < 25; i++) {
437 if ((val = mdio_read(dev, phy_id, i)) >= 0)
438 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
439 }
440}
441
442static int __init mii_probe (struct net_device * dev)
443{
444 struct au1000_private *aup = (struct au1000_private *) dev->priv;
445 int phy_addr;
446
447 aup->mii = NULL;
448
449
450 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
451 u16 mii_status;
452 u16 phy_id0, phy_id1;
453 int i;
454
455 mii_status = mdio_read(dev, phy_addr, MII_STATUS);
456 if (mii_status == 0xffff || mii_status == 0x0000)
457
458 continue;
459
460 phy_id0 = mdio_read(dev, phy_addr, MII_PHY_ID0);
461 phy_id1 = mdio_read(dev, phy_addr, MII_PHY_ID1);
462
463
464 for (i = 0; mii_chip_table[i].phy_id1; i++) {
465 if (phy_id0 == mii_chip_table[i].phy_id0 &&
466 phy_id1 == mii_chip_table[i].phy_id1) {
467 struct mii_phy * mii_phy;
468
469 printk(KERN_INFO "%s: %s at phy address %d\n",
470 dev->name, mii_chip_table[i].name,
471 phy_addr);
472 mii_phy = kmalloc(sizeof(struct mii_phy),
473 GFP_KERNEL);
474 if (mii_phy) {
475 mii_phy->chip_info = mii_chip_table+i;
476 mii_phy->phy_addr = phy_addr;
477 mii_phy->next = aup->mii;
478 aup->phy_ops =
479 mii_chip_table[i].phy_ops;
480 aup->mii = mii_phy;
481 aup->phy_ops->phy_init(dev,phy_addr);
482 } else {
483 printk(KERN_ERR "%s: out of memory\n",
484 dev->name);
485 return -1;
486 }
487
488
489 break;
490 }
491 }
492 }
493
494 if (aup->mii == NULL) {
495 printk(KERN_ERR "%s: No MII transceivers found!\n", dev->name);
496 return -1;
497 }
498
499
500 aup->phy_addr = aup->mii->phy_addr;
501 printk(KERN_INFO "%s: Using %s as default\n",
502 dev->name, aup->mii->chip_info->name);
503
504 return 0;
505}
506
507
508
509
510
511
512
513static db_dest_t *GetFreeDB(struct au1000_private *aup)
514{
515 db_dest_t *pDB;
516 pDB = aup->pDBfree;
517
518 if (pDB) {
519 aup->pDBfree = pDB->pnext;
520 }
521
522 return pDB;
523}
524
525void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
526{
527 db_dest_t *pDBfree = aup->pDBfree;
528 if (pDBfree)
529 pDBfree->pnext = pDB;
530 aup->pDBfree = pDB;
531}
532
533
534
535
536
537
538
539static void *dma_alloc(size_t size, dma_addr_t * dma_handle)
540{
541 void *ret;
542 int gfp = GFP_ATOMIC | GFP_DMA;
543
544 ret = (void *) __get_free_pages(gfp, get_order(size));
545
546 if (ret != NULL) {
547 memset(ret, 0, size);
548 *dma_handle = virt_to_bus(ret);
549 ret = (void *)KSEG0ADDR(ret);
550 }
551 return ret;
552}
553
554
555static void dma_free(void *vaddr, size_t size)
556{
557 vaddr = (void *)KSEG0ADDR(vaddr);
558 free_pages((unsigned long) vaddr, get_order(size));
559}
560
561
562static void enable_rx_tx(struct net_device *dev)
563{
564 struct au1000_private *aup = (struct au1000_private *) dev->priv;
565
566 if (au1000_debug > 4)
567 printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
568
569 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
570 au_sync_delay(10);
571}
572
573static void hard_stop(struct net_device *dev)
574{
575 struct au1000_private *aup = (struct au1000_private *) dev->priv;
576
577 if (au1000_debug > 4)
578 printk(KERN_INFO "%s: hard stop\n", dev->name);
579
580 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
581 au_sync_delay(10);
582}
583
584
585static void reset_mac(struct net_device *dev)
586{
587 u32 flags;
588 struct au1000_private *aup = (struct au1000_private *) dev->priv;
589
590 if (au1000_debug > 4)
591 printk(KERN_INFO "%s: reset mac, aup %x\n",
592 dev->name, (unsigned)aup);
593
594 spin_lock_irqsave(&aup->lock, flags);
595 del_timer(&aup->timer);
596 hard_stop(dev);
597 *aup->enable = MAC_EN_CLOCK_ENABLE;
598 au_sync_delay(2);
599 *aup->enable = 0;
600 au_sync_delay(2);
601 aup->tx_full = 0;
602 spin_unlock_irqrestore(&aup->lock, flags);
603}
604
605
606
607
608
609
610
611static void
612setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
613{
614 int i;
615
616 for (i=0; i<NUM_RX_DMA; i++) {
617 aup->rx_dma_ring[i] =
618 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
619 }
620 for (i=0; i<NUM_TX_DMA; i++) {
621 aup->tx_dma_ring[i] =
622 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
623 }
624}
625
626static int __init au1000_init_module(void)
627{
628 int i;
629 int prid;
630 int base_addr, irq;
631
632 prid = read_32bit_cp0_register(CP0_PRID);
633 for (i=0; i<NUM_INTERFACES; i++) {
634 if ( (prid & 0xffff0000) == 0x00030000 ) {
635 base_addr = au1000_iflist[i].port;
636 irq = au1000_iflist[i].irq;
637 } else if ( (prid & 0xffff0000) == 0x01030000 ) {
638 base_addr = au1500_iflist[i].port;
639 irq = au1500_iflist[i].irq;
640 } else {
641 printk(KERN_ERR "au1000 eth: unknown Processor ID\n");
642 return -ENODEV;
643 }
644 if (au1000_probe1(NULL, base_addr, irq, i) != 0) {
645 return -ENODEV;
646 }
647 }
648 return 0;
649}
650
651static int __init
652au1000_probe1(struct net_device *dev, long ioaddr, int irq, int port_num)
653{
654 static unsigned version_printed = 0;
655 struct au1000_private *aup = NULL;
656 int i, retval = 0;
657 db_dest_t *pDB, *pDBfree;
658 char *pmac, *argptr;
659 char ethaddr[6];
660
661 if (!request_region(ioaddr, MAC_IOSIZE, "Au1000 ENET")) {
662 return -ENODEV;
663 }
664
665 if (version_printed++ == 0) printk(version);
666
667 if (!dev) {
668 dev = init_etherdev(0, sizeof(struct au1000_private));
669 }
670 if (!dev) {
671 printk (KERN_ERR "au1000 eth: init_etherdev failed\n");
672 return -ENODEV;
673 }
674
675 printk("%s: Au1xxx ethernet found at 0x%lx, irq %d\n",
676 dev->name, ioaddr, irq);
677
678
679 if (dev->priv == NULL) {
680 aup = (struct au1000_private *)
681 kmalloc(sizeof(*aup), GFP_KERNEL);
682 if (aup == NULL) {
683 retval = -ENOMEM;
684 goto free_region;
685 }
686 dev->priv = aup;
687 }
688
689 aup = dev->priv;
690 memset(aup, 0, sizeof(*aup));
691
692
693
694 aup->vaddr = (u32)dma_alloc(MAX_BUF_SIZE *
695 (NUM_TX_BUFFS+NUM_RX_BUFFS), &aup->dma_addr);
696 if (!aup->vaddr) {
697 retval = -ENOMEM;
698 goto free_region;
699 }
700
701
702 aup->mac = (volatile mac_reg_t *)((unsigned long)ioaddr);
703
704 switch (ioaddr) {
705 case AU1000_ETH0_BASE:
706 case AU1500_ETH0_BASE:
707
708 if (!get_ethernet_addr(ethaddr)) {
709 memcpy(au1000_mac_addr, ethaddr, sizeof(dev->dev_addr));
710 } else {
711
712 argptr = prom_getcmdline();
713 if ((pmac = strstr(argptr, "ethaddr=")) == NULL) {
714 printk(KERN_INFO "%s: No mac address found\n",
715 dev->name);
716
717 } else {
718 str2eaddr(ethaddr, pmac + strlen("ethaddr="));
719 memcpy(au1000_mac_addr, ethaddr,
720 sizeof(dev->dev_addr));
721 }
722 }
723 if (ioaddr == AU1000_ETH0_BASE)
724 aup->enable = (volatile u32 *)
725 ((unsigned long)AU1000_MAC0_ENABLE);
726 else
727 aup->enable = (volatile u32 *)
728 ((unsigned long)AU1500_MAC0_ENABLE);
729 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(dev->dev_addr));
730 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
731 break;
732 case AU1000_ETH1_BASE:
733 case AU1500_ETH1_BASE:
734 if (ioaddr == AU1000_ETH1_BASE)
735 aup->enable = (volatile u32 *)
736 ((unsigned long)AU1000_MAC1_ENABLE);
737 else
738 aup->enable = (volatile u32 *)
739 ((unsigned long)AU1500_MAC1_ENABLE);
740 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(dev->dev_addr));
741 dev->dev_addr[4] += 0x10;
742 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
743 break;
744 default:
745 printk(KERN_ERR "%s: bad ioaddr\n", dev->name);
746 break;
747
748 }
749
750 aup->phy_addr = PHY_ADDRESS;
751
752
753
754 *aup->enable = MAC_EN_CLOCK_ENABLE;
755 au_sync_delay(2);
756 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 |
757 MAC_EN_RESET2 | MAC_EN_CLOCK_ENABLE;
758 au_sync_delay(2);
759
760 if (mii_probe(dev) != 0) {
761 goto free_region;
762 }
763
764 pDBfree = NULL;
765
766 pDB = aup->db;
767 for (i=0; i<(NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
768 pDB->pnext = pDBfree;
769 pDBfree = pDB;
770 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
771 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
772 pDB++;
773 }
774 aup->pDBfree = pDBfree;
775
776 for (i=0; i<NUM_RX_DMA; i++) {
777 pDB = GetFreeDB(aup);
778 if (!pDB) goto free_region;
779 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
780 aup->rx_db_inuse[i] = pDB;
781 }
782 for (i=0; i<NUM_TX_DMA; i++) {
783 pDB = GetFreeDB(aup);
784 if (!pDB) goto free_region;
785 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
786 aup->tx_dma_ring[i]->len = 0;
787 aup->tx_db_inuse[i] = pDB;
788 }
789
790 spin_lock_init(&aup->lock);
791 dev->base_addr = ioaddr;
792 dev->irq = irq;
793 dev->open = au1000_open;
794 dev->hard_start_xmit = au1000_tx;
795 dev->stop = au1000_close;
796 dev->get_stats = au1000_get_stats;
797 dev->set_multicast_list = &set_rx_mode;
798 dev->do_ioctl = &au1000_ioctl;
799 dev->set_config = &au1000_set_config;
800 dev->tx_timeout = au1000_tx_timeout;
801 dev->watchdog_timeo = ETH_TX_TIMEOUT;
802
803
804
805 ether_setup(dev);
806
807
808
809
810
811 reset_mac(dev);
812 return 0;
813
814free_region:
815 release_region(ioaddr, MAC_IOSIZE);
816 unregister_netdev(dev);
817 if (aup->vaddr)
818 dma_free((void *)aup->vaddr,
819 MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS));
820 if (dev->priv != NULL)
821 kfree(dev->priv);
822 printk(KERN_ERR "%s: au1000_probe1 failed. Returns %d\n",
823 dev->name, retval);
824 kfree(dev);
825 return retval;
826}
827
828
829
830
831
832
833
834
835
836
837
838static int au1000_init(struct net_device *dev)
839{
840 struct au1000_private *aup = (struct au1000_private *) dev->priv;
841 u32 flags;
842 int i;
843 u32 control;
844 u16 link, speed;
845
846 if (au1000_debug > 4) printk("%s: au1000_init\n", dev->name);
847
848 spin_lock_irqsave(&aup->lock, flags);
849
850
851 *aup->enable = MAC_EN_CLOCK_ENABLE;
852 au_sync_delay(2);
853 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 |
854 MAC_EN_RESET2 | MAC_EN_CLOCK_ENABLE;
855 au_sync_delay(20);
856
857 aup->mac->control = 0;
858 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
859 aup->tx_tail = aup->tx_head;
860 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
861
862 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
863 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
864 dev->dev_addr[1]<<8 | dev->dev_addr[0];
865
866 for (i=0; i<NUM_RX_DMA; i++) {
867 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
868 }
869 au_sync();
870
871 aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
872 control = MAC_DISABLE_RX_OWN | MAC_RX_ENABLE | MAC_TX_ENABLE;
873#ifndef CONFIG_CPU_LITTLE_ENDIAN
874 control |= MAC_BIG_ENDIAN;
875#endif
876 if (link && (dev->if_port == IF_PORT_100BASEFX)) {
877 control |= MAC_FULL_DUPLEX;
878 }
879 aup->mac->control = control;
880 au_sync();
881
882 spin_unlock_irqrestore(&aup->lock, flags);
883 return 0;
884}
885
886static void au1000_timer(unsigned long data)
887{
888 struct net_device *dev = (struct net_device *)data;
889 struct au1000_private *aup = (struct au1000_private *) dev->priv;
890 unsigned char if_port;
891 u16 link, speed;
892
893 if (!dev) {
894
895 printk(KERN_ERR "au1000_timer error: NULL dev\n");
896 return;
897 }
898
899 if_port = dev->if_port;
900 if (aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed) == 0) {
901 if (link) {
902 if (!(dev->flags & IFF_RUNNING)) {
903 netif_carrier_on(dev);
904 dev->flags |= IFF_RUNNING;
905 printk(KERN_INFO "%s: link up\n", dev->name);
906 }
907 }
908 else {
909 if (dev->flags & IFF_RUNNING) {
910 netif_carrier_off(dev);
911 dev->flags &= ~IFF_RUNNING;
912 dev->if_port = 0;
913 printk(KERN_INFO "%s: link down\n", dev->name);
914 }
915 }
916 }
917
918 if (link && (dev->if_port != if_port) &&
919 (dev->if_port != IF_PORT_UNKNOWN)) {
920 hard_stop(dev);
921 if (dev->if_port == IF_PORT_100BASEFX) {
922 printk(KERN_INFO "%s: going to full duplex\n",
923 dev->name);
924 aup->mac->control |= MAC_FULL_DUPLEX;
925 au_sync_delay(1);
926 }
927 else {
928 aup->mac->control &= ~MAC_FULL_DUPLEX;
929 au_sync_delay(1);
930 }
931 enable_rx_tx(dev);
932 }
933
934 aup->timer.expires = RUN_AT((1*HZ));
935 aup->timer.data = (unsigned long)dev;
936 aup->timer.function = &au1000_timer;
937 add_timer(&aup->timer);
938
939}
940
941static int au1000_open(struct net_device *dev)
942{
943 int retval;
944 struct au1000_private *aup = (struct au1000_private *) dev->priv;
945
946 MOD_INC_USE_COUNT;
947
948 if (au1000_debug > 4)
949 printk("%s: open: dev=%p\n", dev->name, dev);
950
951 if ((retval = au1000_init(dev))) {
952 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
953 free_irq(dev->irq, dev);
954 MOD_DEC_USE_COUNT;
955 return retval;
956 }
957 netif_start_queue(dev);
958
959 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0,
960 dev->name, dev))) {
961 printk(KERN_ERR "%s: unable to get IRQ %d\n",
962 dev->name, dev->irq);
963 MOD_DEC_USE_COUNT;
964 return retval;
965 }
966
967 aup->timer.expires = RUN_AT((3*HZ));
968 aup->timer.data = (unsigned long)dev;
969 aup->timer.function = &au1000_timer;
970 add_timer(&aup->timer);
971
972 if (au1000_debug > 4)
973 printk("%s: open: Initialization done.\n", dev->name);
974
975 return 0;
976}
977
978static int au1000_close(struct net_device *dev)
979{
980 u32 flags;
981 struct au1000_private *aup = (struct au1000_private *) dev->priv;
982
983 if (au1000_debug > 4)
984 printk("%s: close: dev=%p\n", dev->name, dev);
985
986 spin_lock_irqsave(&aup->lock, flags);
987
988
989 if (netif_device_present(dev)) {
990 netif_stop_queue(dev);
991 }
992
993
994 free_irq(dev->irq, dev);
995 spin_unlock_irqrestore(&aup->lock, flags);
996
997 reset_mac(dev);
998 MOD_DEC_USE_COUNT;
999 return 0;
1000}
1001
1002static void __exit au1000_cleanup_module(void)
1003{
1004}
1005
1006
1007static inline void
1008update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
1009{
1010 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1011 struct net_device_stats *ps = &aup->stats;
1012
1013 ps->tx_packets++;
1014 ps->tx_bytes += pkt_len;
1015
1016 if (status & TX_FRAME_ABORTED) {
1017 if (dev->if_port == IF_PORT_100BASEFX) {
1018 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
1019
1020
1021 ps->tx_errors++;
1022 ps->tx_aborted_errors++;
1023 }
1024 }
1025 else {
1026 ps->tx_errors++;
1027 ps->tx_aborted_errors++;
1028 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
1029 ps->tx_carrier_errors++;
1030 }
1031 }
1032}
1033
1034
1035
1036
1037
1038
1039
1040static void au1000_tx_ack(struct net_device *dev)
1041{
1042 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1043 volatile tx_dma_t *ptxd;
1044
1045 ptxd = aup->tx_dma_ring[aup->tx_tail];
1046
1047 while (ptxd->buff_stat & TX_T_DONE) {
1048 update_tx_stats(dev, ptxd->status, ptxd->len & 0x3ff);
1049 ptxd->buff_stat &= ~TX_T_DONE;
1050 ptxd->len = 0;
1051 au_sync();
1052
1053 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
1054 ptxd = aup->tx_dma_ring[aup->tx_tail];
1055
1056 if (aup->tx_full) {
1057 aup->tx_full = 0;
1058 netif_wake_queue(dev);
1059 }
1060 }
1061}
1062
1063
1064
1065
1066
1067static int au1000_tx(struct sk_buff *skb, struct net_device *dev)
1068{
1069 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1070 volatile tx_dma_t *ptxd;
1071 u32 buff_stat;
1072 db_dest_t *pDB;
1073 int i;
1074
1075 if (au1000_debug > 4)
1076 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
1077 dev->name, (unsigned)aup, skb->len,
1078 skb->data, aup->tx_head);
1079
1080 ptxd = aup->tx_dma_ring[aup->tx_head];
1081 buff_stat = ptxd->buff_stat;
1082 if (buff_stat & TX_DMA_ENABLE) {
1083
1084 netif_stop_queue(dev);
1085 aup->tx_full = 1;
1086 return 1;
1087 }
1088 else if (buff_stat & TX_T_DONE) {
1089 update_tx_stats(dev, ptxd->status, ptxd->len & 0x3ff);
1090 ptxd->len = 0;
1091 }
1092
1093 if (aup->tx_full) {
1094 aup->tx_full = 0;
1095 netif_wake_queue(dev);
1096 }
1097
1098 pDB = aup->tx_db_inuse[aup->tx_head];
1099 memcpy((void *)pDB->vaddr, skb->data, skb->len);
1100 if (skb->len < MAC_MIN_PKT_SIZE) {
1101 for (i=skb->len; i<MAC_MIN_PKT_SIZE; i++) {
1102 ((char *)pDB->vaddr)[i] = 0;
1103 }
1104 ptxd->len = MAC_MIN_PKT_SIZE;
1105 }
1106 else
1107 ptxd->len = skb->len;
1108
1109 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1110 au_sync();
1111 dev_kfree_skb(skb);
1112 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1113 dev->trans_start = jiffies;
1114 return 0;
1115}
1116
1117
1118static inline void update_rx_stats(struct net_device *dev, u32 status)
1119{
1120 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1121 struct net_device_stats *ps = &aup->stats;
1122
1123 ps->rx_packets++;
1124 if (status & RX_MCAST_FRAME)
1125 ps->multicast++;
1126
1127 if (status & RX_ERROR) {
1128 ps->rx_errors++;
1129 if (status & RX_MISSED_FRAME)
1130 ps->rx_missed_errors++;
1131 if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
1132 ps->rx_length_errors++;
1133 if (status & RX_CRC_ERROR)
1134 ps->rx_crc_errors++;
1135 if (status & RX_COLL)
1136 ps->collisions++;
1137 }
1138 else
1139 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
1140
1141}
1142
1143
1144
1145
1146static int au1000_rx(struct net_device *dev)
1147{
1148 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1149 struct sk_buff *skb;
1150 volatile rx_dma_t *prxd;
1151 u32 buff_stat, status;
1152 db_dest_t *pDB;
1153
1154 if (au1000_debug > 4)
1155 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
1156
1157 prxd = aup->rx_dma_ring[aup->rx_head];
1158 buff_stat = prxd->buff_stat;
1159 while (buff_stat & RX_T_DONE) {
1160 status = prxd->status;
1161 pDB = aup->rx_db_inuse[aup->rx_head];
1162 update_rx_stats(dev, status);
1163 if (!(status & RX_ERROR)) {
1164
1165
1166 skb = dev_alloc_skb((status & RX_FRAME_LEN_MASK) + 2);
1167 if (skb == NULL) {
1168 printk(KERN_ERR
1169 "%s: Memory squeeze, dropping packet.\n",
1170 dev->name);
1171 aup->stats.rx_dropped++;
1172 continue;
1173 }
1174 skb->dev = dev;
1175 skb_reserve(skb, 2);
1176 eth_copy_and_sum(skb, (unsigned char *)pDB->vaddr,
1177 status & RX_FRAME_LEN_MASK, 0);
1178 skb_put(skb, status & RX_FRAME_LEN_MASK);
1179 skb->protocol = eth_type_trans(skb, dev);
1180 netif_rx(skb);
1181 }
1182 else {
1183 if (au1000_debug > 4) {
1184 if (status & RX_MISSED_FRAME)
1185 printk("rx miss\n");
1186 if (status & RX_WDOG_TIMER)
1187 printk("rx wdog\n");
1188 if (status & RX_RUNT)
1189 printk("rx runt\n");
1190 if (status & RX_OVERLEN)
1191 printk("rx overlen\n");
1192 if (status & RX_COLL)
1193 printk("rx coll\n");
1194 if (status & RX_MII_ERROR)
1195 printk("rx mii error\n");
1196 if (status & RX_CRC_ERROR)
1197 printk("rx crc error\n");
1198 if (status & RX_LEN_ERROR)
1199 printk("rx len error\n");
1200 if (status & RX_U_CNTRL_FRAME)
1201 printk("rx u control frame\n");
1202 if (status & RX_MISSED_FRAME)
1203 printk("rx miss\n");
1204 }
1205 }
1206 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
1207 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
1208 au_sync();
1209
1210
1211 prxd = aup->rx_dma_ring[aup->rx_head];
1212 buff_stat = prxd->buff_stat;
1213 dev->last_rx = jiffies;
1214 }
1215 return 0;
1216}
1217
1218
1219
1220
1221
1222void au1000_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1223{
1224 struct net_device *dev = (struct net_device *) dev_id;
1225
1226 if (dev == NULL) {
1227 printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name);
1228 return;
1229 }
1230 au1000_tx_ack(dev);
1231 au1000_rx(dev);
1232}
1233
1234
1235
1236
1237
1238
1239static void au1000_tx_timeout(struct net_device *dev)
1240{
1241 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
1242 reset_mac(dev);
1243 au1000_init(dev);
1244}
1245
1246static void set_rx_mode(struct net_device *dev)
1247{
1248 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1249
1250 if (au1000_debug > 4)
1251 printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags);
1252
1253 if (dev->flags & IFF_PROMISC) {
1254 aup->mac->control |= MAC_PROMISCUOUS;
1255 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1256 } else if ((dev->flags & IFF_ALLMULTI) ||
1257 dev->mc_count > MULTICAST_FILTER_LIMIT) {
1258 aup->mac->control |= MAC_PASS_ALL_MULTI;
1259 aup->mac->control &= ~MAC_PROMISCUOUS;
1260 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
1261 } else {
1262 int i;
1263 struct dev_mc_list *mclist;
1264 u32 mc_filter[2];
1265
1266 mc_filter[1] = mc_filter[0] = 0;
1267 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1268 i++, mclist = mclist->next) {
1269 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26, mc_filter);
1270 }
1271 aup->mac->multi_hash_high = mc_filter[1];
1272 aup->mac->multi_hash_low = mc_filter[0];
1273 aup->mac->control &= ~MAC_PROMISCUOUS;
1274 aup->mac->control |= MAC_HASH_MODE;
1275 }
1276}
1277
1278
1279static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1280{
1281 u16 *data = (u16 *)&rq->ifr_data;
1282
1283
1284 switch(cmd) {
1285 case SIOCGMIIPHY:
1286 data[0] = PHY_ADDRESS;
1287
1288 case SIOCGMIIREG:
1289
1290 return 0;
1291
1292 case SIOCSMIIREG:
1293 if (!capable(CAP_NET_ADMIN))
1294 return -EPERM;
1295
1296 return 0;
1297 default:
1298 return -EOPNOTSUPP;
1299 }
1300}
1301
1302
1303static int au1000_set_config(struct net_device *dev, struct ifmap *map)
1304{
1305 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1306 u16 control;
1307
1308 if (au1000_debug > 4) {
1309 printk("%s: set_config called: dev->if_port %d map->port %x\n",
1310 dev->name, dev->if_port, map->port);
1311 }
1312
1313 switch(map->port){
1314 case IF_PORT_UNKNOWN:
1315 printk(KERN_INFO "%s: config phy for aneg\n",
1316 dev->name);
1317 dev->if_port = map->port;
1318
1319 netif_carrier_off(dev);
1320
1321
1322 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1323 control &= ~(MII_CNTL_FDX | MII_CNTL_F100);
1324
1325
1326 mdio_write(dev, aup->phy_addr, MII_CONTROL,
1327 control | MII_CNTL_AUTO |
1328 MII_CNTL_RST_AUTO);
1329
1330 break;
1331
1332 case IF_PORT_10BASET:
1333 printk(KERN_INFO "%s: config phy for 10BaseT\n",
1334 dev->name);
1335 dev->if_port = map->port;
1336
1337
1338 netif_carrier_off(dev);
1339
1340
1341 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1342 control &= ~(MII_CNTL_F100 | MII_CNTL_AUTO |
1343 MII_CNTL_FDX);
1344
1345
1346 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
1347 break;
1348
1349 case IF_PORT_100BASET:
1350 case IF_PORT_100BASETX:
1351 printk(KERN_INFO "%s: config phy for 100BaseTX\n",
1352 dev->name);
1353 dev->if_port = map->port;
1354
1355
1356 netif_carrier_off(dev);
1357
1358
1359
1360 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1361 printk("read control %x\n", control);
1362 control &= ~(MII_CNTL_AUTO | MII_CNTL_FDX);
1363 control |= MII_CNTL_F100;
1364 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
1365 break;
1366
1367 case IF_PORT_100BASEFX:
1368 printk(KERN_INFO "%s: config phy for 100BaseFX\n",
1369 dev->name);
1370 dev->if_port = map->port;
1371
1372
1373 netif_carrier_off(dev);
1374
1375
1376
1377 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
1378 control &= ~MII_CNTL_AUTO;
1379 control |= MII_CNTL_F100 | MII_CNTL_FDX;
1380 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
1381 break;
1382 case IF_PORT_10BASE2:
1383 case IF_PORT_AUI:
1384
1385 printk(KERN_ERR "%s: 10Base2/AUI not supported",
1386 dev->name);
1387 return -EOPNOTSUPP;
1388 break;
1389
1390 default:
1391 printk(KERN_ERR "%s: Invalid media selected",
1392 dev->name);
1393 return -EINVAL;
1394 }
1395 return 0;
1396}
1397
1398static struct net_device_stats *au1000_get_stats(struct net_device *dev)
1399{
1400 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1401
1402 if (au1000_debug > 4)
1403 printk("%s: au1000_get_stats: dev=%p\n", dev->name, dev);
1404
1405 if (netif_device_present(dev)) {
1406 return &aup->stats;
1407 }
1408 return 0;
1409}
1410
1411module_init(au1000_init_module);
1412module_exit(au1000_cleanup_module);
1413
