LXR linux-bk/drivers/net/e1000/e1000

   1/*******************************************************************************
   2
   3  
   4  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
   5  
   6  This program is free software; you can redistribute it and/or modify it 
   7  under the terms of the GNU General Public License as published by the Free 
   8  Software Foundation; either version 2 of the License, or (at your option) 
   9  any later version.
  10  
  11  This program is distributed in the hope that it will be useful, but WITHOUT 
  12  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
  13  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
  14  more details.
  15  
  16  You should have received a copy of the GNU General Public License along with
  17  this program; if not, write to the Free Software Foundation, Inc., 59 
  18  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  19  
  20  The full GNU General Public License is included in this distribution in the
  21  file called LICENSE.
  22  
  23  Contact Information:
  24  Linux NICS <linux.nics@intel.com>
  25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27*******************************************************************************/
  28
  29/* e1000_hw.h
  30 * Structures, enums, and macros for the MAC
  31 */
  32
  33#ifndef _E1000_HW_H_
  34#define _E1000_HW_H_
  35
  36#include "e1000_osdep.h"
  37
  38/* Forward declarations of structures used by the shared code */
  39struct e1000_hw;
  40struct e1000_hw_stats;
  41
  42/* Enumerated types specific to the e1000 hardware */
  43/* Media Access Controlers */
  44typedef enum {
  45    e1000_undefined = 0,
  46    e1000_82542_rev2_0,
  47    e1000_82542_rev2_1,
  48    e1000_82543,
  49    e1000_82544,
  50    e1000_82540,
  51    e1000_82545,
  52    e1000_82546,
  53    e1000_num_macs
  54} e1000_mac_type;
  55
  56/* Media Types */
  57typedef enum {
  58    e1000_media_type_copper = 0,
  59    e1000_media_type_fiber = 1,
  60    e1000_num_media_types
  61} e1000_media_type;
  62
  63typedef enum {
  64    e1000_10_half = 0,
  65    e1000_10_full = 1,
  66    e1000_100_half = 2,
  67    e1000_100_full = 3
  68} e1000_speed_duplex_type;
  69
  70/* Flow Control Settings */
  71typedef enum {
  72    e1000_fc_none = 0,
  73    e1000_fc_rx_pause = 1,
  74    e1000_fc_tx_pause = 2,
  75    e1000_fc_full = 3,
  76    e1000_fc_default = 0xFF
  77} e1000_fc_type;
  78
  79/* PCI bus types */
  80typedef enum {
  81    e1000_bus_type_unknown = 0,
  82    e1000_bus_type_pci,
  83    e1000_bus_type_pcix
  84} e1000_bus_type;
  85
  86/* PCI bus speeds */
  87typedef enum {
  88    e1000_bus_speed_unknown = 0,
  89    e1000_bus_speed_33,
  90    e1000_bus_speed_66,
  91    e1000_bus_speed_100,
  92    e1000_bus_speed_133,
  93    e1000_bus_speed_reserved
  94} e1000_bus_speed;
  95
  96/* PCI bus widths */
  97typedef enum {
  98    e1000_bus_width_unknown = 0,
  99    e1000_bus_width_32,
 100    e1000_bus_width_64
 101} e1000_bus_width;
 102
 103/* PHY status info structure and supporting enums */
 104typedef enum {
 105    e1000_cable_length_50 = 0,
 106    e1000_cable_length_50_80,
 107    e1000_cable_length_80_110,
 108    e1000_cable_length_110_140,
 109    e1000_cable_length_140,
 110    e1000_cable_length_undefined = 0xFF
 111} e1000_cable_length;
 112
 113typedef enum {
 114    e1000_10bt_ext_dist_enable_normal = 0,
 115    e1000_10bt_ext_dist_enable_lower,
 116    e1000_10bt_ext_dist_enable_undefined = 0xFF
 117} e1000_10bt_ext_dist_enable;
 118
 119typedef enum {
 120    e1000_rev_polarity_normal = 0,
 121    e1000_rev_polarity_reversed,
 122    e1000_rev_polarity_undefined = 0xFF
 123} e1000_rev_polarity;
 124
 125typedef enum {
 126    e1000_polarity_reversal_enabled = 0,
 127    e1000_polarity_reversal_disabled,
 128    e1000_polarity_reversal_undefined = 0xFF
 129} e1000_polarity_reversal;
 130
 131typedef enum {
 132    e1000_auto_x_mode_manual_mdi = 0,
 133    e1000_auto_x_mode_manual_mdix,
 134    e1000_auto_x_mode_auto1,
 135    e1000_auto_x_mode_auto2,
 136    e1000_auto_x_mode_undefined = 0xFF
 137} e1000_auto_x_mode;
 138
 139typedef enum {
 140    e1000_1000t_rx_status_not_ok = 0,
 141    e1000_1000t_rx_status_ok,
 142    e1000_1000t_rx_status_undefined = 0xFF
 143} e1000_1000t_rx_status;
 144
 145struct e1000_phy_info {
 146    e1000_cable_length cable_length;
 147    e1000_10bt_ext_dist_enable extended_10bt_distance;
 148    e1000_rev_polarity cable_polarity;
 149    e1000_polarity_reversal polarity_correction;
 150    e1000_auto_x_mode mdix_mode;
 151    e1000_1000t_rx_status local_rx;
 152    e1000_1000t_rx_status remote_rx;
 153};
 154
 155struct e1000_phy_stats {
 156    uint32_t idle_errors;
 157    uint32_t receive_errors;
 158};
 159
 160
 161
 162/* Error Codes */
 163#define E1000_SUCCESS      0
 164#define E1000_ERR_EEPROM   1
 165#define E1000_ERR_PHY      2
 166#define E1000_ERR_CONFIG   3
 167#define E1000_ERR_PARAM    4
 168#define E1000_ERR_MAC_TYPE 5
 169
 170/* Function prototypes */
 171/* Initialization */
 172void e1000_reset_hw(struct e1000_hw *hw);
 173int32_t e1000_init_hw(struct e1000_hw *hw);
 174int32_t e1000_set_mac_type(struct e1000_hw *hw);
 175
 176/* Link Configuration */
 177int32_t e1000_setup_link(struct e1000_hw *hw);
 178int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
 179void e1000_config_collision_dist(struct e1000_hw *hw);
 180int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
 181int32_t e1000_check_for_link(struct e1000_hw *hw);
 182void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
 183int32_t e1000_wait_autoneg(struct e1000_hw *hw);
 184
 185/* PHY */
 186int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
 187int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
 188void e1000_phy_hw_reset(struct e1000_hw *hw);
 189int32_t e1000_phy_reset(struct e1000_hw *hw);
 190int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
 191int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
 192int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
 193
 194/* EEPROM Functions */
 195int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t *data);
 196int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
 197int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
 198int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t data);
 199int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
 200int32_t e1000_read_mac_addr(struct e1000_hw * hw);
 201
 202/* Filters (multicast, vlan, receive) */
 203void e1000_init_rx_addrs(struct e1000_hw *hw);
 204void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad);
 205uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
 206void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
 207void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
 208void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
 209void e1000_clear_vfta(struct e1000_hw *hw);
 210
 211/* LED functions */
 212int32_t e1000_setup_led(struct e1000_hw *hw);
 213int32_t e1000_cleanup_led(struct e1000_hw *hw);
 214int32_t e1000_led_on(struct e1000_hw *hw);
 215int32_t e1000_led_off(struct e1000_hw *hw);
 216
 217/* Adaptive IFS Functions */
 218
 219/* Everything else */
 220void e1000_clear_hw_cntrs(struct e1000_hw *hw);
 221void e1000_reset_adaptive(struct e1000_hw *hw);
 222void e1000_update_adaptive(struct e1000_hw *hw);
 223void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
 224void e1000_get_bus_info(struct e1000_hw *hw);
 225void e1000_pci_set_mwi(struct e1000_hw *hw);
 226void e1000_pci_clear_mwi(struct e1000_hw *hw);
 227void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
 228void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
 229/* Port I/O is only supported on 82544 and newer */
 230uint32_t e1000_io_read(struct e1000_hw *hw, uint32_t port);
 231uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
 232void e1000_io_write(struct e1000_hw *hw, uint32_t port, uint32_t value);
 233void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
 234#define E1000_READ_REG_IO(a, reg) \
 235    e1000_read_reg_io((a), E1000_##reg)
 236#define E1000_WRITE_REG_IO(a, reg, val) \
 237    e1000_write_reg_io((a), E1000_##reg, val)
 238
 239/* PCI Device IDs */
 240#define E1000_DEV_ID_82542          0x1000
 241#define E1000_DEV_ID_82543GC_FIBER  0x1001
 242#define E1000_DEV_ID_82543GC_COPPER 0x1004
 243#define E1000_DEV_ID_82544EI_COPPER 0x1008
 244#define E1000_DEV_ID_82544EI_FIBER  0x1009
 245#define E1000_DEV_ID_82544GC_COPPER 0x100C
 246#define E1000_DEV_ID_82544GC_LOM    0x100D
 247#define E1000_DEV_ID_82540EM        0x100E
 248#define E1000_DEV_ID_82540EM_LOM    0x1015
 249#define E1000_DEV_ID_82545EM_COPPER 0x100F
 250#define E1000_DEV_ID_82545EM_FIBER  0x1011
 251#define E1000_DEV_ID_82546EB_COPPER 0x1010
 252#define E1000_DEV_ID_82546EB_FIBER  0x1012
 253#define NUM_DEV_IDS 13
 254
 255#define NODE_ADDRESS_SIZE 6
 256#define ETH_LENGTH_OF_ADDRESS 6
 257
 258/* MAC decode size is 128K - This is the size of BAR0 */
 259#define MAC_DECODE_SIZE (128 * 1024)
 260
 261#define E1000_82542_2_0_REV_ID 2
 262#define E1000_82542_2_1_REV_ID 3
 263
 264#define SPEED_10    10
 265#define SPEED_100   100
 266#define SPEED_1000  1000
 267#define HALF_DUPLEX 1
 268#define FULL_DUPLEX 2
 269
 270/* The sizes (in bytes) of a ethernet packet */
 271#define ENET_HEADER_SIZE             14
 272#define MAXIMUM_ETHERNET_FRAME_SIZE  1518 /* With FCS */
 273#define MINIMUM_ETHERNET_FRAME_SIZE  64   /* With FCS */
 274#define ETHERNET_FCS_SIZE            4
 275#define MAXIMUM_ETHERNET_PACKET_SIZE \
 276    (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
 277#define MINIMUM_ETHERNET_PACKET_SIZE \
 278    (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
 279#define CRC_LENGTH                   ETHERNET_FCS_SIZE
 280#define MAX_JUMBO_FRAME_SIZE         0x3F00
 281
 282
 283/* 802.1q VLAN Packet Sizes */
 284#define VLAN_TAG_SIZE                     4     /* 802.3ac tag (not DMAed) */
 285
 286/* Ethertype field values */
 287#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
 288#define ETHERNET_IP_TYPE        0x0800  /* IP packets */
 289#define ETHERNET_ARP_TYPE       0x0806  /* Address Resolution Protocol (ARP) */
 290
 291/* Packet Header defines */
 292#define IP_PROTOCOL_TCP    6
 293#define IP_PROTOCOL_UDP    0x11
 294
 295/* This defines the bits that are set in the Interrupt Mask
 296 * Set/Read Register.  Each bit is documented below:
 297 *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 298 *   o RXSEQ  = Receive Sequence Error 
 299 */
 300#define POLL_IMS_ENABLE_MASK ( \
 301    E1000_IMS_RXDMT0 |         \
 302    E1000_IMS_RXSEQ)
 303
 304/* This defines the bits that are set in the Interrupt Mask
 305 * Set/Read Register.  Each bit is documented below:
 306 *   o RXT0   = Receiver Timer Interrupt (ring 0)
 307 *   o TXDW   = Transmit Descriptor Written Back
 308 *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 309 *   o RXSEQ  = Receive Sequence Error
 310 *   o LSC    = Link Status Change
 311 */
 312#define IMS_ENABLE_MASK ( \
 313    E1000_IMS_RXT0   |    \
 314    E1000_IMS_TXDW   |    \
 315    E1000_IMS_RXDMT0 |    \
 316    E1000_IMS_RXSEQ  |    \
 317    E1000_IMS_LSC)
 318
 319/* The number of high/low register pairs in the RAR. The RAR (Receive Address
 320 * Registers) holds the directed and multicast addresses that we monitor. We
 321 * reserve one of these spots for our directed address, allowing us room for
 322 * E1000_RAR_ENTRIES - 1 multicast addresses. 
 323 */
 324#define E1000_RAR_ENTRIES 16
 325
 326#define MIN_NUMBER_OF_DESCRIPTORS 8
 327#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
 328
 329/* Receive Descriptor */
 330struct e1000_rx_desc {
 331    uint64_t buffer_addr; /* Address of the descriptor's data buffer */
 332    uint16_t length;     /* Length of data DMAed into data buffer */
 333    uint16_t csum;       /* Packet checksum */
 334    uint8_t status;      /* Descriptor status */
 335    uint8_t errors;      /* Descriptor Errors */
 336    uint16_t special;
 337};
 338
 339/* Receive Decriptor bit definitions */
 340#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
 341#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
 342#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
 343#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
 344#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
 345#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
 346#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
 347#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
 348#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
 349#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
 350#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
 351#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
 352#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
 353#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
 354#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
 355#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
 356#define E1000_RXD_SPC_PRI_SHIFT 0x000D  /* Priority is in upper 3 of 16 */
 357#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
 358#define E1000_RXD_SPC_CFI_SHIFT 0x000C  /* CFI is bit 12 */
 359
 360/* mask to determine if packets should be dropped due to frame errors */
 361#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
 362    E1000_RXD_ERR_CE  |                \
 363    E1000_RXD_ERR_SE  |                \
 364    E1000_RXD_ERR_SEQ |                \
 365    E1000_RXD_ERR_CXE |                \
 366    E1000_RXD_ERR_RXE)
 367
 368/* Transmit Descriptor */
 369struct e1000_tx_desc {
 370    uint64_t buffer_addr;       /* Address of the descriptor's data buffer */
 371    union {
 372        uint32_t data;
 373        struct {
 374            uint16_t length;    /* Data buffer length */
 375            uint8_t cso;        /* Checksum offset */
 376            uint8_t cmd;        /* Descriptor control */
 377        } flags;
 378    } lower;
 379    union {
 380        uint32_t data;
 381        struct {
 382            uint8_t status;     /* Descriptor status */
 383            uint8_t css;        /* Checksum start */
 384            uint16_t special;
 385        } fields;
 386    } upper;
 387};
 388
 389/* Transmit Descriptor bit definitions */
 390#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
 391#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
 392#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 393#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 394#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
 395#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 396#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
 397#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
 398#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
 399#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 400#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
 401#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
 402#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 403#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
 404#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
 405#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
 406#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
 407#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
 408#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
 409#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
 410
 411/* Offload Context Descriptor */
 412struct e1000_context_desc {
 413    union {
 414        uint32_t ip_config;
 415        struct {
 416            uint8_t ipcss;      /* IP checksum start */
 417            uint8_t ipcso;      /* IP checksum offset */
 418            uint16_t ipcse;     /* IP checksum end */
 419        } ip_fields;
 420    } lower_setup;
 421    union {
 422        uint32_t tcp_config;
 423        struct {
 424            uint8_t tucss;      /* TCP checksum start */
 425            uint8_t tucso;      /* TCP checksum offset */
 426            uint16_t tucse;     /* TCP checksum end */
 427        } tcp_fields;
 428    } upper_setup;
 429    uint32_t cmd_and_length;    /* */
 430    union {
 431        uint32_t data;
 432        struct {
 433            uint8_t status;     /* Descriptor status */
 434            uint8_t hdr_len;    /* Header length */
 435            uint16_t mss;       /* Maximum segment size */
 436        } fields;
 437    } tcp_seg_setup;
 438};
 439
 440/* Offload data descriptor */
 441struct e1000_data_desc {
 442    uint64_t buffer_addr;       /* Address of the descriptor's buffer address */
 443    union {
 444        uint32_t data;
 445        struct {
 446            uint16_t length;    /* Data buffer length */
 447            uint8_t typ_len_ext;        /* */
 448            uint8_t cmd;        /* */
 449        } flags;
 450    } lower;
 451    union {
 452        uint32_t data;
 453        struct {
 454            uint8_t status;     /* Descriptor status */
 455            uint8_t popts;      /* Packet Options */
 456            uint16_t special;   /* */
 457        } fields;
 458    } upper;
 459};
 460
 461/* Filters */
 462#define E1000_NUM_UNICAST          16   /* Unicast filter entries */
 463#define E1000_MC_TBL_SIZE          128  /* Multicast Filter Table (4096 bits) */
 464#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 465
 466
 467/* Receive Address Register */
 468struct e1000_rar {
 469    volatile uint32_t low;      /* receive address low */
 470    volatile uint32_t high;     /* receive address high */
 471};
 472
 473/* The number of entries in the Multicast Table Array (MTA). */
 474#define E1000_NUM_MTA_REGISTERS 128
 475
 476/* IPv4 Address Table Entry */
 477struct e1000_ipv4_at_entry {
 478    volatile uint32_t ipv4_addr;        /* IP Address (RW) */
 479    volatile uint32_t reserved;
 480};
 481
 482/* Four wakeup IP addresses are supported */
 483#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
 484#define E1000_IP4AT_SIZE                  E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
 485#define E1000_IP6AT_SIZE                  1
 486
 487/* IPv6 Address Table Entry */
 488struct e1000_ipv6_at_entry {
 489    volatile uint8_t ipv6_addr[16];
 490};
 491
 492/* Flexible Filter Length Table Entry */
 493struct e1000_fflt_entry {
 494    volatile uint32_t length;   /* Flexible Filter Length (RW) */
 495    volatile uint32_t reserved;
 496};
 497
 498/* Flexible Filter Mask Table Entry */
 499struct e1000_ffmt_entry {
 500    volatile uint32_t mask;     /* Flexible Filter Mask (RW) */
 501    volatile uint32_t reserved;
 502};
 503
 504/* Flexible Filter Value Table Entry */
 505struct e1000_ffvt_entry {
 506    volatile uint32_t value;    /* Flexible Filter Value (RW) */
 507    volatile uint32_t reserved;
 508};
 509
 510/* Four Flexible Filters are supported */
 511#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
 512
 513/* Each Flexible Filter is at most 128 (0x80) bytes in length */
 514#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
 515
 516#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
 517#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 518#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 519
 520/* Register Set. (82543, 82544)
 521 *
 522 * Registers are defined to be 32 bits and  should be accessed as 32 bit values.
 523 * These registers are physically located on the NIC, but are mapped into the 
 524 * host memory address space.
 525 *
 526 * RW - register is both readable and writable
 527 * RO - register is read only
 528 * WO - register is write only
 529 * R/clr - register is read only and is cleared when read
 530 * A - register array
 531 */
 532#define E1000_CTRL     0x00000  /* Device Control - RW */
 533#define E1000_STATUS   0x00008  /* Device Status - RO */
 534#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
 535#define E1000_EERD     0x00014  /* EEPROM Read - RW */
 536#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
 537#define E1000_MDIC     0x00020  /* MDI Control - RW */
 538#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
 539#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
 540#define E1000_FCT      0x00030  /* Flow Control Type - RW */
 541#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
 542#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
 543#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
 544#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
 545#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
 546#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
 547#define E1000_RCTL     0x00100  /* RX Control - RW */
 548#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
 549#define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
 550#define E1000_RXCW     0x00180  /* RX Configuration Word - RO */
 551#define E1000_TCTL     0x00400  /* TX Control - RW */
 552#define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
 553#define E1000_TBT      0x00448  /* TX Burst Timer - RW */
 554#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
 555#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
 556#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
 557#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
 558#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
 559#define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
 560#define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
 561#define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
 562#define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
 563#define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
 564#define E1000_RDTR     0x02820  /* RX Delay Timer - RW */
 565#define E1000_RXDCTL   0x02828  /* RX Descriptor Control - RW */
 566#define E1000_RADV     0x0282C  /* RX Interrupt Absolute Delay Timer - RW */
 567#define E1000_RSRPD    0x02C00  /* RX Small Packet Detect - RW */
 568#define E1000_TXDMAC   0x03000  /* TX DMA Control - RW */
 569#define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
 570#define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
 571#define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
 572#define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
 573#define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
 574#define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
 575#define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
 576#define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
 577#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
 578#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
 579#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
 580#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
 581#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
 582#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
 583#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
 584#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
 585#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
 586#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
 587#define E1000_COLC     0x04028  /* Collision Count - R/clr */
 588#define E1000_DC       0x04030  /* Defer Count - R/clr */
 589#define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
 590#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
 591#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
 592#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
 593#define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
 594#define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
 595#define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
 596#define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
 597#define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
 598#define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
 599#define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
 600#define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
 601#define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
 602#define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
 603#define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
 604#define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
 605#define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
 606#define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
 607#define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
 608#define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
 609#define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
 610#define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
 611#define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
 612#define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
 613#define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
 614#define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
 615#define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
 616#define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
 617#define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
 618#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
 619#define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
 620#define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
 621#define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
 622#define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
 623#define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
 624#define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
 625#define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
 626#define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
 627#define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
 628#define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
 629#define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
 630#define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
 631#define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
 632#define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
 633#define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
 634#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
 635#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
 636#define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
 637#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
 638#define E1000_RA       0x05400  /* Receive Address - RW Array */
 639#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
 640#define E1000_WUC      0x05800  /* Wakeup Control - RW */
 641#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
 642#define E1000_WUS      0x05810  /* Wakeup Status - RO */
 643#define E1000_MANC     0x05820  /* Management Control - RW */
 644#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
 645#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
 646#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
 647#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
 648#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
 649#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
 650#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
 651#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
 652
 653/* Register Set (82542)
 654 *
 655 * Some of the 82542 registers are located at different offsets than they are
 656 * in more current versions of the 8254x. Despite the difference in location,
 657 * the registers function in the same manner.
 658 */
 659#define E1000_82542_CTRL     E1000_CTRL
 660#define E1000_82542_STATUS   E1000_STATUS
 661#define E1000_82542_EECD     E1000_EECD
 662#define E1000_82542_EERD     E1000_EERD
 663#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
 664#define E1000_82542_MDIC     E1000_MDIC
 665#define E1000_82542_FCAL     E1000_FCAL
 666#define E1000_82542_FCAH     E1000_FCAH
 667#define E1000_82542_FCT      E1000_FCT
 668#define E1000_82542_VET      E1000_VET
 669#define E1000_82542_RA       0x00040
 670#define E1000_82542_ICR      E1000_ICR
 671#define E1000_82542_ITR      E1000_ITR
 672#define E1000_82542_ICS      E1000_ICS
 673#define E1000_82542_IMS      E1000_IMS
 674#define E1000_82542_IMC      E1000_IMC
 675#define E1000_82542_RCTL     E1000_RCTL
 676#define E1000_82542_RDTR     0x00108
 677#define E1000_82542_RDBAL    0x00110
 678#define E1000_82542_RDBAH    0x00114
 679#define E1000_82542_RDLEN    0x00118
 680#define E1000_82542_RDH      0x00120
 681#define E1000_82542_RDT      0x00128
 682#define E1000_82542_FCRTH    0x00160
 683#define E1000_82542_FCRTL    0x00168
 684#define E1000_82542_FCTTV    E1000_FCTTV
 685#define E1000_82542_TXCW     E1000_TXCW
 686#define E1000_82542_RXCW     E1000_RXCW
 687#define E1000_82542_MTA      0x00200
 688#define E1000_82542_TCTL     E1000_TCTL
 689#define E1000_82542_TIPG     E1000_TIPG
 690#define E1000_82542_TDBAL    0x00420
 691#define E1000_82542_TDBAH    0x00424
 692#define E1000_82542_TDLEN    0x00428
 693#define E1000_82542_TDH      0x00430
 694#define E1000_82542_TDT      0x00438
 695#define E1000_82542_TIDV     0x00440
 696#define E1000_82542_TBT      E1000_TBT
 697#define E1000_82542_AIT      E1000_AIT
 698#define E1000_82542_VFTA     0x00600
 699#define E1000_82542_LEDCTL   E1000_LEDCTL
 700#define E1000_82542_PBA      E1000_PBA
 701#define E1000_82542_RXDCTL   E1000_RXDCTL
 702#define E1000_82542_RADV     E1000_RADV
 703#define E1000_82542_RSRPD    E1000_RSRPD
 704#define E1000_82542_TXDMAC   E1000_TXDMAC
 705#define E1000_82542_TXDCTL   E1000_TXDCTL
 706#define E1000_82542_TADV     E1000_TADV
 707#define E1000_82542_TSPMT    E1000_TSPMT
 708#define E1000_82542_CRCERRS  E1000_CRCERRS
 709#define E1000_82542_ALGNERRC E1000_ALGNERRC
 710#define E1000_82542_SYMERRS  E1000_SYMERRS
 711#define E1000_82542_RXERRC   E1000_RXERRC
 712#define E1000_82542_MPC      E1000_MPC
 713#define E1000_82542_SCC      E1000_SCC
 714#define E1000_82542_ECOL     E1000_ECOL
 715#define E1000_82542_MCC      E1000_MCC
 716#define E1000_82542_LATECOL  E1000_LATECOL
 717#define E1000_82542_COLC     E1000_COLC
 718#define E1000_82542_DC       E1000_DC
 719#define E1000_82542_TNCRS    E1000_TNCRS
 720#define E1000_82542_SEC      E1000_SEC
 721#define E1000_82542_CEXTERR  E1000_CEXTERR
 722#define E1000_82542_RLEC     E1000_RLEC
 723#define E1000_82542_XONRXC   E1000_XONRXC
 724#define E1000_82542_XONTXC   E1000_XONTXC
 725#define E1000_82542_XOFFRXC  E1000_XOFFRXC
 726#define E1000_82542_XOFFTXC  E1000_XOFFTXC
 727#define E1000_82542_FCRUC    E1000_FCRUC
 728#define E1000_82542_PRC64    E1000_PRC64
 729#define E1000_82542_PRC127   E1000_PRC127
 730#define E1000_82542_PRC255   E1000_PRC255
 731#define E1000_82542_PRC511   E1000_PRC511
 732#define E1000_82542_PRC1023  E1000_PRC1023
 733#define E1000_82542_PRC1522  E1000_PRC1522
 734#define E1000_82542_GPRC     E1000_GPRC
 735#define E1000_82542_BPRC     E1000_BPRC
 736#define E1000_82542_MPRC     E1000_MPRC
 737#define E1000_82542_GPTC     E1000_GPTC
 738#define E1000_82542_GORCL    E1000_GORCL
 739#define E1000_82542_GORCH    E1000_GORCH
 740#define E1000_82542_GOTCL    E1000_GOTCL
 741#define E1000_82542_GOTCH    E1000_GOTCH
 742#define E1000_82542_RNBC     E1000_RNBC
 743#define E1000_82542_RUC      E1000_RUC
 744#define E1000_82542_RFC      E1000_RFC
 745#define E1000_82542_ROC      E1000_ROC
 746#define E1000_82542_RJC      E1000_RJC
 747#define E1000_82542_MGTPRC   E1000_MGTPRC
 748#define E1000_82542_MGTPDC   E1000_MGTPDC
 749#define E1000_82542_MGTPTC   E1000_MGTPTC
 750#define E1000_82542_TORL     E1000_TORL
 751#define E1000_82542_TORH     E1000_TORH
 752#define E1000_82542_TOTL     E1000_TOTL
 753#define E1000_82542_TOTH     E1000_TOTH
 754#define E1000_82542_TPR      E1000_TPR
 755#define E1000_82542_TPT      E1000_TPT
 756#define E1000_82542_PTC64    E1000_PTC64
 757#define E1000_82542_PTC127   E1000_PTC127
 758#define E1000_82542_PTC255   E1000_PTC255
 759#define E1000_82542_PTC511   E1000_PTC511
 760#define E1000_82542_PTC1023  E1000_PTC1023
 761#define E1000_82542_PTC1522  E1000_PTC1522
 762#define E1000_82542_MPTC     E1000_MPTC
 763#define E1000_82542_BPTC     E1000_BPTC
 764#define E1000_82542_TSCTC    E1000_TSCTC
 765#define E1000_82542_TSCTFC   E1000_TSCTFC
 766#define E1000_82542_RXCSUM   E1000_RXCSUM
 767#define E1000_82542_WUC      E1000_WUC
 768#define E1000_82542_WUFC     E1000_WUFC
 769#define E1000_82542_WUS      E1000_WUS
 770#define E1000_82542_MANC     E1000_MANC
 771#define E1000_82542_IPAV     E1000_IPAV
 772#define E1000_82542_IP4AT    E1000_IP4AT
 773#define E1000_82542_IP6AT    E1000_IP6AT
 774#define E1000_82542_WUPL     E1000_WUPL
 775#define E1000_82542_WUPM     E1000_WUPM
 776#define E1000_82542_FFLT     E1000_FFLT
 777#define E1000_82542_FFMT     E1000_FFMT
 778#define E1000_82542_FFVT     E1000_FFVT
 779
 780/* Statistics counters collected by the MAC */
 781struct e1000_hw_stats {
 782    uint64_t crcerrs;
 783    uint64_t algnerrc;
 784    uint64_t symerrs;
 785    uint64_t rxerrc;
 786    uint64_t mpc;
 787    uint64_t scc;
 788    uint64_t ecol;
 789    uint64_t mcc;
 790    uint64_t latecol;
 791    uint64_t colc;
 792    uint64_t dc;
 793    uint64_t tncrs;
 794    uint64_t sec;
 795    uint64_t cexterr;
 796    uint64_t rlec;
 797    uint64_t xonrxc;
 798    uint64_t xontxc;
 799    uint64_t xoffrxc;
 800    uint64_t xofftxc;
 801    uint64_t fcruc;
 802    uint64_t prc64;
 803    uint64_t prc127;
 804    uint64_t prc255;
 805    uint64_t prc511;
 806    uint64_t prc1023;
 807    uint64_t prc1522;
 808    uint64_t gprc;
 809    uint64_t bprc;
 810    uint64_t mprc;
 811    uint64_t gptc;
 812    uint64_t gorcl;
 813    uint64_t gorch;
 814    uint64_t gotcl;
 815    uint64_t gotch;
 816    uint64_t rnbc;
 817    uint64_t ruc;
 818    uint64_t rfc;
 819    uint64_t roc;
 820    uint64_t rjc;
 821    uint64_t mgprc;
 822    uint64_t mgpdc;
 823    uint64_t mgptc;
 824    uint64_t torl;
 825    uint64_t torh;
 826    uint64_t totl;
 827    uint64_t toth;
 828    uint64_t tpr;
 829    uint64_t tpt;
 830    uint64_t ptc64;
 831    uint64_t ptc127;
 832    uint64_t ptc255;
 833    uint64_t ptc511;
 834    uint64_t ptc1023;
 835    uint64_t ptc1522;
 836    uint64_t mptc;
 837    uint64_t bptc;
 838    uint64_t tsctc;
 839    uint64_t tsctfc;
 840};
 841
 842/* Structure containing variables used by the shared code (e1000_hw.c) */
 843struct e1000_hw {
 844    uint8_t *hw_addr;
 845    e1000_mac_type mac_type;
 846    e1000_media_type media_type;
 847    void *back;
 848    e1000_fc_type fc;
 849    e1000_bus_speed bus_speed;
 850    e1000_bus_width bus_width;
 851    e1000_bus_type bus_type;
 852    uint32_t io_base;
 853    uint32_t phy_id;
 854    uint32_t phy_addr;
 855    uint32_t original_fc;
 856    uint32_t txcw;
 857    uint32_t autoneg_failed;
 858    uint32_t max_frame_size;
 859    uint32_t min_frame_size;
 860    uint32_t mc_filter_type;
 861    uint32_t num_mc_addrs;
 862    uint32_t collision_delta;
 863    uint32_t tx_packet_delta;
 864    uint32_t ledctl_default;
 865    uint32_t ledctl_mode1;
 866    uint32_t ledctl_mode2;
 867    uint16_t autoneg_advertised;
 868    uint16_t pci_cmd_word;
 869    uint16_t fc_high_water;
 870    uint16_t fc_low_water;
 871    uint16_t fc_pause_time;
 872    uint16_t current_ifs_val;
 873    uint16_t ifs_min_val;
 874    uint16_t ifs_max_val;
 875    uint16_t ifs_step_size;
 876    uint16_t ifs_ratio;
 877    uint16_t device_id;
 878    uint16_t vendor_id;
 879    uint16_t subsystem_id;
 880    uint16_t subsystem_vendor_id;
 881    uint8_t revision_id;
 882    uint8_t autoneg;
 883    uint8_t mdix;
 884    uint8_t forced_speed_duplex;
 885    uint8_t wait_autoneg_complete;
 886    uint8_t dma_fairness;
 887    uint8_t mac_addr[NODE_ADDRESS_SIZE];
 888    uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
 889    boolean_t disable_polarity_correction;
 890    boolean_t get_link_status;
 891    boolean_t tbi_compatibility_en;
 892    boolean_t tbi_compatibility_on;
 893    boolean_t fc_send_xon;
 894    boolean_t report_tx_early;
 895    boolean_t adaptive_ifs;
 896    boolean_t ifs_params_forced;
 897    boolean_t in_ifs_mode;
 898};
 899
 900
 901#define E1000_EEPROM_SWDPIN0   0x0001   /* SWDPIN 0 EEPROM Value */
 902#define E1000_EEPROM_LED_LOGIC 0x0020   /* Led Logic Word */
 903
 904/* Register Bit Masks */
 905/* Device Control */
 906#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
 907#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
 908#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
 909#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
 910#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
 911#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
 912#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
 913#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
 914#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
 915#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
 916#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
 917#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
 918#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
 919#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
 920#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
 921#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
 922#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
 923#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
 924#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
 925#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
 926#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
 927#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
 928#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
 929#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
 930#define E1000_CTRL_RST      0x04000000  /* Global reset */
 931#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
 932#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
 933#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
 934#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
 935#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
 936
 937/* Device Status */
 938#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
 939#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
 940#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
 941#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
 942#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
 943#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
 944#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
 945#define E1000_STATUS_SPEED_MASK 0x000000C0
 946#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
 947#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
 948#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
 949#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
 950#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
 951#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
 952#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
 953#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
 954#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
 955
 956/* Constants used to intrepret the masked PCI-X bus speed. */
 957#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed  50-66 MHz */
 958#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed  66-100 MHz */
 959#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
 960
 961/* EEPROM/Flash Control */
 962#define E1000_EECD_SK        0x00000001 /* EEPROM Clock */
 963#define E1000_EECD_CS        0x00000002 /* EEPROM Chip Select */
 964#define E1000_EECD_DI        0x00000004 /* EEPROM Data In */
 965#define E1000_EECD_DO        0x00000008 /* EEPROM Data Out */
 966#define E1000_EECD_FWE_MASK  0x00000030 
 967#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
 968#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
 969#define E1000_EECD_FWE_SHIFT 4
 970#define E1000_EECD_SIZE      0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
 971#define E1000_EECD_REQ       0x00000040 /* EEPROM Access Request */
 972#define E1000_EECD_GNT       0x00000080 /* EEPROM Access Grant */
 973#define E1000_EECD_PRES      0x00000100 /* EEPROM Present */
 974
 975/* EEPROM Read */
 976#define E1000_EERD_START      0x00000001 /* Start Read */
 977#define E1000_EERD_DONE       0x00000010 /* Read Done */
 978#define E1000_EERD_ADDR_SHIFT 8
 979#define E1000_EERD_ADDR_MASK  0x0000FF00 /* Read Address */
 980#define E1000_EERD_DATA_SHIFT 16
 981#define E1000_EERD_DATA_MASK  0xFFFF0000 /* Read Data */
 982
 983/* Extended Device Control */
 984#define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */ 
 985#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
 986#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
 987#define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
 988#define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
 989#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
 990#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
 991#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
 992#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
 993#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
 994#define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
 995#define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
 996#define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
 997#define E1000_CTRL_EXT_SDP7_DIR  0x00000800 /* Direction of SDP7 0=in 1=out */
 998#define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
 999#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
1000#define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */

1001#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
1002#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1003#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1004#define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
1005#define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
1006#define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
1007#define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
1008#define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
1009#define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
1010
1011/* MDI Control */
1012#define E1000_MDIC_DATA_MASK 0x0000FFFF
1013#define E1000_MDIC_REG_MASK  0x001F0000
1014#define E1000_MDIC_REG_SHIFT 16
1015#define E1000_MDIC_PHY_MASK  0x03E00000
1016#define E1000_MDIC_PHY_SHIFT 21
1017#define E1000_MDIC_OP_WRITE  0x04000000
1018#define E1000_MDIC_OP_READ   0x08000000
1019#define E1000_MDIC_READY     0x10000000
1020#define E1000_MDIC_INT_EN    0x20000000
1021#define E1000_MDIC_ERROR     0x40000000
1022
1023/* LED Control */
1024#define E1000_LEDCTL_LED0_MODE_MASK  0x0000000F
1025#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1026#define E1000_LEDCTL_LED0_IVRT       0x00000040
1027#define E1000_LEDCTL_LED0_BLINK      0x00000080
1028#define E1000_LEDCTL_LED1_MODE_MASK  0x00000F00
1029#define E1000_LEDCTL_LED1_MODE_SHIFT 8
1030#define E1000_LEDCTL_LED1_IVRT       0x00004000
1031#define E1000_LEDCTL_LED1_BLINK      0x00008000
1032#define E1000_LEDCTL_LED2_MODE_MASK  0x000F0000
1033#define E1000_LEDCTL_LED2_MODE_SHIFT 16
1034#define E1000_LEDCTL_LED2_IVRT       0x00400000
1035#define E1000_LEDCTL_LED2_BLINK      0x00800000
1036#define E1000_LEDCTL_LED3_MODE_MASK  0x0F000000
1037#define E1000_LEDCTL_LED3_MODE_SHIFT 24
1038#define E1000_LEDCTL_LED3_IVRT       0x40000000
1039#define E1000_LEDCTL_LED3_BLINK      0x80000000
1040
1041#define E1000_LEDCTL_MODE_LINK_10_1000  0x0
1042#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1043#define E1000_LEDCTL_MODE_LINK_UP       0x2
1044#define E1000_LEDCTL_MODE_ACTIVITY      0x3
1045#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1046#define E1000_LEDCTL_MODE_LINK_10       0x5
1047#define E1000_LEDCTL_MODE_LINK_100      0x6
1048#define E1000_LEDCTL_MODE_LINK_1000     0x7
1049#define E1000_LEDCTL_MODE_PCIX_MODE     0x8
1050#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
1051#define E1000_LEDCTL_MODE_COLLISION     0xA
1052#define E1000_LEDCTL_MODE_BUS_SPEED     0xB
1053#define E1000_LEDCTL_MODE_BUS_SIZE      0xC
1054#define E1000_LEDCTL_MODE_PAUSED        0xD
1055#define E1000_LEDCTL_MODE_LED_ON        0xE
1056#define E1000_LEDCTL_MODE_LED_OFF       0xF
1057
1058/* Receive Address */
1059#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
1060
1061/* Interrupt Cause Read */
1062#define E1000_ICR_TXDW    0x00000001    /* Transmit desc written back */
1063#define E1000_ICR_TXQE    0x00000002    /* Transmit Queue empty */
1064#define E1000_ICR_LSC     0x00000004    /* Link Status Change */
1065#define E1000_ICR_RXSEQ   0x00000008    /* rx sequence error */
1066#define E1000_ICR_RXDMT0  0x00000010    /* rx desc min. threshold (0) */
1067#define E1000_ICR_RXO     0x00000040    /* rx overrun */
1068#define E1000_ICR_RXT0    0x00000080    /* rx timer intr (ring 0) */
1069#define E1000_ICR_MDAC    0x00000200    /* MDIO access complete */
1070#define E1000_ICR_RXCFG   0x00000400    /* RX /c/ ordered set */
1071#define E1000_ICR_GPI_EN0 0x00000800    /* GP Int 0 */
1072#define E1000_ICR_GPI_EN1 0x00001000    /* GP Int 1 */
1073#define E1000_ICR_GPI_EN2 0x00002000    /* GP Int 2 */
1074#define E1000_ICR_GPI_EN3 0x00004000    /* GP Int 3 */
1075#define E1000_ICR_TXD_LOW 0x00008000
1076#define E1000_ICR_SRPD    0x00010000
1077
1078/* Interrupt Cause Set */
1079#define E1000_ICS_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
1080#define E1000_ICS_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
1081#define E1000_ICS_LSC     E1000_ICR_LSC         /* Link Status Change */
1082#define E1000_ICS_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
1083#define E1000_ICS_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
1084#define E1000_ICS_RXO     E1000_ICR_RXO         /* rx overrun */
1085#define E1000_ICS_RXT0    E1000_ICR_RXT0        /* rx timer intr */
1086#define E1000_ICS_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
1087#define E1000_ICS_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
1088#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
1089#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
1090#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
1091#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
1092#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1093#define E1000_ICS_SRPD    E1000_ICR_SRPD
1094
1095/* Interrupt Mask Set */
1096#define E1000_IMS_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
1097#define E1000_IMS_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
1098#define E1000_IMS_LSC     E1000_ICR_LSC         /* Link Status Change */
1099#define E1000_IMS_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
1100#define E1000_IMS_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
1101#define E1000_IMS_RXO     E1000_ICR_RXO         /* rx overrun */
1102#define E1000_IMS_RXT0    E1000_ICR_RXT0        /* rx timer intr */
1103#define E1000_IMS_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
1104#define E1000_IMS_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
1105#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
1106#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
1107#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
1108#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
1109#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1110#define E1000_IMS_SRPD    E1000_ICR_SRPD
1111
1112/* Interrupt Mask Clear */
1113#define E1000_IMC_TXDW    E1000_ICR_TXDW        /* Transmit desc written back */
1114#define E1000_IMC_TXQE    E1000_ICR_TXQE        /* Transmit Queue empty */
1115#define E1000_IMC_LSC     E1000_ICR_LSC         /* Link Status Change */
1116#define E1000_IMC_RXSEQ   E1000_ICR_RXSEQ       /* rx sequence error */
1117#define E1000_IMC_RXDMT0  E1000_ICR_RXDMT0      /* rx desc min. threshold */
1118#define E1000_IMC_RXO     E1000_ICR_RXO         /* rx overrun */
1119#define E1000_IMC_RXT0    E1000_ICR_RXT0        /* rx timer intr */
1120#define E1000_IMC_MDAC    E1000_ICR_MDAC        /* MDIO access complete */
1121#define E1000_IMC_RXCFG   E1000_ICR_RXCFG       /* RX /c/ ordered set */
1122#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0     /* GP Int 0 */
1123#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1     /* GP Int 1 */
1124#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2     /* GP Int 2 */
1125#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3     /* GP Int 3 */
1126#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1127#define E1000_IMC_SRPD    E1000_ICR_SRPD
1128
1129/* Receive Control */
1130#define E1000_RCTL_RST          0x00000001      /* Software reset */
1131#define E1000_RCTL_EN           0x00000002      /* enable */
1132#define E1000_RCTL_SBP          0x00000004      /* store bad packet */
1133#define E1000_RCTL_UPE          0x00000008      /* unicast promiscuous enable */
1134#define E1000_RCTL_MPE          0x00000010      /* multicast promiscuous enab */
1135#define E1000_RCTL_LPE          0x00000020      /* long packet enable */
1136#define E1000_RCTL_LBM_NO       0x00000000      /* no loopback mode */
1137#define E1000_RCTL_LBM_MAC      0x00000040      /* MAC loopback mode */
1138#define E1000_RCTL_LBM_SLP      0x00000080      /* serial link loopback mode */
1139#define E1000_RCTL_LBM_TCVR     0x000000C0      /* tcvr loopback mode */
1140#define E1000_RCTL_RDMTS_HALF   0x00000000      /* rx desc min threshold size */
1141#define E1000_RCTL_RDMTS_QUAT   0x00000100      /* rx desc min threshold size */
1142#define E1000_RCTL_RDMTS_EIGTH  0x00000200      /* rx desc min threshold size */
1143#define E1000_RCTL_MO_SHIFT     12              /* multicast offset shift */
1144#define E1000_RCTL_MO_0         0x00000000      /* multicast offset 11:0 */
1145#define E1000_RCTL_MO_1         0x00001000      /* multicast offset 12:1 */
1146#define E1000_RCTL_MO_2         0x00002000      /* multicast offset 13:2 */
1147#define E1000_RCTL_MO_3         0x00003000      /* multicast offset 15:4 */
1148#define E1000_RCTL_MDR          0x00004000      /* multicast desc ring 0 */
1149#define E1000_RCTL_BAM          0x00008000      /* broadcast enable */
1150/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1151#define E1000_RCTL_SZ_2048      0x00000000      /* rx buffer size 2048 */
1152#define E1000_RCTL_SZ_1024      0x00010000      /* rx buffer size 1024 */
1153#define E1000_RCTL_SZ_512       0x00020000      /* rx buffer size 512 */
1154#define E1000_RCTL_SZ_256       0x00030000      /* rx buffer size 256 */
1155/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1156#define E1000_RCTL_SZ_16384     0x00010000      /* rx buffer size 16384 */
1157#define E1000_RCTL_SZ_8192      0x00020000      /* rx buffer size 8192 */
1158#define E1000_RCTL_SZ_4096      0x00030000      /* rx buffer size 4096 */
1159#define E1000_RCTL_VFE          0x00040000      /* vlan filter enable */
1160#define E1000_RCTL_CFIEN        0x00080000      /* canonical form enable */
1161#define E1000_RCTL_CFI          0x00100000      /* canonical form indicator */
1162#define E1000_RCTL_DPF          0x00400000      /* discard pause frames */
1163#define E1000_RCTL_PMCF         0x00800000      /* pass MAC control frames */
1164#define E1000_RCTL_BSEX         0x02000000      /* Buffer size extension */
1165
1166/* Receive Descriptor */
1167#define E1000_RDT_DELAY 0x0000ffff      /* Delay timer (1=1024us) */
1168#define E1000_RDT_FPDB  0x80000000      /* Flush descriptor block */
1169#define E1000_RDLEN_LEN 0x0007ff80      /* descriptor length */
1170#define E1000_RDH_RDH   0x0000ffff      /* receive descriptor head */
1171#define E1000_RDT_RDT   0x0000ffff      /* receive descriptor tail */
1172
1173/* Flow Control */
1174#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
1175#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
1176#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
1177#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
1178
1179/* Receive Descriptor Control */
1180#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1181#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1182#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1183#define E1000_RXDCTL_GRAN    0x01000000 /* RXDCTL Granularity */
1184
1185/* Transmit Descriptor Control */
1186#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1187#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1188#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1189#define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
1190#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1191#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1192
1193/* Transmit Configuration Word */
1194#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
1195#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
1196#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
1197#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
1198#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
1199#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
1200#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
1201#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
1202#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
1203#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
1204
1205/* Receive Configuration Word */
1206#define E1000_RXCW_CW    0x0000ffff     /* RxConfigWord mask */
1207#define E1000_RXCW_NC    0x04000000     /* Receive config no carrier */
1208#define E1000_RXCW_IV    0x08000000     /* Receive config invalid */
1209#define E1000_RXCW_CC    0x10000000     /* Receive config change */
1210#define E1000_RXCW_C     0x20000000     /* Receive config */
1211#define E1000_RXCW_SYNCH 0x40000000     /* Receive config synch */
1212#define E1000_RXCW_ANC   0x80000000     /* Auto-neg complete */
1213
1214/* Transmit Control */
1215#define E1000_TCTL_RST    0x00000001    /* software reset */
1216#define E1000_TCTL_EN     0x00000002    /* enable tx */
1217#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
1218#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
1219#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
1220#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
1221#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
1222#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
1223#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
1224#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
1225
1226/* Receive Checksum Control */
1227#define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
1228#define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
1229#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
1230#define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
1231
1232/* Definitions for power management and wakeup registers */
1233/* Wake Up Control */
1234#define E1000_WUC_APME       0x00000001 /* APM Enable */
1235#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
1236#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1237#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
1238
1239/* Wake Up Filter Control */
1240#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1241#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
1242#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
1243#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
1244#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
1245#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
1246#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1247#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1248#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1249#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1250#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1251#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1252#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1253#define E1000_WUFC_FLX_OFFSET 16       /* Offset to the Flexible Filters bits */
1254#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1255
1256/* Wake Up Status */
1257#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1258#define E1000_WUS_MAG  0x00000002 /* Magic Packet Received */
1259#define E1000_WUS_EX   0x00000004 /* Directed Exact Received */
1260#define E1000_WUS_MC   0x00000008 /* Directed Multicast Received */
1261#define E1000_WUS_BC   0x00000010 /* Broadcast Received */
1262#define E1000_WUS_ARP  0x00000020 /* ARP Request Packet Received */
1263#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1264#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1265#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1266#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1267#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1268#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1269#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1270
1271/* Management Control */
1272#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
1273#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
1274#define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
1275#define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
1276#define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
1277#define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
1278#define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
1279#define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
1280#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
1281#define E1000_MANC_NEIGHBOR_EN   0x00004000 /* Enable Neighbor Discovery 
1282                                             * Filtering */
1283#define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
1284#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
1285#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
1286#define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
1287#define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
1288#define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
1289#define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
1290#define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
1291#define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
1292
1293#define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
1294#define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
1295
1296/* Wake Up Packet Length */
1297#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
1298
1299#define E1000_MDALIGN          4096
1300
1301/* EEPROM Commands */
1302#define EEPROM_READ_OPCODE  0x6  /* EERPOM read opcode */
1303#define EEPROM_WRITE_OPCODE 0x5  /* EERPOM write opcode */
1304#define EEPROM_ERASE_OPCODE 0x7  /* EERPOM erase opcode */
1305#define EEPROM_EWEN_OPCODE  0x13 /* EERPOM erase/write enable */
1306#define EEPROM_EWDS_OPCODE  0x10 /* EERPOM erast/write disable */
1307
1308/* EEPROM Word Offsets */
1309#define EEPROM_COMPAT              0x0003
1310#define EEPROM_ID_LED_SETTINGS     0x0004
1311#define EEPROM_INIT_CONTROL1_REG   0x000A
1312#define EEPROM_INIT_CONTROL2_REG   0x000F
1313#define EEPROM_FLASH_VERSION       0x0032
1314#define EEPROM_CHECKSUM_REG        0x003F
1315
1316/* Word definitions for ID LED Settings */
1317#define ID_LED_RESERVED_0000 0x0000
1318#define ID_LED_RESERVED_FFFF 0xFFFF
1319#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2 << 12) | \
1320                              (ID_LED_OFF1_OFF2 << 8) | \
1321                              (ID_LED_DEF1_DEF2 << 4) | \
1322                              (ID_LED_DEF1_DEF2))
1323#define ID_LED_DEF1_DEF2     0x1
1324#define ID_LED_DEF1_ON2      0x2
1325#define ID_LED_DEF1_OFF2     0x3
1326#define ID_LED_ON1_DEF2      0x4
1327#define ID_LED_ON1_ON2       0x5
1328#define ID_LED_ON1_OFF2      0x6
1329#define ID_LED_OFF1_DEF2     0x7
1330#define ID_LED_OFF1_ON2      0x8
1331#define ID_LED_OFF1_OFF2     0x9
1332
1333/* Mask bits for fields in Word 0x03 of the EEPROM */
1334#define EEPROM_COMPAT_SERVER 0x0400
1335#define EEPROM_COMPAT_CLIENT 0x0200
1336
1337/* Mask bits for fields in Word 0x0a of the EEPROM */
1338#define EEPROM_WORD0A_ILOS   0x0010
1339#define EEPROM_WORD0A_SWDPIO 0x01E0
1340#define EEPROM_WORD0A_LRST   0x0200
1341#define EEPROM_WORD0A_FD     0x0400
1342#define EEPROM_WORD0A_66MHZ  0x0800
1343
1344/* Mask bits for fields in Word 0x0f of the EEPROM */
1345#define EEPROM_WORD0F_PAUSE_MASK 0x3000
1346#define EEPROM_WORD0F_PAUSE      0x1000
1347#define EEPROM_WORD0F_ASM_DIR    0x2000
1348#define EEPROM_WORD0F_ANE        0x0800
1349#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1350
1351/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
1352#define EEPROM_SUM 0xBABA
1353
1354/* EEPROM Map defines (WORD OFFSETS)*/
1355#define EEPROM_NODE_ADDRESS_BYTE_0 0
1356#define EEPROM_PBA_BYTE_1          8
1357
1358/* EEPROM Map Sizes (Byte Counts) */
1359#define PBA_SIZE 4
1360
1361/* Collision related configuration parameters */
1362#define E1000_COLLISION_THRESHOLD       16
1363#define E1000_CT_SHIFT                  4
1364#define E1000_COLLISION_DISTANCE        64
1365#define E1000_FDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
1366#define E1000_HDX_COLLISION_DISTANCE    E1000_COLLISION_DISTANCE
1367#define E1000_GB_HDX_COLLISION_DISTANCE 512
1368#define E1000_COLD_SHIFT                12
1369
1370/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
1371#define REQ_TX_DESCRIPTOR_MULTIPLE  8
1372#define REQ_RX_DESCRIPTOR_MULTIPLE  8
1373
1374/* Default values for the transmit IPG register */
1375#define DEFAULT_82542_TIPG_IPGT        10
1376#define DEFAULT_82543_TIPG_IPGT_FIBER  9
1377#define DEFAULT_82543_TIPG_IPGT_COPPER 8
1378
1379#define E1000_TIPG_IPGT_MASK  0x000003FF
1380#define E1000_TIPG_IPGR1_MASK 0x000FFC00
1381#define E1000_TIPG_IPGR2_MASK 0x3FF00000
1382
1383#define DEFAULT_82542_TIPG_IPGR1 2
1384#define DEFAULT_82543_TIPG_IPGR1 8
1385#define E1000_TIPG_IPGR1_SHIFT  10
1386
1387#define DEFAULT_82542_TIPG_IPGR2 10
1388#define DEFAULT_82543_TIPG_IPGR2 6
1389#define E1000_TIPG_IPGR2_SHIFT  20
1390
1391#define E1000_TXDMAC_DPP 0x00000001
1392
1393/* Adaptive IFS defines */
1394#define TX_THRESHOLD_START     8
1395#define TX_THRESHOLD_INCREMENT 10
1396#define TX_THRESHOLD_DECREMENT 1
1397#define TX_THRESHOLD_STOP      190
1398#define TX_THRESHOLD_DISABLE   0
1399#define TX_THRESHOLD_TIMER_MS  10000
1400#define MIN_NUM_XMITS          1000
1401#define IFS_MAX                80
1402#define IFS_STEP               10
1403#define IFS_MIN                40
1404#define IFS_RATIO              4
1405
1406/* PBA constants */
1407#define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
1408#define E1000_PBA_24K 0x0018
1409#define E1000_PBA_40K 0x0028
1410#define E1000_PBA_48K 0x0030    /* 48KB, default RX allocation */
1411
1412/* Flow Control Constants */
1413#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
1414#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1415#define FLOW_CONTROL_TYPE         0x8808
1416
1417/* The historical defaults for the flow control values are given below. */
1418#define FC_DEFAULT_HI_THRESH        (0x8000)    /* 32KB */
1419#define FC_DEFAULT_LO_THRESH        (0x4000)    /* 16KB */
1420#define FC_DEFAULT_TX_TIMER         (0x100)     /* ~130 us */
1421
1422/* PCIX Config space */
1423#define PCIX_COMMAND_REGISTER    0xE6
1424#define PCIX_STATUS_REGISTER_LO  0xE8
1425#define PCIX_STATUS_REGISTER_HI  0xEA
1426
1427#define PCIX_COMMAND_MMRBC_MASK      0x000C
1428#define PCIX_COMMAND_MMRBC_SHIFT     0x2
1429#define PCIX_STATUS_HI_MMRBC_MASK    0x0060
1430#define PCIX_STATUS_HI_MMRBC_SHIFT   0x5
1431#define PCIX_STATUS_HI_MMRBC_4K      0x3
1432#define PCIX_STATUS_HI_MMRBC_2K      0x2
1433
1434
1435/* The number of bits that we need to shift right to move the "pause"
1436 * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
1437 * in the TXCW register 
1438 */
1439#define PAUSE_SHIFT 5
1440
1441/* The number of bits that we need to shift left to move the "SWDPIO"
1442 * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
1443 * in the CTRL register 
1444 */
1445#define SWDPIO_SHIFT 17
1446
1447/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
1448 * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
1449 * Extended CTRL register.
1450 * in the CTRL register 
1451 */
1452#define SWDPIO__EXT_SHIFT 4
1453
1454/* The number of bits that we need to shift left to move the "ILOS"
1455 * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
1456 * in the CTRL register 
1457 */
1458#define ILOS_SHIFT  3
1459
1460
1461#define RECEIVE_BUFFER_ALIGN_SIZE  (256)
1462
1463/* The number of milliseconds we wait for auto-negotiation to complete */
1464#define LINK_UP_TIMEOUT             500
1465
1466#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1467
1468/* The carrier extension symbol, as received by the NIC. */
1469#define CARRIER_EXTENSION   0x0F
1470
1471/* TBI_ACCEPT macro definition:
1472 *
1473 * This macro requires:
1474 *      adapter = a pointer to struct e1000_hw 
1475 *      status = the 8 bit status field of the RX descriptor with EOP set
1476 *      error = the 8 bit error field of the RX descriptor with EOP set
1477 *      length = the sum of all the length fields of the RX descriptors that
1478 *               make up the current frame
1479 *      last_byte = the last byte of the frame DMAed by the hardware
1480 *      max_frame_length = the maximum frame length we want to accept.
1481 *      min_frame_length = the minimum frame length we want to accept.
1482 *
1483 * This macro is a conditional that should be used in the interrupt 
1484 * handler's Rx processing routine when RxErrors have been detected.
1485 *
1486 * Typical use:
1487 *  ...
1488 *  if (TBI_ACCEPT) {
1489 *      accept_frame = TRUE;
1490 *      e1000_tbi_adjust_stats(adapter, MacAddress);
1491 *      frame_length--;
1492 *  } else {
1493 *      accept_frame = FALSE;
1494 *  }
1495 *  ...
1496 */
1497
1498#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1499    ((adapter)->tbi_compatibility_on && \
1500     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1501     ((last_byte) == CARRIER_EXTENSION) && \
1502     (((status) & E1000_RXD_STAT_VP) ? \
1503          (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1504           ((length) <= ((adapter)->max_frame_size + 1))) : \
1505          (((length) > (adapter)->min_frame_size) && \
1506           ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1507
1508
1509/* Structures, enums, and macros for the PHY */
1510
1511/* Bit definitions for the Management Data IO (MDIO) and Management Data
1512 * Clock (MDC) pins in the Device Control Register.
1513 */
1514#define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
1515#define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
1516#define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
1517#define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
1518#define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
1519#define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
1520#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
1521#define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
1522
1523/* PHY 1000 MII Register/Bit Definitions */
1524/* PHY Registers defined by IEEE */
1525#define PHY_CTRL         0x00 /* Control Register */
1526#define PHY_STATUS       0x01 /* Status Regiser */
1527#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
1528#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
1529#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
1530#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
1531#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
1532#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
1533#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1534#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
1535#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1536#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
1537
1538/* M88E1000 Specific Registers */
1539#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
1540#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
1541#define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
1542#define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
1543#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
1544#define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
1545
1546#define MAX_PHY_REG_ADDRESS 0x1F        /* 5 bit address bus (0-0x1F) */
1547
1548/* PHY Control Register */
1549#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
1550#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
1551#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
1552#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
1553#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
1554#define MII_CR_POWER_DOWN       0x0800  /* Power down */
1555#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
1556#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
1557#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
1558#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
1559
1560/* PHY Status Register */
1561#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
1562#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
1563#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
1564#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
1565#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
1566#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
1567#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1568#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
1569#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
1570#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
1571#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
1572#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
1573#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
1574#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
1575#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
1576
1577/* Autoneg Advertisement Register */
1578#define NWAY_AR_SELECTOR_FIELD 0x0001   /* indicates IEEE 802.3 CSMA/CD */
1579#define NWAY_AR_10T_HD_CAPS    0x0020   /* 10T   Half Duplex Capable */
1580#define NWAY_AR_10T_FD_CAPS    0x0040   /* 10T   Full Duplex Capable */
1581#define NWAY_AR_100TX_HD_CAPS  0x0080   /* 100TX Half Duplex Capable */
1582#define NWAY_AR_100TX_FD_CAPS  0x0100   /* 100TX Full Duplex Capable */
1583#define NWAY_AR_100T4_CAPS     0x0200   /* 100T4 Capable */
1584#define NWAY_AR_PAUSE          0x0400   /* Pause operation desired */
1585#define NWAY_AR_ASM_DIR        0x0800   /* Asymmetric Pause Direction bit */
1586#define NWAY_AR_REMOTE_FAULT   0x2000   /* Remote Fault detected */
1587#define NWAY_AR_NEXT_PAGE      0x8000   /* Next Page ability supported */
1588
1589/* Link Partner Ability Register (Base Page) */
1590#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1591#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
1592#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
1593#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
1594#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
1595#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
1596#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
1597#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
1598#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
1599#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
1600#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
1601
1602/* Autoneg Expansion Register */
1603#define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
1604#define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
1605#define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
1606#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1607#define NWAY_ER_PAR_DETECT_FAULT  0x0100 /* LP is 100TX Full Duplex Capable */
1608
1609/* Next Page TX Register */
1610#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1611#define NPTX_TOGGLE         0x0800 /* Toggles between exchanges
1612                                    * of different NP
1613                                    */
1614#define NPTX_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg
1615                                    * 0 = cannot comply with msg
1616                                    */
1617#define NPTX_MSG_PAGE       0x2000 /* formatted(1)/unformatted(0) pg */
1618#define NPTX_NEXT_PAGE      0x8000 /* 1 = addition NP will follow 
1619                                    * 0 = sending last NP
1620                                    */
1621
1622/* Link Partner Next Page Register */
1623#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1624#define LP_RNPR_TOGGLE         0x0800 /* Toggles between exchanges
1625                                       * of different NP
1626                                       */
1627#define LP_RNPR_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg 
1628                                       * 0 = cannot comply with msg
1629                                       */
1630#define LP_RNPR_MSG_PAGE       0x2000  /* formatted(1)/unformatted(0) pg */
1631#define LP_RNPR_ACKNOWLDGE     0x4000  /* 1 = ACK / 0 = NO ACK */
1632#define LP_RNPR_NEXT_PAGE      0x8000  /* 1 = addition NP will follow
1633                                        * 0 = sending last NP 
1634                                        */
1635
1636/* 1000BASE-T Control Register */
1637#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
1638#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
1639#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
1640#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
1641                                        /* 0=DTE device */
1642#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
1643                                        /* 0=Configure PHY as Slave */
1644#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
1645                                        /* 0=Automatic Master/Slave config */
1646#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1647#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
1648#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
1649#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
1650#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
1651
1652/* 1000BASE-T Status Register */
1653#define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
1654#define SR_1000T_ASYM_PAUSE_DIR   0x0100 /* LP asymmetric pause direction bit */
1655#define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
1656#define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
1657#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1658#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
1659#define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local TX is Master, 0=Slave */
1660#define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
1661#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
1662#define SR_1000T_LOCAL_RX_STATUS_SHIFT  13
1663
1664/* Extended Status Register */
1665#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
1666#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
1667#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
1668#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
1669
1670#define PHY_TX_POLARITY_MASK   0x0100 /* register 10h bit 8 (polarity bit) */
1671#define PHY_TX_NORMAL_POLARITY 0      /* register 10h bit 8 (normal polarity) */
1672
1673#define AUTO_POLARITY_DISABLE  0x0010 /* register 11h bit 4 */
1674                                      /* (0=enable, 1=disable) */
1675
1676/* M88E1000 PHY Specific Control Register */
1677#define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
1678#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
1679#define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
1680#define M88E1000_PSCR_CLK125_DISABLE    0x0010 /* 1=CLK125 low, 
1681                                                * 0=CLK125 toggling
1682                                                */
1683#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
1684                                               /* Manual MDI configuration */
1685#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
1686#define M88E1000_PSCR_AUTO_X_1000T     0x0040  /* 1000BASE-T: Auto crossover,
1687                                                *  100BASE-TX/10BASE-T: 
1688                                                *  MDI Mode
1689                                                */
1690#define M88E1000_PSCR_AUTO_X_MODE      0x0060  /* Auto crossover enabled 
1691                                                * all speeds. 
1692                                                */
1693#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 
1694                                        /* 1=Enable Extended 10BASE-T distance
1695                                         * (Lower 10BASE-T RX Threshold)
1696                                         * 0=Normal 10BASE-T RX Threshold */
1697#define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
1698                                        /* 1=5-Bit interface in 100BASE-TX
1699                                         * 0=MII interface in 100BASE-TX */
1700#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
1701#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
1702#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
1703
1704#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT    1
1705#define M88E1000_PSCR_AUTO_X_MODE_SHIFT          5
1706#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
1707
1708/* M88E1000 PHY Specific Status Register */
1709#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
1710#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
1711#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
1712#define M88E1000_PSSR_CABLE_LENGTH       0x0380 /* 0=<50M;1=50-80M;2=80-110M;
1713                                            * 3=110-140M;4=>140M */
1714#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
1715#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
1716#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
1717#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
1718#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
1719#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
1720#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
1721#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
1722
1723#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
1724#define M88E1000_PSSR_MDIX_SHIFT         6
1725#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1726
1727/* M88E1000 Extended PHY Specific Control Register */
1728#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1729#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000 /* 1=Lost lock detect enabled.
1730                                              * Will assert lost lock and bring
1731                                              * link down if idle not seen
1732                                              * within 1ms in 1000BASE-T 
1733                                              */
1734/* Number of times we will attempt to autonegotiate before downshifting if we
1735 * are the master */
1736#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1737#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000    
1738#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
1739#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
1740#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
1741/* Number of times we will attempt to autonegotiate before downshifting if we
1742 * are the slave */
1743#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
1744#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
1745#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
1746#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
1747#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
1748#define M88E1000_EPSCR_TX_CLK_2_5     0x0060 /* 2.5 MHz TX_CLK */
1749#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
1750#define M88E1000_EPSCR_TX_CLK_0       0x0000 /* NO  TX_CLK */
1751
1752/* Bit definitions for valid PHY IDs. */
1753#define M88E1000_E_PHY_ID  0x01410C50
1754#define M88E1000_I_PHY_ID  0x01410C30
1755#define M88E1011_I_PHY_ID  0x01410C20
1756#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
1757#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
1758
1759/* Miscellaneous PHY bit definitions. */
1760#define PHY_PREAMBLE        0xFFFFFFFF
1761#define PHY_SOF             0x01
1762#define PHY_OP_READ         0x02
1763#define PHY_OP_WRITE        0x01
1764#define PHY_TURNAROUND      0x02
1765#define PHY_PREAMBLE_SIZE   32
1766#define MII_CR_SPEED_1000   0x0040
1767#define MII_CR_SPEED_100    0x2000
1768#define MII_CR_SPEED_10     0x0000
1769#define E1000_PHY_ADDRESS   0x01
1770#define PHY_AUTO_NEG_TIME   45  /* 4.5 Seconds */
1771#define PHY_FORCE_TIME      20  /* 2.0 Seconds */
1772#define PHY_REVISION_MASK   0xFFFFFFF0
1773#define DEVICE_SPEED_MASK   0x00000300  /* Device Ctrl Reg Speed Mask */
1774#define REG4_SPEED_MASK     0x01E0
1775#define REG9_SPEED_MASK     0x0300
1776#define ADVERTISE_10_HALF   0x0001
1777#define ADVERTISE_10_FULL   0x0002
1778#define ADVERTISE_100_HALF  0x0004
1779#define ADVERTISE_100_FULL  0x0008
1780#define ADVERTISE_1000_HALF 0x0010
1781#define ADVERTISE_1000_FULL 0x0020
1782#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F  /* Everything but 1000-Half */
1783
1784#endif /* _E1000_HW_H_ */
1785