linux/sound/pci/hda/patch_ca0132.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * HD audio interface patch for Creative CA0132 chip
   4 *
   5 * Copyright (c) 2011, Creative Technology Ltd.
   6 *
   7 * Based on patch_ca0110.c
   8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   9 */
  10
  11#include <linux/init.h>
  12#include <linux/delay.h>
  13#include <linux/slab.h>
  14#include <linux/mutex.h>
  15#include <linux/module.h>
  16#include <linux/firmware.h>
  17#include <linux/kernel.h>
  18#include <linux/types.h>
  19#include <linux/io.h>
  20#include <linux/pci.h>
  21#include <asm/io.h>
  22#include <sound/core.h>
  23#include <sound/hda_codec.h>
  24#include "hda_local.h"
  25#include "hda_auto_parser.h"
  26#include "hda_jack.h"
  27
  28#include "ca0132_regs.h"
  29
  30/* Enable this to see controls for tuning purpose. */
  31/*#define ENABLE_TUNING_CONTROLS*/
  32
  33#ifdef ENABLE_TUNING_CONTROLS
  34#include <sound/tlv.h>
  35#endif
  36
  37#define FLOAT_ZERO      0x00000000
  38#define FLOAT_ONE       0x3f800000
  39#define FLOAT_TWO       0x40000000
  40#define FLOAT_THREE     0x40400000
  41#define FLOAT_FIVE      0x40a00000
  42#define FLOAT_SIX       0x40c00000
  43#define FLOAT_EIGHT     0x41000000
  44#define FLOAT_MINUS_5   0xc0a00000
  45
  46#define UNSOL_TAG_DSP   0x16
  47
  48#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  49#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  50
  51#define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  52#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  53#define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  54
  55#define MASTERCONTROL                           0x80
  56#define MASTERCONTROL_ALLOC_DMA_CHAN            10
  57#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  58
  59#define WIDGET_CHIP_CTRL      0x15
  60#define WIDGET_DSP_CTRL       0x16
  61
  62#define MEM_CONNID_MICIN1     3
  63#define MEM_CONNID_MICIN2     5
  64#define MEM_CONNID_MICOUT1    12
  65#define MEM_CONNID_MICOUT2    14
  66#define MEM_CONNID_WUH        10
  67#define MEM_CONNID_DSP        16
  68#define MEM_CONNID_DMIC       100
  69
  70#define SCP_SET    0
  71#define SCP_GET    1
  72
  73#define EFX_FILE   "ctefx.bin"
  74#define DESKTOP_EFX_FILE   "ctefx-desktop.bin"
  75#define R3DI_EFX_FILE  "ctefx-r3di.bin"
  76
  77#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  78MODULE_FIRMWARE(EFX_FILE);
  79MODULE_FIRMWARE(DESKTOP_EFX_FILE);
  80MODULE_FIRMWARE(R3DI_EFX_FILE);
  81#endif
  82
  83static const char *const dirstr[2] = { "Playback", "Capture" };
  84
  85#define NUM_OF_OUTPUTS 2
  86static const char *const out_type_str[2] = { "Speakers", "Headphone" };
  87enum {
  88        SPEAKER_OUT,
  89        HEADPHONE_OUT,
  90};
  91
  92enum {
  93        DIGITAL_MIC,
  94        LINE_MIC_IN
  95};
  96
  97/* Strings for Input Source Enum Control */
  98static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
  99#define IN_SRC_NUM_OF_INPUTS 3
 100enum {
 101        REAR_MIC,
 102        REAR_LINE_IN,
 103        FRONT_MIC,
 104};
 105
 106enum {
 107#define VNODE_START_NID    0x80
 108        VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 109        VNID_MIC,
 110        VNID_HP_SEL,
 111        VNID_AMIC1_SEL,
 112        VNID_HP_ASEL,
 113        VNID_AMIC1_ASEL,
 114        VNODE_END_NID,
 115#define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 116
 117#define EFFECT_START_NID    0x90
 118#define OUT_EFFECT_START_NID    EFFECT_START_NID
 119        SURROUND = OUT_EFFECT_START_NID,
 120        CRYSTALIZER,
 121        DIALOG_PLUS,
 122        SMART_VOLUME,
 123        X_BASS,
 124        EQUALIZER,
 125        OUT_EFFECT_END_NID,
 126#define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 127
 128#define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 129        ECHO_CANCELLATION = IN_EFFECT_START_NID,
 130        VOICE_FOCUS,
 131        MIC_SVM,
 132        NOISE_REDUCTION,
 133        IN_EFFECT_END_NID,
 134#define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 135
 136        VOICEFX = IN_EFFECT_END_NID,
 137        PLAY_ENHANCEMENT,
 138        CRYSTAL_VOICE,
 139        EFFECT_END_NID,
 140        OUTPUT_SOURCE_ENUM,
 141        INPUT_SOURCE_ENUM,
 142        XBASS_XOVER,
 143        EQ_PRESET_ENUM,
 144        SMART_VOLUME_ENUM,
 145        MIC_BOOST_ENUM,
 146        AE5_HEADPHONE_GAIN_ENUM,
 147        AE5_SOUND_FILTER_ENUM,
 148        ZXR_HEADPHONE_GAIN,
 149        SPEAKER_CHANNEL_CFG_ENUM,
 150        SPEAKER_FULL_RANGE_FRONT,
 151        SPEAKER_FULL_RANGE_REAR,
 152        BASS_REDIRECTION,
 153        BASS_REDIRECTION_XOVER,
 154#define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 155};
 156
 157/* Effects values size*/
 158#define EFFECT_VALS_MAX_COUNT 12
 159
 160/*
 161 * Default values for the effect slider controls, they are in order of their
 162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
 163 * X-bass.
 164 */
 165static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
 166/* Amount of effect level sliders for ca0132_alt controls. */
 167#define EFFECT_LEVEL_SLIDERS 5
 168
 169/* Latency introduced by DSP blocks in milliseconds. */
 170#define DSP_CAPTURE_INIT_LATENCY        0
 171#define DSP_CRYSTAL_VOICE_LATENCY       124
 172#define DSP_PLAYBACK_INIT_LATENCY       13
 173#define DSP_PLAY_ENHANCEMENT_LATENCY    30
 174#define DSP_SPEAKER_OUT_LATENCY         7
 175
 176struct ct_effect {
 177        char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 178        hda_nid_t nid;
 179        int mid; /*effect module ID*/
 180        int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 181        int direct; /* 0:output; 1:input*/
 182        int params; /* number of default non-on/off params */
 183        /*effect default values, 1st is on/off. */
 184        unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 185};
 186
 187#define EFX_DIR_OUT 0
 188#define EFX_DIR_IN  1
 189
 190static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 191        { .name = "Surround",
 192          .nid = SURROUND,
 193          .mid = 0x96,
 194          .reqs = {0, 1},
 195          .direct = EFX_DIR_OUT,
 196          .params = 1,
 197          .def_vals = {0x3F800000, 0x3F2B851F}
 198        },
 199        { .name = "Crystalizer",
 200          .nid = CRYSTALIZER,
 201          .mid = 0x96,
 202          .reqs = {7, 8},
 203          .direct = EFX_DIR_OUT,
 204          .params = 1,
 205          .def_vals = {0x3F800000, 0x3F266666}
 206        },
 207        { .name = "Dialog Plus",
 208          .nid = DIALOG_PLUS,
 209          .mid = 0x96,
 210          .reqs = {2, 3},
 211          .direct = EFX_DIR_OUT,
 212          .params = 1,
 213          .def_vals = {0x00000000, 0x3F000000}
 214        },
 215        { .name = "Smart Volume",
 216          .nid = SMART_VOLUME,
 217          .mid = 0x96,
 218          .reqs = {4, 5, 6},
 219          .direct = EFX_DIR_OUT,
 220          .params = 2,
 221          .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
 222        },
 223        { .name = "X-Bass",
 224          .nid = X_BASS,
 225          .mid = 0x96,
 226          .reqs = {24, 23, 25},
 227          .direct = EFX_DIR_OUT,
 228          .params = 2,
 229          .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
 230        },
 231        { .name = "Equalizer",
 232          .nid = EQUALIZER,
 233          .mid = 0x96,
 234          .reqs = {9, 10, 11, 12, 13, 14,
 235                        15, 16, 17, 18, 19, 20},
 236          .direct = EFX_DIR_OUT,
 237          .params = 11,
 238          .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
 239                       0x00000000, 0x00000000, 0x00000000, 0x00000000,
 240                       0x00000000, 0x00000000, 0x00000000, 0x00000000}
 241        },
 242        { .name = "Echo Cancellation",
 243          .nid = ECHO_CANCELLATION,
 244          .mid = 0x95,
 245          .reqs = {0, 1, 2, 3},
 246          .direct = EFX_DIR_IN,
 247          .params = 3,
 248          .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 249        },
 250        { .name = "Voice Focus",
 251          .nid = VOICE_FOCUS,
 252          .mid = 0x95,
 253          .reqs = {6, 7, 8, 9},
 254          .direct = EFX_DIR_IN,
 255          .params = 3,
 256          .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 257        },
 258        { .name = "Mic SVM",
 259          .nid = MIC_SVM,
 260          .mid = 0x95,
 261          .reqs = {44, 45},
 262          .direct = EFX_DIR_IN,
 263          .params = 1,
 264          .def_vals = {0x00000000, 0x3F3D70A4}
 265        },
 266        { .name = "Noise Reduction",
 267          .nid = NOISE_REDUCTION,
 268          .mid = 0x95,
 269          .reqs = {4, 5},
 270          .direct = EFX_DIR_IN,
 271          .params = 1,
 272          .def_vals = {0x3F800000, 0x3F000000}
 273        },
 274        { .name = "VoiceFX",
 275          .nid = VOICEFX,
 276          .mid = 0x95,
 277          .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
 278          .direct = EFX_DIR_IN,
 279          .params = 8,
 280          .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
 281                       0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
 282                       0x00000000}
 283        }
 284};
 285
 286/* Tuning controls */
 287#ifdef ENABLE_TUNING_CONTROLS
 288
 289enum {
 290#define TUNING_CTL_START_NID  0xC0
 291        WEDGE_ANGLE = TUNING_CTL_START_NID,
 292        SVM_LEVEL,
 293        EQUALIZER_BAND_0,
 294        EQUALIZER_BAND_1,
 295        EQUALIZER_BAND_2,
 296        EQUALIZER_BAND_3,
 297        EQUALIZER_BAND_4,
 298        EQUALIZER_BAND_5,
 299        EQUALIZER_BAND_6,
 300        EQUALIZER_BAND_7,
 301        EQUALIZER_BAND_8,
 302        EQUALIZER_BAND_9,
 303        TUNING_CTL_END_NID
 304#define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 305};
 306
 307struct ct_tuning_ctl {
 308        char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 309        hda_nid_t parent_nid;
 310        hda_nid_t nid;
 311        int mid; /*effect module ID*/
 312        int req; /*effect module request*/
 313        int direct; /* 0:output; 1:input*/
 314        unsigned int def_val;/*effect default values*/
 315};
 316
 317static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 318        { .name = "Wedge Angle",
 319          .parent_nid = VOICE_FOCUS,
 320          .nid = WEDGE_ANGLE,
 321          .mid = 0x95,
 322          .req = 8,
 323          .direct = EFX_DIR_IN,
 324          .def_val = 0x41F00000
 325        },
 326        { .name = "SVM Level",
 327          .parent_nid = MIC_SVM,
 328          .nid = SVM_LEVEL,
 329          .mid = 0x95,
 330          .req = 45,
 331          .direct = EFX_DIR_IN,
 332          .def_val = 0x3F3D70A4
 333        },
 334        { .name = "EQ Band0",
 335          .parent_nid = EQUALIZER,
 336          .nid = EQUALIZER_BAND_0,
 337          .mid = 0x96,
 338          .req = 11,
 339          .direct = EFX_DIR_OUT,
 340          .def_val = 0x00000000
 341        },
 342        { .name = "EQ Band1",
 343          .parent_nid = EQUALIZER,
 344          .nid = EQUALIZER_BAND_1,
 345          .mid = 0x96,
 346          .req = 12,
 347          .direct = EFX_DIR_OUT,
 348          .def_val = 0x00000000
 349        },
 350        { .name = "EQ Band2",
 351          .parent_nid = EQUALIZER,
 352          .nid = EQUALIZER_BAND_2,
 353          .mid = 0x96,
 354          .req = 13,
 355          .direct = EFX_DIR_OUT,
 356          .def_val = 0x00000000
 357        },
 358        { .name = "EQ Band3",
 359          .parent_nid = EQUALIZER,
 360          .nid = EQUALIZER_BAND_3,
 361          .mid = 0x96,
 362          .req = 14,
 363          .direct = EFX_DIR_OUT,
 364          .def_val = 0x00000000
 365        },
 366        { .name = "EQ Band4",
 367          .parent_nid = EQUALIZER,
 368          .nid = EQUALIZER_BAND_4,
 369          .mid = 0x96,
 370          .req = 15,
 371          .direct = EFX_DIR_OUT,
 372          .def_val = 0x00000000
 373        },
 374        { .name = "EQ Band5",
 375          .parent_nid = EQUALIZER,
 376          .nid = EQUALIZER_BAND_5,
 377          .mid = 0x96,
 378          .req = 16,
 379          .direct = EFX_DIR_OUT,
 380          .def_val = 0x00000000
 381        },
 382        { .name = "EQ Band6",
 383          .parent_nid = EQUALIZER,
 384          .nid = EQUALIZER_BAND_6,
 385          .mid = 0x96,
 386          .req = 17,
 387          .direct = EFX_DIR_OUT,
 388          .def_val = 0x00000000
 389        },
 390        { .name = "EQ Band7",
 391          .parent_nid = EQUALIZER,
 392          .nid = EQUALIZER_BAND_7,
 393          .mid = 0x96,
 394          .req = 18,
 395          .direct = EFX_DIR_OUT,
 396          .def_val = 0x00000000
 397        },
 398        { .name = "EQ Band8",
 399          .parent_nid = EQUALIZER,
 400          .nid = EQUALIZER_BAND_8,
 401          .mid = 0x96,
 402          .req = 19,
 403          .direct = EFX_DIR_OUT,
 404          .def_val = 0x00000000
 405        },
 406        { .name = "EQ Band9",
 407          .parent_nid = EQUALIZER,
 408          .nid = EQUALIZER_BAND_9,
 409          .mid = 0x96,
 410          .req = 20,
 411          .direct = EFX_DIR_OUT,
 412          .def_val = 0x00000000
 413        }
 414};
 415#endif
 416
 417/* Voice FX Presets */
 418#define VOICEFX_MAX_PARAM_COUNT 9
 419
 420struct ct_voicefx {
 421        char *name;
 422        hda_nid_t nid;
 423        int mid;
 424        int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 425};
 426
 427struct ct_voicefx_preset {
 428        char *name; /*preset name*/
 429        unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 430};
 431
 432static const struct ct_voicefx ca0132_voicefx = {
 433        .name = "VoiceFX Capture Switch",
 434        .nid = VOICEFX,
 435        .mid = 0x95,
 436        .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
 437};
 438
 439static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 440        { .name = "Neutral",
 441          .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
 442                    0x44FA0000, 0x3F800000, 0x3F800000,
 443                    0x3F800000, 0x00000000, 0x00000000 }
 444        },
 445        { .name = "Female2Male",
 446          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 447                    0x44FA0000, 0x3F19999A, 0x3F866666,
 448                    0x3F800000, 0x00000000, 0x00000000 }
 449        },
 450        { .name = "Male2Female",
 451          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 452                    0x450AC000, 0x4017AE14, 0x3F6B851F,
 453                    0x3F800000, 0x00000000, 0x00000000 }
 454        },
 455        { .name = "ScrappyKid",
 456          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 457                    0x44FA0000, 0x40400000, 0x3F28F5C3,
 458                    0x3F800000, 0x00000000, 0x00000000 }
 459        },
 460        { .name = "Elderly",
 461          .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
 462                    0x44E10000, 0x3FB33333, 0x3FB9999A,
 463                    0x3F800000, 0x3E3A2E43, 0x00000000 }
 464        },
 465        { .name = "Orc",
 466          .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
 467                    0x45098000, 0x3F266666, 0x3FC00000,
 468                    0x3F800000, 0x00000000, 0x00000000 }
 469        },
 470        { .name = "Elf",
 471          .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
 472                    0x45193000, 0x3F8E147B, 0x3F75C28F,
 473                    0x3F800000, 0x00000000, 0x00000000 }
 474        },
 475        { .name = "Dwarf",
 476          .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
 477                    0x45007000, 0x3F451EB8, 0x3F7851EC,
 478                    0x3F800000, 0x00000000, 0x00000000 }
 479        },
 480        { .name = "AlienBrute",
 481          .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 482                    0x451F6000, 0x3F266666, 0x3FA7D945,
 483                    0x3F800000, 0x3CF5C28F, 0x00000000 }
 484        },
 485        { .name = "Robot",
 486          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 487                    0x44FA0000, 0x3FB2718B, 0x3F800000,
 488                    0xBC07010E, 0x00000000, 0x00000000 }
 489        },
 490        { .name = "Marine",
 491          .vals = { 0x3F800000, 0x43C20000, 0x44906000,
 492                    0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 493                    0x3F0A3D71, 0x00000000, 0x00000000 }
 494        },
 495        { .name = "Emo",
 496          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 497                    0x44FA0000, 0x3F800000, 0x3F800000,
 498                    0x3E4CCCCD, 0x00000000, 0x00000000 }
 499        },
 500        { .name = "DeepVoice",
 501          .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 502                    0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 503                    0x3F800000, 0x00000000, 0x00000000 }
 504        },
 505        { .name = "Munchkin",
 506          .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 507                    0x44FA0000, 0x3F800000, 0x3F1A043C,
 508                    0x3F800000, 0x00000000, 0x00000000 }
 509        }
 510};
 511
 512/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
 513
 514#define EQ_PRESET_MAX_PARAM_COUNT 11
 515
 516struct ct_eq {
 517        char *name;
 518        hda_nid_t nid;
 519        int mid;
 520        int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
 521};
 522
 523struct ct_eq_preset {
 524        char *name; /*preset name*/
 525        unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
 526};
 527
 528static const struct ct_eq ca0132_alt_eq_enum = {
 529        .name = "FX: Equalizer Preset Switch",
 530        .nid = EQ_PRESET_ENUM,
 531        .mid = 0x96,
 532        .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
 533};
 534
 535
 536static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
 537        { .name = "Flat",
 538         .vals = { 0x00000000, 0x00000000, 0x00000000,
 539                   0x00000000, 0x00000000, 0x00000000,
 540                   0x00000000, 0x00000000, 0x00000000,
 541                   0x00000000, 0x00000000            }
 542        },
 543        { .name = "Acoustic",
 544         .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
 545                   0x40000000, 0x00000000, 0x00000000,
 546                   0x00000000, 0x00000000, 0x40000000,
 547                   0x40000000, 0x40000000            }
 548        },
 549        { .name = "Classical",
 550         .vals = { 0x00000000, 0x00000000, 0x40C00000,
 551                   0x40C00000, 0x40466666, 0x00000000,
 552                   0x00000000, 0x00000000, 0x00000000,
 553                   0x40466666, 0x40466666            }
 554        },
 555        { .name = "Country",
 556         .vals = { 0x00000000, 0xBF99999A, 0x00000000,
 557                   0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
 558                   0x00000000, 0x00000000, 0x40000000,
 559                   0x40466666, 0x40800000            }
 560        },
 561        { .name = "Dance",
 562         .vals = { 0x00000000, 0xBF99999A, 0x40000000,
 563                   0x40466666, 0x40866666, 0xBF99999A,
 564                   0xBF99999A, 0x00000000, 0x00000000,
 565                   0x40800000, 0x40800000            }
 566        },
 567        { .name = "Jazz",
 568         .vals = { 0x00000000, 0x00000000, 0x00000000,
 569                   0x3F8CCCCD, 0x40800000, 0x40800000,
 570                   0x40800000, 0x00000000, 0x3F8CCCCD,
 571                   0x40466666, 0x40466666            }
 572        },
 573        { .name = "New Age",
 574         .vals = { 0x00000000, 0x00000000, 0x40000000,
 575                   0x40000000, 0x00000000, 0x00000000,
 576                   0x00000000, 0x3F8CCCCD, 0x40000000,
 577                   0x40000000, 0x40000000            }
 578        },
 579        { .name = "Pop",
 580         .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
 581                   0x40000000, 0x40000000, 0x00000000,
 582                   0xBF99999A, 0xBF99999A, 0x00000000,
 583                   0x40466666, 0x40C00000            }
 584        },
 585        { .name = "Rock",
 586         .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
 587                   0x3F8CCCCD, 0x40000000, 0xBF99999A,
 588                   0xBF99999A, 0x00000000, 0x00000000,
 589                   0x40800000, 0x40800000            }
 590        },
 591        { .name = "Vocal",
 592         .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
 593                   0xBF99999A, 0x00000000, 0x40466666,
 594                   0x40800000, 0x40466666, 0x00000000,
 595                   0x00000000, 0x3F8CCCCD            }
 596        }
 597};
 598
 599/*
 600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
 601 * set as not being full range, and bass redirection is enabled, all
 602 * frequencies below the crossover frequency are redirected to the LFE
 603 * channel. If the surround configuration has no LFE channel, this can't be
 604 * enabled. X-Bass must be disabled when using these.
 605 */
 606enum speaker_range_reqs {
 607        SPEAKER_BASS_REDIRECT            = 0x15,
 608        SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
 609        /* Between 0x16-0x1a are the X-Bass reqs. */
 610        SPEAKER_FULL_RANGE_FRONT_L_R     = 0x1a,
 611        SPEAKER_FULL_RANGE_CENTER_LFE    = 0x1b,
 612        SPEAKER_FULL_RANGE_REAR_L_R      = 0x1c,
 613        SPEAKER_FULL_RANGE_SURROUND_L_R  = 0x1d,
 614        SPEAKER_BASS_REDIRECT_SUB_GAIN   = 0x1e,
 615};
 616
 617/*
 618 * Definitions for the DSP req's to handle speaker tuning. These all belong to
 619 * module ID 0x96, the output effects module.
 620 */
 621enum speaker_tuning_reqs {
 622        /*
 623         * Currently, this value is always set to 0.0f. However, on Windows,
 624         * when selecting certain headphone profiles on the new Sound Blaster
 625         * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
 626         * sent. This gets the speaker EQ address area, which is then used to
 627         * send over (presumably) an equalizer profile for the specific
 628         * headphone setup. It is sent using the same method the DSP
 629         * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
 630         * file exists in linux firmware tree but goes unused. It would also
 631         * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
 632         * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
 633         * set to 1.0f.
 634         */
 635        SPEAKER_TUNING_USE_SPEAKER_EQ           = 0x1f,
 636        SPEAKER_TUNING_ENABLE_CENTER_EQ         = 0x20,
 637        SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL     = 0x21,
 638        SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL    = 0x22,
 639        SPEAKER_TUNING_CENTER_VOL_LEVEL         = 0x23,
 640        SPEAKER_TUNING_LFE_VOL_LEVEL            = 0x24,
 641        SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL      = 0x25,
 642        SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL     = 0x26,
 643        SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL  = 0x27,
 644        SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
 645        /*
 646         * Inversion is used when setting headphone virtualization to line
 647         * out. Not sure why this is, but it's the only place it's ever used.
 648         */
 649        SPEAKER_TUNING_FRONT_LEFT_INVERT        = 0x29,
 650        SPEAKER_TUNING_FRONT_RIGHT_INVERT       = 0x2a,
 651        SPEAKER_TUNING_CENTER_INVERT            = 0x2b,
 652        SPEAKER_TUNING_LFE_INVERT               = 0x2c,
 653        SPEAKER_TUNING_REAR_LEFT_INVERT         = 0x2d,
 654        SPEAKER_TUNING_REAR_RIGHT_INVERT        = 0x2e,
 655        SPEAKER_TUNING_SURROUND_LEFT_INVERT     = 0x2f,
 656        SPEAKER_TUNING_SURROUND_RIGHT_INVERT    = 0x30,
 657        /* Delay is used when setting surround speaker distance in Windows. */
 658        SPEAKER_TUNING_FRONT_LEFT_DELAY         = 0x31,
 659        SPEAKER_TUNING_FRONT_RIGHT_DELAY        = 0x32,
 660        SPEAKER_TUNING_CENTER_DELAY             = 0x33,
 661        SPEAKER_TUNING_LFE_DELAY                = 0x34,
 662        SPEAKER_TUNING_REAR_LEFT_DELAY          = 0x35,
 663        SPEAKER_TUNING_REAR_RIGHT_DELAY         = 0x36,
 664        SPEAKER_TUNING_SURROUND_LEFT_DELAY      = 0x37,
 665        SPEAKER_TUNING_SURROUND_RIGHT_DELAY     = 0x38,
 666        /* Of these two, only mute seems to ever be used. */
 667        SPEAKER_TUNING_MAIN_VOLUME              = 0x39,
 668        SPEAKER_TUNING_MUTE                     = 0x3a,
 669};
 670
 671/* Surround output channel count configuration structures. */
 672#define SPEAKER_CHANNEL_CFG_COUNT 5
 673enum {
 674        SPEAKER_CHANNELS_2_0,
 675        SPEAKER_CHANNELS_2_1,
 676        SPEAKER_CHANNELS_4_0,
 677        SPEAKER_CHANNELS_4_1,
 678        SPEAKER_CHANNELS_5_1,
 679};
 680
 681struct ca0132_alt_speaker_channel_cfg {
 682        char *name;
 683        unsigned int val;
 684};
 685
 686static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
 687        { .name = "2.0",
 688          .val = FLOAT_ONE
 689        },
 690        { .name = "2.1",
 691          .val = FLOAT_TWO
 692        },
 693        { .name = "4.0",
 694          .val = FLOAT_FIVE
 695        },
 696        { .name = "4.1",
 697          .val = FLOAT_SIX
 698        },
 699        { .name = "5.1",
 700          .val = FLOAT_EIGHT
 701        }
 702};
 703
 704/*
 705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
 706 * and I don't know what the third req is, but it's always zero. I assume it's
 707 * some sort of update or set command to tell the DSP there's new volume info.
 708 */
 709#define DSP_VOL_OUT 0
 710#define DSP_VOL_IN  1
 711
 712struct ct_dsp_volume_ctl {
 713        hda_nid_t vnid;
 714        int mid; /* module ID*/
 715        unsigned int reqs[3]; /* scp req ID */
 716};
 717
 718static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
 719        { .vnid = VNID_SPK,
 720          .mid = 0x32,
 721          .reqs = {3, 4, 2}
 722        },
 723        { .vnid = VNID_MIC,
 724          .mid = 0x37,
 725          .reqs = {2, 3, 1}
 726        }
 727};
 728
 729/* Values for ca0113_mmio_command_set for selecting output. */
 730#define AE_CA0113_OUT_SET_COMMANDS 6
 731struct ae_ca0113_output_set {
 732        unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
 733        unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
 734        unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
 735};
 736
 737static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
 738        .group =  { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 739        .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 740                    /* Speakers. */
 741        .vals =   { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
 742                    /* Headphones. */
 743                    { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
 744};
 745
 746static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
 747        .group  = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 748        .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 749                    /* Speakers. */
 750        .vals   = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
 751                    /* Headphones. */
 752                    { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
 753};
 754
 755/* ae5 ca0113 command sequences to set headphone gain levels. */
 756#define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
 757struct ae5_headphone_gain_set {
 758        char *name;
 759        unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
 760};
 761
 762static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
 763        { .name = "Low (16-31",
 764          .vals = { 0xff, 0x2c, 0xf5, 0x32 }
 765        },
 766        { .name = "Medium (32-149",
 767          .vals = { 0x38, 0xa8, 0x3e, 0x4c }
 768        },
 769        { .name = "High (150-600",
 770          .vals = { 0xff, 0xff, 0xff, 0x7f }
 771        }
 772};
 773
 774struct ae5_filter_set {
 775        char *name;
 776        unsigned int val;
 777};
 778
 779static const struct ae5_filter_set ae5_filter_presets[] = {
 780        { .name = "Slow Roll Off",
 781          .val = 0xa0
 782        },
 783        { .name = "Minimum Phase",
 784          .val = 0xc0
 785        },
 786        { .name = "Fast Roll Off",
 787          .val = 0x80
 788        }
 789};
 790
 791/*
 792 * Data structures for storing audio router remapping data. These are used to
 793 * remap a currently active streams ports.
 794 */
 795struct chipio_stream_remap_data {
 796        unsigned int stream_id;
 797        unsigned int count;
 798
 799        unsigned int offset[16];
 800        unsigned int value[16];
 801};
 802
 803static const struct chipio_stream_remap_data stream_remap_data[] = {
 804        { .stream_id = 0x14,
 805          .count     = 0x04,
 806          .offset    = { 0x00, 0x04, 0x08, 0x0c },
 807          .value     = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
 808        },
 809        { .stream_id = 0x0c,
 810          .count     = 0x0c,
 811          .offset    = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
 812                         0x20, 0x24, 0x28, 0x2c },
 813          .value     = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
 814                         0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
 815                         0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
 816        },
 817        { .stream_id = 0x0c,
 818          .count     = 0x08,
 819          .offset    = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
 820          .value     = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
 821                         0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
 822        }
 823};
 824
 825enum hda_cmd_vendor_io {
 826        /* for DspIO node */
 827        VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 828        VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 829
 830        VENDOR_DSPIO_STATUS                  = 0xF01,
 831        VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 832        VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 833        VENDOR_DSPIO_DSP_INIT                = 0x703,
 834        VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 835        VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 836
 837        /* for ChipIO node */
 838        VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 839        VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 840        VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 841        VENDOR_CHIPIO_DATA_LOW               = 0x300,
 842        VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 843
 844        VENDOR_CHIPIO_8051_WRITE_DIRECT      = 0x500,
 845        VENDOR_CHIPIO_8051_READ_DIRECT       = 0xD00,
 846
 847        VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 848        VENDOR_CHIPIO_STATUS                 = 0xF01,
 849        VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 850        VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 851
 852        VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 853        VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 854        VENDOR_CHIPIO_8051_PMEM_READ         = 0xF08,
 855        VENDOR_CHIPIO_8051_IRAM_WRITE        = 0x709,
 856        VENDOR_CHIPIO_8051_IRAM_READ         = 0xF09,
 857
 858        VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 859        VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 860
 861        VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 862        VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 863        VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 864        VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 865        VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 866        VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 867        VENDOR_CHIPIO_PARAM_SET              = 0x710,
 868        VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 869
 870        VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 871        VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 872        VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 873        VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 874
 875        VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 876        VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 877        VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 878        VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 879
 880        VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 881        VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 882        VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 883        VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 884        VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 885        VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 886
 887        VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 888};
 889
 890/*
 891 *  Control flag IDs
 892 */
 893enum control_flag_id {
 894        /* Connection manager stream setup is bypassed/enabled */
 895        CONTROL_FLAG_C_MGR                  = 0,
 896        /* DSP DMA is bypassed/enabled */
 897        CONTROL_FLAG_DMA                    = 1,
 898        /* 8051 'idle' mode is disabled/enabled */
 899        CONTROL_FLAG_IDLE_ENABLE            = 2,
 900        /* Tracker for the SPDIF-in path is bypassed/enabled */
 901        CONTROL_FLAG_TRACKER                = 3,
 902        /* DigitalOut to Spdif2Out connection is disabled/enabled */
 903        CONTROL_FLAG_SPDIF2OUT              = 4,
 904        /* Digital Microphone is disabled/enabled */
 905        CONTROL_FLAG_DMIC                   = 5,
 906        /* ADC_B rate is 48 kHz/96 kHz */
 907        CONTROL_FLAG_ADC_B_96KHZ            = 6,
 908        /* ADC_C rate is 48 kHz/96 kHz */
 909        CONTROL_FLAG_ADC_C_96KHZ            = 7,
 910        /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 911        CONTROL_FLAG_DAC_96KHZ              = 8,
 912        /* DSP rate is 48 kHz/96 kHz */
 913        CONTROL_FLAG_DSP_96KHZ              = 9,
 914        /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 915        CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 916        /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 917        CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 918        /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 919        CONTROL_FLAG_DECODE_LOOP            = 12,
 920        /* De-emphasis filter on DAC-1 disabled/enabled */
 921        CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 922        /* De-emphasis filter on DAC-2 disabled/enabled */
 923        CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 924        /* De-emphasis filter on DAC-3 disabled/enabled */
 925        CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 926        /* High-pass filter on ADC_B disabled/enabled */
 927        CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 928        /* High-pass filter on ADC_C disabled/enabled */
 929        CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 930        /* Common mode on Port_A disabled/enabled */
 931        CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 932        /* Common mode on Port_D disabled/enabled */
 933        CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 934        /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 935        CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 936        /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 937        CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 938        /* ASI rate is 48kHz/96kHz */
 939        CONTROL_FLAG_ASI_96KHZ              = 22,
 940        /* DAC power settings able to control attached ports no/yes */
 941        CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 942        /* Clock Stop OK reporting is disabled/enabled */
 943        CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 944        /* Number of control flags */
 945        CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 946};
 947
 948/*
 949 * Control parameter IDs
 950 */
 951enum control_param_id {
 952        /* 0: None, 1: Mic1In*/
 953        CONTROL_PARAM_VIP_SOURCE               = 1,
 954        /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 955        CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 956        /* Port A output stage gain setting to use when 16 Ohm output
 957         * impedance is selected*/
 958        CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 959        /* Port D output stage gain setting to use when 16 Ohm output
 960         * impedance is selected*/
 961        CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 962
 963        /*
 964         * This control param name was found in the 8051 memory, and makes
 965         * sense given the fact the AE-5 uses it and has the ASI flag set.
 966         */
 967        CONTROL_PARAM_ASI                      = 23,
 968
 969        /* Stream Control */
 970
 971        /* Select stream with the given ID */
 972        CONTROL_PARAM_STREAM_ID                = 24,
 973        /* Source connection point for the selected stream */
 974        CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 975        /* Destination connection point for the selected stream */
 976        CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 977        /* Number of audio channels in the selected stream */
 978        CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 979        /*Enable control for the selected stream */
 980        CONTROL_PARAM_STREAM_CONTROL           = 28,
 981
 982        /* Connection Point Control */
 983
 984        /* Select connection point with the given ID */
 985        CONTROL_PARAM_CONN_POINT_ID            = 29,
 986        /* Connection point sample rate */
 987        CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 988
 989        /* Node Control */
 990
 991        /* Select HDA node with the given ID */
 992        CONTROL_PARAM_NODE_ID                  = 31
 993};
 994
 995/*
 996 *  Dsp Io Status codes
 997 */
 998enum hda_vendor_status_dspio {
 999        /* Success */
1000        VENDOR_STATUS_DSPIO_OK                       = 0x00,
1001        /* Busy, unable to accept new command, the host must retry */
1002        VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
1003        /* SCP command queue is full */
1004        VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
1005        /* SCP response queue is empty */
1006        VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1007};
1008
1009/*
1010 *  Chip Io Status codes
1011 */
1012enum hda_vendor_status_chipio {
1013        /* Success */
1014        VENDOR_STATUS_CHIPIO_OK   = 0x00,
1015        /* Busy, unable to accept new command, the host must retry */
1016        VENDOR_STATUS_CHIPIO_BUSY = 0x01
1017};
1018
1019/*
1020 *  CA0132 sample rate
1021 */
1022enum ca0132_sample_rate {
1023        SR_6_000        = 0x00,
1024        SR_8_000        = 0x01,
1025        SR_9_600        = 0x02,
1026        SR_11_025       = 0x03,
1027        SR_16_000       = 0x04,
1028        SR_22_050       = 0x05,
1029        SR_24_000       = 0x06,
1030        SR_32_000       = 0x07,
1031        SR_44_100       = 0x08,
1032        SR_48_000       = 0x09,
1033        SR_88_200       = 0x0A,
1034        SR_96_000       = 0x0B,
1035        SR_144_000      = 0x0C,
1036        SR_176_400      = 0x0D,
1037        SR_192_000      = 0x0E,
1038        SR_384_000      = 0x0F,
1039
1040        SR_COUNT        = 0x10,
1041
1042        SR_RATE_UNKNOWN = 0x1F
1043};
1044
1045enum dsp_download_state {
1046        DSP_DOWNLOAD_FAILED = -1,
1047        DSP_DOWNLOAD_INIT   = 0,
1048        DSP_DOWNLOADING     = 1,
1049        DSP_DOWNLOADED      = 2
1050};
1051
1052/* retrieve parameters from hda format */
1053#define get_hdafmt_chs(fmt)     (fmt & 0xf)
1054#define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
1055#define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
1056#define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
1057
1058/*
1059 * CA0132 specific
1060 */
1061
1062struct ca0132_spec {
1063        const struct snd_kcontrol_new *mixers[5];
1064        unsigned int num_mixers;
1065        const struct hda_verb *base_init_verbs;
1066        const struct hda_verb *base_exit_verbs;
1067        const struct hda_verb *chip_init_verbs;
1068        const struct hda_verb *desktop_init_verbs;
1069        struct hda_verb *spec_init_verbs;
1070        struct auto_pin_cfg autocfg;
1071
1072        /* Nodes configurations */
1073        struct hda_multi_out multiout;
1074        hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1075        hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1076        unsigned int num_outputs;
1077        hda_nid_t input_pins[AUTO_PIN_LAST];
1078        hda_nid_t adcs[AUTO_PIN_LAST];
1079        hda_nid_t dig_out;
1080        hda_nid_t dig_in;
1081        unsigned int num_inputs;
1082        hda_nid_t shared_mic_nid;
1083        hda_nid_t shared_out_nid;
1084        hda_nid_t unsol_tag_hp;
1085        hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1086        hda_nid_t unsol_tag_amic1;
1087
1088        /* chip access */
1089        struct mutex chipio_mutex; /* chip access mutex */
1090        u32 curr_chip_addx;
1091
1092        /* DSP download related */
1093        enum dsp_download_state dsp_state;
1094        unsigned int dsp_stream_id;
1095        unsigned int wait_scp;
1096        unsigned int wait_scp_header;
1097        unsigned int wait_num_data;
1098        unsigned int scp_resp_header;
1099        unsigned int scp_resp_data[4];
1100        unsigned int scp_resp_count;
1101        bool startup_check_entered;
1102        bool dsp_reload;
1103
1104        /* mixer and effects related */
1105        unsigned char dmic_ctl;
1106        int cur_out_type;
1107        int cur_mic_type;
1108        long vnode_lvol[VNODES_COUNT];
1109        long vnode_rvol[VNODES_COUNT];
1110        long vnode_lswitch[VNODES_COUNT];
1111        long vnode_rswitch[VNODES_COUNT];
1112        long effects_switch[EFFECTS_COUNT];
1113        long voicefx_val;
1114        long cur_mic_boost;
1115        /* ca0132_alt control related values */
1116        unsigned char in_enum_val;
1117        unsigned char out_enum_val;
1118        unsigned char channel_cfg_val;
1119        unsigned char speaker_range_val[2];
1120        unsigned char mic_boost_enum_val;
1121        unsigned char smart_volume_setting;
1122        unsigned char bass_redirection_val;
1123        long bass_redirect_xover_freq;
1124        long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1125        long xbass_xover_freq;
1126        long eq_preset_val;
1127        unsigned int tlv[4];
1128        struct hda_vmaster_mute_hook vmaster_mute;
1129        /* AE-5 Control values */
1130        unsigned char ae5_headphone_gain_val;
1131        unsigned char ae5_filter_val;
1132        /* ZxR Control Values */
1133        unsigned char zxr_gain_set;
1134
1135        struct hda_codec *codec;
1136        struct delayed_work unsol_hp_work;
1137        int quirk;
1138
1139#ifdef ENABLE_TUNING_CONTROLS
1140        long cur_ctl_vals[TUNING_CTLS_COUNT];
1141#endif
1142        /*
1143         * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1144         * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1145         * things.
1146         */
1147        bool use_pci_mmio;
1148        void __iomem *mem_base;
1149
1150        /*
1151         * Whether or not to use the alt functions like alt_select_out,
1152         * alt_select_in, etc. Only used on desktop codecs for now, because of
1153         * surround sound support.
1154         */
1155        bool use_alt_functions;
1156
1157        /*
1158         * Whether or not to use alt controls:  volume effect sliders, EQ
1159         * presets, smart volume presets, and new control names with FX prefix.
1160         * Renames PlayEnhancement and CrystalVoice too.
1161         */
1162        bool use_alt_controls;
1163};
1164
1165/*
1166 * CA0132 quirks table
1167 */
1168enum {
1169        QUIRK_NONE,
1170        QUIRK_ALIENWARE,
1171        QUIRK_ALIENWARE_M17XR4,
1172        QUIRK_SBZ,
1173        QUIRK_ZXR,
1174        QUIRK_ZXR_DBPRO,
1175        QUIRK_R3DI,
1176        QUIRK_R3D,
1177        QUIRK_AE5,
1178        QUIRK_AE7,
1179};
1180
1181#ifdef CONFIG_PCI
1182#define ca0132_quirk(spec)              ((spec)->quirk)
1183#define ca0132_use_pci_mmio(spec)       ((spec)->use_pci_mmio)
1184#define ca0132_use_alt_functions(spec)  ((spec)->use_alt_functions)
1185#define ca0132_use_alt_controls(spec)   ((spec)->use_alt_controls)
1186#else
1187#define ca0132_quirk(spec)              ({ (void)(spec); QUIRK_NONE; })
1188#define ca0132_use_alt_functions(spec)  ({ (void)(spec); false; })
1189#define ca0132_use_pci_mmio(spec)       ({ (void)(spec); false; })
1190#define ca0132_use_alt_controls(spec)   ({ (void)(spec); false; })
1191#endif
1192
1193static const struct hda_pintbl alienware_pincfgs[] = {
1194        { 0x0b, 0x90170110 }, /* Builtin Speaker */
1195        { 0x0c, 0x411111f0 }, /* N/A */
1196        { 0x0d, 0x411111f0 }, /* N/A */
1197        { 0x0e, 0x411111f0 }, /* N/A */
1198        { 0x0f, 0x0321101f }, /* HP */
1199        { 0x10, 0x411111f0 }, /* Headset?  disabled for now */
1200        { 0x11, 0x03a11021 }, /* Mic */
1201        { 0x12, 0xd5a30140 }, /* Builtin Mic */
1202        { 0x13, 0x411111f0 }, /* N/A */
1203        { 0x18, 0x411111f0 }, /* N/A */
1204        {}
1205};
1206
1207/* Sound Blaster Z pin configs taken from Windows Driver */
1208static const struct hda_pintbl sbz_pincfgs[] = {
1209        { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1210        { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1211        { 0x0d, 0x014510f0 }, /* Digital Out */
1212        { 0x0e, 0x01c510f0 }, /* SPDIF In */
1213        { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1214        { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1215        { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1216        { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1217        { 0x13, 0x908700f0 }, /* What U Hear In*/
1218        { 0x18, 0x50d000f0 }, /* N/A */
1219        {}
1220};
1221
1222/* Sound Blaster ZxR pin configs taken from Windows Driver */
1223static const struct hda_pintbl zxr_pincfgs[] = {
1224        { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1225        { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1226        { 0x0d, 0x014510f0 }, /* Digital Out */
1227        { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1228        { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1229        { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1230        { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1231        { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1232        { 0x13, 0x908700f0 }, /* What U Hear In*/
1233        { 0x18, 0x50d000f0 }, /* N/A */
1234        {}
1235};
1236
1237/* Recon3D pin configs taken from Windows Driver */
1238static const struct hda_pintbl r3d_pincfgs[] = {
1239        { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1240        { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1241        { 0x0d, 0x014510f0 }, /* Digital Out */
1242        { 0x0e, 0x01c520f0 }, /* SPDIF In */
1243        { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1244        { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1245        { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1246        { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1247        { 0x13, 0x908700f0 }, /* What U Hear In*/
1248        { 0x18, 0x50d000f0 }, /* N/A */
1249        {}
1250};
1251
1252/* Sound Blaster AE-5 pin configs taken from Windows Driver */
1253static const struct hda_pintbl ae5_pincfgs[] = {
1254        { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1255        { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1256        { 0x0d, 0x014510f0 }, /* Digital Out */
1257        { 0x0e, 0x01c510f0 }, /* SPDIF In */
1258        { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1259        { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1260        { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1261        { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1262        { 0x13, 0x908700f0 }, /* What U Hear In*/
1263        { 0x18, 0x50d000f0 }, /* N/A */
1264        {}
1265};
1266
1267/* Recon3D integrated pin configs taken from Windows Driver */
1268static const struct hda_pintbl r3di_pincfgs[] = {
1269        { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1270        { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1271        { 0x0d, 0x014510f0 }, /* Digital Out */
1272        { 0x0e, 0x41c520f0 }, /* SPDIF In */
1273        { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1274        { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1275        { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1276        { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1277        { 0x13, 0x908700f0 }, /* What U Hear In*/
1278        { 0x18, 0x500000f0 }, /* N/A */
1279        {}
1280};
1281
1282static const struct hda_pintbl ae7_pincfgs[] = {
1283        { 0x0b, 0x01017010 },
1284        { 0x0c, 0x014510f0 },
1285        { 0x0d, 0x414510f0 },
1286        { 0x0e, 0x01c520f0 },
1287        { 0x0f, 0x01017114 },
1288        { 0x10, 0x01017011 },
1289        { 0x11, 0x018170ff },
1290        { 0x12, 0x01a170f0 },
1291        { 0x13, 0x908700f0 },
1292        { 0x18, 0x500000f0 },
1293        {}
1294};
1295
1296static const struct snd_pci_quirk ca0132_quirks[] = {
1297        SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1298        SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1299        SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1300        SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1301        SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1302        SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1303        SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1304        SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1305        SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1306        SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1307        SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1308        SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1309        SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1310        SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1311        SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1312        SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1313        SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1314        {}
1315};
1316
1317/* Output selection quirk info structures. */
1318#define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1319#define MAX_QUIRK_SCP_SET_VALS 2
1320struct ca0132_alt_out_set_info {
1321        unsigned int dac2port; /* ParamID 0x0d value. */
1322
1323        bool has_hda_gpio;
1324        char hda_gpio_pin;
1325        char hda_gpio_set;
1326
1327        unsigned int mmio_gpio_count;
1328        char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1329        char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1330
1331        unsigned int scp_cmds_count;
1332        unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1333        unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1334        unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1335
1336        bool has_chipio_write;
1337        unsigned int chipio_write_addr;
1338        unsigned int chipio_write_data;
1339};
1340
1341struct ca0132_alt_out_set_quirk_data {
1342        int quirk_id;
1343
1344        bool has_headphone_gain;
1345        bool is_ae_series;
1346
1347        struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1348};
1349
1350static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1351        { .quirk_id = QUIRK_R3DI,
1352          .has_headphone_gain = false,
1353          .is_ae_series       = false,
1354          .out_set_info = {
1355                /* Speakers. */
1356                { .dac2port         = 0x24,
1357                  .has_hda_gpio     = true,
1358                  .hda_gpio_pin     = 2,
1359                  .hda_gpio_set     = 1,
1360                  .mmio_gpio_count  = 0,
1361                  .scp_cmds_count   = 0,
1362                  .has_chipio_write = false,
1363                },
1364                /* Headphones. */
1365                { .dac2port         = 0x21,
1366                  .has_hda_gpio     = true,
1367                  .hda_gpio_pin     = 2,
1368                  .hda_gpio_set     = 0,
1369                  .mmio_gpio_count  = 0,
1370                  .scp_cmds_count   = 0,
1371                  .has_chipio_write = false,
1372                } },
1373        },
1374        { .quirk_id = QUIRK_R3D,
1375          .has_headphone_gain = false,
1376          .is_ae_series       = false,
1377          .out_set_info = {
1378                /* Speakers. */
1379                { .dac2port         = 0x24,
1380                  .has_hda_gpio     = false,
1381                  .mmio_gpio_count  = 1,
1382                  .mmio_gpio_pin    = { 1 },
1383                  .mmio_gpio_set    = { 1 },
1384                  .scp_cmds_count   = 0,
1385                  .has_chipio_write = false,
1386                },
1387                /* Headphones. */
1388                { .dac2port         = 0x21,
1389                  .has_hda_gpio     = false,
1390                  .mmio_gpio_count  = 1,
1391                  .mmio_gpio_pin    = { 1 },
1392                  .mmio_gpio_set    = { 0 },
1393                  .scp_cmds_count   = 0,
1394                  .has_chipio_write = false,
1395                } },
1396        },
1397        { .quirk_id = QUIRK_SBZ,
1398          .has_headphone_gain = false,
1399          .is_ae_series       = false,
1400          .out_set_info = {
1401                /* Speakers. */
1402                { .dac2port         = 0x18,
1403                  .has_hda_gpio     = false,
1404                  .mmio_gpio_count  = 3,
1405                  .mmio_gpio_pin    = { 7, 4, 1 },
1406                  .mmio_gpio_set    = { 0, 1, 1 },
1407                  .scp_cmds_count   = 0,
1408                  .has_chipio_write = false, },
1409                /* Headphones. */
1410                { .dac2port         = 0x12,
1411                  .has_hda_gpio     = false,
1412                  .mmio_gpio_count  = 3,
1413                  .mmio_gpio_pin    = { 7, 4, 1 },
1414                  .mmio_gpio_set    = { 1, 1, 0 },
1415                  .scp_cmds_count   = 0,
1416                  .has_chipio_write = false,
1417                } },
1418        },
1419        { .quirk_id = QUIRK_ZXR,
1420          .has_headphone_gain = true,
1421          .is_ae_series       = false,
1422          .out_set_info = {
1423                /* Speakers. */
1424                { .dac2port         = 0x24,
1425                  .has_hda_gpio     = false,
1426                  .mmio_gpio_count  = 3,
1427                  .mmio_gpio_pin    = { 2, 3, 5 },
1428                  .mmio_gpio_set    = { 1, 1, 0 },
1429                  .scp_cmds_count   = 0,
1430                  .has_chipio_write = false,
1431                },
1432                /* Headphones. */
1433                { .dac2port         = 0x21,
1434                  .has_hda_gpio     = false,
1435                  .mmio_gpio_count  = 3,
1436                  .mmio_gpio_pin    = { 2, 3, 5 },
1437                  .mmio_gpio_set    = { 0, 1, 1 },
1438                  .scp_cmds_count   = 0,
1439                  .has_chipio_write = false,
1440                } },
1441        },
1442        { .quirk_id = QUIRK_AE5,
1443          .has_headphone_gain = true,
1444          .is_ae_series       = true,
1445          .out_set_info = {
1446                /* Speakers. */
1447                { .dac2port          = 0xa4,
1448                  .has_hda_gpio      = false,
1449                  .mmio_gpio_count   = 0,
1450                  .scp_cmds_count    = 2,
1451                  .scp_cmd_mid       = { 0x96, 0x96 },
1452                  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1453                                         SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1454                  .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
1455                  .has_chipio_write  = true,
1456                  .chipio_write_addr = 0x0018b03c,
1457                  .chipio_write_data = 0x00000012
1458                },
1459                /* Headphones. */
1460                { .dac2port          = 0xa1,
1461                  .has_hda_gpio      = false,
1462                  .mmio_gpio_count   = 0,
1463                  .scp_cmds_count    = 2,
1464                  .scp_cmd_mid       = { 0x96, 0x96 },
1465                  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1466                                         SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1467                  .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
1468                  .has_chipio_write  = true,
1469                  .chipio_write_addr = 0x0018b03c,
1470                  .chipio_write_data = 0x00000012
1471                } },
1472        },
1473        { .quirk_id = QUIRK_AE7,
1474          .has_headphone_gain = true,
1475          .is_ae_series       = true,
1476          .out_set_info = {
1477                /* Speakers. */
1478                { .dac2port          = 0x58,
1479                  .has_hda_gpio      = false,
1480                  .mmio_gpio_count   = 1,
1481                  .mmio_gpio_pin     = { 0 },
1482                  .mmio_gpio_set     = { 1 },
1483                  .scp_cmds_count    = 2,
1484                  .scp_cmd_mid       = { 0x96, 0x96 },
1485                  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1486                                         SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1487                  .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
1488                  .has_chipio_write  = true,
1489                  .chipio_write_addr = 0x0018b03c,
1490                  .chipio_write_data = 0x00000000
1491                },
1492                /* Headphones. */
1493                { .dac2port          = 0x58,
1494                  .has_hda_gpio      = false,
1495                  .mmio_gpio_count   = 1,
1496                  .mmio_gpio_pin     = { 0 },
1497                  .mmio_gpio_set     = { 1 },
1498                  .scp_cmds_count    = 2,
1499                  .scp_cmd_mid       = { 0x96, 0x96 },
1500                  .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1501                                         SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1502                  .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
1503                  .has_chipio_write  = true,
1504                  .chipio_write_addr = 0x0018b03c,
1505                  .chipio_write_data = 0x00000010
1506                } },
1507        }
1508};
1509
1510/*
1511 * CA0132 codec access
1512 */
1513static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1514                unsigned int verb, unsigned int parm, unsigned int *res)
1515{
1516        unsigned int response;
1517        response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1518        *res = response;
1519
1520        return ((response == -1) ? -1 : 0);
1521}
1522
1523static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1524                unsigned short converter_format, unsigned int *res)
1525{
1526        return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1527                                converter_format & 0xffff, res);
1528}
1529
1530static int codec_set_converter_stream_channel(struct hda_codec *codec,
1531                                hda_nid_t nid, unsigned char stream,
1532                                unsigned char channel, unsigned int *res)
1533{
1534        unsigned char converter_stream_channel = 0;
1535
1536        converter_stream_channel = (stream << 4) | (channel & 0x0f);
1537        return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1538                                converter_stream_channel, res);
1539}
1540
1541/* Chip access helper function */
1542static int chipio_send(struct hda_codec *codec,
1543                       unsigned int reg,
1544                       unsigned int data)
1545{
1546        unsigned int res;
1547        unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1548
1549        /* send bits of data specified by reg */
1550        do {
1551                res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1552                                         reg, data);
1553                if (res == VENDOR_STATUS_CHIPIO_OK)
1554                        return 0;
1555                msleep(20);
1556        } while (time_before(jiffies, timeout));
1557
1558        return -EIO;
1559}
1560
1561/*
1562 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1563 */
1564static int chipio_write_address(struct hda_codec *codec,
1565                                unsigned int chip_addx)
1566{
1567        struct ca0132_spec *spec = codec->spec;
1568        int res;
1569
1570        if (spec->curr_chip_addx == chip_addx)
1571                        return 0;
1572
1573        /* send low 16 bits of the address */
1574        res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1575                          chip_addx & 0xffff);
1576
1577        if (res != -EIO) {
1578                /* send high 16 bits of the address */
1579                res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1580                                  chip_addx >> 16);
1581        }
1582
1583        spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1584
1585        return res;
1586}
1587
1588/*
1589 * Write data through the vendor widget -- NOT protected by the Mutex!
1590 */
1591static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1592{
1593        struct ca0132_spec *spec = codec->spec;
1594        int res;
1595
1596        /* send low 16 bits of the data */
1597        res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1598
1599        if (res != -EIO) {
1600                /* send high 16 bits of the data */
1601                res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1602                                  data >> 16);
1603        }
1604
1605        /*If no error encountered, automatically increment the address
1606        as per chip behaviour*/
1607        spec->curr_chip_addx = (res != -EIO) ?
1608                                        (spec->curr_chip_addx + 4) : ~0U;
1609        return res;
1610}
1611
1612/*
1613 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1614 */
1615static int chipio_write_data_multiple(struct hda_codec *codec,
1616                                      const u32 *data,
1617                                      unsigned int count)
1618{
1619        int status = 0;
1620
1621        if (data == NULL) {
1622                codec_dbg(codec, "chipio_write_data null ptr\n");
1623                return -EINVAL;
1624        }
1625
1626        while ((count-- != 0) && (status == 0))
1627                status = chipio_write_data(codec, *data++);
1628
1629        return status;
1630}
1631
1632
1633/*
1634 * Read data through the vendor widget -- NOT protected by the Mutex!
1635 */
1636static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1637{
1638        struct ca0132_spec *spec = codec->spec;
1639        int res;
1640
1641        /* post read */
1642        res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1643
1644        if (res != -EIO) {
1645                /* read status */
1646                res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1647        }
1648
1649        if (res != -EIO) {
1650                /* read data */
1651                *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1652                                           VENDOR_CHIPIO_HIC_READ_DATA,
1653                                           0);
1654        }
1655
1656        /*If no error encountered, automatically increment the address
1657        as per chip behaviour*/
1658        spec->curr_chip_addx = (res != -EIO) ?
1659                                        (spec->curr_chip_addx + 4) : ~0U;
1660        return res;
1661}
1662
1663/*
1664 * Write given value to the given address through the chip I/O widget.
1665 * protected by the Mutex
1666 */
1667static int chipio_write(struct hda_codec *codec,
1668                unsigned int chip_addx, const unsigned int data)
1669{
1670        struct ca0132_spec *spec = codec->spec;
1671        int err;
1672
1673        mutex_lock(&spec->chipio_mutex);
1674
1675        /* write the address, and if successful proceed to write data */
1676        err = chipio_write_address(codec, chip_addx);
1677        if (err < 0)
1678                goto exit;
1679
1680        err = chipio_write_data(codec, data);
1681        if (err < 0)
1682                goto exit;
1683
1684exit:
1685        mutex_unlock(&spec->chipio_mutex);
1686        return err;
1687}
1688
1689/*
1690 * Write given value to the given address through the chip I/O widget.
1691 * not protected by the Mutex
1692 */
1693static int chipio_write_no_mutex(struct hda_codec *codec,
1694                unsigned int chip_addx, const unsigned int data)
1695{
1696        int err;
1697
1698
1699        /* write the address, and if successful proceed to write data */
1700        err = chipio_write_address(codec, chip_addx);
1701        if (err < 0)
1702                goto exit;
1703
1704        err = chipio_write_data(codec, data);
1705        if (err < 0)
1706                goto exit;
1707
1708exit:
1709        return err;
1710}
1711
1712/*
1713 * Write multiple values to the given address through the chip I/O widget.
1714 * protected by the Mutex
1715 */
1716static int chipio_write_multiple(struct hda_codec *codec,
1717                                 u32 chip_addx,
1718                                 const u32 *data,
1719                                 unsigned int count)
1720{
1721        struct ca0132_spec *spec = codec->spec;
1722        int status;
1723
1724        mutex_lock(&spec->chipio_mutex);
1725        status = chipio_write_address(codec, chip_addx);
1726        if (status < 0)
1727                goto error;
1728
1729        status = chipio_write_data_multiple(codec, data, count);
1730error:
1731        mutex_unlock(&spec->chipio_mutex);
1732
1733        return status;
1734}
1735
1736/*
1737 * Read the given address through the chip I/O widget
1738 * protected by the Mutex
1739 */
1740static int chipio_read(struct hda_codec *codec,
1741                unsigned int chip_addx, unsigned int *data)
1742{
1743        struct ca0132_spec *spec = codec->spec;
1744        int err;
1745
1746        mutex_lock(&spec->chipio_mutex);
1747
1748        /* write the address, and if successful proceed to write data */
1749        err = chipio_write_address(codec, chip_addx);
1750        if (err < 0)
1751                goto exit;
1752
1753        err = chipio_read_data(codec, data);
1754        if (err < 0)
1755                goto exit;
1756
1757exit:
1758        mutex_unlock(&spec->chipio_mutex);
1759        return err;
1760}
1761
1762/*
1763 * Set chip control flags through the chip I/O widget.
1764 */
1765static void chipio_set_control_flag(struct hda_codec *codec,
1766                                    enum control_flag_id flag_id,
1767                                    bool flag_state)
1768{
1769        unsigned int val;
1770        unsigned int flag_bit;
1771
1772        flag_bit = (flag_state ? 1 : 0);
1773        val = (flag_bit << 7) | (flag_id);
1774        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1775                            VENDOR_CHIPIO_FLAG_SET, val);
1776}
1777
1778/*
1779 * Set chip parameters through the chip I/O widget.
1780 */
1781static void chipio_set_control_param(struct hda_codec *codec,
1782                enum control_param_id param_id, int param_val)
1783{
1784        struct ca0132_spec *spec = codec->spec;
1785        int val;
1786
1787        if ((param_id < 32) && (param_val < 8)) {
1788                val = (param_val << 5) | (param_id);
1789                snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1790                                    VENDOR_CHIPIO_PARAM_SET, val);
1791        } else {
1792                mutex_lock(&spec->chipio_mutex);
1793                if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1794                        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1795                                            VENDOR_CHIPIO_PARAM_EX_ID_SET,
1796                                            param_id);
1797                        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1798                                            VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1799                                            param_val);
1800                }
1801                mutex_unlock(&spec->chipio_mutex);
1802        }
1803}
1804
1805/*
1806 * Set chip parameters through the chip I/O widget. NO MUTEX.
1807 */
1808static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1809                enum control_param_id param_id, int param_val)
1810{
1811        int val;
1812
1813        if ((param_id < 32) && (param_val < 8)) {
1814                val = (param_val << 5) | (param_id);
1815                snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1816                                    VENDOR_CHIPIO_PARAM_SET, val);
1817        } else {
1818                if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1819                        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1820                                            VENDOR_CHIPIO_PARAM_EX_ID_SET,
1821                                            param_id);
1822                        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1823                                            VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1824                                            param_val);
1825                }
1826        }
1827}
1828/*
1829 * Connect stream to a source point, and then connect
1830 * that source point to a destination point.
1831 */
1832static void chipio_set_stream_source_dest(struct hda_codec *codec,
1833                                int streamid, int source_point, int dest_point)
1834{
1835        chipio_set_control_param_no_mutex(codec,
1836                        CONTROL_PARAM_STREAM_ID, streamid);
1837        chipio_set_control_param_no_mutex(codec,
1838                        CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1839        chipio_set_control_param_no_mutex(codec,
1840                        CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1841}
1842
1843/*
1844 * Set number of channels in the selected stream.
1845 */
1846static void chipio_set_stream_channels(struct hda_codec *codec,
1847                                int streamid, unsigned int channels)
1848{
1849        chipio_set_control_param_no_mutex(codec,
1850                        CONTROL_PARAM_STREAM_ID, streamid);
1851        chipio_set_control_param_no_mutex(codec,
1852                        CONTROL_PARAM_STREAMS_CHANNELS, channels);
1853}
1854
1855/*
1856 * Enable/Disable audio stream.
1857 */
1858static void chipio_set_stream_control(struct hda_codec *codec,
1859                                int streamid, int enable)
1860{
1861        chipio_set_control_param_no_mutex(codec,
1862                        CONTROL_PARAM_STREAM_ID, streamid);
1863        chipio_set_control_param_no_mutex(codec,
1864                        CONTROL_PARAM_STREAM_CONTROL, enable);
1865}
1866
1867/*
1868 * Get ChipIO audio stream's status.
1869 */
1870static void chipio_get_stream_control(struct hda_codec *codec,
1871                                int streamid, unsigned int *enable)
1872{
1873        chipio_set_control_param_no_mutex(codec,
1874                        CONTROL_PARAM_STREAM_ID, streamid);
1875        *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1876                           VENDOR_CHIPIO_PARAM_GET,
1877                           CONTROL_PARAM_STREAM_CONTROL);
1878}
1879
1880/*
1881 * Set sampling rate of the connection point. NO MUTEX.
1882 */
1883static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1884                                int connid, enum ca0132_sample_rate rate)
1885{
1886        chipio_set_control_param_no_mutex(codec,
1887                        CONTROL_PARAM_CONN_POINT_ID, connid);
1888        chipio_set_control_param_no_mutex(codec,
1889                        CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1890}
1891
1892/*
1893 * Set sampling rate of the connection point.
1894 */
1895static void chipio_set_conn_rate(struct hda_codec *codec,
1896                                int connid, enum ca0132_sample_rate rate)
1897{
1898        chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1899        chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1900                                 rate);
1901}
1902
1903/*
1904 * Writes to the 8051's internal address space directly instead of indirectly,
1905 * giving access to the special function registers located at addresses
1906 * 0x80-0xFF.
1907 */
1908static void chipio_8051_write_direct(struct hda_codec *codec,
1909                unsigned int addr, unsigned int data)
1910{
1911        unsigned int verb;
1912
1913        verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1914        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1915}
1916
1917/*
1918 * Writes to the 8051's exram, which has 16-bits of address space.
1919 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1920 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1921 * setting the pmem bank selection SFR.
1922 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1923 * being writable.
1924 */
1925static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr)
1926{
1927        unsigned int tmp;
1928
1929        /* Lower 8-bits. */
1930        tmp = addr & 0xff;
1931        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1932                            VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp);
1933
1934        /* Upper 8-bits. */
1935        tmp = (addr >> 8) & 0xff;
1936        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1937                            VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp);
1938}
1939
1940static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data)
1941{
1942        /* 8-bits of data. */
1943        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1944                            VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1945}
1946
1947static unsigned int chipio_8051_get_data(struct hda_codec *codec)
1948{
1949        return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1950                                   VENDOR_CHIPIO_8051_DATA_READ, 0);
1951}
1952
1953/* PLL_PMU writes share the lower address register of the 8051 exram writes. */
1954static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
1955{
1956        /* 8-bits of data. */
1957        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1958                            VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
1959}
1960
1961static void chipio_8051_write_exram(struct hda_codec *codec,
1962                unsigned int addr, unsigned int data)
1963{
1964        struct ca0132_spec *spec = codec->spec;
1965
1966        mutex_lock(&spec->chipio_mutex);
1967
1968        chipio_8051_set_address(codec, addr);
1969        chipio_8051_set_data(codec, data);
1970
1971        mutex_unlock(&spec->chipio_mutex);
1972}
1973
1974static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec,
1975                unsigned int addr, unsigned int data)
1976{
1977        chipio_8051_set_address(codec, addr);
1978        chipio_8051_set_data(codec, data);
1979}
1980
1981/* Readback data from the 8051's exram. No mutex. */
1982static void chipio_8051_read_exram(struct hda_codec *codec,
1983                unsigned int addr, unsigned int *data)
1984{
1985        chipio_8051_set_address(codec, addr);
1986        *data = chipio_8051_get_data(codec);
1987}
1988
1989static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
1990                unsigned int addr, unsigned int data)
1991{
1992        struct ca0132_spec *spec = codec->spec;
1993
1994        mutex_lock(&spec->chipio_mutex);
1995
1996        chipio_8051_set_address(codec, addr & 0xff);
1997        chipio_8051_set_data_pll(codec, data);
1998
1999        mutex_unlock(&spec->chipio_mutex);
2000}
2001
2002static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
2003                unsigned int addr, unsigned int data)
2004{
2005        chipio_8051_set_address(codec, addr & 0xff);
2006        chipio_8051_set_data_pll(codec, data);
2007}
2008
2009/*
2010 * Enable clocks.
2011 */
2012static void chipio_enable_clocks(struct hda_codec *codec)
2013{
2014        struct ca0132_spec *spec = codec->spec;
2015
2016        mutex_lock(&spec->chipio_mutex);
2017
2018        chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2019        chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2020        chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2021
2022        mutex_unlock(&spec->chipio_mutex);
2023}
2024
2025/*
2026 * CA0132 DSP IO stuffs
2027 */
2028static int dspio_send(struct hda_codec *codec, unsigned int reg,
2029                      unsigned int data)
2030{
2031        int res;
2032        unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2033
2034        /* send bits of data specified by reg to dsp */
2035        do {
2036                res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2037                if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2038                        return res;
2039                msleep(20);
2040        } while (time_before(jiffies, timeout));
2041
2042        return -EIO;
2043}
2044
2045/*
2046 * Wait for DSP to be ready for commands
2047 */
2048static void dspio_write_wait(struct hda_codec *codec)
2049{
2050        int status;
2051        unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2052
2053        do {
2054                status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2055                                                VENDOR_DSPIO_STATUS, 0);
2056                if ((status == VENDOR_STATUS_DSPIO_OK) ||
2057                    (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
2058                        break;
2059                msleep(1);
2060        } while (time_before(jiffies, timeout));
2061}
2062
2063/*
2064 * Write SCP data to DSP
2065 */
2066static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
2067{
2068        struct ca0132_spec *spec = codec->spec;
2069        int status;
2070
2071        dspio_write_wait(codec);
2072
2073        mutex_lock(&spec->chipio_mutex);
2074        status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
2075                            scp_data & 0xffff);
2076        if (status < 0)
2077                goto error;
2078
2079        status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
2080                                    scp_data >> 16);
2081        if (status < 0)
2082                goto error;
2083
2084        /* OK, now check if the write itself has executed*/
2085        status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2086                                    VENDOR_DSPIO_STATUS, 0);
2087error:
2088        mutex_unlock(&spec->chipio_mutex);
2089
2090        return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
2091                        -EIO : 0;
2092}
2093
2094/*
2095 * Write multiple SCP data to DSP
2096 */
2097static int dspio_write_multiple(struct hda_codec *codec,
2098                                unsigned int *buffer, unsigned int size)
2099{
2100        int status = 0;
2101        unsigned int count;
2102
2103        if (buffer == NULL)
2104                return -EINVAL;
2105
2106        count = 0;
2107        while (count < size) {
2108                status = dspio_write(codec, *buffer++);
2109                if (status != 0)
2110                        break;
2111                count++;
2112        }
2113
2114        return status;
2115}
2116
2117static int dspio_read(struct hda_codec *codec, unsigned int *data)
2118{
2119        int status;
2120
2121        status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2122        if (status == -EIO)
2123                return status;
2124
2125        status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2126        if (status == -EIO ||
2127            status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
2128                return -EIO;
2129
2130        *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2131                                   VENDOR_DSPIO_SCP_READ_DATA, 0);
2132
2133        return 0;
2134}
2135
2136static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2137                               unsigned int *buf_size, unsigned int size_count)
2138{
2139        int status = 0;
2140        unsigned int size = *buf_size;
2141        unsigned int count;
2142        unsigned int skip_count;
2143        unsigned int dummy;
2144
2145        if (buffer == NULL)
2146                return -1;
2147
2148        count = 0;
2149        while (count < size && count < size_count) {
2150                status = dspio_read(codec, buffer++);
2151                if (status != 0)
2152                        break;
2153                count++;
2154        }
2155
2156        skip_count = count;
2157        if (status == 0) {
2158                while (skip_count < size) {
2159                        status = dspio_read(codec, &dummy);
2160                        if (status != 0)
2161                                break;
2162                        skip_count++;
2163                }
2164        }
2165        *buf_size = count;
2166
2167        return status;
2168}
2169
2170/*
2171 * Construct the SCP header using corresponding fields
2172 */
2173static inline unsigned int
2174make_scp_header(unsigned int target_id, unsigned int source_id,
2175                unsigned int get_flag, unsigned int req,
2176                unsigned int device_flag, unsigned int resp_flag,
2177                unsigned int error_flag, unsigned int data_size)
2178{
2179        unsigned int header = 0;
2180
2181        header = (data_size & 0x1f) << 27;
2182        header |= (error_flag & 0x01) << 26;
2183        header |= (resp_flag & 0x01) << 25;
2184        header |= (device_flag & 0x01) << 24;
2185        header |= (req & 0x7f) << 17;
2186        header |= (get_flag & 0x01) << 16;
2187        header |= (source_id & 0xff) << 8;
2188        header |= target_id & 0xff;
2189
2190        return header;
2191}
2192
2193/*
2194 * Extract corresponding fields from SCP header
2195 */
2196static inline void
2197extract_scp_header(unsigned int header,
2198                   unsigned int *target_id, unsigned int *source_id,
2199                   unsigned int *get_flag, unsigned int *req,
2200                   unsigned int *device_flag, unsigned int *resp_flag,
2201                   unsigned int *error_flag, unsigned int *data_size)
2202{
2203        if (data_size)
2204                *data_size = (header >> 27) & 0x1f;
2205        if (error_flag)
2206                *error_flag = (header >> 26) & 0x01;
2207        if (resp_flag)
2208                *resp_flag = (header >> 25) & 0x01;
2209        if (device_flag)
2210                *device_flag = (header >> 24) & 0x01;
2211        if (req)
2212                *req = (header >> 17) & 0x7f;
2213        if (get_flag)
2214                *get_flag = (header >> 16) & 0x01;
2215        if (source_id)
2216                *source_id = (header >> 8) & 0xff;
2217        if (target_id)
2218                *target_id = header & 0xff;
2219}
2220
2221#define SCP_MAX_DATA_WORDS  (16)
2222
2223/* Structure to contain any SCP message */
2224struct scp_msg {
2225        unsigned int hdr;
2226        unsigned int data[SCP_MAX_DATA_WORDS];
2227};
2228
2229static void dspio_clear_response_queue(struct hda_codec *codec)
2230{
2231        unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2232        unsigned int dummy = 0;
2233        int status;
2234
2235        /* clear all from the response queue */
2236        do {
2237                status = dspio_read(codec, &dummy);
2238        } while (status == 0 && time_before(jiffies, timeout));
2239}
2240
2241static int dspio_get_response_data(struct hda_codec *codec)
2242{
2243        struct ca0132_spec *spec = codec->spec;
2244        unsigned int data = 0;
2245        unsigned int count;
2246
2247        if (dspio_read(codec, &data) < 0)
2248                return -EIO;
2249
2250        if ((data & 0x00ffffff) == spec->wait_scp_header) {
2251                spec->scp_resp_header = data;
2252                spec->scp_resp_count = data >> 27;
2253                count = spec->wait_num_data;
2254                dspio_read_multiple(codec, spec->scp_resp_data,
2255                                    &spec->scp_resp_count, count);
2256                return 0;
2257        }
2258
2259        return -EIO;
2260}
2261
2262/*
2263 * Send SCP message to DSP
2264 */
2265static int dspio_send_scp_message(struct hda_codec *codec,
2266                                  unsigned char *send_buf,
2267                                  unsigned int send_buf_size,
2268                                  unsigned char *return_buf,
2269                                  unsigned int return_buf_size,
2270                                  unsigned int *bytes_returned)
2271{
2272        struct ca0132_spec *spec = codec->spec;
2273        int status = -1;
2274        unsigned int scp_send_size = 0;
2275        unsigned int total_size;
2276        bool waiting_for_resp = false;
2277        unsigned int header;
2278        struct scp_msg *ret_msg;
2279        unsigned int resp_src_id, resp_target_id;
2280        unsigned int data_size, src_id, target_id, get_flag, device_flag;
2281
2282        if (bytes_returned)
2283                *bytes_returned = 0;
2284
2285        /* get scp header from buffer */
2286        header = *((unsigned int *)send_buf);
2287        extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2288                           &device_flag, NULL, NULL, &data_size);
2289        scp_send_size = data_size + 1;
2290        total_size = (scp_send_size * 4);
2291
2292        if (send_buf_size < total_size)
2293                return -EINVAL;
2294
2295        if (get_flag || device_flag) {
2296                if (!return_buf || return_buf_size < 4 || !bytes_returned)
2297                        return -EINVAL;
2298
2299                spec->wait_scp_header = *((unsigned int *)send_buf);
2300
2301                /* swap source id with target id */
2302                resp_target_id = src_id;
2303                resp_src_id = target_id;
2304                spec->wait_scp_header &= 0xffff0000;
2305                spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2306                spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2307                spec->wait_scp = 1;
2308                waiting_for_resp = true;
2309        }
2310
2311        status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2312                                      scp_send_size);
2313        if (status < 0) {
2314                spec->wait_scp = 0;
2315                return status;
2316        }
2317
2318        if (waiting_for_resp) {
2319                unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2320                memset(return_buf, 0, return_buf_size);
2321                do {
2322                        msleep(20);
2323                } while (spec->wait_scp && time_before(jiffies, timeout));
2324                waiting_for_resp = false;
2325                if (!spec->wait_scp) {
2326                        ret_msg = (struct scp_msg *)return_buf;
2327                        memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2328                        memcpy(&ret_msg->data, spec->scp_resp_data,
2329                               spec->wait_num_data);
2330                        *bytes_returned = (spec->scp_resp_count + 1) * 4;
2331                        status = 0;
2332                } else {
2333                        status = -EIO;
2334                }
2335                spec->wait_scp = 0;
2336        }
2337
2338        return status;
2339}
2340
2341/**
2342 * dspio_scp - Prepare and send the SCP message to DSP
2343 * @codec: the HDA codec
2344 * @mod_id: ID of the DSP module to send the command
2345 * @src_id: ID of the source
2346 * @req: ID of request to send to the DSP module
2347 * @dir: SET or GET
2348 * @data: pointer to the data to send with the request, request specific
2349 * @len: length of the data, in bytes
2350 * @reply: point to the buffer to hold data returned for a reply
2351 * @reply_len: length of the reply buffer returned from GET
2352 *
2353 * Returns zero or a negative error code.
2354 */
2355static int dspio_scp(struct hda_codec *codec,
2356                int mod_id, int src_id, int req, int dir, const void *data,
2357                unsigned int len, void *reply, unsigned int *reply_len)
2358{
2359        int status = 0;
2360        struct scp_msg scp_send, scp_reply;
2361        unsigned int ret_bytes, send_size, ret_size;
2362        unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2363        unsigned int reply_data_size;
2364
2365        memset(&scp_send, 0, sizeof(scp_send));
2366        memset(&scp_reply, 0, sizeof(scp_reply));
2367
2368        if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2369                return -EINVAL;
2370
2371        if (dir == SCP_GET && reply == NULL) {
2372                codec_dbg(codec, "dspio_scp get but has no buffer\n");
2373                return -EINVAL;
2374        }
2375
2376        if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2377                codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2378                return -EINVAL;
2379        }
2380
2381        scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2382                                       0, 0, 0, len/sizeof(unsigned int));
2383        if (data != NULL && len > 0) {
2384                len = min((unsigned int)(sizeof(scp_send.data)), len);
2385                memcpy(scp_send.data, data, len);
2386        }
2387
2388        ret_bytes = 0;
2389        send_size = sizeof(unsigned int) + len;
2390        status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2391                                        send_size, (unsigned char *)&scp_reply,
2392                                        sizeof(scp_reply), &ret_bytes);
2393
2394        if (status < 0) {
2395                codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2396                return status;
2397        }
2398
2399        /* extract send and reply headers members */
2400        extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2401                           NULL, NULL, NULL, NULL, NULL);
2402        extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2403                           &reply_resp_flag, &reply_error_flag,
2404                           &reply_data_size);
2405
2406        if (!send_get_flag)
2407                return 0;
2408
2409        if (reply_resp_flag && !reply_error_flag) {
2410                ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2411                                        / sizeof(unsigned int);
2412
2413                if (*reply_len < ret_size*sizeof(unsigned int)) {
2414                        codec_dbg(codec, "reply too long for buf\n");
2415                        return -EINVAL;
2416                } else if (ret_size != reply_data_size) {
2417                        codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2418                        return -EINVAL;
2419                } else if (!reply) {
2420                        codec_dbg(codec, "NULL reply\n");
2421                        return -EINVAL;
2422                } else {
2423                        *reply_len = ret_size*sizeof(unsigned int);
2424                        memcpy(reply, scp_reply.data, *reply_len);
2425                }
2426        } else {
2427                codec_dbg(codec, "reply ill-formed or errflag set\n");
2428                return -EIO;
2429        }
2430
2431        return status;
2432}
2433
2434/*
2435 * Set DSP parameters
2436 */
2437static int dspio_set_param(struct hda_codec *codec, int mod_id,
2438                        int src_id, int req, const void *data, unsigned int len)
2439{
2440        return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2441                        NULL);
2442}
2443
2444static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2445                        int req, const unsigned int data)
2446{
2447        return dspio_set_param(codec, mod_id, 0x20, req, &data,
2448                        sizeof(unsigned int));
2449}
2450
2451/*
2452 * Allocate a DSP DMA channel via an SCP message
2453 */
2454static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2455{
2456        int status = 0;
2457        unsigned int size = sizeof(dma_chan);
2458
2459        codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
2460        status = dspio_scp(codec, MASTERCONTROL, 0x20,
2461                        MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2462                        dma_chan, &size);
2463
2464        if (status < 0) {
2465                codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2466                return status;
2467        }
2468
2469        if ((*dma_chan + 1) == 0) {
2470                codec_dbg(codec, "no free dma channels to allocate\n");
2471                return -EBUSY;
2472        }
2473
2474        codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2475        codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
2476
2477        return status;
2478}
2479
2480/*
2481 * Free a DSP DMA via an SCP message
2482 */
2483static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2484{
2485        int status = 0;
2486        unsigned int dummy = 0;
2487
2488        codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
2489        codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2490
2491        status = dspio_scp(codec, MASTERCONTROL, 0x20,
2492                        MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2493                        sizeof(dma_chan), NULL, &dummy);
2494
2495        if (status < 0) {
2496                codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2497                return status;
2498        }
2499
2500        codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
2501
2502        return status;
2503}
2504
2505/*
2506 * (Re)start the DSP
2507 */
2508static int dsp_set_run_state(struct hda_codec *codec)
2509{
2510        unsigned int dbg_ctrl_reg;
2511        unsigned int halt_state;
2512        int err;
2513
2514        err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2515        if (err < 0)
2516                return err;
2517
2518        halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2519                      DSP_DBGCNTL_STATE_LOBIT;
2520
2521        if (halt_state != 0) {
2522                dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2523                                  DSP_DBGCNTL_SS_MASK);
2524                err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2525                                   dbg_ctrl_reg);
2526                if (err < 0)
2527                        return err;
2528
2529                dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2530                                DSP_DBGCNTL_EXEC_MASK;
2531                err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2532                                   dbg_ctrl_reg);
2533                if (err < 0)
2534                        return err;
2535        }
2536
2537        return 0;
2538}
2539
2540/*
2541 * Reset the DSP
2542 */
2543static int dsp_reset(struct hda_codec *codec)
2544{
2545        unsigned int res;
2546        int retry = 20;
2547
2548        codec_dbg(codec, "dsp_reset\n");
2549        do {
2550                res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2551                retry--;
2552        } while (res == -EIO && retry);
2553
2554        if (!retry) {
2555                codec_dbg(codec, "dsp_reset timeout\n");
2556                return -EIO;
2557        }
2558
2559        return 0;
2560}
2561
2562/*
2563 * Convert chip address to DSP address
2564 */
2565static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2566                                        bool *code, bool *yram)
2567{
2568        *code = *yram = false;
2569
2570        if (UC_RANGE(chip_addx, 1)) {
2571                *code = true;
2572                return UC_OFF(chip_addx);
2573        } else if (X_RANGE_ALL(chip_addx, 1)) {
2574                return X_OFF(chip_addx);
2575        } else if (Y_RANGE_ALL(chip_addx, 1)) {
2576                *yram = true;
2577                return Y_OFF(chip_addx);
2578        }
2579
2580        return INVALID_CHIP_ADDRESS;
2581}
2582
2583/*
2584 * Check if the DSP DMA is active
2585 */
2586static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2587{
2588        unsigned int dma_chnlstart_reg;
2589
2590        chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2591
2592        return ((dma_chnlstart_reg & (1 <<
2593                        (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2594}
2595
2596static int dsp_dma_setup_common(struct hda_codec *codec,
2597                                unsigned int chip_addx,
2598                                unsigned int dma_chan,
2599                                unsigned int port_map_mask,
2600                                bool ovly)
2601{
2602        int status = 0;
2603        unsigned int chnl_prop;
2604        unsigned int dsp_addx;
2605        unsigned int active;
2606        bool code, yram;
2607
2608        codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2609
2610        if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2611                codec_dbg(codec, "dma chan num invalid\n");
2612                return -EINVAL;
2613        }
2614
2615        if (dsp_is_dma_active(codec, dma_chan)) {
2616                codec_dbg(codec, "dma already active\n");
2617                return -EBUSY;
2618        }
2619
2620        dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2621
2622        if (dsp_addx == INVALID_CHIP_ADDRESS) {
2623                codec_dbg(codec, "invalid chip addr\n");
2624                return -ENXIO;
2625        }
2626
2627        chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2628        active = 0;
2629
2630        codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2631
2632        if (ovly) {
2633                status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2634                                     &chnl_prop);
2635
2636                if (status < 0) {
2637                        codec_dbg(codec, "read CHNLPROP Reg fail\n");
2638                        return status;
2639                }
2640                codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2641        }
2642
2643        if (!code)
2644                chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2645        else
2646                chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2647
2648        chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2649
2650        status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2651        if (status < 0) {
2652                codec_dbg(codec, "write CHNLPROP Reg fail\n");
2653                return status;
2654        }
2655        codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2656
2657        if (ovly) {
2658                status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2659                                     &active);
2660
2661                if (status < 0) {
2662                        codec_dbg(codec, "read ACTIVE Reg fail\n");
2663                        return status;
2664                }
2665                codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2666        }
2667
2668        active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2669                DSPDMAC_ACTIVE_AAR_MASK;
2670
2671        status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2672        if (status < 0) {
2673                codec_dbg(codec, "write ACTIVE Reg fail\n");
2674                return status;
2675        }
2676
2677        codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2678
2679        status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2680                              port_map_mask);
2681        if (status < 0) {
2682                codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2683                return status;
2684        }
2685        codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2686
2687        status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2688                        DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2689        if (status < 0) {
2690                codec_dbg(codec, "write IRQCNT Reg fail\n");
2691                return status;
2692        }
2693        codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2694
2695        codec_dbg(codec,
2696                   "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2697                   "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2698                   chip_addx, dsp_addx, dma_chan,
2699                   port_map_mask, chnl_prop, active);
2700
2701        codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2702
2703        return 0;
2704}
2705
2706/*
2707 * Setup the DSP DMA per-transfer-specific registers
2708 */
2709static int dsp_dma_setup(struct hda_codec *codec,
2710                        unsigned int chip_addx,
2711                        unsigned int count,
2712                        unsigned int dma_chan)
2713{
2714        int status = 0;
2715        bool code, yram;
2716        unsigned int dsp_addx;
2717        unsigned int addr_field;
2718        unsigned int incr_field;
2719        unsigned int base_cnt;
2720        unsigned int cur_cnt;
2721        unsigned int dma_cfg = 0;
2722        unsigned int adr_ofs = 0;
2723        unsigned int xfr_cnt = 0;
2724        const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2725                                                DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2726
2727        codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2728
2729        if (count > max_dma_count) {
2730                codec_dbg(codec, "count too big\n");
2731                return -EINVAL;
2732        }
2733
2734        dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2735        if (dsp_addx == INVALID_CHIP_ADDRESS) {
2736                codec_dbg(codec, "invalid chip addr\n");
2737                return -ENXIO;
2738        }
2739
2740        codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2741
2742        addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2743        incr_field   = 0;
2744
2745        if (!code) {
2746                addr_field <<= 1;
2747                if (yram)
2748                        addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2749
2750                incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2751        }
2752
2753        dma_cfg = addr_field + incr_field;
2754        status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2755                                dma_cfg);
2756        if (status < 0) {
2757                codec_dbg(codec, "write DMACFG Reg fail\n");
2758                return status;
2759        }
2760        codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2761
2762        adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2763                                                        (code ? 0 : 1));
2764
2765        status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2766                                adr_ofs);
2767        if (status < 0) {
2768                codec_dbg(codec, "write DSPADROFS Reg fail\n");
2769                return status;
2770        }
2771        codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2772
2773        base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2774
2775        cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2776
2777        xfr_cnt = base_cnt | cur_cnt;
2778
2779        status = chipio_write(codec,
2780                                DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2781        if (status < 0) {
2782                codec_dbg(codec, "write XFRCNT Reg fail\n");
2783                return status;
2784        }
2785        codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2786
2787        codec_dbg(codec,
2788                   "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2789                   "ADROFS=0x%x, XFRCNT=0x%x\n",
2790                   chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2791
2792        codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2793
2794        return 0;
2795}
2796
2797/*
2798 * Start the DSP DMA
2799 */
2800static int dsp_dma_start(struct hda_codec *codec,
2801                         unsigned int dma_chan, bool ovly)
2802{
2803        unsigned int reg = 0;
2804        int status = 0;
2805
2806        codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2807
2808        if (ovly) {
2809                status = chipio_read(codec,
2810                                     DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2811
2812                if (status < 0) {
2813                        codec_dbg(codec, "read CHNLSTART reg fail\n");
2814                        return status;
2815                }
2816                codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2817
2818                reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2819                                DSPDMAC_CHNLSTART_DIS_MASK);
2820        }
2821
2822        status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2823                        reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2824        if (status < 0) {
2825                codec_dbg(codec, "write CHNLSTART reg fail\n");
2826                return status;
2827        }
2828        codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2829
2830        return status;
2831}
2832
2833/*
2834 * Stop the DSP DMA
2835 */
2836static int dsp_dma_stop(struct hda_codec *codec,
2837                        unsigned int dma_chan, bool ovly)
2838{
2839        unsigned int reg = 0;
2840        int status = 0;
2841
2842        codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2843
2844        if (ovly) {
2845                status = chipio_read(codec,
2846                                     DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2847
2848                if (status < 0) {
2849                        codec_dbg(codec, "read CHNLSTART reg fail\n");
2850                        return status;
2851                }
2852                codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2853                reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2854                                DSPDMAC_CHNLSTART_DIS_MASK);
2855        }
2856
2857        status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2858                        reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2859        if (status < 0) {
2860                codec_dbg(codec, "write CHNLSTART reg fail\n");
2861                return status;
2862        }
2863        codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2864
2865        return status;
2866}
2867
2868/**
2869 * dsp_allocate_router_ports - Allocate router ports
2870 *
2871 * @codec: the HDA codec
2872 * @num_chans: number of channels in the stream
2873 * @ports_per_channel: number of ports per channel
2874 * @start_device: start device
2875 * @port_map: pointer to the port list to hold the allocated ports
2876 *
2877 * Returns zero or a negative error code.
2878 */
2879static int dsp_allocate_router_ports(struct hda_codec *codec,
2880                                     unsigned int num_chans,
2881                                     unsigned int ports_per_channel,
2882                                     unsigned int start_device,
2883                                     unsigned int *port_map)
2884{
2885        int status = 0;
2886        int res;
2887        u8 val;
2888
2889        status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2890        if (status < 0)
2891                return status;
2892
2893        val = start_device << 6;
2894        val |= (ports_per_channel - 1) << 4;
2895        val |= num_chans - 1;
2896
2897        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2898                            VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2899                            val);
2900
2901        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2902                            VENDOR_CHIPIO_PORT_ALLOC_SET,
2903                            MEM_CONNID_DSP);
2904
2905        status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2906        if (status < 0)
2907                return status;
2908
2909        res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2910                                VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2911
2912        *port_map = res;
2913
2914        return (res < 0) ? res : 0;
2915}
2916
2917/*
2918 * Free router ports
2919 */
2920static int dsp_free_router_ports(struct hda_codec *codec)
2921{
2922        int status = 0;
2923
2924        status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2925        if (status < 0)
2926                return status;
2927
2928        snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2929                            VENDOR_CHIPIO_PORT_FREE_SET,
2930                            MEM_CONNID_DSP);
2931
2932        status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2933
2934        return status;
2935}
2936
2937/*
2938 * Allocate DSP ports for the download stream
2939 */
2940static int dsp_allocate_ports(struct hda_codec *codec,
2941                        unsigned int num_chans,
2942                        unsigned int rate_multi, unsigned int *port_map)
2943{
2944        int status;
2945
2946        codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2947
2948        if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2949                codec_dbg(codec, "bad rate multiple\n");
2950                return -EINVAL;
2951        }
2952
2953        status = dsp_allocate_router_ports(codec, num_chans,
2954                                           rate_multi, 0, port_map);
2955
2956        codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2957
2958        return status;
2959}
2960
2961static int dsp_allocate_ports_format(struct hda_codec *codec,
2962                        const unsigned short fmt,
2963                        unsigned int *port_map)
2964{
2965        int status;
2966        unsigned int num_chans;
2967
2968        unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2969        unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2970        unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2971
2972        if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2973                codec_dbg(codec, "bad rate multiple\n");
2974                return -EINVAL;
2975        }
2976
2977        num_chans = get_hdafmt_chs(fmt) + 1;
2978
2979        status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2980
2981        return status;
2982}
2983
2984/*
2985 * free DSP ports
2986 */
2987static int dsp_free_ports(struct hda_codec *codec)
2988{
2989        int status;
2990
2991        codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2992
2993        status = dsp_free_router_ports(codec);
2994        if (status < 0) {
2995                codec_dbg(codec, "free router ports fail\n");
2996                return status;
2997        }
2998        codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2999
3000        return status;
3001}
3002
3003/*
3004 *  HDA DMA engine stuffs for DSP code download
3005 */
3006struct dma_engine {
3007        struct hda_codec *codec;
3008        unsigned short m_converter_format;
3009        struct snd_dma_buffer *dmab;
3010        unsigned int buf_size;
3011};
3012
3013
3014enum dma_state {
3015        DMA_STATE_STOP  = 0,
3016        DMA_STATE_RUN   = 1
3017};
3018
3019static int dma_convert_to_hda_format(struct hda_codec *codec,
3020                unsigned int sample_rate,
3021                unsigned short channels,
3022                unsigned short *hda_format)
3023{
3024        unsigned int format_val;
3025
3026        format_val = snd_hdac_calc_stream_format(sample_rate,
3027                                channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
3028
3029        if (hda_format)
3030                *hda_format = (unsigned short)format_val;
3031
3032        return 0;
3033}
3034
3035/*
3036 *  Reset DMA for DSP download
3037 */
3038static int dma_reset(struct dma_engine *dma)
3039{
3040        struct hda_codec *codec = dma->codec;
3041        struct ca0132_spec *spec = codec->spec;
3042        int status;
3043
3044        if (dma->dmab->area)
3045                snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
3046
3047        status = snd_hda_codec_load_dsp_prepare(codec,
3048                        dma->m_converter_format,
3049                        dma->buf_size,
3050                        dma->dmab);
3051        if (status < 0)
3052                return status;
3053        spec->dsp_stream_id = status;
3054        return 0;
3055}
3056
3057static int dma_set_state(struct dma_engine *dma, enum dma_state state)
3058{
3059        bool cmd;
3060
3061        switch (state) {
3062        case DMA_STATE_STOP:
3063                cmd = false;
3064                break;
3065        case DMA_STATE_RUN:
3066                cmd = true;
3067                break;
3068        default:
3069                return 0;
3070        }
3071
3072        snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
3073        return 0;
3074}
3075
3076static unsigned int dma_get_buffer_size(struct dma_engine *dma)
3077{
3078        return dma->dmab->bytes;
3079}
3080
3081static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
3082{
3083        return dma->dmab->area;
3084}
3085
3086static int dma_xfer(struct dma_engine *dma,
3087                const unsigned int *data,
3088                unsigned int count)
3089{
3090        memcpy(dma->dmab->area, data, count);
3091        return 0;
3092}
3093
3094static void dma_get_converter_format(
3095                struct dma_engine *dma,
3096                unsigned short *format)
3097{
3098        if (format)
3099                *format = dma->m_converter_format;
3100}
3101
3102static unsigned int dma_get_stream_id(struct dma_engine *dma)
3103{
3104        struct ca0132_spec *spec = dma->codec->spec;
3105
3106        return spec->dsp_stream_id;
3107}
3108
3109struct dsp_image_seg {
3110        u32 magic;
3111        u32 chip_addr;
3112        u32 count;
3113        u32 data[];
3114};
3115
3116static const u32 g_magic_value = 0x4c46584d;
3117static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3118
3119static bool is_valid(const struct dsp_image_seg *p)
3120{
3121        return p->magic == g_magic_value;
3122}
3123
3124static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3125{
3126        return g_chip_addr_magic_value == p->chip_addr;
3127}
3128
3129static bool is_last(const struct dsp_image_seg *p)
3130{
3131        return p->count == 0;
3132}
3133
3134static size_t dsp_sizeof(const struct dsp_image_seg *p)
3135{
3136        return struct_size(p, data, p->count);
3137}
3138
3139static const struct dsp_image_seg *get_next_seg_ptr(
3140                                const struct dsp_image_seg *p)
3141{
3142        return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3143}
3144
3145/*
3146 * CA0132 chip DSP transfer stuffs.  For DSP download.
3147 */
3148#define INVALID_DMA_CHANNEL (~0U)
3149
3150/*
3151 * Program a list of address/data pairs via the ChipIO widget.
3152 * The segment data is in the format of successive pairs of words.
3153 * These are repeated as indicated by the segment's count field.
3154 */
3155static int dspxfr_hci_write(struct hda_codec *codec,
3156                        const struct dsp_image_seg *fls)
3157{
3158        int status;
3159        const u32 *data;
3160        unsigned int count;
3161
3162        if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3163                codec_dbg(codec, "hci_write invalid params\n");
3164                return -EINVAL;
3165        }
3166
3167        count = fls->count;
3168        data = (u32 *)(fls->data);
3169        while (count >= 2) {
3170                status = chipio_write(codec, data[0], data[1]);
3171                if (status < 0) {
3172                        codec_dbg(codec, "hci_write chipio failed\n");
3173                        return status;
3174                }
3175                count -= 2;
3176                data  += 2;
3177        }
3178        return 0;
3179}
3180
3181/**
3182 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine.
3183 *
3184 * @codec: the HDA codec
3185 * @fls: pointer to a fast load image
3186 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3187 *         no relocation
3188 * @dma_engine: pointer to DMA engine to be used for DSP download
3189 * @dma_chan: The number of DMA channels used for DSP download
3190 * @port_map_mask: port mapping
3191 * @ovly: TRUE if overlay format is required
3192 *
3193 * Returns zero or a negative error code.
3194 */
3195static int dspxfr_one_seg(struct hda_codec *codec,
3196                        const struct dsp_image_seg *fls,
3197                        unsigned int reloc,
3198                        struct dma_engine *dma_engine,
3199                        unsigned int dma_chan,
3200                        unsigned int port_map_mask,
3201                        bool ovly)
3202{
3203        int status = 0;
3204        bool comm_dma_setup_done = false;
3205        const unsigned int *data;
3206        unsigned int chip_addx;
3207        unsigned int words_to_write;
3208        unsigned int buffer_size_words;
3209        unsigned char *buffer_addx;
3210        unsigned short hda_format;
3211        unsigned int sample_rate_div;
3212        unsigned int sample_rate_mul;
3213        unsigned int num_chans;
3214        unsigned int hda_frame_size_words;
3215        unsigned int remainder_words;
3216        const u32 *data_remainder;
3217        u32 chip_addx_remainder;
3218        unsigned int run_size_words;
3219        const struct dsp_image_seg *hci_write = NULL;
3220        unsigned long timeout;
3221        bool dma_active;
3222
3223        if (fls == NULL)
3224                return -EINVAL;
3225        if (is_hci_prog_list_seg(fls)) {
3226                hci_write = fls;
3227                fls = get_next_seg_ptr(fls);
3228        }
3229
3230        if (hci_write && (!fls || is_last(fls))) {
3231                codec_dbg(codec, "hci_write\n");
3232                return dspxfr_hci_write(codec, hci_write);
3233        }
3234
3235        if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3236                codec_dbg(codec, "Invalid Params\n");
3237                return -EINVAL;
3238        }
3239
3240        data = fls->data;
3241        chip_addx = fls->chip_addr;
3242        words_to_write = fls->count;
3243
3244        if (!words_to_write)
3245                return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3246        if (reloc)
3247                chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3248
3249        if (!UC_RANGE(chip_addx, words_to_write) &&
3250            !X_RANGE_ALL(chip_addx, words_to_write) &&
3251            !Y_RANGE_ALL(chip_addx, words_to_write)) {
3252                codec_dbg(codec, "Invalid chip_addx Params\n");
3253                return -EINVAL;
3254        }
3255
3256        buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3257                                        sizeof(u32);
3258
3259        buffer_addx = dma_get_buffer_addr(dma_engine);
3260
3261        if (buffer_addx == NULL) {
3262                codec_dbg(codec, "dma_engine buffer NULL\n");
3263                return -EINVAL;
3264        }
3265
3266        dma_get_converter_format(dma_engine, &hda_format);
3267        sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3268        sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3269        num_chans = get_hdafmt_chs(hda_format) + 1;
3270
3271        hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3272                        (num_chans * sample_rate_mul / sample_rate_div));
3273
3274        if (hda_frame_size_words == 0) {
3275                codec_dbg(codec, "frmsz zero\n");
3276                return -EINVAL;
3277        }
3278
3279        buffer_size_words = min(buffer_size_words,
3280                                (unsigned int)(UC_RANGE(chip_addx, 1) ?
3281                                65536 : 32768));
3282        buffer_size_words -= buffer_size_words % hda_frame_size_words;
3283        codec_dbg(codec,
3284                   "chpadr=0x%08x frmsz=%u nchan=%u "
3285                   "rate_mul=%u div=%u bufsz=%u\n",
3286                   chip_addx, hda_frame_size_words, num_chans,
3287                   sample_rate_mul, sample_rate_div, buffer_size_words);
3288
3289        if (buffer_size_words < hda_frame_size_words) {
3290                codec_dbg(codec, "dspxfr_one_seg:failed\n");
3291                return -EINVAL;
3292        }
3293
3294        remainder_words = words_to_write % hda_frame_size_words;
3295        data_remainder = data;
3296        chip_addx_remainder = chip_addx;
3297
3298        data += remainder_words;
3299        chip_addx += remainder_words*sizeof(u32);
3300        words_to_write -= remainder_words;
3301
3302        while (words_to_write != 0) {
3303                run_size_words = min(buffer_size_words, words_to_write);
3304                codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3305                            words_to_write, run_size_words, remainder_words);
3306                dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3307                if (!comm_dma_setup_done) {
3308                        status = dsp_dma_stop(codec, dma_chan, ovly);
3309                        if (status < 0)
3310                                return status;
3311                        status = dsp_dma_setup_common(codec, chip_addx,
3312                                                dma_chan, port_map_mask, ovly);
3313                        if (status < 0)
3314                                return status;
3315                        comm_dma_setup_done = true;
3316                }
3317
3318                status = dsp_dma_setup(codec, chip_addx,
3319                                                run_size_words, dma_chan);
3320                if (status < 0)
3321                        return status;
3322                status = dsp_dma_start(codec, dma_chan, ovly);
3323                if (status < 0)
3324                        return status;
3325                if (!dsp_is_dma_active(codec, dma_chan)) {
3326                        codec_dbg(codec, "dspxfr:DMA did not start\n");
3327                        return -EIO;
3328                }
3329                status = dma_set_state(dma_engine, DMA_STATE_RUN);
3330                if (status < 0)
3331                        return status;
3332                if (remainder_words != 0) {
3333                        status = chipio_write_multiple(codec,
3334                                                chip_addx_remainder,
3335                                                data_remainder,
3336                                                remainder_words);
3337                        if (status < 0)
3338                                return status;
3339                        remainder_words = 0;
3340                }
3341                if (hci_write) {
3342                        status = dspxfr_hci_write(codec, hci_write);
3343                        if (status < 0)
3344                                return status;
3345                        hci_write = NULL;
3346                }
3347
3348                timeout = jiffies + msecs_to_jiffies(2000);
3349                do {
3350                        dma_active = dsp_is_dma_active(codec, dma_chan);
3351                        if (!dma_active)
3352                                break;
3353                        msleep(20);
3354                } while (time_before(jiffies, timeout));
3355                if (dma_active)
3356                        break;
3357
3358                codec_dbg(codec, "+++++ DMA complete\n");
3359                dma_set_state(dma_engine, DMA_STATE_STOP);
3360                status = dma_reset(dma_engine);
3361
3362                if (status < 0)
3363                        return status;
3364
3365                data += run_size_words;
3366                chip_addx += run_size_words*sizeof(u32);
3367                words_to_write -= run_size_words;
3368        }
3369
3370        if (remainder_words != 0) {
3371                status = chipio_write_multiple(codec, chip_addx_remainder,
3372                                        data_remainder, remainder_words);
3373        }
3374
3375        return status;
3376}
3377
3378/**
3379 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories
3380 *
3381 * @codec: the HDA codec
3382 * @fls_data: pointer to a fast load image
3383 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3384 *         no relocation
3385 * @sample_rate: sampling rate of the stream used for DSP download
3386 * @channels: channels of the stream used for DSP download
3387 * @ovly: TRUE if overlay format is required
3388 *
3389 * Returns zero or a negative error code.
3390 */
3391static int dspxfr_image(struct hda_codec *codec,
3392                        const struct dsp_image_seg *fls_data,
3393                        unsigned int reloc,
3394                        unsigned int sample_rate,
3395                        unsigned short channels,
3396                        bool ovly)
3397{
3398        struct ca0132_spec *spec = codec->spec;
3399        int status;
3400        unsigned short hda_format = 0;
3401        unsigned int response;
3402        unsigned char stream_id = 0;
3403        struct dma_engine *dma_engine;
3404        unsigned int dma_chan;
3405        unsigned int port_map_mask;
3406
3407        if (fls_data == NULL)
3408                return -EINVAL;
3409
3410        dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3411        if (!dma_engine)
3412                return -ENOMEM;
3413
3414        dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3415        if (!dma_engine->dmab) {
3416                kfree(dma_engine);
3417                return -ENOMEM;
3418        }
3419
3420        dma_engine->codec = codec;
3421        dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3422        dma_engine->m_converter_format = hda_format;
3423        dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3424                        DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3425
3426        dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3427
3428        status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3429                                        hda_format, &response);
3430
3431        if (status < 0) {
3432                codec_dbg(codec, "set converter format fail\n");
3433                goto exit;
3434        }
3435
3436        status = snd_hda_codec_load_dsp_prepare(codec,
3437                                dma_engine->m_converter_format,
3438                                dma_engine->buf_size,
3439                                dma_engine->dmab);
3440        if (status < 0)
3441                goto exit;
3442        spec->dsp_stream_id = status;
3443
3444        if (ovly) {
3445                status = dspio_alloc_dma_chan(codec, &dma_chan);
3446                if (status < 0) {
3447                        codec_dbg(codec, "alloc dmachan fail\n");
3448                        dma_chan = INVALID_DMA_CHANNEL;
3449                        goto exit;
3450                }
3451        }
3452
3453        port_map_mask = 0;
3454        status = dsp_allocate_ports_format(codec, hda_format,
3455                                        &port_map_mask);
3456        if (status < 0) {
3457                codec_dbg(codec, "alloc ports fail\n");
3458                goto exit;
3459        }
3460
3461        stream_id = dma_get_stream_id(dma_engine);
3462        status = codec_set_converter_stream_channel(codec,
3463                        WIDGET_CHIP_CTRL, stream_id, 0, &response);
3464        if (status < 0) {
3465                codec_dbg(codec, "set stream chan fail\n");
3466                goto exit;
3467        }
3468
3469        while ((fls_data != NULL) && !is_last(fls_data)) {
3470                if (!is_valid(fls_data)) {
3471                        codec_dbg(codec, "FLS check fail\n");
3472                        status = -EINVAL;
3473                        goto exit;
3474                }
3475                status = dspxfr_one_seg(codec, fls_data, reloc,
3476                                        dma_engine, dma_chan,
3477                                        port_map_mask, ovly);
3478                if (status < 0)
3479                        break;
3480
3481                if (is_hci_prog_list_seg(fls_data))
3482                        fls_data = get_next_seg_ptr(fls_data);
3483
3484                if ((fls_data != NULL) && !is_last(fls_data))
3485                        fls_data = get_next_seg_ptr(fls_data);
3486        }
3487
3488        if (port_map_mask != 0)
3489                status = dsp_free_ports(codec);
3490
3491        if (status < 0)
3492                goto exit;
3493
3494        status = codec_set_converter_stream_channel(codec,
3495                                WIDGET_CHIP_CTRL, 0, 0, &response);
3496
3497exit:
3498        if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3499                dspio_free_dma_chan(codec, dma_chan);
3500
3501        if (dma_engine->dmab->area)
3502                snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3503        kfree(dma_engine->dmab);
3504        kfree(dma_engine);
3505
3506        return status;
3507}
3508
3509/*
3510 * CA0132 DSP download stuffs.
3511 */
3512static void dspload_post_setup(struct hda_codec *codec)
3513{
3514        struct ca0132_spec *spec = codec->spec;
3515        codec_dbg(codec, "---- dspload_post_setup ------\n");
3516        if (!ca0132_use_alt_functions(spec)) {
3517                /*set DSP speaker to 2.0 configuration*/
3518                chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3519                chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3520
3521                /*update write pointer*/
3522                chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3523        }
3524}
3525
3526/**
3527 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3528 *
3529 * @codec: the HDA codec
3530 * @fls: pointer to a fast load image
3531 * @ovly: TRUE if overlay format is required
3532 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3533 *         no relocation
3534 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3535 * @router_chans: number of audio router channels to be allocated (0 means use
3536 *                internal defaults; max is 32)
3537 *
3538 * Download DSP from a DSP Image Fast Load structure. This structure is a
3539 * linear, non-constant sized element array of structures, each of which
3540 * contain the count of the data to be loaded, the data itself, and the
3541 * corresponding starting chip address of the starting data location.
3542 * Returns zero or a negative error code.
3543 */
3544static int dspload_image(struct hda_codec *codec,
3545                        const struct dsp_image_seg *fls,
3546                        bool ovly,
3547                        unsigned int reloc,
3548                        bool autostart,
3549                        int router_chans)
3550{
3551        int status = 0;
3552        unsigned int sample_rate;
3553        unsigned short channels;
3554
3555        codec_dbg(codec, "---- dspload_image begin ------\n");
3556        if (router_chans == 0) {
3557                if (!ovly)
3558                        router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3559                else
3560                        router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3561        }
3562
3563        sample_rate = 48000;
3564        channels = (unsigned short)router_chans;
3565
3566        while (channels > 16) {
3567                sample_rate *= 2;
3568                channels /= 2;
3569        }
3570
3571        do {
3572                codec_dbg(codec, "Ready to program DMA\n");
3573                if (!ovly)
3574                        status = dsp_reset(codec);
3575
3576                if (status < 0)
3577                        break;
3578
3579                codec_dbg(codec, "dsp_reset() complete\n");
3580                status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3581                                      ovly);
3582
3583                if (status < 0)
3584                        break;
3585
3586                codec_dbg(codec, "dspxfr_image() complete\n");
3587                if (autostart && !ovly) {
3588                        dspload_post_setup(codec);
3589                        status = dsp_set_run_state(codec);
3590                }
3591
3592                codec_dbg(codec, "LOAD FINISHED\n");
3593        } while (0);
3594
3595        return status;
3596}
3597
3598#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3599static bool dspload_is_loaded(struct hda_codec *codec)
3600{
3601        unsigned int data = 0;
3602        int status = 0;
3603
3604        status = chipio_read(codec, 0x40004, &data);
3605        if ((status < 0) || (data != 1))
3606                return false;
3607
3608        return true;
3609}
3610#else
3611#define dspload_is_loaded(codec)        false
3612#endif
3613
3614static bool dspload_wait_loaded(struct hda_codec *codec)
3615{
3616        unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3617
3618        do {
3619                if (dspload_is_loaded(codec)) {
3620                        codec_info(codec, "ca0132 DSP downloaded and running\n");
3621                        return true;
3622                }
3623                msleep(20);
3624        } while (time_before(jiffies, timeout));
3625
3626        codec_err(codec, "ca0132 failed to download DSP\n");
3627        return false;
3628}
3629
3630/*
3631 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3632 * based cards, and has a second mmio region, region2, that's used for special
3633 * commands.
3634 */
3635
3636/*
3637 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3638 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3639 * The first eight bits are just the number of the pin. So far, I've only seen
3640 * this number go to 7.
3641 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3642 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3643 * then off to send that bit.
3644 */
3645static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3646                bool enable)
3647{
3648        struct ca0132_spec *spec = codec->spec;
3649        unsigned short gpio_data;
3650
3651        gpio_data = gpio_pin & 0xF;
3652        gpio_data |= ((enable << 8) & 0x100);
3653
3654        writew(gpio_data, spec->mem_base + 0x320);
3655}
3656
3657/*
3658 * Special pci region2 commands that are only used by the AE-5. They follow
3659 * a set format, and require reads at certain points to seemingly 'clear'
3660 * the response data. My first tests didn't do these reads, and would cause
3661 * the card to get locked up until the memory was read. These commands
3662 * seem to work with three distinct values that I've taken to calling group,
3663 * target-id, and value.
3664 */
3665static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3666                unsigned int target, unsigned int value)
3667{
3668        struct ca0132_spec *spec = codec->spec;
3669        unsigned int write_val;
3670
3671        writel(0x0000007e, spec->mem_base + 0x210);
3672        readl(spec->mem_base + 0x210);
3673        writel(0x0000005a, spec->mem_base + 0x210);
3674        readl(spec->mem_base + 0x210);
3675        readl(spec->mem_base + 0x210);
3676
3677        writel(0x00800005, spec->mem_base + 0x20c);
3678        writel(group, spec->mem_base + 0x804);
3679
3680        writel(0x00800005, spec->mem_base + 0x20c);
3681        write_val = (target & 0xff);
3682        write_val |= (value << 8);
3683
3684
3685        writel(write_val, spec->mem_base + 0x204);
3686        /*
3687         * Need delay here or else it goes too fast and works inconsistently.
3688         */
3689        msleep(20);
3690
3691        readl(spec->mem_base + 0x860);
3692        readl(spec->mem_base + 0x854);
3693        readl(spec->mem_base + 0x840);
3694
3695        writel(0x00800004, spec->mem_base + 0x20c);
3696        writel(0x00000000, spec->mem_base + 0x210);
3697        readl(spec->mem_base + 0x210);
3698        readl(spec->mem_base + 0x210);
3699}
3700
3701/*
3702 * This second type of command is used for setting the sound filter type.
3703 */
3704static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3705                unsigned int group, unsigned int target, unsigned int value)
3706{
3707        struct ca0132_spec *spec = codec->spec;
3708        unsigned int write_val;
3709
3710        writel(0x0000007e, spec->mem_base + 0x210);
3711        readl(spec->mem_base + 0x210);
3712        writel(0x0000005a, spec->mem_base + 0x210);
3713        readl(spec->mem_base + 0x210);
3714        readl(spec->mem_base + 0x210);
3715
3716        writel(0x00800003, spec->mem_base + 0x20c);
3717        writel(group, spec->mem_base + 0x804);
3718
3719        writel(0x00800005, spec->mem_base + 0x20c);
3720        write_val = (target & 0xff);
3721        write_val |= (value << 8);
3722
3723
3724        writel(write_val, spec->mem_base + 0x204);
3725        msleep(20);
3726        readl(spec->mem_base + 0x860);
3727        readl(spec->mem_base + 0x854);
3728        readl(spec->mem_base + 0x840);
3729
3730        writel(0x00800004, spec->mem_base + 0x20c);
3731        writel(0x00000000, spec->mem_base + 0x210);
3732        readl(spec->mem_base + 0x210);
3733        readl(spec->mem_base + 0x210);
3734}
3735
3736/*
3737 * Setup GPIO for the other variants of Core3D.
3738 */
3739
3740/*
3741 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3742 * the card shows as having no GPIO pins.
3743 */
3744static void ca0132_gpio_init(struct hda_codec *codec)
3745{
3746        struct ca0132_spec *spec = codec->spec;
3747
3748        switch (ca0132_quirk(spec)) {
3749        case QUIRK_SBZ:
3750        case QUIRK_AE5:
3751        case QUIRK_AE7:
3752                snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3753                snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3754                snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3755                break;
3756        case QUIRK_R3DI:
3757                snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3758                snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3759                break;
3760        default:
3761                break;
3762        }
3763
3764}
3765
3766/* Sets the GPIO for audio output. */
3767static void ca0132_gpio_setup(struct hda_codec *codec)
3768{
3769        struct ca0132_spec *spec = codec->spec;
3770
3771        switch (ca0132_quirk(spec)) {
3772        case QUIRK_SBZ:
3773                snd_hda_codec_write(codec, 0x01, 0,
3774                                AC_VERB_SET_GPIO_DIRECTION, 0x07);
3775                snd_hda_codec_write(codec, 0x01, 0,
3776                                AC_VERB_SET_GPIO_MASK, 0x07);
3777                snd_hda_codec_write(codec, 0x01, 0,
3778                                AC_VERB_SET_GPIO_DATA, 0x04);
3779                snd_hda_codec_write(codec, 0x01, 0,
3780                                AC_VERB_SET_GPIO_DATA, 0x06);
3781                break;
3782        case QUIRK_R3DI:
3783                snd_hda_codec_write(codec, 0x01, 0,
3784                                AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3785                snd_hda_codec_write(codec, 0x01, 0,
3786                                AC_VERB_SET_GPIO_MASK, 0x1F);
3787                snd_hda_codec_write(codec, 0x01, 0,
3788                                AC_VERB_SET_GPIO_DATA, 0x0C);
3789                break;
3790        default:
3791                break;
3792        }
3793}
3794
3795/*
3796 * GPIO control functions for the Recon3D integrated.
3797 */
3798
3799enum r3di_gpio_bit {
3800        /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3801        R3DI_MIC_SELECT_BIT = 1,
3802        /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3803        R3DI_OUT_SELECT_BIT = 2,
3804        /*
3805         * I dunno what this actually does, but it stays on until the dsp
3806         * is downloaded.
3807         */
3808        R3DI_GPIO_DSP_DOWNLOADING = 3,
3809        /*
3810         * Same as above, no clue what it does, but it comes on after the dsp
3811         * is downloaded.
3812         */
3813        R3DI_GPIO_DSP_DOWNLOADED = 4
3814};
3815
3816enum r3di_mic_select {
3817        /* Set GPIO bit 1 to 0 for rear mic */
3818        R3DI_REAR_MIC = 0,
3819        /* Set GPIO bit 1 to 1 for front microphone*/
3820        R3DI_FRONT_MIC = 1
3821};
3822
3823enum r3di_out_select {
3824        /* Set GPIO bit 2 to 0 for headphone */
3825        R3DI_HEADPHONE_OUT = 0,
3826        /* Set GPIO bit 2 to 1 for speaker */
3827        R3DI_LINE_OUT = 1
3828};
3829enum r3di_dsp_status {
3830        /* Set GPIO bit 3 to 1 until DSP is downloaded */
3831        R3DI_DSP_DOWNLOADING = 0,
3832        /* Set GPIO bit 4 to 1 once DSP is downloaded */
3833        R3DI_DSP_DOWNLOADED = 1
3834};
3835
3836
3837static void r3di_gpio_mic_set(struct hda_codec *codec,
3838                enum r3di_mic_select cur_mic)
3839{
3840        unsigned int cur_gpio;
3841
3842        /* Get the current GPIO Data setup */
3843        cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3844
3845        switch (cur_mic) {
3846        case R3DI_REAR_MIC:
3847                cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3848                break;
3849        case R3DI_FRONT_MIC:
3850                cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3851                break;
3852        }
3853        snd_hda_codec_write(codec, codec->core.afg, 0,
3854                            AC_VERB_SET_GPIO_DATA, cur_gpio);
3855}
3856
3857static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3858                enum r3di_dsp_status dsp_status)
3859{
3860        unsigned int cur_gpio;
3861
3862        /* Get the current GPIO Data setup */
3863        cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3864
3865        switch (dsp_status) {
3866        case R3DI_DSP_DOWNLOADING:
3867                cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3868                snd_hda_codec_write(codec, codec->core.afg, 0,
3869                                AC_VERB_SET_GPIO_DATA, cur_gpio);
3870                break;
3871        case R3DI_DSP_DOWNLOADED:
3872                /* Set DOWNLOADING bit to 0. */
3873                cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3874
3875                snd_hda_codec_write(codec, codec->core.afg, 0,
3876                                AC_VERB_SET_GPIO_DATA, cur_gpio);
3877
3878                cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3879                break;
3880        }
3881
3882        snd_hda_codec_write(codec, codec->core.afg, 0,
3883                            AC_VERB_SET_GPIO_DATA, cur_gpio);
3884}
3885
3886/*
3887 * PCM callbacks
3888 */
3889static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3890                        struct hda_codec *codec,
3891                        unsigned int stream_tag,
3892                        unsigned int format,
3893                        struct snd_pcm_substream *substream)
3894{
3895        struct ca0132_spec *spec = codec->spec;
3896
3897        snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3898
3899        return 0;
3900}
3901
3902static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3903                        struct hda_codec *codec,
3904                        struct snd_pcm_substream *substream)
3905{
3906        struct ca0132_spec *spec = codec->spec;
3907
3908        if (spec->dsp_state == DSP_DOWNLOADING)
3909                return 0;
3910
3911        /*If Playback effects are on, allow stream some time to flush
3912         *effects tail*/
3913        if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3914                msleep(50);
3915
3916        snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3917
3918        return 0;
3919}
3920
3921static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3922                        struct hda_codec *codec,
3923                        struct snd_pcm_substream *substream)
3924{
3925        struct ca0132_spec *spec = codec->spec;
3926        unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3927        struct snd_pcm_runtime *runtime = substream->runtime;
3928
3929        if (spec->dsp_state != DSP_DOWNLOADED)
3930                return 0;
3931
3932        /* Add latency if playback enhancement and either effect is enabled. */
3933        if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3934                if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3935                    (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3936                        latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3937        }
3938
3939        /* Applying Speaker EQ adds latency as well. */
3940        if (spec->cur_out_type == SPEAKER_OUT)
3941                latency += DSP_SPEAKER_OUT_LATENCY;
3942
3943        return (latency * runtime->rate) / 1000;
3944}
3945
3946/*
3947 * Digital out
3948 */
3949static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3950                                        struct hda_codec *codec,
3951                                        struct snd_pcm_substream *substream)
3952{
3953        struct ca0132_spec *spec = codec->spec;
3954        return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3955}
3956
3957static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3958                        struct hda_codec *codec,
3959                        unsigned int stream_tag,
3960                        unsigned int format,
3961                        struct snd_pcm_substream *substream)
3962{
3963        struct ca0132_spec *spec = codec->spec;
3964        return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3965                                             stream_tag, format, substream);
3966}
3967
3968static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3969                        struct hda_codec *codec,
3970                        struct snd_pcm_substream *substream)
3971{
3972        struct ca0132_spec *spec = codec->spec;
3973        return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3974}
3975
3976static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3977                                         struct hda_codec *codec,
3978                                         struct snd_pcm_substream *substream)
3979{
3980        struct ca0132_spec *spec = codec->spec;
3981        return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3982}
3983
3984/*
3985 * Analog capture
3986 */
3987static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3988                                        struct hda_codec *codec,
3989                                        unsigned int stream_tag,
3990                                        unsigned int format,
3991                                        struct snd_pcm_substream *substream)
3992{
3993        snd_hda_codec_setup_stream(codec, hinfo->nid,
3994                                   stream_tag, 0, format);
3995
3996        return 0;
3997}
3998
3999static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
4000                        struct hda_codec *codec,
4001                        struct snd_pcm_substream *substream)
4002{
4003        struct ca0132_spec *spec = codec->spec;
4004
4005        if (spec->dsp_state == DSP_DOWNLOADING)
4006                return 0;
4007
4008        snd_hda_codec_cleanup_stream(codec, hinfo->nid);
4009        return 0;
4010}
4011
4012static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
4013                        struct hda_codec *codec,
4014                        struct snd_pcm_substream *substream)
4015{
4016        struct ca0132_spec *spec = codec->spec;
4017        unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
4018        struct snd_pcm_runtime *runtime = substream->runtime;
4019
4020        if (spec->dsp_state != DSP_DOWNLOADED)
4021                return 0;
4022
4023        if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4024                latency += DSP_CRYSTAL_VOICE_LATENCY;
4025
4026        return (latency * runtime->rate) / 1000;
4027}
4028
4029/*
4030 * Controls stuffs.
4031 */
4032
4033/*
4034 * Mixer controls helpers.
4035 */
4036#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
4037        { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4038          .name = xname, \
4039          .subdevice = HDA_SUBDEV_AMP_FLAG, \
4040          .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4041                        SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4042                        SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4043          .info = ca0132_volume_info, \
4044          .get = ca0132_volume_get, \
4045          .put = ca0132_volume_put, \
4046          .tlv = { .c = ca0132_volume_tlv }, \
4047          .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4048
4049/*
4050 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
4051 * volume put, which is used for setting the DSP volume. This was done because
4052 * the ca0132 functions were taking too much time and causing lag.
4053 */
4054#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
4055        { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4056          .name = xname, \
4057          .subdevice = HDA_SUBDEV_AMP_FLAG, \
4058          .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4059                        SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4060                        SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4061          .info = snd_hda_mixer_amp_volume_info, \
4062          .get = snd_hda_mixer_amp_volume_get, \
4063          .put = ca0132_alt_volume_put, \
4064          .tlv = { .c = snd_hda_mixer_amp_tlv }, \
4065          .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4066
4067#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
4068        { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4069          .name = xname, \
4070          .subdevice = HDA_SUBDEV_AMP_FLAG, \
4071          .info = snd_hda_mixer_amp_switch_info, \
4072          .get = ca0132_switch_get, \
4073          .put = ca0132_switch_put, \
4074          .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4075
4076/* stereo */
4077#define CA0132_CODEC_VOL(xname, nid, dir) \
4078        CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
4079#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
4080        CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
4081#define CA0132_CODEC_MUTE(xname, nid, dir) \
4082        CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
4083
4084/* lookup tables */
4085/*
4086 * Lookup table with decibel values for the DSP. When volume is changed in
4087 * Windows, the DSP is also sent the dB value in floating point. In Windows,
4088 * these values have decimal points, probably because the Windows driver
4089 * actually uses floating point. We can't here, so I made a lookup table of
4090 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
4091 * DAC's, and 9 is the maximum.
4092 */
4093static const unsigned int float_vol_db_lookup[] = {
40940xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
40950xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
40960xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
40970xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
40980xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
40990xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
41000xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
41010xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
41020xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
41030xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
41040xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
41050xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
41060xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
41070xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
41080xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
41090x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
41100x40C00000, 0x40E00000, 0x41000000, 0x41100000
4111};
4112
4113/*
4114 * This table counts from float 0 to 1 in increments of .01, which is
4115 * useful for a few different sliders.
4116 */
4117static const unsigned int float_zero_to_one_lookup[] = {
41180x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
41190x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
41200x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
41210x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
41220x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
41230x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
41240x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
41250x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
41260x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
41270x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
41280x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
41290x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
41300x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
41310x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
41320x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
41330x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
41340x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4135};
4136
4137/*
4138 * This table counts from float 10 to 1000, which is the range of the x-bass
4139 * crossover slider in Windows.
4140 */
4141static const unsigned int float_xbass_xover_lookup[] = {
41420x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
41430x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
41440x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
41450x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
41460x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
41470x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
41480x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
41490x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
41500x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
41510x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
41520x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
41530x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
41540x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
41550x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
41560x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
41570x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
41580x44728000, 0x44750000, 0x44778000, 0x447A0000
4159};
4160
4161/* The following are for tuning of products */
4162#ifdef ENABLE_TUNING_CONTROLS
4163
4164static const unsigned int voice_focus_vals_lookup[] = {
41650x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
41660x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
41670x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
41680x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
41690x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
41700x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
41710x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
41720x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
41730x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
41740x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
41750x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
41760x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
41770x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
41780x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
41790x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
41800x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
41810x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
41820x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
41830x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
41840x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
41850x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
41860x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
41870x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
41880x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
41890x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
41900x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
41910x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4192};
4193
4194static const unsigned int mic_svm_vals_lookup[] = {
41950x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
41960x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
41970x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
41980x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
41990x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
42000x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
42010x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
42020x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
42030x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
42040x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
42050x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
42060x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
42070x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
42080x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
42090x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
42100x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
42110x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4212};
4213
4214static const unsigned int equalizer_vals_lookup[] = {
42150xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
42160xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
42170xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
42180xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
42190x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
42200x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
42210x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
42220x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
42230x41C00000
4224};
4225
4226static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4227                          const unsigned int *lookup, int idx)
4228{
4229        int i = 0;
4230
4231        for (i = 0; i < TUNING_CTLS_COUNT; i++)
4232                if (nid == ca0132_tuning_ctls[i].nid)
4233                        break;
4234
4235        snd_hda_power_up(codec);
4236        dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4237                        ca0132_tuning_ctls[i].req,
4238                        &(lookup[idx]), sizeof(unsigned int));
4239        snd_hda_power_down(codec);
4240
4241        return 1;
4242}
4243
4244static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4245                          struct snd_ctl_elem_value *ucontrol)
4246{
4247        struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4248        struct ca0132_spec *spec = codec->spec;
4249        hda_nid_t nid = get_amp_nid(kcontrol);
4250        long *valp = ucontrol->value.integer.value;
4251        int idx = nid - TUNING_CTL_START_NID;
4252
4253        *valp = spec->cur_ctl_vals[idx];
4254        return 0;
4255}
4256
4257static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4258                              struct snd_ctl_elem_info *uinfo)
4259{
4260        int chs = get_amp_channels(kcontrol);
4261        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4262        uinfo->count = chs == 3 ? 2 : 1;
4263        uinfo->value.integer.min = 20;
4264        uinfo->value.integer.max = 180;
4265        uinfo->value.integer.step = 1;
4266
4267        return 0;
4268}
4269
4270static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4271                                struct snd_ctl_elem_value *ucontrol)
4272{
4273        struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4274        struct ca0132_spec *spec = codec->spec;
4275        hda_nid_t nid = get_amp_nid(kcontrol);
4276        long *valp = ucontrol->value.integer.value;
4277        int idx;
4278
4279        idx = nid - TUNING_CTL_START_NID;
4280        /* any change? */
4281        if (spec->cur_ctl_vals[idx] == *valp)
4282                return 0;
4283
4284        spec->cur_ctl_vals[idx] = *valp;
4285
4286        idx = *valp - 20;
4287        tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4288
4289        return 1;
4290}
4291
4292static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4293                              struct snd_ctl_elem_info *uinfo)
4294{
4295        int chs = get_amp_channels(kcontrol);
4296        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4297        uinfo->count = chs == 3 ? 2 : 1;
4298        uinfo->value.integer.min = 0;
4299        uinfo->value.integer.max = 100;
4300        uinfo->value.integer.step = 1;
4301
4302        return 0;
4303}
4304
4305static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4306                                struct snd_ctl_elem_value *ucontrol)
4307{
4308        struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4309        struct ca0132_spec *spec = codec->spec;
4310        hda_nid_t nid = get_amp_nid(kcontrol);
4311        long *valp = ucontrol->value.integer.value;
4312        int idx;
4313
4314        idx = nid - TUNING_CTL_START_NID;
4315        /* any change? */
4316        if (spec->cur_ctl_vals[idx] == *valp)
4317                return 0;
4318
4319        spec->cur_ctl_vals[idx] = *valp;
4320
4321        idx = *valp;
4322        tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4323
4324        return 0;
4325}
4326
4327static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4328                              struct snd_ctl_elem_info *uinfo)
4329{
4330        int chs = get_amp_channels(kcontrol);
4331        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4332        uinfo->count = chs == 3 ? 2 : 1;
4333        uinfo->value.integer.min = 0;
4334        uinfo->value.integer.max = 48;
4335        uinfo->value.integer.step = 1;
4336
4337        return 0;
4338}
4339
4340static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4341                                struct snd_ctl_elem_value *ucontrol)
4342{
4343        struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4344        struct ca0132_spec *spec = codec->spec;
4345        hda_nid_t nid = get_amp_nid(kcontrol);
4346        long *valp = ucontrol->value.integer.value;
4347        int idx;
4348
4349        idx = nid - TUNING_CTL_START_NID;
4350        /* any change? */
4351        if (spec->cur_ctl_vals[idx] == *valp)
4352                return 0;
4353
4354        spec->cur_ctl_vals[idx] = *valp;
4355
4356        idx = *valp;
4357        tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4358
4359        return 1;
4360}
4361
4362static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4363static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4364
4365static int add_tuning_control(struct hda_codec *codec,
4366                                hda_nid_t pnid, hda_nid_t nid,
4367                                const char *name, int dir)
4368{
4369        char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4370        int type = dir ? HDA_INPUT : HDA_OUTPUT;
4371        struct snd_kcontrol_new knew =
4372                HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4373
4374        knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4375                        SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4376        knew.tlv.c = 0;
4377        knew.tlv.p = 0;
4378        switch (pnid) {
4379        case VOICE_FOCUS:
4380                knew.info = voice_focus_ctl_info;
4381                knew.get = tuning_ctl_get;
4382                knew.put = voice_focus_ctl_put;
4383                knew.tlv.p = voice_focus_db_scale;
4384                break;
4385        case MIC_SVM:
4386                knew.info = mic_svm_ctl_info;
4387                knew.get = tuning_ctl_get;
4388                knew.put = mic_svm_ctl_put;
4389                break;
4390        case EQUALIZER:
4391                knew.info = equalizer_ctl_info;
4392                knew.get = tuning_ctl_get;
4393                knew.put = equalizer_ctl_put;
4394                knew.tlv.p = eq_db_scale;
4395                break;
4396        default:
4397                return 0;
4398        }
4399        knew.private_value =
4400                HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4401        sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4402        return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4403}
4404
4405static int add_tuning_ctls(struct hda_codec *codec)
4406{
4407        int i;
4408        int err;
4409
4410        for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4411                err = add_tuning_control(codec,
4412                                        ca0132_tuning_ctls[i].parent_nid,
4413                                        ca0132_tuning_ctls[i].nid,
4414                                        ca0132_tuning_ctls[i].name,
4415                                        ca0132_tuning_ctls[i].direct);
4416                if (err < 0)
4417                        return err;
4418        }
4419
4420        return 0;
4421}
4422
4423static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4424{
4425        struct ca0132_spec *spec = codec->spec;
4426        int i;
4427
4428        /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
4429        spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4430        /* SVM level defaults to 0.74. */
4431        spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4432
4433        /* EQ defaults to 0dB. */
4434        for (i = 2; i < TUNING_CTLS_COUNT; i++)
4435                spec->cur_ctl_vals[i] = 24;
4436}
4437#endif /*ENABLE_TUNING_CONTROLS*/
4438
4439/*
4440 * Select the active output.
4441 * If autodetect is enabled, output will be selected based on jack detection.
4442 * If jack inserted, headphone will be selected, else built-in speakers
4443 * If autodetect is disabled, output will be selected based on selection.
4444 */
4445static int ca0132_select_out(struct hda_codec *codec)
4446{
4447        struct ca0132_spec *spec = codec->spec;
4448        unsigned int pin_ctl;
4449        int jack_present;
4450        int auto_jack;
4451        unsigned int tmp;
4452        int err;
4453
4454        codec_dbg(codec, "ca0132_select_out\n");
4455
4456        snd_hda_power_up_pm(codec);
4457
4458        auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4459
4460        if (auto_jack)
4461                jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4462        else
4463                jack_present =
4464                        spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4465
4466        if (jack_present)
4467                spec->cur_out_type = HEADPHONE_OUT;
4468        else
4469                spec->cur_out_type = SPEAKER_OUT;
4470
4471        if (spec->cur_out_type == SPEAKER_OUT) {
4472                codec_dbg(codec, "ca0132_select_out speaker\n");
4473                /*speaker out config*/
4474                tmp = FLOAT_ONE;
4475                err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4476                if (err < 0)
4477                        goto exit;
4478                /*enable speaker EQ*/
4479                tmp = FLOAT_ONE;
4480                err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4481                if (err < 0)
4482                        goto exit;
4483
4484                /* Setup EAPD */
4485                snd_hda_codec_write(codec, spec->out_pins[1], 0,
4486                                    VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4487                snd_hda_codec_write(codec, spec->out_pins[0], 0,
4488                                    AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4489                snd_hda_codec_write(codec, spec->out_pins[0], 0,
4490                                    VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4491                snd_hda_codec_write(codec, spec->out_pins[0], 0,
4492                                    AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4493
4494                /* disable headphone node */
4495                pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4496                                        AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4497                snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4498                                    pin_ctl & ~PIN_HP);
4499                /* enable speaker node */
4500                pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4501                                AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4502                snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4503                                    pin_ctl | PIN_OUT);
4504        } else {
4505                codec_dbg(codec, "ca0132_select_out hp\n");
4506                /*headphone out config*/
4507                tmp = FLOAT_ZERO;
4508                err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4509                if (err < 0)
4510                        goto exit;
4511                /*disable speaker EQ*/
4512                tmp = FLOAT_ZERO;
4513                err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4514                if (err < 0)
4515                        goto exit;
4516
4517                /* Setup EAPD */
4518                snd_hda_codec_write(codec, spec->out_pins[0], 0,
4519                                    VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4520                snd_hda_codec_write(codec, spec->out_pins[0], 0,
4521                                    AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4522                snd_hda_codec_write(codec, spec->out_pins[1], 0,
4523                                    VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4524                snd_hda_codec_write(codec, spec->out_pins[0], 0,
4525                                    AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4526
4527                /* disable speaker*/
4528                pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4529                                        AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4530                snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4531                                    pin_ctl & ~PIN_HP);
4532                /* enable headphone*/
4533                pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4534                                        AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4535                snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4536                                    pin_ctl | PIN_HP);
4537        }
4538
4539exit:
4540        snd_hda_power_down_pm(codec);
4541
4542        return err < 0 ? err : 0;
4543}
4544
4545static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4546static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4547static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4548
4549static void ae5_mmio_select_out(struct hda_codec *codec)
4550{
4551        struct ca0132_spec *spec = codec->spec;
4552        const struct ae_ca0113_output_set *out_cmds;
4553        unsigned int i;
4554
4555        if (ca0132_quirk(spec) == QUIRK_AE5)
4556                out_cmds = &ae5_ca0113_output_presets;
4557        else
4558                out_cmds = &ae7_ca0113_output_presets;
4559
4560        for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4561                ca0113_mmio_command_set(codec, out_cmds->group[i],
4562                                out_cmds->target[i],
4563                                out_cmds->vals[spec->cur_out_type][i]);
4564}
4565
4566static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4567{
4568        struct ca0132_spec *spec = codec->spec;
4569        int quirk = ca0132_quirk(spec);
4570        unsigned int tmp;
4571        int err;
4572
4573        /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4574        if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4575                        || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4576                return 0;
4577
4578        /* Set front L/R full range. Zero for full-range, one for redirection. */
4579        tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4580        err = dspio_set_uint_param(codec, 0x96,
4581                        SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4582        if (err < 0)
4583                return err;
4584
4585        /* When setting full-range rear, both rear and center/lfe are set. */
4586        tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4587        err = dspio_set_uint_param(codec, 0x96,
4588                        SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4589        if (err < 0)
4590                return err;
4591
4592        err = dspio_set_uint_param(codec, 0x96,
4593                        SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4594        if (err < 0)
4595                return err;
4596
4597        /*
4598         * Only the AE series cards set this value when setting full-range,
4599         * and it's always 1.0f.
4600         */
4601        if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4602                err = dspio_set_uint_param(codec, 0x96,
4603                                SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4604                if (err < 0)
4605                        return err;
4606        }
4607
4608        return 0;
4609}
4610
4611static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4612                bool val)
4613{
4614        struct ca0132_spec *spec = codec->spec;
4615        unsigned int tmp;
4616        int err;
4617
4618        if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4619                        spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4620                tmp = FLOAT_ONE;
4621        else
4622                tmp = FLOAT_ZERO;
4623
4624        err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4625        if (err < 0)
4626                return err;
4627
4628        /* If it is enabled, make sure to set the crossover frequency. */
4629        if (tmp) {
4630                tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4631                err = dspio_set_uint_param(codec, 0x96,
4632                                SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4633                if (err < 0)
4634                        return err;
4635        }
4636
4637        return 0;
4638}
4639
4640/*
4641 * These are the commands needed to setup output on each of the different card
4642 * types.
4643 */
4644static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4645                const struct ca0132_alt_out_set_quirk_data **quirk_data)
4646{
4647        struct ca0132_spec *spec = codec->spec;
4648        int quirk = ca0132_quirk(spec);
4649        unsigned int i;
4650
4651        *quirk_data = NULL;
4652        for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4653                if (quirk_out_set_data[i].quirk_id == quirk) {
4654                        *quirk_data = &quirk_out_set_data[i];
4655                        return;
4656                }
4657        }
4658}
4659
4660static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4661{
4662        const struct ca0132_alt_out_set_quirk_data *quirk_data;
4663        const struct ca0132_alt_out_set_info *out_info;
4664        struct ca0132_spec *spec = codec->spec;
4665        unsigned int i, gpio_data;
4666        int err;
4667
4668        ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4669        if (!quirk_data)
4670                return 0;
4671
4672        out_info = &quirk_data->out_set_info[spec->cur_out_type];
4673        if (quirk_data->is_ae_series)
4674                ae5_mmio_select_out(codec);
4675
4676        if (out_info->has_hda_gpio) {
4677                gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4678                                AC_VERB_GET_GPIO_DATA, 0);
4679
4680                if (out_info->hda_gpio_set)
4681                        gpio_data |= (1 << out_info->hda_gpio_pin);
4682                else
4683                        gpio_data &= ~(1 << out_info->hda_gpio_pin);
4684
4685                snd_hda_codec_write(codec, codec->core.afg, 0,
4686                                    AC_VERB_SET_GPIO_DATA, gpio_data);
4687        }
4688
4689        if (out_info->mmio_gpio_count) {
4690                for (i = 0; i < out_info->mmio_gpio_count; i++) {
4691                        ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4692                                        out_info->mmio_gpio_set[i]);
4693                }
4694        }
4695
4696        if (out_info->scp_cmds_count) {
4697                for (i = 0; i < out_info->scp_cmds_count; i++) {
4698                        err = dspio_set_uint_param(codec,
4699                                        out_info->scp_cmd_mid[i],
4700                                        out_info->scp_cmd_req[i],
4701                                        out_info->scp_cmd_val[i]);
4702                        if (err < 0)
4703                                return err;
4704                }
4705        }
4706
4707        chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4708
4709        if (out_info->has_chipio_write) {
4710                chipio_write(codec, out_info->chipio_write_addr,
4711                                out_info->chipio_write_data);
4712        }
4713
4714        if (quirk_data->has_headphone_gain) {
4715                if (spec->cur_out_type != HEADPHONE_OUT) {
4716                        if (quirk_data->is_ae_series)
4717                                ae5_headphone_gain_set(codec, 2);
4718                        else
4719                                zxr_headphone_gain_set(codec, 0);
4720                } else {
4721                        if (quirk_data->is_ae_series)
4722                                ae5_headphone_gain_set(codec,
4723                                                spec->ae5_headphone_gain_val);
4724                        else
4725                                zxr_headphone_gain_set(codec,
4726                                                spec->zxr_gain_set);
4727                }
4728        }
4729
4730        return 0;
4731}
4732
4733static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4734                bool out_enable, bool hp_enable)
4735{
4736        unsigned int pin_ctl;
4737
4738        pin_ctl = snd_hda_codec_read(codec, nid, 0,
4739                        AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4740
4741        pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~