linux/sound/pci/cs46xx/cs46xx_lib.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
   4 *                   Abramo Bagnara <abramo@alsa-project.org>
   5 *                   Cirrus Logic, Inc.
   6 *  Routines for control of Cirrus Logic CS461x chips
   7 *
   8 *  KNOWN BUGS:
   9 *    - Sometimes the SPDIF input DSP tasks get's unsynchronized
  10 *      and the SPDIF get somewhat "distorcionated", or/and left right channel
  11 *      are swapped. To get around this problem when it happens, mute and unmute 
  12 *      the SPDIF input mixer control.
  13 *    - On the Hercules Game Theater XP the amplifier are sometimes turned
  14 *      off on inadecuate moments which causes distorcions on sound.
  15 *
  16 *  TODO:
  17 *    - Secondary CODEC on some soundcards
  18 *    - SPDIF input support for other sample rates then 48khz
  19 *    - Posibility to mix the SPDIF output with analog sources.
  20 *    - PCM channels for Center and LFE on secondary codec
  21 *
  22 *  NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
  23 *        is default configuration), no SPDIF, no secondary codec, no
  24 *        multi channel PCM.  But known to work.
  25 *
  26 *  FINALLY: A credit to the developers Tom and Jordan 
  27 *           at Cirrus for have helping me out with the DSP, however we
  28 *           still don't have sufficient documentation and technical
  29 *           references to be able to implement all fancy feutures
  30 *           supported by the cs46xx DSP's. 
  31 *           Benny <benny@hostmobility.com>
  32 */
  33
  34#include <linux/delay.h>
  35#include <linux/pci.h>
  36#include <linux/pm.h>
  37#include <linux/init.h>
  38#include <linux/interrupt.h>
  39#include <linux/slab.h>
  40#include <linux/gameport.h>
  41#include <linux/mutex.h>
  42#include <linux/export.h>
  43#include <linux/module.h>
  44#include <linux/firmware.h>
  45#include <linux/vmalloc.h>
  46#include <linux/io.h>
  47
  48#include <sound/core.h>
  49#include <sound/control.h>
  50#include <sound/info.h>
  51#include <sound/pcm.h>
  52#include <sound/pcm_params.h>
  53#include "cs46xx.h"
  54
  55#include "cs46xx_lib.h"
  56#include "dsp_spos.h"
  57
  58static void amp_voyetra(struct snd_cs46xx *chip, int change);
  59
  60#ifdef CONFIG_SND_CS46XX_NEW_DSP
  61static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
  62static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
  63static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
  64static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
  65static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
  66static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
  67#endif
  68
  69static const struct snd_pcm_ops snd_cs46xx_playback_ops;
  70static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
  71static const struct snd_pcm_ops snd_cs46xx_capture_ops;
  72static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
  73
  74static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
  75                                            unsigned short reg,
  76                                            int codec_index)
  77{
  78        int count;
  79        unsigned short result,tmp;
  80        u32 offset = 0;
  81
  82        if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
  83                       codec_index != CS46XX_SECONDARY_CODEC_INDEX))
  84                return 0xffff;
  85
  86        chip->active_ctrl(chip, 1);
  87
  88        if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
  89                offset = CS46XX_SECONDARY_CODEC_OFFSET;
  90
  91        /*
  92         *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  93         *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97 
  94         *  3. Write ACCTL = Control Register = 460h for initiating the write7---55
  95         *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
  96         *  5. if DCV not cleared, break and return error
  97         *  6. Read ACSTS = Status Register = 464h, check VSTS bit
  98         */
  99
 100        snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 101
 102        tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 103        if ((tmp & ACCTL_VFRM) == 0) {
 104                dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
 105                snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
 106                msleep(50);
 107                tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
 108                snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
 109
 110        }
 111
 112        /*
 113         *  Setup the AC97 control registers on the CS461x to send the
 114         *  appropriate command to the AC97 to perform the read.
 115         *  ACCAD = Command Address Register = 46Ch
 116         *  ACCDA = Command Data Register = 470h
 117         *  ACCTL = Control Register = 460h
 118         *  set DCV - will clear when process completed
 119         *  set CRW - Read command
 120         *  set VFRM - valid frame enabled
 121         *  set ESYN - ASYNC generation enabled
 122         *  set RSTN - ARST# inactive, AC97 codec not reset
 123         */
 124
 125        snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
 126        snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
 127        if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 128                snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW | 
 129                                   ACCTL_VFRM | ACCTL_ESYN |
 130                                   ACCTL_RSTN);
 131                snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
 132                                   ACCTL_VFRM | ACCTL_ESYN |
 133                                   ACCTL_RSTN);
 134        } else {
 135                snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 136                                   ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
 137                                   ACCTL_RSTN);
 138        }
 139
 140        /*
 141         *  Wait for the read to occur.
 142         */
 143        for (count = 0; count < 1000; count++) {
 144                /*
 145                 *  First, we want to wait for a short time.
 146                 */
 147                udelay(10);
 148                /*
 149                 *  Now, check to see if the read has completed.
 150                 *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 151                 */
 152                if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
 153                        goto ok1;
 154        }
 155
 156        dev_err(chip->card->dev,
 157                "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 158        result = 0xffff;
 159        goto end;
 160        
 161 ok1:
 162        /*
 163         *  Wait for the valid status bit to go active.
 164         */
 165        for (count = 0; count < 100; count++) {
 166                /*
 167                 *  Read the AC97 status register.
 168                 *  ACSTS = Status Register = 464h
 169                 *  VSTS - Valid Status
 170                 */
 171                if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
 172                        goto ok2;
 173                udelay(10);
 174        }
 175        
 176        dev_err(chip->card->dev,
 177                "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
 178                codec_index, reg);
 179        result = 0xffff;
 180        goto end;
 181
 182 ok2:
 183        /*
 184         *  Read the data returned from the AC97 register.
 185         *  ACSDA = Status Data Register = 474h
 186         */
 187#if 0
 188        dev_dbg(chip->card->dev,
 189                "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
 190                        snd_cs46xx_peekBA0(chip, BA0_ACSDA),
 191                        snd_cs46xx_peekBA0(chip, BA0_ACCAD));
 192#endif
 193
 194        //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
 195        result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 196 end:
 197        chip->active_ctrl(chip, -1);
 198        return result;
 199}
 200
 201static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
 202                                            unsigned short reg)
 203{
 204        struct snd_cs46xx *chip = ac97->private_data;
 205        unsigned short val;
 206        int codec_index = ac97->num;
 207
 208        if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 209                       codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 210                return 0xffff;
 211
 212        val = snd_cs46xx_codec_read(chip, reg, codec_index);
 213
 214        return val;
 215}
 216
 217
 218static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
 219                                   unsigned short reg,
 220                                   unsigned short val,
 221                                   int codec_index)
 222{
 223        int count;
 224
 225        if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 226                       codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 227                return;
 228
 229        chip->active_ctrl(chip, 1);
 230
 231        /*
 232         *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 233         *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 234         *  3. Write ACCTL = Control Register = 460h for initiating the write
 235         *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 236         *  5. if DCV not cleared, break and return error
 237         */
 238
 239        /*
 240         *  Setup the AC97 control registers on the CS461x to send the
 241         *  appropriate command to the AC97 to perform the read.
 242         *  ACCAD = Command Address Register = 46Ch
 243         *  ACCDA = Command Data Register = 470h
 244         *  ACCTL = Control Register = 460h
 245         *  set DCV - will clear when process completed
 246         *  reset CRW - Write command
 247         *  set VFRM - valid frame enabled
 248         *  set ESYN - ASYNC generation enabled
 249         *  set RSTN - ARST# inactive, AC97 codec not reset
 250         */
 251        snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
 252        snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
 253        snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 254
 255        if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 256                snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
 257                                   ACCTL_ESYN | ACCTL_RSTN);
 258                snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
 259                                   ACCTL_ESYN | ACCTL_RSTN);
 260        } else {
 261                snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 262                                   ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 263        }
 264
 265        for (count = 0; count < 4000; count++) {
 266                /*
 267                 *  First, we want to wait for a short time.
 268                 */
 269                udelay(10);
 270                /*
 271                 *  Now, check to see if the write has completed.
 272                 *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 273                 */
 274                if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
 275                        goto end;
 276                }
 277        }
 278        dev_err(chip->card->dev,
 279                "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
 280                codec_index, reg, val);
 281 end:
 282        chip->active_ctrl(chip, -1);
 283}
 284
 285static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
 286                                   unsigned short reg,
 287                                   unsigned short val)
 288{
 289        struct snd_cs46xx *chip = ac97->private_data;
 290        int codec_index = ac97->num;
 291
 292        if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 293                       codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 294                return;
 295
 296        snd_cs46xx_codec_write(chip, reg, val, codec_index);
 297}
 298
 299
 300/*
 301 *  Chip initialization
 302 */
 303
 304int snd_cs46xx_download(struct snd_cs46xx *chip,
 305                        u32 *src,
 306                        unsigned long offset,
 307                        unsigned long len)
 308{
 309        void __iomem *dst;
 310        unsigned int bank = offset >> 16;
 311        offset = offset & 0xffff;
 312
 313        if (snd_BUG_ON((offset & 3) || (len & 3)))
 314                return -EINVAL;
 315        dst = chip->region.idx[bank+1].remap_addr + offset;
 316        len /= sizeof(u32);
 317
 318        /* writel already converts 32-bit value to right endianess */
 319        while (len-- > 0) {
 320                writel(*src++, dst);
 321                dst += sizeof(u32);
 322        }
 323        return 0;
 324}
 325
 326static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
 327{
 328#ifdef __LITTLE_ENDIAN
 329        memcpy(dst, src, len);
 330#else
 331        u32 *_dst = dst;
 332        const __le32 *_src = src;
 333        len /= 4;
 334        while (len-- > 0)
 335                *_dst++ = le32_to_cpu(*_src++);
 336#endif
 337}
 338
 339#ifdef CONFIG_SND_CS46XX_NEW_DSP
 340
 341static const char *module_names[CS46XX_DSP_MODULES] = {
 342        "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
 343};
 344
 345MODULE_FIRMWARE("cs46xx/cwc4630");
 346MODULE_FIRMWARE("cs46xx/cwcasync");
 347MODULE_FIRMWARE("cs46xx/cwcsnoop");
 348MODULE_FIRMWARE("cs46xx/cwcbinhack");
 349MODULE_FIRMWARE("cs46xx/cwcdma");
 350
 351static void free_module_desc(struct dsp_module_desc *module)
 352{
 353        if (!module)
 354                return;
 355        kfree(module->module_name);
 356        kfree(module->symbol_table.symbols);
 357        if (module->segments) {
 358                int i;
 359                for (i = 0; i < module->nsegments; i++)
 360                        kfree(module->segments[i].data);
 361                kfree(module->segments);
 362        }
 363        kfree(module);
 364}
 365
 366/* firmware binary format:
 367 * le32 nsymbols;
 368 * struct {
 369 *      le32 address;
 370 *      char symbol_name[DSP_MAX_SYMBOL_NAME];
 371 *      le32 symbol_type;
 372 * } symbols[nsymbols];
 373 * le32 nsegments;
 374 * struct {
 375 *      le32 segment_type;
 376 *      le32 offset;
 377 *      le32 size;
 378 *      le32 data[size];
 379 * } segments[nsegments];
 380 */
 381
 382static int load_firmware(struct snd_cs46xx *chip,
 383                         struct dsp_module_desc **module_ret,
 384                         const char *fw_name)
 385{
 386        int i, err;
 387        unsigned int nums, fwlen, fwsize;
 388        const __le32 *fwdat;
 389        struct dsp_module_desc *module = NULL;
 390        const struct firmware *fw;
 391        char fw_path[32];
 392
 393        sprintf(fw_path, "cs46xx/%s", fw_name);
 394        err = request_firmware(&fw, fw_path, &chip->pci->dev);
 395        if (err < 0)
 396                return err;
 397        fwsize = fw->size / 4;
 398        if (fwsize < 2) {
 399                err = -EINVAL;
 400                goto error;
 401        }
 402
 403        err = -ENOMEM;
 404        module = kzalloc(sizeof(*module), GFP_KERNEL);
 405        if (!module)
 406                goto error;
 407        module->module_name = kstrdup(fw_name, GFP_KERNEL);
 408        if (!module->module_name)
 409                goto error;
 410
 411        fwlen = 0;
 412        fwdat = (const __le32 *)fw->data;
 413        nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
 414        if (nums >= 40)
 415                goto error_inval;
 416        module->symbol_table.symbols =
 417                kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
 418        if (!module->symbol_table.symbols)
 419                goto error;
 420        for (i = 0; i < nums; i++) {
 421                struct dsp_symbol_entry *entry =
 422                        &module->symbol_table.symbols[i];
 423                if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
 424                        goto error_inval;
 425                entry->address = le32_to_cpu(fwdat[fwlen++]);
 426                memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
 427                fwlen += DSP_MAX_SYMBOL_NAME / 4;
 428                entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
 429        }
 430
 431        if (fwlen >= fwsize)
 432                goto error_inval;
 433        nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
 434        if (nums > 10)
 435                goto error_inval;
 436        module->segments =
 437                kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
 438        if (!module->segments)
 439                goto error;
 440        for (i = 0; i < nums; i++) {
 441                struct dsp_segment_desc *entry = &module->segments[i];
 442                if (fwlen + 3 > fwsize)
 443                        goto error_inval;
 444                entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
 445                entry->offset = le32_to_cpu(fwdat[fwlen++]);
 446                entry->size = le32_to_cpu(fwdat[fwlen++]);
 447                if (fwlen + entry->size > fwsize)
 448                        goto error_inval;
 449                entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
 450                if (!entry->data)
 451                        goto error;
 452                memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
 453                fwlen += entry->size;
 454        }
 455
 456        *module_ret = module;
 457        release_firmware(fw);
 458        return 0;
 459
 460 error_inval:
 461        err = -EINVAL;
 462 error:
 463        free_module_desc(module);
 464        release_firmware(fw);
 465        return err;
 466}
 467
 468int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
 469                         unsigned long offset,
 470                         unsigned long len) 
 471{
 472        void __iomem *dst;
 473        unsigned int bank = offset >> 16;
 474        offset = offset & 0xffff;
 475
 476        if (snd_BUG_ON((offset & 3) || (len & 3)))
 477                return -EINVAL;
 478        dst = chip->region.idx[bank+1].remap_addr + offset;
 479        len /= sizeof(u32);
 480
 481        /* writel already converts 32-bit value to right endianess */
 482        while (len-- > 0) {
 483                writel(0, dst);
 484                dst += sizeof(u32);
 485        }
 486        return 0;
 487}
 488
 489#else /* old DSP image */
 490
 491struct ba1_struct {
 492        struct {
 493                u32 offset;
 494                u32 size;
 495        } memory[BA1_MEMORY_COUNT];
 496        u32 map[BA1_DWORD_SIZE];
 497};
 498
 499MODULE_FIRMWARE("cs46xx/ba1");
 500
 501static int load_firmware(struct snd_cs46xx *chip)
 502{
 503        const struct firmware *fw;
 504        int i, size, err;
 505
 506        err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
 507        if (err < 0)
 508                return err;
 509        if (fw->size != sizeof(*chip->ba1)) {
 510                err = -EINVAL;
 511                goto error;
 512        }
 513
 514        chip->ba1 = vmalloc(sizeof(*chip->ba1));
 515        if (!chip->ba1) {
 516                err = -ENOMEM;
 517                goto error;
 518        }
 519
 520        memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
 521
 522        /* sanity check */
 523        size = 0;
 524        for (i = 0; i < BA1_MEMORY_COUNT; i++)
 525                size += chip->ba1->memory[i].size;
 526        if (size > BA1_DWORD_SIZE * 4)
 527                err = -EINVAL;
 528
 529 error:
 530        release_firmware(fw);
 531        return err;
 532}
 533
 534int snd_cs46xx_download_image(struct snd_cs46xx *chip)
 535{
 536        int idx, err;
 537        unsigned int offset = 0;
 538        struct ba1_struct *ba1 = chip->ba1;
 539
 540        for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
 541                err = snd_cs46xx_download(chip,
 542                                          &ba1->map[offset],
 543                                          ba1->memory[idx].offset,
 544                                          ba1->memory[idx].size);
 545                if (err < 0)
 546                        return err;
 547                offset += ba1->memory[idx].size >> 2;
 548        }       
 549        return 0;
 550}
 551#endif /* CONFIG_SND_CS46XX_NEW_DSP */
 552
 553/*
 554 *  Chip reset
 555 */
 556
 557static void snd_cs46xx_reset(struct snd_cs46xx *chip)
 558{
 559        int idx;
 560
 561        /*
 562         *  Write the reset bit of the SP control register.
 563         */
 564        snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
 565
 566        /*
 567         *  Write the control register.
 568         */
 569        snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
 570
 571        /*
 572         *  Clear the trap registers.
 573         */
 574        for (idx = 0; idx < 8; idx++) {
 575                snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
 576                snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
 577        }
 578        snd_cs46xx_poke(chip, BA1_DREG, 0);
 579
 580        /*
 581         *  Set the frame timer to reflect the number of cycles per frame.
 582         */
 583        snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 584}
 585
 586static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout) 
 587{
 588        u32 i, status = 0;
 589        /*
 590         * Make sure the previous FIFO write operation has completed.
 591         */
 592        for(i = 0; i < 50; i++){
 593                status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
 594    
 595                if( !(status & SERBST_WBSY) )
 596                        break;
 597
 598                mdelay(retry_timeout);
 599        }
 600  
 601        if(status & SERBST_WBSY) {
 602                dev_err(chip->card->dev,
 603                        "failure waiting for FIFO command to complete\n");
 604                return -EINVAL;
 605        }
 606
 607        return 0;
 608}
 609
 610static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
 611{
 612        int idx, powerdown = 0;
 613        unsigned int tmp;
 614
 615        /*
 616         *  See if the devices are powered down.  If so, we must power them up first
 617         *  or they will not respond.
 618         */
 619        tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
 620        if (!(tmp & CLKCR1_SWCE)) {
 621                snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
 622                powerdown = 1;
 623        }
 624
 625        /*
 626         *  We want to clear out the serial port FIFOs so we don't end up playing
 627         *  whatever random garbage happens to be in them.  We fill the sample FIFOS
 628         *  with zero (silence).
 629         */
 630        snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
 631
 632        /*
 633         *  Fill all 256 sample FIFO locations.
 634         */
 635        for (idx = 0; idx < 0xFF; idx++) {
 636                /*
 637                 *  Make sure the previous FIFO write operation has completed.
 638                 */
 639                if (cs46xx_wait_for_fifo(chip,1)) {
 640                        dev_dbg(chip->card->dev,
 641                                "failed waiting for FIFO at addr (%02X)\n",
 642                                idx);
 643
 644                        if (powerdown)
 645                                snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 646          
 647                        break;
 648                }
 649                /*
 650                 *  Write the serial port FIFO index.
 651                 */
 652                snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
 653                /*
 654                 *  Tell the serial port to load the new value into the FIFO location.
 655                 */
 656                snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
 657        }
 658        /*
 659         *  Now, if we powered up the devices, then power them back down again.
 660         *  This is kinda ugly, but should never happen.
 661         */
 662        if (powerdown)
 663                snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 664}
 665
 666static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
 667{
 668        int cnt;
 669
 670        /*
 671         *  Set the frame timer to reflect the number of cycles per frame.
 672         */
 673        snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 674        /*
 675         *  Turn on the run, run at frame, and DMA enable bits in the local copy of
 676         *  the SP control register.
 677         */
 678        snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
 679        /*
 680         *  Wait until the run at frame bit resets itself in the SP control
 681         *  register.
 682         */
 683        for (cnt = 0; cnt < 25; cnt++) {
 684                udelay(50);
 685                if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
 686                        break;
 687        }
 688
 689        if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
 690                dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
 691}
 692
 693static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
 694{
 695        /*
 696         *  Turn off the run, run at frame, and DMA enable bits in the local copy of
 697         *  the SP control register.
 698         */
 699        snd_cs46xx_poke(chip, BA1_SPCR, 0);
 700}
 701
 702/*
 703 *  Sample rate routines
 704 */
 705
 706#define GOF_PER_SEC 200
 707
 708static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
 709{
 710        unsigned long flags;
 711        unsigned int tmp1, tmp2;
 712        unsigned int phiIncr;
 713        unsigned int correctionPerGOF, correctionPerSec;
 714
 715        /*
 716         *  Compute the values used to drive the actual sample rate conversion.
 717         *  The following formulas are being computed, using inline assembly
 718         *  since we need to use 64 bit arithmetic to compute the values:
 719         *
 720         *  phiIncr = floor((Fs,in * 2^26) / Fs,out)
 721         *  correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 722         *                                   GOF_PER_SEC)
 723         *  ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
 724         *                       GOF_PER_SEC * correctionPerGOF
 725         *
 726         *  i.e.
 727         *
 728         *  phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
 729         *  correctionPerGOF:correctionPerSec =
 730         *      dividend:remainder(ulOther / GOF_PER_SEC)
 731         */
 732        tmp1 = rate << 16;
 733        phiIncr = tmp1 / 48000;
 734        tmp1 -= phiIncr * 48000;
 735        tmp1 <<= 10;
 736        phiIncr <<= 10;
 737        tmp2 = tmp1 / 48000;
 738        phiIncr += tmp2;
 739        tmp1 -= tmp2 * 48000;
 740        correctionPerGOF = tmp1 / GOF_PER_SEC;
 741        tmp1 -= correctionPerGOF * GOF_PER_SEC;
 742        correctionPerSec = tmp1;
 743
 744        /*
 745         *  Fill in the SampleRateConverter control block.
 746         */
 747        spin_lock_irqsave(&chip->reg_lock, flags);
 748        snd_cs46xx_poke(chip, BA1_PSRC,
 749          ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 750        snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
 751        spin_unlock_irqrestore(&chip->reg_lock, flags);
 752}
 753
 754static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
 755{
 756        unsigned long flags;
 757        unsigned int phiIncr, coeffIncr, tmp1, tmp2;
 758        unsigned int correctionPerGOF, correctionPerSec, initialDelay;
 759        unsigned int frameGroupLength, cnt;
 760
 761        /*
 762         *  We can only decimate by up to a factor of 1/9th the hardware rate.
 763         *  Correct the value if an attempt is made to stray outside that limit.
 764         */
 765        if ((rate * 9) < 48000)
 766                rate = 48000 / 9;
 767
 768        /*
 769         *  We can not capture at a rate greater than the Input Rate (48000).
 770         *  Return an error if an attempt is made to stray outside that limit.
 771         */
 772        if (rate > 48000)
 773                rate = 48000;
 774
 775        /*
 776         *  Compute the values used to drive the actual sample rate conversion.
 777         *  The following formulas are being computed, using inline assembly
 778         *  since we need to use 64 bit arithmetic to compute the values:
 779         *
 780         *     coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
 781         *     phiIncr = floor((Fs,in * 2^26) / Fs,out)
 782         *     correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 783         *                                GOF_PER_SEC)
 784         *     correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
 785         *                          GOF_PER_SEC * correctionPerGOF
 786         *     initialDelay = ceil((24 * Fs,in) / Fs,out)
 787         *
 788         * i.e.
 789         *
 790         *     coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
 791         *     phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
 792         *     correctionPerGOF:correctionPerSec =
 793         *          dividend:remainder(ulOther / GOF_PER_SEC)
 794         *     initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
 795         */
 796
 797        tmp1 = rate << 16;
 798        coeffIncr = tmp1 / 48000;
 799        tmp1 -= coeffIncr * 48000;
 800        tmp1 <<= 7;
 801        coeffIncr <<= 7;
 802        coeffIncr += tmp1 / 48000;
 803        coeffIncr ^= 0xFFFFFFFF;
 804        coeffIncr++;
 805        tmp1 = 48000 << 16;
 806        phiIncr = tmp1 / rate;
 807        tmp1 -= phiIncr * rate;
 808        tmp1 <<= 10;
 809        phiIncr <<= 10;
 810        tmp2 = tmp1 / rate;
 811        phiIncr += tmp2;
 812        tmp1 -= tmp2 * rate;
 813        correctionPerGOF = tmp1 / GOF_PER_SEC;
 814        tmp1 -= correctionPerGOF * GOF_PER_SEC;
 815        correctionPerSec = tmp1;
 816        initialDelay = DIV_ROUND_UP(48000 * 24, rate);
 817
 818        /*
 819         *  Fill in the VariDecimate control block.
 820         */
 821        spin_lock_irqsave(&chip->reg_lock, flags);
 822        snd_cs46xx_poke(chip, BA1_CSRC,
 823                ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 824        snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
 825        snd_cs46xx_poke(chip, BA1_CD,
 826                (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
 827        snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
 828        spin_unlock_irqrestore(&chip->reg_lock, flags);
 829
 830        /*
 831         *  Figure out the frame group length for the write back task.  Basically,
 832         *  this is just the factors of 24000 (2^6*3*5^3) that are not present in
 833         *  the output sample rate.
 834         */
 835        frameGroupLength = 1;
 836        for (cnt = 2; cnt <= 64; cnt *= 2) {
 837                if (((rate / cnt) * cnt) != rate)
 838                        frameGroupLength *= 2;
 839        }
 840        if (((rate / 3) * 3) != rate) {
 841                frameGroupLength *= 3;
 842        }
 843        for (cnt = 5; cnt <= 125; cnt *= 5) {
 844                if (((rate / cnt) * cnt) != rate) 
 845                        frameGroupLength *= 5;
 846        }
 847
 848        /*
 849         * Fill in the WriteBack control block.
 850         */
 851        spin_lock_irqsave(&chip->reg_lock, flags);
 852        snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
 853        snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
 854        snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
 855        snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
 856        snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
 857        spin_unlock_irqrestore(&chip->reg_lock, flags);
 858}
 859
 860/*
 861 *  PCM part
 862 */
 863
 864static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
 865                                     struct snd_pcm_indirect *rec, size_t bytes)
 866{
 867        struct snd_pcm_runtime *runtime = substream->runtime;
 868        struct snd_cs46xx_pcm * cpcm = runtime->private_data;
 869        memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
 870}
 871
 872static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
 873{
 874        struct snd_pcm_runtime *runtime = substream->runtime;
 875        struct snd_cs46xx_pcm * cpcm = runtime->private_data;
 876        return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
 877                                                  snd_cs46xx_pb_trans_copy);
 878}
 879
 880static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
 881                                     struct snd_pcm_indirect *rec, size_t bytes)
 882{
 883        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 884        struct snd_pcm_runtime *runtime = substream->runtime;
 885        memcpy(runtime->dma_area + rec->sw_data,
 886               chip->capt.hw_buf.area + rec->hw_data, bytes);
 887}
 888
 889static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
 890{
 891        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 892        return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
 893                                                 snd_cs46xx_cp_trans_copy);
 894}
 895
 896static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
 897{
 898        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 899        size_t ptr;
 900        struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 901
 902        if (snd_BUG_ON(!cpcm->pcm_channel))
 903                return -ENXIO;
 904
 905#ifdef CONFIG_SND_CS46XX_NEW_DSP
 906        ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 907#else
 908        ptr = snd_cs46xx_peek(chip, BA1_PBA);
 909#endif
 910        ptr -= cpcm->hw_buf.addr;
 911        return ptr >> cpcm->shift;
 912}
 913
 914static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
 915{
 916        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 917        size_t ptr;
 918        struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 919
 920#ifdef CONFIG_SND_CS46XX_NEW_DSP
 921        if (snd_BUG_ON(!cpcm->pcm_channel))
 922                return -ENXIO;
 923        ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 924#else
 925        ptr = snd_cs46xx_peek(chip, BA1_PBA);
 926#endif
 927        ptr -= cpcm->hw_buf.addr;
 928        return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
 929}
 930
 931static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
 932{
 933        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 934        size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 935        return ptr >> chip->capt.shift;
 936}
 937
 938static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
 939{
 940        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 941        size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 942        return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
 943}
 944
 945static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
 946                                       int cmd)
 947{
 948        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 949        /*struct snd_pcm_runtime *runtime = substream->runtime;*/
 950        int result = 0;
 951
 952#ifdef CONFIG_SND_CS46XX_NEW_DSP
 953        struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 954        if (! cpcm->pcm_channel) {
 955                return -ENXIO;
 956        }
 957#endif
 958        switch (cmd) {
 959        case SNDRV_PCM_TRIGGER_START:
 960        case SNDRV_PCM_TRIGGER_RESUME:
 961#ifdef CONFIG_SND_CS46XX_NEW_DSP
 962                /* magic value to unmute PCM stream  playback volume */
 963                snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 
 964                                       SCBVolumeCtrl) << 2, 0x80008000);
 965
 966                if (cpcm->pcm_channel->unlinked)
 967                        cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
 968
 969                if (substream->runtime->periods != CS46XX_FRAGS)
 970                        snd_cs46xx_playback_transfer(substream);
 971#else
 972                spin_lock(&chip->reg_lock);
 973                if (substream->runtime->periods != CS46XX_FRAGS)
 974                        snd_cs46xx_playback_transfer(substream);
 975                { unsigned int tmp;
 976                tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 977                tmp &= 0x0000ffff;
 978                snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
 979                }
 980                spin_unlock(&chip->reg_lock);
 981#endif
 982                break;
 983        case SNDRV_PCM_TRIGGER_STOP:
 984        case SNDRV_PCM_TRIGGER_SUSPEND:
 985#ifdef CONFIG_SND_CS46XX_NEW_DSP
 986                /* magic mute channel */
 987                snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 
 988                                       SCBVolumeCtrl) << 2, 0xffffffff);
 989
 990                if (!cpcm->pcm_channel->unlinked)
 991                        cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
 992#else
 993                spin_lock(&chip->reg_lock);
 994                { unsigned int tmp;
 995                tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 996                tmp &= 0x0000ffff;
 997                snd_cs46xx_poke(chip, BA1_PCTL, tmp);
 998                }
 999                spin_unlock(&chip->reg_lock);
1000#endif
1001                break;
1002        default:
1003                result = -EINVAL;
1004                break;
1005        }
1006
1007        return result;
1008}
1009
1010static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1011                                      int cmd)
1012{
1013        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1014        unsigned int tmp;
1015        int result = 0;
1016
1017        spin_lock(&chip->reg_lock);
1018        switch (cmd) {
1019        case SNDRV_PCM_TRIGGER_START:
1020        case SNDRV_PCM_TRIGGER_RESUME:
1021                tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1022                tmp &= 0xffff0000;
1023                snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1024                break;
1025        case SNDRV_PCM_TRIGGER_STOP:
1026        case SNDRV_PCM_TRIGGER_SUSPEND:
1027                tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1028                tmp &= 0xffff0000;
1029                snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1030                break;
1031        default:
1032                result = -EINVAL;
1033                break;
1034        }
1035        spin_unlock(&chip->reg_lock);
1036
1037        return result;
1038}
1039
1040#ifdef CONFIG_SND_CS46XX_NEW_DSP
1041static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1042                                       int sample_rate) 
1043{
1044
1045        /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1046        if ( cpcm->pcm_channel == NULL) {
1047                cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, 
1048                                                                   cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1049                if (cpcm->pcm_channel == NULL) {
1050                        dev_err(chip->card->dev,
1051                                "failed to create virtual PCM channel\n");
1052                        return -ENOMEM;
1053                }
1054                cpcm->pcm_channel->sample_rate = sample_rate;
1055        } else
1056        /* if sample rate is changed */
1057        if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1058                int unlinked = cpcm->pcm_channel->unlinked;
1059                cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1060
1061                cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel(chip, sample_rate, cpcm,
1062                                                                  cpcm->hw_buf.addr,
1063                                                                  cpcm->pcm_channel_id);
1064                if (!cpcm->pcm_channel) {
1065                        dev_err(chip->card->dev,
1066                                "failed to re-create virtual PCM channel\n");
1067                        return -ENOMEM;
1068                }
1069
1070                if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1071                cpcm->pcm_channel->sample_rate = sample_rate;
1072        }
1073
1074        return 0;
1075}
1076#endif
1077
1078
1079static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1080                                         struct snd_pcm_hw_params *hw_params)
1081{
1082        struct snd_pcm_runtime *runtime = substream->runtime;
1083        struct snd_cs46xx_pcm *cpcm;
1084        int err;
1085#ifdef CONFIG_SND_CS46XX_NEW_DSP
1086        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1087        int sample_rate = params_rate(hw_params);
1088        int period_size = params_period_bytes(hw_params);
1089#endif
1090        cpcm = runtime->private_data;
1091
1092#ifdef CONFIG_SND_CS46XX_NEW_DSP
1093        if (snd_BUG_ON(!sample_rate))
1094                return -ENXIO;
1095
1096        mutex_lock(&chip->spos_mutex);
1097
1098        if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1099                mutex_unlock(&chip->spos_mutex);
1100                return -ENXIO;
1101        }
1102
1103        snd_BUG_ON(!cpcm->pcm_channel);
1104        if (!cpcm->pcm_channel) {
1105                mutex_unlock(&chip->spos_mutex);
1106                return -ENXIO;
1107        }
1108
1109
1110        if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1111                 mutex_unlock(&chip->spos_mutex);
1112                 return -EINVAL;
1113         }
1114
1115        dev_dbg(chip->card->dev,
1116                "period_size (%d), periods (%d) buffer_size(%d)\n",
1117                     period_size, params_periods(hw_params),
1118                     params_buffer_bytes(hw_params));
1119#endif
1120
1121        if (params_periods(hw_params) == CS46XX_FRAGS) {
1122                if (runtime->dma_area != cpcm->hw_buf.area)
1123                        snd_pcm_lib_free_pages(substream);
1124                runtime->dma_area = cpcm->hw_buf.area;
1125                runtime->dma_addr = cpcm->hw_buf.addr;
1126                runtime->dma_bytes = cpcm->hw_buf.bytes;
1127
1128
1129#ifdef CONFIG_SND_CS46XX_NEW_DSP
1130                if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1131                        substream->ops = &snd_cs46xx_playback_ops;
1132                } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1133                        substream->ops = &snd_cs46xx_playback_rear_ops;
1134                } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1135                        substream->ops = &snd_cs46xx_playback_clfe_ops;
1136                } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1137                        substream->ops = &snd_cs46xx_playback_iec958_ops;
1138                } else {
1139                        snd_BUG();
1140                }
1141#else
1142                substream->ops = &snd_cs46xx_playback_ops;
1143#endif
1144
1145        } else {
1146                if (runtime->dma_area == cpcm->hw_buf.area) {
1147                        runtime->dma_area = NULL;
1148                        runtime->dma_addr = 0;
1149                        runtime->dma_bytes = 0;
1150                }
1151                err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1152                if (err < 0) {
1153#ifdef CONFIG_SND_CS46XX_NEW_DSP
1154                        mutex_unlock(&chip->spos_mutex);
1155#endif
1156                        return err;
1157                }
1158
1159#ifdef CONFIG_SND_CS46XX_NEW_DSP
1160                if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1161                        substream->ops = &snd_cs46xx_playback_indirect_ops;
1162                } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1163                        substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1164                } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1165                        substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1166                } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1167                        substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1168                } else {
1169                        snd_BUG();
1170                }
1171#else
1172                substream->ops = &snd_cs46xx_playback_indirect_ops;
1173#endif
1174
1175        }
1176
1177#ifdef CONFIG_SND_CS46XX_NEW_DSP
1178        mutex_unlock(&chip->spos_mutex);
1179#endif
1180
1181        return 0;
1182}
1183
1184static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1185{
1186        /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1187        struct snd_pcm_runtime *runtime = substream->runtime;
1188        struct snd_cs46xx_pcm *cpcm;
1189
1190        cpcm = runtime->private_data;
1191
1192        /* if play_back open fails, then this function
1193           is called and cpcm can actually be NULL here */
1194        if (!cpcm) return -ENXIO;
1195
1196        if (runtime->dma_area != cpcm->hw_buf.area)
1197                snd_pcm_lib_free_pages(substream);
1198    
1199        runtime->dma_area = NULL;
1200        runtime->dma_addr = 0;
1201        runtime->dma_bytes = 0;
1202
1203        return 0;
1204}
1205
1206static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1207{
1208        unsigned int tmp;
1209        unsigned int pfie;
1210        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1211        struct snd_pcm_runtime *runtime = substream->runtime;
1212        struct snd_cs46xx_pcm *cpcm;
1213
1214        cpcm = runtime->private_data;
1215
1216#ifdef CONFIG_SND_CS46XX_NEW_DSP
1217        if (snd_BUG_ON(!cpcm->pcm_channel))
1218                return -ENXIO;
1219
1220        pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1221        pfie &= ~0x0000f03f;
1222#else
1223        /* old dsp */
1224        pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1225        pfie &= ~0x0000f03f;
1226#endif
1227
1228        cpcm->shift = 2;
1229        /* if to convert from stereo to mono */
1230        if (runtime->channels == 1) {
1231                cpcm->shift--;
1232                pfie |= 0x00002000;
1233        }
1234        /* if to convert from 8 bit to 16 bit */
1235        if (snd_pcm_format_width(runtime->format) == 8) {
1236                cpcm->shift--;
1237                pfie |= 0x00001000;
1238        }
1239        /* if to convert to unsigned */
1240        if (snd_pcm_format_unsigned(runtime->format))
1241                pfie |= 0x00008000;
1242
1243        /* Never convert byte order when sample stream is 8 bit */
1244        if (snd_pcm_format_width(runtime->format) != 8) {
1245                /* convert from big endian to little endian */
1246                if (snd_pcm_format_big_endian(runtime->format))
1247                        pfie |= 0x00004000;
1248        }
1249        
1250        memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1251        cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1252        cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1253
1254#ifdef CONFIG_SND_CS46XX_NEW_DSP
1255
1256        tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1257        tmp &= ~0x000003ff;
1258        tmp |= (4 << cpcm->shift) - 1;
1259        /* playback transaction count register */
1260        snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1261
1262        /* playback format && interrupt enable */
1263        snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1264#else
1265        snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1266        tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1267        tmp &= ~0x000003ff;
1268        tmp |= (4 << cpcm->shift) - 1;
1269        snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1270        snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1271        snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1272#endif
1273
1274        return 0;
1275}
1276
1277static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1278                                        struct snd_pcm_hw_params *hw_params)
1279{
1280        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1281        struct snd_pcm_runtime *runtime = substream->runtime;
1282        int err;
1283
1284#ifdef CONFIG_SND_CS46XX_NEW_DSP
1285        cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1286#endif
1287        if (runtime->periods == CS46XX_FRAGS) {
1288                if (runtime->dma_area != chip->capt.hw_buf.area)
1289                        snd_pcm_lib_free_pages(substream);
1290                runtime->dma_area = chip->capt.hw_buf.area;
1291                runtime->dma_addr = chip->capt.hw_buf.addr;
1292                runtime->dma_bytes = chip->capt.hw_buf.bytes;
1293                substream->ops = &snd_cs46xx_capture_ops;
1294        } else {
1295                if (runtime->dma_area == chip->capt.hw_buf.area) {
1296                        runtime->dma_area = NULL;
1297                        runtime->dma_addr = 0;
1298                        runtime->dma_bytes = 0;
1299                }
1300                err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1301                if (err < 0)
1302                        return err;
1303                substream->ops = &snd_cs46xx_capture_indirect_ops;
1304        }
1305
1306        return 0;
1307}
1308
1309static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1310{
1311        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1312        struct snd_pcm_runtime *runtime = substream->runtime;
1313
1314        if (runtime->dma_area != chip->capt.hw_buf.area)
1315                snd_pcm_lib_free_pages(substream);
1316        runtime->dma_area = NULL;
1317        runtime->dma_addr = 0;
1318        runtime->dma_bytes = 0;
1319
1320        return 0;
1321}
1322
1323static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1324{
1325        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1326        struct snd_pcm_runtime *runtime = substream->runtime;
1327
1328        snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1329        chip->capt.shift = 2;
1330        memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1331        chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1332        chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1333        snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1334
1335        return 0;
1336}
1337
1338static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1339{
1340        struct snd_cs46xx *chip = dev_id;
1341        u32 status1;
1342#ifdef CONFIG_SND_CS46XX_NEW_DSP
1343        struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1344        u32 status2;
1345        int i;
1346        struct snd_cs46xx_pcm *cpcm = NULL;
1347#endif
1348
1349        /*
1350         *  Read the Interrupt Status Register to clear the interrupt
1351         */
1352        status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1353        if ((status1 & 0x7fffffff) == 0) {
1354                snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1355                return IRQ_NONE;
1356        }
1357
1358#ifdef CONFIG_SND_CS46XX_NEW_DSP
1359        status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1360
1361        for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1362                if (i <= 15) {
1363                        if ( status1 & (1 << i) ) {
1364                                if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1365                                        if (chip->capt.substream)
1366                                                snd_pcm_period_elapsed(chip->capt.substream);
1367                                } else {
1368                                        if (ins->pcm_channels[i].active &&
1369                                            ins->pcm_channels[i].private_data &&
1370                                            !ins->pcm_channels[i].unlinked) {
1371                                                cpcm = ins->pcm_channels[i].private_data;
1372                                                snd_pcm_period_elapsed(cpcm->substream);
1373                                        }
1374                                }
1375                        }
1376                } else {
1377                        if ( status2 & (1 << (i - 16))) {
1378                                if (ins->pcm_channels[i].active && 
1379                                    ins->pcm_channels[i].private_data &&
1380                                    !ins->pcm_channels[i].unlinked) {
1381                                        cpcm = ins->pcm_channels[i].private_data;
1382                                        snd_pcm_period_elapsed(cpcm->substream);
1383                                }
1384                        }
1385                }
1386        }
1387
1388#else
1389        /* old dsp */
1390        if ((status1 & HISR_VC0) && chip->playback_pcm) {
1391                if (chip->playback_pcm->substream)
1392                        snd_pcm_period_elapsed(chip->playback_pcm->substream);
1393        }
1394        if ((status1 & HISR_VC1) && chip->pcm) {
1395                if (chip->capt.substream)
1396                        snd_pcm_period_elapsed(chip->capt.substream);
1397        }
1398#endif
1399
1400        if ((status1 & HISR_MIDI) && chip->rmidi) {
1401                unsigned char c;
1402                
1403                spin_lock(&chip->reg_lock);
1404                while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1405                        c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1406                        if ((chip->midcr & MIDCR_RIE) == 0)
1407                                continue;
1408                        snd_rawmidi_receive(chip->midi_input, &c, 1);
1409                }
1410                while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1411                        if ((chip->midcr & MIDCR_TIE) == 0)
1412                                break;
1413                        if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1414                                chip->midcr &= ~MIDCR_TIE;
1415                                snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1416                                break;
1417                        }
1418                        snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1419                }
1420                spin_unlock(&chip->reg_lock);
1421        }
1422        /*
1423         *  EOI to the PCI part....reenables interrupts
1424         */
1425        snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1426
1427        return IRQ_HANDLED;
1428}
1429
1430static const struct snd_pcm_hardware snd_cs46xx_playback =
1431{
1432        .info =                 (SNDRV_PCM_INFO_MMAP |
1433                                 SNDRV_PCM_INFO_INTERLEAVED | 
1434                                 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1435                                 /*SNDRV_PCM_INFO_RESUME*/ |
1436                                 SNDRV_PCM_INFO_SYNC_APPLPTR),
1437        .formats =              (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1438                                 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1439                                 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1440        .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1441        .rate_min =             5500,
1442        .rate_max =             48000,
1443        .channels_min =         1,
1444        .channels_max =         2,
1445        .buffer_bytes_max =     (256 * 1024),
1446        .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1447        .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1448        .periods_min =          CS46XX_FRAGS,
1449        .periods_max =          1024,
1450        .fifo_size =            0,
1451};
1452
1453static const struct snd_pcm_hardware snd_cs46xx_capture =
1454{
1455        .info =                 (SNDRV_PCM_INFO_MMAP |
1456                                 SNDRV_PCM_INFO_INTERLEAVED |
1457                                 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1458                                 /*SNDRV_PCM_INFO_RESUME*/ |
1459                                 SNDRV_PCM_INFO_SYNC_APPLPTR),
1460        .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1461        .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1462        .rate_min =             5500,
1463        .rate_max =             48000,
1464        .channels_min =         2,
1465        .channels_max =         2,
1466        .buffer_bytes_max =     (256 * 1024),
1467        .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1468        .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1469        .periods_min =          CS46XX_FRAGS,
1470        .periods_max =          1024,
1471        .fifo_size =            0,
1472};
1473
1474#ifdef CONFIG_SND_CS46XX_NEW_DSP
1475
1476static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1477
1478static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1479        .count = ARRAY_SIZE(period_sizes),
1480        .list = period_sizes,
1481        .mask = 0
1482};
1483
1484#endif
1485
1486static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1487{
1488        kfree(runtime->private_data);
1489}
1490
1491static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1492{
1493        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1494        struct snd_cs46xx_pcm * cpcm;
1495        struct snd_pcm_runtime *runtime = substream->runtime;
1496
1497        cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1498        if (cpcm == NULL)
1499                return -ENOMEM;
1500        if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1501                                PAGE_SIZE, &cpcm->hw_buf) < 0) {
1502                kfree(cpcm);
1503                return -ENOMEM;
1504        }
1505
1506        runtime->hw = snd_cs46xx_playback;
1507        runtime->private_data = cpcm;
1508        runtime->private_free = snd_cs46xx_pcm_free_substream;
1509
1510        cpcm->substream = substream;
1511#ifdef CONFIG_SND_CS46XX_NEW_DSP
1512        mutex_lock(&chip->spos_mutex);
1513        cpcm->pcm_channel = NULL; 
1514        cpcm->pcm_channel_id = pcm_channel_id;
1515
1516
1517        snd_pcm_hw_constraint_list(runtime, 0,
1518                                   SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 
1519                                   &hw_constraints_period_sizes);
1520
1521        mutex_unlock(&chip->spos_mutex);
1522#else
1523        chip->playback_pcm = cpcm; /* HACK */
1524#endif
1525
1526        if (chip->accept_valid)
1527                substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1528        chip->active_ctrl(chip, 1);
1529
1530        return 0;
1531}
1532
1533static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1534{
1535        dev_dbg(substream->pcm->card->dev, "open front channel\n");
1536        return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1537}
1538
1539#ifdef CONFIG_SND_CS46XX_NEW_DSP
1540static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1541{
1542        dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1543        return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1544}
1545
1546static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1547{
1548        dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1549        return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1550}
1551
1552static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1553{
1554        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1555
1556        dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1557
1558        mutex_lock(&chip->spos_mutex);
1559        cs46xx_iec958_pre_open (chip);
1560        mutex_unlock(&chip->spos_mutex);
1561
1562        return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1563}
1564
1565static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1566
1567static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1568{
1569        int err;
1570        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1571  
1572        dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1573
1574        err = snd_cs46xx_playback_close(substream);
1575
1576        mutex_lock(&chip->spos_mutex);
1577        cs46xx_iec958_post_close (chip);
1578        mutex_unlock(&chip->spos_mutex);
1579
1580        return err;
1581}
1582#endif
1583
1584static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1585{
1586        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1587
1588        if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1589                                PAGE_SIZE, &chip->capt.hw_buf) < 0)
1590                return -ENOMEM;
1591        chip->capt.substream = substream;
1592        substream->runtime->hw = snd_cs46xx_capture;
1593
1594        if (chip->accept_valid)
1595                substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1596
1597        chip->active_ctrl(chip, 1);
1598
1599#ifdef CONFIG_SND_CS46XX_NEW_DSP
1600        snd_pcm_hw_constraint_list(substream->runtime, 0,
1601                                   SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 
1602                                   &hw_constraints_period_sizes);
1603#endif
1604        return 0;
1605}
1606
1607static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1608{
1609        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1610        struct snd_pcm_runtime *runtime = substream->runtime;
1611        struct snd_cs46xx_pcm * cpcm;
1612
1613        cpcm = runtime->private_data;
1614
1615        /* when playback_open fails, then cpcm can be NULL */
1616        if (!cpcm) return -ENXIO;
1617
1618#ifdef CONFIG_SND_CS46XX_NEW_DSP
1619        mutex_lock(&chip->spos_mutex);
1620        if (cpcm->pcm_channel) {
1621                cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1622                cpcm->pcm_channel = NULL;
1623        }
1624        mutex_unlock(&chip->spos_mutex);
1625#else
1626        chip->playback_pcm = NULL;
1627#endif
1628
1629        cpcm->substream = NULL;
1630        snd_dma_free_pages(&cpcm->hw_buf);
1631        chip->active_ctrl(chip, -1);
1632
1633        return 0;
1634}
1635
1636static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1637{
1638        struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1639
1640        chip->capt.substream = NULL;
1641        snd_dma_free_pages(&chip->capt.hw_buf);
1642        chip->active_ctrl(chip, -1);
1643
1644        return 0;
1645}
1646
1647#ifdef CONFIG_SND_CS46XX_NEW_DSP
1648static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1649        .open =                 snd_cs46xx_playback_open_rear,
1650        .close =                snd_cs46xx_playback_close,
1651        .hw_params =            snd_cs46xx_playback_hw_params,
1652        .hw_free =              snd_cs46xx_playback_hw_free,
1653        .prepare =              snd_cs46xx_playback_prepare,
1654        .trigger =              snd_cs46xx_playback_trigger,
1655        .pointer =              snd_cs46xx_playback_direct_pointer,
1656};
1657
1658static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1659        .open =                 snd_cs46xx_playback_open_rear,
1660        .close =                snd_cs46xx_playback_close,
1661        .hw_params =            snd_cs46xx_playback_hw_params,
1662        .hw_free =              snd_cs46xx_playback_hw_free,
1663        .prepare =              snd_cs46xx_playback_prepare,
1664        .trigger =              snd_cs46xx_playback_trigger,
1665        .pointer =              snd_cs46xx_playback_indirect_pointer,
1666        .ack =                  snd_cs46xx_playback_transfer,
1667};
1668
1669static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1670        .open =                 snd_cs46xx_playback_open_clfe,
1671        .close =                snd_cs46xx_playback_close,
1672        .hw_params =            snd_cs46xx_playback_hw_params,
1673        .hw_free =              snd_cs46xx_playback_hw_free,
1674        .prepare =              snd_cs46xx_playback_prepare,
1675        .trigger =              snd_cs46xx_playback_trigger,
1676        .pointer =              snd_cs46xx_playback_direct_pointer,
1677};
1678
1679static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1680        .open =                 snd_cs46xx_playback_open_clfe,
1681        .close =                snd_cs46xx_playback_close,
1682        .hw_params =            snd_cs46xx_playback_hw_params,
1683        .hw_free =              snd_cs46xx_playback_hw_free,
1684        .prepare =              snd_cs46xx_playback_prepare,
1685        .trigger =              snd_cs46xx_playback_trigger,
1686        .pointer =              snd_cs46xx_playback_indirect_pointer,
1687        .ack =                  snd_cs46xx_playback_transfer,
1688};
1689
1690static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1691        .open =                 snd_cs46xx_playback_open_iec958,
1692        .close =                snd_cs46xx_playback_close_iec958,
1693        .hw_params =            snd_cs46xx_playback_hw_params,
1694        .hw_free =              snd_cs46xx_playback_hw_free,
1695        .prepare =              snd_cs46xx_playback_prepare,
1696        .trigger =              snd_cs46xx_playback_trigger,
1697        .pointer =              snd_cs46xx_playback_direct_pointer,
1698};
1699
1700static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1701        .open =                 snd_cs46xx_playback_open_iec958,
1702        .close =                snd_cs46xx_playback_close_iec958,
1703        .hw_params =            snd_cs46xx_playback_hw_params,
1704        .hw_free =              snd_cs46xx_playback_hw_free,
1705        .prepare =              snd_cs46xx_playback_prepare,
1706        .trigger =              snd_cs46xx_playback_trigger,
1707        .pointer =              snd_cs46xx_playback_indirect_pointer,
1708        .ack =                  snd_cs46xx_playback_transfer,
1709};
1710
1711#endif
1712
1713static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1714        .open =                 snd_cs46xx_playback_open,
1715        .close =                snd_cs46xx_playback_close,
1716        .hw_params =            snd_cs46xx_playback_hw_params,
1717        .hw_free =              snd_cs46xx_playback_hw_free,
1718        .prepare =              snd_cs46xx_playback_prepare,
1719        .trigger =              snd_cs46xx_playback_trigger,
1720        .pointer =              snd_cs46xx_playback_direct_pointer,
1721};
1722
1723static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1724        .open =                 snd_cs46xx_playback_open,
1725        .close =                snd_cs46xx_playback_close,
1726        .hw_params =            snd_cs46xx_playback_hw_params,
1727        .hw_free =              snd_cs46xx_playback_hw_free,
1728        .prepare =              snd_cs46xx_playback_prepare,
1729        .trigger =              snd_cs46xx_playback_trigger,
1730        .pointer =              snd_cs46xx_playback_indirect_pointer,
1731        .ack =                  snd_cs46xx_playback_transfer,
1732};
1733
1734static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1735        .open =                 snd_cs46xx_capture_open,
1736        .close =                snd_cs46xx_capture_close,
1737        .hw_params =            snd_cs46xx_capture_hw_params,
1738        .hw_free =              snd_cs46xx_capture_hw_free,
1739        .prepare =              snd_cs46xx_capture_prepare,
1740        .trigger =              snd_cs46xx_capture_trigger,
1741        .pointer =              snd_cs46xx_capture_direct_pointer,
1742};
1743
1744static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1745        .open =                 snd_cs46xx_capture_open,
1746        .close =                snd_cs46xx_capture_close,
1747        .hw_params =            snd_cs46xx_capture_hw_params,
1748        .hw_free =              snd_cs46xx_capture_hw_free,
1749        .prepare =              snd_cs46xx_capture_prepare,
1750        .trigger =              snd_cs46xx_capture_trigger,
1751        .pointer =              snd_cs46xx_capture_indirect_pointer,
1752        .ack =                  snd_cs46xx_capture_transfer,
1753};
1754
1755#ifdef CONFIG_SND_CS46XX_NEW_DSP
1756#define MAX_PLAYBACK_CHANNELS   (DSP_MAX_PCM_CHANNELS - 1)
1757#else
1758#define MAX_PLAYBACK_CHANNELS   1
1759#endif
1760
1761int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1762{
1763        struct snd_pcm *pcm;
1764        int err;
1765
1766        err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm);
1767        if (err < 0)
1768                return err;
1769
1770        pcm->private_data = chip;
1771
1772        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1773        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1774
1775        /* global setup */
1776        pcm->info_flags = 0;
1777        strcpy(pcm->name, "CS46xx");
1778        chip->pcm = pcm;
1779
1780        snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1781                                              &chip->pci->dev,
1782                                              64*1024, 256*1024);
1783
1784        return 0;
1785}
1786
1787
1788#ifdef CONFIG_SND_CS46XX_NEW_DSP
1789int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1790{
1791        struct snd_pcm *pcm;
1792        int err;
1793
1794        err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1795        if (err < 0)
1796                return err;
1797
1798        pcm->private_data = chip;
1799
1800        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1801
1802        /* global setup */
1803        pcm->info_flags = 0;
1804        strcpy(pcm->name, "CS46xx - Rear");
1805        chip->pcm_rear = pcm;
1806
1807        snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1808                                              &chip->pci->dev,
1809                                              64*1024, 256*1024);
1810
1811        return 0;
1812}
1813
1814int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1815{
1816        struct snd_pcm *pcm;
1817        int err;
1818
1819        err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1820        if (err < 0)
1821                return err;
1822
1823        pcm->private_data = chip;
1824
1825        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1826
1827        /* global setup */
1828        pcm->info_flags = 0;
1829        strcpy(pcm->name, "CS46xx - Center LFE");
1830        chip->pcm_center_lfe = pcm;
1831
1832        snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1833                                              &chip->pci->dev,
1834                                              64*1024, 256*1024);
1835
1836        return 0;
1837}
1838
1839int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1840{
1841        struct snd_pcm *pcm;
1842        int err;
1843
1844        err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm);
1845        if (err < 0)
1846                return err;
1847
1848        pcm->private_data = chip;
1849
1850        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1851
1852        /* global setup */
1853        pcm->info_flags = 0;
1854        strcpy(pcm->name, "CS46xx - IEC958");
1855        chip->pcm_iec958 = pcm;
1856
1857        snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1858                                              &chip->pci->dev,
1859                                              64*1024, 256*1024);
1860
1861        return 0;
1862}
1863#endif
1864
1865/*
1866 *  Mixer routines
1867 */
1868static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1869{
1870        struct snd_cs46xx *chip = bus->private_data;
1871
1872        chip->ac97_bus = NULL;
1873}
1874
1875static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1876{
1877        struct snd_cs46xx *chip = ac97->private_data;
1878
1879        if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1880                       ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1881                return;
1882
1883        if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1884                chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1885                chip->eapd_switch = NULL;
1886        }
1887        else
1888                chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1889}
1890
1891static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol, 
1892                               struct snd_ctl_elem_info *uinfo)
1893{
1894        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1895        uinfo->count = 2;
1896        uinfo->value.integer.min = 0;
1897        uinfo->value.integer.max = 0x7fff;
1898        return 0;
1899}
1900
1901static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1902{
1903        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1904        int reg = kcontrol->private_value;
1905        unsigned int val = snd_cs46xx_peek(chip, reg);
1906        ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1907        ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1908        return 0;
1909}
1910
1911static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1912{
1913        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1914        int reg = kcontrol->private_value;
1915        unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 | 
1916                            (0xffff - ucontrol->value.integer.value[1]));
1917        unsigned int old = snd_cs46xx_peek(chip, reg);
1918        int change = (old != val);
1919
1920        if (change) {
1921                snd_cs46xx_poke(chip, reg, val);
1922        }
1923
1924        return change;
1925}
1926
1927#ifdef CONFIG_SND_CS46XX_NEW_DSP
1928
1929static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1930{
1931        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1932
1933        ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1934        ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1935
1936        return 0;
1937}
1938
1939static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1940{
1941        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1942        int change = 0;
1943
1944        if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1945            chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1946                cs46xx_dsp_set_dac_volume(chip,
1947                                          ucontrol->value.integer.value[0],
1948                                          ucontrol->value.integer.value[1]);
1949                change = 1;
1950        }
1951
1952        return change;
1953}
1954
1955#if 0
1956static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1957{
1958        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1959
1960        ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1961        ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1962        return 0;
1963}
1964
1965static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1966{
1967        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1968        int change = 0;
1969
1970        if (chip->dsp_spos_instance->spdif_input_volume_left  != ucontrol->value.integer.value[0] ||
1971            chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1972                cs46xx_dsp_set_iec958_volume (chip,
1973                                              ucontrol->value.integer.value[0],
1974                                              ucontrol->value.integer.value[1]);
1975                change = 1;
1976        }
1977
1978        return change;
1979}
1980#endif
1981
1982#define snd_mixer_boolean_info          snd_ctl_boolean_mono_info
1983
1984static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol, 
1985                                 struct snd_ctl_elem_value *ucontrol)
1986{
1987        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1988        int reg = kcontrol->private_value;
1989
1990        if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1991                ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1992        else
1993                ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1994
1995        return 0;
1996}
1997
1998static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol, 
1999                                  struct snd_ctl_elem_value *ucontrol)
2000{
2001        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2002        int change, res;
2003
2004        switch (kcontrol->private_value) {
2005        case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
2006                mutex_lock(&chip->spos_mutex);
2007                change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2008                if (ucontrol->value.integer.value[0] && !change) 
2009                        cs46xx_dsp_enable_spdif_out(chip);
2010                else if (change && !ucontrol->value.integer.value[0])
2011                        cs46xx_dsp_disable_spdif_out(chip);
2012
2013                res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
2014                mutex_unlock(&chip->spos_mutex);
2015                break;
2016        case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2017                change = chip->dsp_spos_instance->spdif_status_in;
2018                if (ucontrol->value.integer.value[0] && !change) {
2019                        cs46xx_dsp_enable_spdif_in(chip);
2020                        /* restore volume */
2021                }
2022                else if (change && !ucontrol->value.integer.value[0])
2023                        cs46xx_dsp_disable_spdif_in(chip);
2024                
2025                res = (change != chip->dsp_spos_instance->spdif_status_in);
2026                break;
2027        default:
2028                res = -EINVAL;
2029                snd_BUG(); /* should never happen ... */
2030        }
2031
2032        return res;
2033}
2034
2035static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol, 
2036                                      struct snd_ctl_elem_value *ucontrol)
2037{
2038        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2039        struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2040
2041        if (ins->adc_input != NULL) 
2042                ucontrol->value.integer.value[0] = 1;
2043        else 
2044                ucontrol->value.integer.value[0] = 0;
2045        
2046        return 0;
2047}
2048
2049static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol, 
2050                                      struct snd_ctl_elem_value *ucontrol)
2051{
2052        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2053        struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2054        int change = 0;
2055
2056        if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2057                cs46xx_dsp_enable_adc_capture(chip);
2058                change = 1;
2059        } else  if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2060                cs46xx_dsp_disable_adc_capture(chip);
2061                change = 1;
2062        }
2063        return change;
2064}
2065
2066static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol, 
2067                                      struct snd_ctl_elem_value *ucontrol)
2068{
2069        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2070        struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2071
2072        if (ins->pcm_input != NULL) 
2073                ucontrol->value.integer.value[0] = 1;
2074        else 
2075                ucontrol->value.integer.value[0] = 0;
2076
2077        return 0;
2078}
2079
2080
2081static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol, 
2082                                      struct snd_ctl_elem_value *ucontrol)
2083{
2084        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2085        struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2086        int change = 0;
2087
2088        if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2089                cs46xx_dsp_enable_pcm_capture(chip);
2090                change = 1;
2091        } else  if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2092                cs46xx_dsp_disable_pcm_capture(chip);
2093                change = 1;
2094        }
2095
2096        return change;
2097}
2098
2099static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol, 
2100                                     struct snd_ctl_elem_value *ucontrol)
2101{
2102        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2103
2104        int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2105
2106        if (val1 & EGPIODR_GPOE0)
2107                ucontrol->value.integer.value[0] = 1;
2108        else
2109                ucontrol->value.integer.value[0] = 0;
2110
2111        return 0;
2112}
2113
2114/*
2115 *      Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2116 */ 
2117static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol, 
2118                                       struct snd_ctl_elem_value *ucontrol)
2119{
2120        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2121        int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2122        int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2123
2124        if (ucontrol->value.integer.value[0]) {
2125                /* optical is default */
2126                snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 
2127                                   EGPIODR_GPOE0 | val1);  /* enable EGPIO0 output */
2128                snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 
2129                                   EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2130        } else {
2131                /* coaxial */
2132                snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE0); /* disable */
2133                snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2134        }
2135
2136        /* checking diff from the EGPIO direction register 
2137           should be enough */
2138        return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2139}
2140
2141
2142static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2143{
2144        uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2145        uinfo->count = 1;
2146        return 0;
2147}
2148
2149static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2150                                        struct snd_ctl_elem_value *ucontrol)
2151{
2152        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2153        struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2154
2155        mutex_lock(&chip->spos_mutex);
2156        ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2157        ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2158        ucontrol->value.iec958.status[2] = 0;
2159        ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2160        mutex_unlock(&chip->spos_mutex);
2161
2162        return 0;
2163}
2164
2165static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2166                                        struct snd_ctl_elem_value *ucontrol)
2167{
2168        struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2169        struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2170        unsigned int val;
2171        int change;
2172
2173        mutex_lock(&chip->spos_mutex);
2174        val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2175                ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2176                ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3]))  |
2177                /* left and right validity bit */
2178                (1 << 13) | (1 << 12);
2179
2180
2181        change = (unsigned int)ins->spdif_csuv_default != val;
2182        ins->spdif_csuv_default = val;
2183
2184        if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2185                cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2186
2187        mutex_unlock(&chip->spos_mutex);
2188
2189        return change;
2190}
2191
2192static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2193                                     struct snd_ctl_elem_value *ucontrol)
2194{
2195        ucontrol->value.iec958.status[0] = 0xff;
2196        ucontrol->value.iec958.status[1] = 0xff;
2197        ucontrol->value.iec958.status[2] = 0x00;
2198        ucontrol->value.iec958.status[3] = 0xff;
2199        return 0;
2200}
2201
2202static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2203                                         struct snd_ctl_elem_value *ucontrol)
2204{
2205        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2206        struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2207
2208        mutex_lock(&chip->spos_mutex);
2209        ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2210        ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2211        ucontrol->value.iec958.status[2] = 0;
2212        ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2213        mutex_unlock(&chip->spos_mutex);
2214
2215        return 0;
2216}
2217
2218static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2219                                        struct snd_ctl_elem_value *ucontrol)
2220{
2221        struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2222        struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2223        unsigned int val;
2224        int change;
2225
2226        mutex_lock(&chip->spos_mutex);
2227        val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2228                ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2229                ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2230                /* left and right validity bit */
2231                (1 << 13) | (1 << 12);
2232
2233
2234        change = ins->spdif_csuv_stream != val;
2235        ins->spdif_csuv_stream = val;
2236
2237        if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2238                cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2239
2240        mutex_unlock(&chip->spos_mutex);
2241
2242        return change;
2243}
2244
2245#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2246
2247
2248static const struct snd_kcontrol_new snd_cs46xx_controls[] = {
2249{
2250        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2251        .name = "DAC Volume",
2252        .info = snd_cs46xx_vol_info,
2253#ifndef CONFIG_SND_CS46XX_NEW_DSP
2254        .get = snd_cs46xx_vol_get,
2255        .put = snd_cs46xx_vol_put,
2256        .private_value = BA1_PVOL,
2257#else
2258        .get = snd_cs46xx_vol_dac_get,
2259        .put = snd_cs46xx_vol_dac_put,
2260#endif
2261},
2262
2263{
2264        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2265        .name = "ADC Volume",
2266        .info = snd_cs46xx_vol_info,
2267        .get = snd_cs46xx_vol_get,
2268        .put = snd_cs46xx_vol_put,
2269#ifndef CONFIG_SND_CS46XX_NEW_DSP
2270        .private_value = BA1_CVOL,
2271#else
2272        .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2273#endif
2274},
2275#ifdef CONFIG_SND_CS46XX_NEW_DSP
2276{
2277        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2278        .name = "ADC Capture Switch",
2279        .info = snd_mixer_boolean_info,
2280        .get = snd_cs46xx_adc_capture_get,
2281        .put = snd_cs46xx_adc_capture_put
2282},
2283{
2284        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2285        .name = "DAC Capture Switch",
2286        .info = snd_mixer_boolean_info,
2287        .get = snd_cs46xx_pcm_capture_get,
2288        .put = snd_cs46xx_pcm_capture_put
2289},
2290{
2291        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2292        .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2293        .info = snd_mixer_boolean_info,
2294        .get = snd_cs46xx_iec958_get,
2295        .put = snd_cs46xx_iec958_put,
2296        .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2297},
2298{
2299        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2300        .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2301        .info = snd_mixer_boolean_info,
2302        .get = snd_cs46xx_iec958_get,
2303        .put = snd_cs46xx_iec958_put,
2304        .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2305},
2306#if 0
2307/* Input IEC958 volume does not work for the moment. (Benny) */
2308{
2309        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2310        .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2311        .info = snd_cs46xx_vol_info,
2312        .get = snd_cs46xx_vol_iec958_get,
2313        .put = snd_cs46xx_vol_iec958_put,
2314        .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2315},
2316#endif
2317{
2318        .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2319        .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2320        .info =  snd_cs46xx_spdif_info,
2321        .get =   snd_cs46xx_spdif_default_get,
2322        .put =   snd_cs46xx_spdif_default_put,
2323},
2324{
2325        .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2326        .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2327        .info =  snd_cs46xx_spdif_info,
2328        .get =   snd_cs46xx_spdif_mask_get,
2329        .access = SNDRV_CTL_ELEM_ACCESS_READ
2330},
2331{
2332        .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2333        .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2334        .info =  snd_cs46xx_spdif_info,
2335        .get =   snd_cs46xx_spdif_stream_get,
2336        .put =   snd_cs46xx_spdif_stream_put
2337},
2338
2339#endif
2340};
2341
2342#ifdef CONFIG_SND_CS46XX_NEW_DSP
2343/* set primary cs4294 codec into Extended Audio Mode */
2344static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol, 
2345                                    struct snd_ctl_elem_value *ucontrol)
2346{
2347        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2348        unsigned short val;
2349        val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2350        ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2351        return 0;
2352}
2353
2354static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol, 
2355                                    struct snd_ctl_elem_value *ucontrol)
2356{
2357        struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2358        return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2359                                    AC97_CSR_ACMODE, 0x200,
2360                                    ucontrol->value.integer.value[0] ? 0 : 0x200);
2361}
2362
2363static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2364        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2365        .name = "Duplicate Front",
2366        .info = snd_mixer_boolean_info,
2367        .get = snd_cs46xx_front_dup_get,
2368        .put = snd_cs46xx_front_dup_put,
2369};
2370#endif
2371
2372#ifdef CONFIG_SND_CS46XX_NEW_DSP
2373/* Only available on the Hercules Game Theater XP soundcard */
2374static const struct snd_kcontrol_new snd_hercules_controls[] = {
2375{
2376        .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2377        .name = "Optical/Coaxial SPDIF Input Switch",
2378        .info = snd_mixer_boolean_info,
2379        .get = snd_herc_spdif_select_get,
2380        .put = snd_herc_spdif_select_put,
2381},
2382};
2383
2384
2385static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2386{
2387        unsigned long end_time;
2388        int err;
2389
2390        /* reset to defaults */
2391        snd_ac97_write(ac97, AC97_RESET, 0);    
2392
2393        /* set the desired CODEC mode */
2394        if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2395                dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2396                snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2397        } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2398                dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2399                snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2400        } else {
2401                snd_BUG(); /* should never happen ... */
2402        }
2403
2404        udelay(50);
2405
2406        /* it's necessary to wait awhile until registers are accessible after RESET */
2407        /* because the PCM or MASTER volume registers can be modified, */
2408        /* the REC_GAIN register is used for tests */
2409        end_time = jiffies + HZ;
2410        do {
2411                unsigned short ext_mid;
2412    
2413                /* use preliminary reads to settle the communication */
2414                snd_ac97_read(ac97, AC97_RESET);
2415                snd_ac97_read(ac97, AC97_VENDOR_ID1);
2416                snd_ac97_read(ac97, AC97_VENDOR_ID2);
2417                /* modem? */
2418                ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2419                if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2420                        return;
2421
2422                /* test if we can write to the record gain volume register */
2423                snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2424                err = snd_ac97_read(ac97, AC97_REC_GAIN);
2425                if (err == 0x8a05)
2426                        return;
2427
2428                msleep(10);
2429        } while (time_after_eq(end_time, jiffies));
2430
2431        dev_err(ac97->bus->card->dev,
2432                "CS46xx secondary codec doesn't respond!\n");
2433}
2434#endif
2435
2436static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2437{
2438        int idx, err;
2439        struct snd_ac97_template ac97;
2440
2441        memset(&ac97, 0, sizeof(ac97));
2442        ac97.private_data = chip;
2443        ac97.private_free = snd_cs46xx_mixer_free_ac97;
2444        ac97.num = codec;
2445        if (chip->amplifier_ctrl == amp_voyetra)
2446                ac97.scaps = AC97_SCAP_INV_EAPD;
2447
2448        if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2449                snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2450                udelay(10);
2451                if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2452                        dev_dbg(chip->card->dev,
2453                                "secondary codec not present\n");
2454                        return -ENXIO;
2455                }
2456        }
2457
2458        snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2459        for (idx = 0; idx < 100; ++idx) {
2460                if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2461                        err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2462                        return err;
2463                }
2464                msleep(10);
2465        }
2466        dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2467        return -ENXIO;
2468}
2469
2470int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2471{
2472        struct snd_card *card = chip->card;
2473        struct snd_ctl_elem_id id;
2474        int err;
2475        unsigned int idx;
2476        static const struct snd_ac97_bus_ops ops = {
2477#ifdef CONFIG_SND_CS46XX_NEW_DSP
2478                .reset = snd_cs46xx_codec_reset,
2479#endif
2480                .write = snd_cs46xx_ac97_write,
2481                .read = snd_cs46xx_ac97_read,
2482        };
2483
2484        /* detect primary codec */
2485        chip->nr_ac97_codecs = 0;
2486        dev_dbg(chip->card->dev, "detecting primary codec\n");
2487        err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
2488        if (err < 0)
2489                return err;
2490        chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2491
2492        if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2493                return -ENXIO;
2494        chip->nr_ac97_codecs = 1;
2495
2496#ifdef CONFIG_SND_CS46XX_NEW_DSP
2497        dev_dbg(chip->card->dev, "detecting secondary codec\n");
2498        /* try detect a secondary codec */
2499        if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2500                chip->nr_ac97_codecs = 2;
2501#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2502
2503        /* add cs4630 mixer controls */
2504        for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2505                struct snd_kcontrol *kctl;
2506                kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2507                if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2508                        kctl->id.device = spdif_device;
2509                err = snd_ctl_add(card, kctl);
2510                if (err < 0)
2511                        return err;
2512        }
2513
2514        /* get EAPD mixer switch (for voyetra hack) */
2515        memset(&id, 0, sizeof(id));
2516        id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2517        strcpy(id.name, "External Amplifier");
2518        chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2519    
2520#ifdef CONFIG_SND_CS46XX_NEW_DSP
2521        if (chip->nr_ac97_codecs == 1) {
2522                unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2523                if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2524                        err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2525                        if (err < 0)
2526                                return err;
2527                        snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2528                                             AC97_CSR_ACMODE, 0x200);
2529                }
2530        }
2531        /* do soundcard specific mixer setup */
2532        if (chip->mixer_init) {
2533                dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2534                chip->mixer_init(chip);
2535        }
2536#endif
2537
2538        /* turn on amplifier */
2539        chip->amplifier_ctrl(chip, 1);
2540    
2541        return 0;
2542}
2543
2544/*
2545 *  RawMIDI interface
2546 */
2547
2548static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2549{
2550        snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2551        udelay(100);
2552        snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2553}
2554
2555static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2556{
2557        struct snd_cs46xx *chip = substream->rmidi->private_data;
2558
2559        chip->active_ctrl(chip, 1);
2560        spin_lock_irq(&chip->reg_lock);
2561        chip->uartm |= CS46XX_MODE_INPUT;
2562        chip->midcr |= MIDCR_RXE;
2563        chip->midi_input = substream;
2564        if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2565                snd_cs46xx_midi_reset(chip);
2566        } else {
2567                snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2568        }
2569        spin_unlock_irq(&chip->reg_lock);
2570        return 0;
2571}
2572
2573static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2574{
2575        struct snd_cs46xx *chip = substream->rmidi->private_data;
2576
2577        spin_lock_irq(&chip->reg_lock);
2578        chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2579        chip->midi_input = NULL;
2580        if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2581                snd_cs46xx_midi_reset(chip);
2582        } else {
2583                snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2584        }
2585        chip->uartm &= ~CS46XX_MODE_INPUT;
2586        spin_unlock_irq(&chip->reg_lock);
2587        chip->active_ctrl(chip, -1);
2588        return 0;
2589}
2590
2591static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2592{
2593        struct snd_cs46xx *chip = substream->rmidi->private_data;
2594
2595        chip->active_ctrl(chip, 1);
2596
2597        spin_lock_irq(&chip->reg_lock);
2598        chip->uartm |= CS46XX_MODE_OUTPUT;
2599        chip->midcr |= MIDCR_TXE;
2600        chip->midi_output = substream;
2601        if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2602                snd_cs46xx_midi_reset(chip);
2603        } else {
2604                snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2605        }
2606        spin_unlock_irq(&chip->reg_lock);
2607        return 0;
2608}
2609
2610static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2611{
2612        struct snd_cs46xx *chip = substream->rmidi->private_data;
2613
2614        spin_lock_irq(&chip->reg_lock);
2615        chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2616        chip->midi_output = NULL;
2617        if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2618                snd_cs46xx_midi_reset(chip);
2619        } else {
2620                snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2621        }
2622        chip->uartm &= ~CS46XX_MODE_OUTPUT;
2623        spin_unlock_irq(&chip->reg_lock);
2624        chip->active_ctrl(chip, -1);
2625        return 0;
2626}
2627
2628static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2629{
2630        unsigned long flags;
2631        struct snd_cs46xx *chip = substream->rmidi->private_data;
2632
2633        spin_lock_irqsave(&chip->reg_lock, flags);
2634        if (up) {
2635                if ((chip->midcr & MIDCR_RIE) == 0) {
2636                        chip->midcr |= MIDCR_RIE;
2637                        snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2638                }
2639        } else {
2640                if (chip->midcr & MIDCR_RIE) {
2641                        chip->midcr &= ~MIDCR_RIE;
2642                        snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2643                }
2644        }
2645        spin_unlock_irqrestore(&chip->reg_lock, flags);
2646}
2647
2648static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2649{
2650        unsigned long flags;
2651        struct snd_cs46xx *chip = substream->rmidi->private_data;
2652        unsigned char byte;
2653
2654        spin_lock_irqsave(&chip->reg_lock, flags);
2655        if (up) {
2656                if ((chip->midcr & MIDCR_TIE) == 0) {
2657                        chip->midcr |= MIDCR_TIE;
2658                        /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2659                        while ((chip->midcr & MIDCR_TIE) &&
2660                               (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2661                                if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2662                                        chip->midcr &= ~MIDCR_TIE;
2663                                } else {
2664                                        snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2665                                }
2666                        }
2667                        snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2668                }
2669        } else {
2670                if (chip->midcr & MIDCR_TIE) {
2671                        chip->midcr &= ~MIDCR_TIE;
2672                        snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2673                }
2674        }
2675        spin_unlock_irqrestore(&chip->reg_lock, flags);
2676}
2677
2678static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2679{
2680        .open =         snd_cs46xx_midi_output_open,
2681        .close =        snd_cs46xx_midi_output_close,
2682        .trigger =      snd_cs46xx_midi_output_trigger,
2683};
2684
2685static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2686{
2687        .open =         snd_cs46xx_midi_input_open,
2688        .close =        snd_cs46xx_midi_input_close,
2689        .trigger =      snd_cs46xx_midi_input_trigger,
2690};
2691
2692int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2693{
2694        struct snd_rawmidi *rmidi;
2695        int err;
2696
2697        err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi);
2698        if (err < 0)
2699                return err;
2700        strcpy(rmidi->name, "CS46XX");
2701        snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2702        snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2703        rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2704        rmidi->private_data = chip;
2705        chip->rmidi = rmidi;
2706        return 0;
2707}
2708
2709
2710/*
2711 * gameport interface
2712 */
2713
2714#if IS_REACHABLE(CONFIG_GAMEPORT)
2715
2716static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2717{
2718        struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2719
2720        if (snd_BUG_ON(!chip))
2721                return;
2722        snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF);  //outb(gameport->io, 0xFF);
2723}
2724
2725static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2726{
2727        struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2728
2729        if (snd_BUG_ON(!chip))
2730                return 0;
2731        return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2732}
2733
2734static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2735{
2736        struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2737        unsigned js1, js2, jst;
2738
2739        if (snd_BUG_ON(!chip))
2740                return 0;
2741
2742        js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2743        js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2744        jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2745        
2746        *buttons = (~jst >> 4) & 0x0F; 
2747        
2748        axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2749        axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2750        axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2751        axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2752
2753        for(jst=0;jst<4;++jst)
2754                if(axes[jst]==0xFFFF) axes[jst] = -1;
2755        return 0;
2756}
2757
2758static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2759{
2760        switch (mode) {
2761        case GAMEPORT_MODE_COOKED:
2762                return 0;
2763        case GAMEPORT_MODE_RAW:
2764                return 0;
2765        default:
2766                return -1;
2767        }
2768        return 0;
2769}
2770
2771int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2772{
2773        struct gameport *gp;
2774
2775        chip->gameport = gp = gameport_allocate_port();
2776        if (!gp) {
2777                dev_err(chip->card->dev,
2778                        "cannot allocate memory for gameport\n");
2779                return -ENOMEM;
2780        }
2781
2782        gameport_set_name(gp, "CS46xx Gameport");
2783        gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2784        gameport_set_dev_parent(gp, &chip->pci->dev);
2785        gameport_set_port_data(gp, chip);
2786
2787        gp->open = snd_cs46xx_gameport_open;
2788        gp->read = snd_cs46xx_gameport_read;
2789        gp->trigger = snd_cs46xx_gameport_trigger;
2790        gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2791
2792        snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2793        snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2794
2795        gameport_register_port(gp);
2796
2797        return 0;
2798}
2799
2800static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2801{
2802        if (chip->gameport) {
2803                gameport_unregister_port(chip->gameport);
2804                chip->gameport = NULL;
2805        }
2806}
2807#else
2808int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2809static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2810#endif /* CONFIG_GAMEPORT */
2811
2812#ifdef CONFIG_SND_PROC_FS
2813/*
2814 *  proc interface
2815 */
2816
2817static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2818                                  void *file_private_data,
2819                                  struct file *file, char __user *buf,
2820                                  size_t count, loff_t pos)
2821{
2822        struct snd_cs46xx_region *region = entry->private_data;
2823        
2824        if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2825                return -EFAULT;
2826        return count;
2827}
2828
2829static const struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2830        .read = snd_cs46xx_io_read,
2831};
2832
2833static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2834{
2835        struct snd_info_entry *entry;
2836        int idx;
2837        
2838        for (idx = 0; idx < 5; idx++) {
2839                struct snd_cs46xx_region *region = &chip->region.idx[idx];
2840                if (! snd_card_proc_new(card, region->name, &entry)) {
2841                        entry->content = SNDRV_INFO_CONTENT_DATA;
2842                        entry->private_data = chip;
2843                        entry->c.ops = &snd_cs46xx_proc_io_ops;
2844                        entry->size = region->size;
2845                        entry->mode = S_IFREG | 0400;
2846                }
2847        }
2848#ifdef CONFIG_SND_CS46XX_NEW_DSP
2849        cs46xx_dsp_proc_init(card, chip);
2850#endif
2851        return 0;
2852}
2853
2854static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2855{
2856#ifdef CONFIG_SND_CS46XX_NEW_DSP
2857        cs46xx_dsp_proc_done(chip);
2858#endif
2859        return 0;
2860}
2861#else /* !CONFIG_SND_PROC_FS */
2862#define snd_cs46xx_proc_init(card, chip)
2863#define snd_cs46xx_proc_done(chip)
2864#endif
2865
2866/*
2867 * stop the h/w
2868 */
2869static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2870{
2871        unsigned int tmp;
2872
2873        tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2874        tmp &= ~0x0000f03f;
2875        tmp |=  0x00000010;
2876        snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt disable */
2877
2878        tmp = snd_cs46xx_peek(chip, BA1_CIE);
2879        tmp &= ~0x0000003f;
2880        tmp |=  0x00000011;
2881        snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt disable */
2882
2883        /*
2884         *  Stop playback DMA.
2885         */
2886        tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2887        snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2888
2889        /*
2890         *  Stop capture DMA.
2891         */
2892        tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2893        snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2894
2895        /*
2896         *  Reset the processor.
2897         */
2898        snd_cs46xx_reset(chip);
2899
2900        snd_cs46xx_proc_stop(chip);
2901
2902        /*
2903         *  Power down the PLL.
2904         */
2905        snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2906
2907        /*
2908         *  Turn off the Processor by turning off the software clock enable flag in 
2909         *  the clock control register.
2910         */
2911        tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2912        snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2913}
2914
2915
2916static int snd_cs46xx_free(struct snd_cs46xx *chip)
2917{
2918        int idx;
2919
2920        if (snd_BUG_ON(!chip))
2921                return -EINVAL;
2922
2923        if (chip->active_ctrl)
2924                chip->active_ctrl(chip, 1);
2925
2926        snd_cs46xx_remove_gameport(chip);
2927
2928        if (chip->amplifier_ctrl)
2929                chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2930        
2931        snd_cs46xx_proc_done(chip);
2932
2933        if (chip->region.idx[0].resource)
2934                snd_cs46xx_hw_stop(chip);
2935
2936        if (chip->irq >= 0)
2937                free_irq(chip->irq, chip);
2938
2939        if (chip->active_ctrl)
2940                chip->active_ctrl(chip, -chip->amplifier);
2941
2942        for (idx = 0; idx < 5; idx++) {
2943                struct snd_cs46xx_region *region = &chip->region.idx[idx];
2944
2945                iounmap(region->remap_addr);
2946                release_and_free_resource(region->resource);
2947        }
2948
2949#ifdef CONFIG_SND_CS46XX_NEW_DSP
2950        if (chip->dsp_spos_instance) {
2951                cs46xx_dsp_spos_destroy(chip);
2952                chip->dsp_spos_instance = NULL;
2953        }
2954        for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2955                free_module_desc(chip->modules[idx]);
2956#else
2957        vfree(chip->ba1);
2958#endif
2959        
2960#ifdef CONFIG_PM_SLEEP
2961        kfree(chip->saved_regs);
2962#endif
2963
2964        pci_disable_device(chip->pci);
2965        kfree(chip);
2966        return 0;
2967}
2968
2969static int snd_cs46xx_dev_free(struct snd_device *device)
2970{
2971        struct snd_cs46xx *chip = device->device_data;
2972        return snd_cs46xx_free(chip);
2973}
2974
2975/*
2976 *  initialize chip
2977 */
2978static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2979{
2980        int timeout;
2981
2982        /* 
2983         *  First, blast the clock control register to zero so that the PLL starts
2984         *  out in a known state, and blast the master serial port control register
2985         *  to zero so that the serial ports also start out in a known state.
2986         */
2987        snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2988        snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2989
2990        /*
2991         *  If we are in AC97 mode, then we must set the part to a host controlled
2992         *  AC-link.  Otherwise, we won't be able to bring up the link.
2993         */        
2994#ifdef CONFIG_SND_CS46XX_NEW_DSP
2995        snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 | 
2996                           SERACC_TWO_CODECS);  /* 2.00 dual codecs */
2997        /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2998#else
2999        snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
3000#endif
3001
3002        /*
3003         *  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
3004         *  spec) and then drive it high.  This is done for non AC97 modes since
3005         *  there might be logic external to the CS461x that uses the ARST# line
3006         *  for a reset.
3007         */
3008        snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
3009#ifdef CONFIG_SND_CS46XX_NEW_DSP
3010        snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3011#endif
3012        udelay(50);
3013        snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3014#ifdef CONFIG_SND_CS46XX_NEW_DSP
3015        snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3016#endif
3017    
3018        /*
3019         *  The first thing we do here is to enable sync generation.  As soon
3020         *  as we start receiving bit clock, we'll start producing the SYNC
3021         *  signal.
3022         */
3023        snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3024#ifdef CONFIG_SND_CS46XX_NEW_DSP
3025        snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3026#endif
3027
3028        /*
3029         *  Now wait for a short while to allow the AC97 part to start
3030         *  generating bit clock (so we don't try to start the PLL without an
3031         *  input clock).
3032         */
3033        mdelay(10);
3034
3035        /*
3036         *  Set the serial port timing configuration, so that
3037         *  the clock control circuit gets its clock from the correct place.
3038         */
3039        snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3040
3041        /*
3042         *  Write the selected clock control setup to the hardware.  Do not turn on
3043         *  SWCE yet (if requested), so that the devices clocked by the output of
3044         *  PLL are not clocked until the PLL is stable.
3045         */
3046        snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3047        snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3048        snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3049
3050        /*
3051         *  Power up the PLL.
3052         */
3053        snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3054
3055        /*
3056         *  Wait until the PLL has stabilized.
3057         */
3058        msleep(100);
3059
3060        /*
3061         *  Turn on clocking of the core so that we can setup the serial ports.
3062         */
3063        snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3064
3065        /*
3066         * Enable FIFO  Host Bypass
3067         */
3068        snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3069
3070        /*
3071         *  Fill the serial port FIFOs with silence.
3072         */
3073        snd_cs46xx_clear_serial_FIFOs(chip);
3074
3075        /*
3076         *  Set the serial port FIFO pointer to the first sample in the FIFO.
3077         */
3078        /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3079
3080        /*
3081         *  Write the serial port configuration to the part.  The master
3082         *  enable bit is not set until all other values have been written.
3083         */
3084        snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3085        snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3086        snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3087
3088
3089#ifdef CONFIG_SND_CS46XX_NEW_DSP
3090        snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3091        snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3092        snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3093        snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3094        snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3095#endif
3096
3097        mdelay(5);
3098
3099
3100        /*
3101         * Wait for the codec ready signal from the AC97 codec.
3102         */
3103        timeout = 150;
3104        while (timeout-- > 0) {
3105                /*
3106                 *  Read the AC97 status register to see if we've seen a CODEC READY
3107                 *  signal from the AC97 codec.
3108                 */
3109                if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3110                        goto ok1;
3111                msleep(10);
3112        }
3113
3114
3115        dev_err(chip->card->dev,
3116                "create - never read codec ready from AC'97\n");
3117        dev_err(chip->card->dev,
3118                "it is not probably bug, try to use CS4236 driver\n");
3119        return -EIO;
3120 ok1:
3121#ifdef CONFIG_SND_CS46XX_NEW_DSP
3122        {
3123                int count;
3124                for (count = 0; count < 150; count++) {
3125                        /* First, we want to wait for a short time. */
3126                        udelay(25);
3127        
3128                        if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3129                                break;
3130                }
3131
3132                /*
3133                 *  Make sure CODEC is READY.
3134                 */
3135                if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3136                        dev_dbg(chip->card->dev,
3137                                "never read card ready from secondary AC'97\n");
3138        }
3139#endif
3140
3141        /*
3142         *  Assert the vaid frame signal so that we can start sending commands
3143         *  to the AC97 codec.
3144         */
3145        snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3146#ifdef CONFIG_SND_CS46XX_NEW_DSP
3147        snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3148#endif
3149
3150
3151        /*
3152         *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
3153         *  the codec is pumping ADC data across the AC-link.
3154         */
3155        timeout = 150;
3156        while (timeout-- > 0) {
3157                /*
3158                 *  Read the input slot valid register and see if input slots 3 and
3159                 *  4 are valid yet.
3160                 */
3161                if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3162                        goto ok2;
3163                msleep(10);
3164        }
3165
3166#ifndef CONFIG_SND_CS46XX_NEW_DSP
3167        dev_err(chip->card->dev,
3168                "create - never read ISV3 & ISV4 from AC'97\n");
3169        return -EIO;
3170#else
3171        /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3172           Reloading the driver may help, if there's other soundcards 
3173           with the same problem I would like to know. (Benny) */
3174
3175        dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3176        dev_err(chip->card->dev,
3177                "Try reloading the ALSA driver, if you find something\n");
3178        dev_err(chip->card->dev,
3179                "broken or not working on your soundcard upon\n");
3180        dev_err(chip->card->dev,
3181                "this message please report to alsa-devel@alsa-project.org\n");
3182
3183        return -EIO;
3184#endif
3185 ok2:
3186
3187        /*
3188         *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
3189         *  commense the transfer of digital audio data to the AC97 codec.
3190         */
3191
3192        snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3193
3194
3195        /*
3196         *  Power down the DAC and ADC.  We will power them up (if) when we need
3197         *  them.
3198         */
3199        /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3200
3201        /*
3202         *  Turn off the Processor by turning off the software clock enable flag in 
3203         *  the clock control register.
3204         */
3205        /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3206        /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3207
3208        return 0;
3209}
3210
3211/*
3212 *  start and load DSP 
3213 */
3214
3215static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3216{
3217        unsigned int tmp;
3218
3219        snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3220        
3221        tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3222        tmp &= ~0x0000f03f;
3223        snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt enable */
3224
3225        tmp = snd_cs46xx_peek(chip, BA1_CIE);
3226        tmp &= ~0x0000003f;
3227        tmp |=  0x00000001;
3228        snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt enable */
3229}
3230
3231int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3232{       
3233        unsigned int tmp;
3234#ifdef CONFIG_SND_CS46XX_NEW_DSP
3235        int i;
3236#endif
3237        int err;
3238
3239        /*
3240         *  Reset the processor.
3241         */
3242        snd_cs46xx_reset(chip);
3243        /*
3244         *  Download the image to the processor.
3245         */
3246#ifdef CONFIG_SND_CS46XX_NEW_DSP
3247        for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3248                err = load_firmware(chip, &chip->modules[i], module_names[i]);
3249                if (err < 0) {
3250                        dev_err(chip->card->dev, "firmware load error [%s]\n",
3251                                   module_names[i]);
3252                        return err;
3253                }
3254                err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3255                if (err < 0) {
3256                        dev_err(chip->card->dev, "image download error [%s]\n",
3257                                   module_names[i]);
3258                        return err;
3259                }
3260        }
3261
3262        if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3263                return -EIO;
3264#else
3265        err = load_firmware(chip);
3266        if (err < 0)
3267                return err;
3268
3269        /* old image */
3270        err = snd_cs46xx_download_image(chip);
3271        if (err < 0) {
3272                dev_err(chip->card->dev, "image download error\n");
3273                return err;
3274        }
3275
3276        /*
3277         *  Stop playback DMA.
3278         */
3279        tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3280        chip->play_ctl = tmp & 0xffff0000;
3281        snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3282#endif
3283
3284        /*
3285         *  Stop capture DMA.
3286         */
3287        tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3288        chip->capt.ctl = tmp & 0x0000ffff;
3289        snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3290
3291        mdelay(5);
3292
3293        snd_cs46xx_set_play_sample_rate(chip, 8000);
3294        snd_cs46xx_set_capture_sample_rate(chip, 8000);
3295
3296        snd_cs46xx_proc_start(chip);
3297
3298        cs46xx_enable_stream_irqs(chip);
3299        
3300#ifndef CONFIG_SND_CS46XX_NEW_DSP
3301        /* set the attenuation to 0dB */ 
3302        snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3303        snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3304#endif
3305
3306        return 0;
3307}
3308
3309
3310/*
3311 *      AMP control - null AMP
3312 */
3313 
3314static void amp_none(struct snd_cs46xx *chip, int change)
3315{       
3316}
3317
3318#ifdef CONFIG_SND_CS46XX_NEW_DSP
3319static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3320{
3321        
3322        u32 idx, valid_slots,tmp,powerdown = 0;
3323        u16 modem_power,pin_config,logic_type;
3324
3325        dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3326
3327        /*
3328         *  See if the devices are powered down.  If so, we must power them up first
3329         *  or they will not respond.
3330         */
3331        tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3332
3333        if (!(tmp & CLKCR1_SWCE)) {
3334                snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3335                powerdown = 1;
3336        }
3337
3338        /*
3339         * Clear PRA.  The Bonzo chip will be used for GPIO not for modem
3340         * stuff.
3341         */
3342        if(chip->nr_ac97_codecs != 2) {
3343                dev_err(chip->card->dev,
3344                        "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3345                return -EINVAL;
3346        }
3347
3348        modem_power = snd_cs46xx_codec_read (chip, 
3349                                             AC97_EXTENDED_MSTATUS,
3350                                             CS46XX_SECONDARY_CODEC_INDEX);
3351        modem_power &=0xFEFF;
3352
3353        snd_cs46xx_codec_write(chip, 
3354                               AC97_EXTENDED_MSTATUS, modem_power,
3355                               CS46XX_SECONDARY_CODEC_INDEX);
3356
3357        /*
3358         * Set GPIO pin's 7 and 8 so that they are configured for output.
3359         */
3360        pin_config = snd_cs46xx_codec_read (chip, 
3361                                            AC97_GPIO_CFG,
3362                                            CS46XX_SECONDARY_CODEC_INDEX);
3363        pin_config &=0x27F;
3364
3365        snd_cs46xx_codec_write(chip, 
3366                               AC97_GPIO_CFG, pin_config,
3367                               CS46XX_SECONDARY_CODEC_INDEX);
3368    
3369        /*
3370         * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3371         */
3372
3373        logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3374                                           CS46XX_SECONDARY_CODEC_INDEX);
3375        logic_type &=0x27F; 
3376
3377        snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3378                                CS46XX_SECONDARY_CODEC_INDEX);
3379
3380        valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3381        valid_slots |= 0x200;
3382        snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3383
3384        if ( cs46xx_wait_for_fifo(chip,1) ) {
3385                dev_dbg(chip->card->dev, "FIFO is busy\n");
3386          
3387          return -EINVAL;
3388        }
3389
3390        /*
3391         * Fill slots 12 with the correct value for the GPIO pins. 
3392         */
3393        for(idx = 0x90; idx <= 0x9F; idx++) {
3394                /*
3395                 * Initialize the fifo so that bits 7 and 8 are on.
3396                 *
3397                 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3398                 * the left.  0x1800 corresponds to bits 7 and 8.
3399                 */
3400                snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3401
3402                /*
3403                 * Wait for command to complete
3404                 */
3405                if ( cs46xx_wait_for_fifo(chip,200) ) {
3406                        dev_dbg(chip->card->dev,
3407                                "failed waiting for FIFO at addr (%02X)\n",
3408                                idx);
3409
3410                        return -EINVAL;
3411                }
3412            
3413                /*
3414                 * Write the serial port FIFO index.
3415                 */
3416                snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3417      
3418                /*
3419                 * Tell the serial port to load the new value into the FIFO location.
3420                 */
3421                snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3422        }
3423
3424        /* wait for last command to complete */
3425        cs46xx_wait_for_fifo(chip,200);
3426
3427        /*
3428         *  Now, if we powered up the devices, then power them back down again.
3429         *  This is kinda ugly, but should never happen.
3430         */
3431        if (powerdown)
3432                snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3433
3434        return 0;
3435}
3436#endif
3437
3438/*
3439 *      Crystal EAPD mode
3440 */
3441 
3442static void amp_voyetra(struct snd_cs46xx *chip, int change)
3443{
3444        /* Manage the EAPD bit on the Crystal 4297 
3445           and the Analog AD1885 */
3446           
3447#ifdef CONFIG_SND_CS46XX_NEW_DSP
3448        int old = chip->amplifier;
3449#endif
3450        int oval, val;
3451        
3452        chip->amplifier += change;
3453        oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3454                                     CS46XX_PRIMARY_CODEC_INDEX);
3455        val = oval;
3456        if (chip->amplifier) {
3457                /* Turn the EAPD amp on */
3458                val |= 0x8000;
3459        } else {
3460                /* Turn the EAPD amp off */
3461                val &= ~0x8000;
3462        }
3463        if (val != oval) {
3464                snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3465                                       CS46XX_PRIMARY_CODEC_INDEX);
3466                if (chip->eapd_switch)
3467                        snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3468                                       &chip->eapd_switch->id);
3469        }
3470
3471#ifdef CONFIG_SND_CS46XX_NEW_DSP
3472        if (chip->amplifier && !old) {
3473                voyetra_setup_eapd_slot(chip);
3474        }
3475#endif
3476}
3477
3478static void hercules_init(struct snd_cs46xx *chip) 
3479{
3480        /* default: AMP off, and SPDIF input optical */
3481        snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3482        snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3483}
3484
3485
3486/*
3487 *      Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3488 */ 
3489static void amp_hercules(struct snd_cs46xx *chip, int change)
3490{
3491        int old = chip->amplifier;
3492        int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3493        int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3494
3495        chip->amplifier += change;
3496        if (chip->amplifier && !old) {
3497                dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3498
3499                snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 
3500                                   EGPIODR_GPOE2 | val1);     /* enable EGPIO2 output */
3501                snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 
3502                                   EGPIOPTR_GPPT2 | val2);   /* open-drain on output */
3503        } else if (old && !chip->amplifier) {
3504                dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3505                snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE2); /* disable */
3506                snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3507        }
3508}
3509
3510static void voyetra_mixer_init (struct snd_cs46xx *chip)
3511{
3512        dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3513
3514        /* Enable SPDIF out */
3515        snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3516        snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3517}
3518
3519static void hercules_mixer_init (struct snd_cs46xx *chip)
3520{
3521#ifdef CONFIG_SND_CS46XX_NEW_DSP
3522        unsigned int idx;
3523        int err;
3524        struct snd_card *card = chip->card;
3525#endif
3526
3527        /* set EGPIO to default */
3528        hercules_init(chip);
3529
3530        dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3531
3532#ifdef CONFIG_SND_CS46XX_NEW_DSP
3533        if (chip->in_suspend)
3534                return;
3535
3536        for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3537                struct snd_kcontrol *kctl;
3538
3539                kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3540                err = snd_ctl_add(card, kctl);
3541                if (err < 0) {
3542                        dev_err(card->dev,
3543                                "failed to initialize Hercules mixer (%d)\n",
3544                                err);
3545                        break;
3546                }
3547        }
3548#endif
3549}
3550
3551
3552#if 0
3553/*
3554 *      Untested
3555 */
3556 
3557static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3558{
3559        chip->amplifier += change;
3560
3561        if (chip->amplifier) {
3562                /* Switch the GPIO pins 7 and 8 to open drain */
3563                snd_cs46xx_codec_write(chip, 0x4C,
3564                                       snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3565                snd_cs46xx_codec_write(chip, 0x4E,
3566                                       snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3567                /* Now wake the AMP (this might be backwards) */
3568                snd_cs46xx_codec_write(chip, 0x54,
3569                                       snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3570        } else {
3571                snd_cs46xx_codec_write(chip, 0x54,
3572                                       snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3573        }
3574}
3575#endif
3576
3577
3578/*
3579 *      Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3580 *      whenever we need to beat on the chip.
3581 *
3582 *      The original idea and code for this hack comes from David Kaiser at
3583 *      Linuxcare. Perhaps one day Crystal will document their chips well
3584 *      enough to make them useful.
3585 */
3586 
3587static void clkrun_hack(struct snd_cs46xx *chip, int change)
3588{
3589        u16 control, nval;
3590        
3591        if (!chip->acpi_port)
3592                return;
3593
3594        chip->amplifier += change;
3595        
3596        /* Read ACPI port */    
3597        nval = control = inw(chip->acpi_port + 0x10);
3598
3599        /* Flip CLKRUN off while running */
3600        if (! chip->amplifier)
3601                nval |= 0x2000;
3602        else
3603                nval &= ~0x2000;
3604        if (nval != control)
3605                outw(nval, chip->acpi_port + 0x10);
3606}
3607
3608        
3609/*
3610 * detect intel piix4
3611 */
3612static void clkrun_init(struct snd_cs46xx *chip)
3613{
3614        struct pci_dev *pdev;
3615        u8 pp;
3616
3617        chip->acpi_port = 0;
3618        
3619        pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3620                PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3621        if (pdev == NULL)
3622                return;         /* Not a thinkpad thats for sure */
3623
3624        /* Find the control port */             
3625        pci_read_config_byte(pdev, 0x41, &pp);
3626        chip->acpi_port = pp << 8;
3627        pci_dev_put(pdev);
3628}
3629
3630
3631/*
3632 * Card subid table
3633 */
3634 
3635struct cs_card_type
3636{
3637        u16 vendor;
3638        u16 id;
3639        char *name;
3640        void (*init)(struct snd_cs46xx *);
3641        void (*amp)(struct snd_cs46xx *, int);
3642        void (*active)(struct snd_cs46xx *, int);
3643        void (*mixer_init)(struct snd_cs46xx *);
3644};
3645
3646static struct cs_card_type cards[] = {
3647        {
3648                .vendor = 0x1489,
3649                .id = 0x7001,
3650                .name = "Genius Soundmaker 128 value",
3651                /* nothing special */
3652        },
3653        {
3654                .vendor = 0x5053,
3655                .id = 0x3357,
3656                .name = "Voyetra",
3657                .amp = amp_voyetra,
3658                .mixer_init = voyetra_mixer_init,
3659        },
3660        {
3661                .vendor = 0x1071,
3662                .id = 0x6003,
3663                .name = "Mitac MI6020/21",
3664                .amp = amp_voyetra,
3665        },
3666        /* Hercules Game Theatre XP */
3667        {
3668                .vendor = 0x14af, /* Guillemot Corporation */
3669                .id = 0x0050,
3670                .name = "Hercules Game Theatre XP",
3671                .amp = amp_hercules,
3672                .mixer_init = hercules_mixer_init,
3673        },
3674        {
3675                .vendor = 0x1681,
3676                .id = 0x0050,
3677                .name = "Hercules Game Theatre XP",
3678                .amp = amp_hercules,
3679                .mixer_init = hercules_mixer_init,
3680        },
3681        {
3682                .vendor = 0x1681,
3683                .id = 0x0051,
3684                .name = "Hercules Game Theatre XP",
3685                .amp = amp_hercules,
3686                .mixer_init = hercules_mixer_init,
3687
3688        },
3689        {
3690                .vendor = 0x1681,
3691                .id = 0x0052,
3692                .name = "Hercules Game Theatre XP",
3693                .amp = amp_hercules,
3694                .mixer_init = hercules_mixer_init,
3695        },
3696        {
3697                .vendor = 0x1681,
3698                .id = 0x0053,
3699                .name = "Hercules Game Theatre XP",
3700                .amp = amp_hercules,
3701                .mixer_init = hercules_mixer_init,
3702        },
3703        {
3704                .vendor = 0x1681,
3705                .id = 0x0054,
3706                .name = "Hercules Game Theatre XP",
3707                .amp = amp_hercules,
3708                .mixer_init = hercules_mixer_init,
3709        },
3710        /* Herculess Fortissimo */
3711        {
3712                .vendor = 0x1681,
3713                .id = 0xa010,
3714                .name = "Hercules Gamesurround Fortissimo II",
3715        },
3716        {
3717                .vendor = 0x1681,
3718                .id = 0xa011,
3719                .name = "Hercules Gamesurround Fortissimo III 7.1",
3720        },
3721        /* Teratec */
3722        {
3723                .vendor = 0x153b,
3724                .id = 0x112e,
3725                .name = "Terratec DMX XFire 1024",
3726        },
3727        {
3728                .vendor = 0x153b,
3729                .id = 0x1136,
3730                .name = "Terratec SiXPack 5.1",
3731        },
3732        /* Not sure if the 570 needs the clkrun hack */
3733        {
3734                .vendor = PCI_VENDOR_ID_IBM,
3735                .id = 0x0132,
3736                .name = "Thinkpad 570",
3737                .init = clkrun_init,
3738                .active = clkrun_hack,
3739        },
3740        {
3741                .vendor = PCI_VENDOR_ID_IBM,
3742                .id = 0x0153,
3743                .name = "Thinkpad 600X/A20/T20",
3744                .init = clkrun_init,
3745                .active = clkrun_hack,
3746        },
3747        {
3748                .vendor = PCI_VENDOR_ID_IBM,
3749                .id = 0x1010,
3750                .name = "Thinkpad 600E (unsupported)",
3751        },
3752        {} /* terminator */
3753};
3754
3755
3756/*
3757 * APM support
3758 */
3759#ifdef CONFIG_PM_SLEEP
3760static const unsigned int saved_regs[] = {
3761        BA0_ACOSV,
3762        /*BA0_ASER_FADDR,*/
3763        BA0_ASER_MASTER,
3764        BA1_PVOL,
3765        BA1_CVOL,
3766};
3767
3768static int snd_cs46xx_suspend(struct device *dev)
3769{
3770        struct snd_card *card = dev_get_drvdata(dev);
3771        struct snd_cs46xx *chip = card->private_data;
3772        int i, amp_saved;
3773
3774        snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3775        chip->in_suspend = 1;
3776        // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3777        // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3778
3779        snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3780        snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3781
3782        /* save some registers */
3783        for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3784                chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3785
3786        amp_saved = chip->amplifier;
3787        /* turn off amp */
3788        chip->amplifier_ctrl(chip, -chip->amplifier);
3789        snd_cs46xx_hw_stop(chip);
3790        /* disable CLKRUN */
3791        chip->active_ctrl(chip, -chip->amplifier);
3792        chip->amplifier = amp_saved; /* restore the status */
3793        return 0;
3794}
3795
3796static int snd_cs46xx_resume(struct device *dev)
3797{
3798        struct snd_card *card = dev_get_drvdata(dev);
3799        struct snd_cs46xx *chip = card->private_data;
3800        int amp_saved;
3801#ifdef CONFIG_SND_CS46XX_NEW_DSP
3802        int i;
3803#endif
3804        unsigned int tmp;
3805
3806        amp_saved = chip->amplifier;
3807        chip->amplifier = 0;
3808        chip->active_ctrl(chip, 1); /* force to on */
3809
3810        snd_cs46xx_chip_init(chip);
3811
3812        snd_cs46xx_reset(chip);
3813#ifdef CONFIG_SND_CS46XX_NEW_DSP
3814        cs46xx_dsp_resume(chip);
3815        /* restore some registers */
3816        for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3817                snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3818#else
3819        snd_cs46xx_download_image(chip);
3820#endif
3821
3822#if 0
3823        snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE, 
3824                               chip->ac97_general_purpose);
3825        snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL, 
3826                               chip->ac97_powerdown);
3827        mdelay(10);
3828        snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3829                               chip->ac97_powerdown);
3830        mdelay(5);
3831#endif
3832
3833        snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3834        snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3835
3836        /*
3837         *  Stop capture DMA.
3838         */
3839        tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3840        chip->capt.ctl = tmp & 0x0000ffff;
3841        snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3842
3843        mdelay(5);
3844
3845        /* reset playback/capture */
3846        snd_cs46xx_set_play_sample_rate(chip, 8000);
3847        snd_cs46xx_set_capture_sample_rate(chip, 8000);
3848        snd_cs46xx_proc_start(chip);
3849
3850        cs46xx_enable_stream_irqs(chip);
3851
3852        if (amp_saved)
3853                chip->amplifier_ctrl(chip, 1); /* turn amp on */
3854        else
3855                chip->active_ctrl(chip, -1); /* disable CLKRUN */
3856        chip->amplifier = amp_saved;
3857        chip->in_suspend = 0;
3858        snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3859        return 0;
3860}
3861
3862SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3863#endif /* CONFIG_PM_SLEEP */
3864
3865
3866/*
3867 */
3868
3869int snd_cs46xx_create(struct snd_card *card,
3870                      struct pci_dev *pci,
3871                      int external_amp, int thinkpad,
3872                      struct snd_cs46xx **rchip)
3873{
3874        struct snd_cs46xx *chip;
3875        int err, idx;
3876        struct snd_cs46xx_region *region;
3877        struct cs_card_type *cp;
3878        u16 ss_card, ss_vendor;
3879        static const struct snd_device_ops ops = {
3880                .dev_free =     snd_cs46xx_dev_free,
3881        };
3882        
3883        *rchip = NULL;
3884
3885        /* enable PCI device */
3886        err = pci_enable_device(pci);
3887        if (err < 0)
3888                return err;
3889
3890        chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3891        if (chip == NULL) {
3892                pci_disable_device(pci);
3893                return -ENOMEM;
3894        }
3895        spin_lock_init(&chip->reg_lock);
3896#ifdef CONFIG_SND_CS46XX_NEW_DSP
3897        mutex_init(&chip->spos_mutex);
3898#endif
3899        chip->card = card;
3900        chip->pci = pci;
3901        chip->irq = -1;
3902        chip->ba0_addr = pci_resource_start(pci, 0);
3903        chip->ba1_addr = pci_resource_start(pci, 1);
3904        if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3905            chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3906                dev_err(chip->card->dev,
3907                        "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3908                           chip->ba0_addr, chip->ba1_addr);
3909                snd_cs46xx_free(chip);
3910                return -ENOMEM;
3911        }
3912
3913        region = &chip->region.name.ba0;
3914        strcpy(region->name, "CS46xx_BA0");
3915        region->base = chip->ba0_addr;
3916        region->size = CS46XX_BA0_SIZE;
3917
3918        region = &chip->region.name.data0;
3919        strcpy(region->name, "CS46xx_BA1_data0");
3920        region->base = chip->ba1_addr + BA1_SP_DMEM0;
3921        region->size = CS46XX_BA1_DATA0_SIZE;
3922
3923        region = &chip->region.name.data1;
3924        strcpy(region->name, "CS46xx_BA1_data1");
3925        region->base = chip->ba1_addr + BA1_SP_DMEM1;
3926        region->size = CS46XX_BA1_DATA1_SIZE;
3927
3928        region = &chip->region.name.pmem;
3929        strcpy(region->name, "CS46xx_BA1_pmem");
3930        region->base = chip->ba1_addr + BA1_SP_PMEM;
3931        region->size = CS46XX_BA1_PRG_SIZE;
3932
3933        region = &chip->region.name.reg;
3934        strcpy(region->name, "CS46xx_BA1_reg");
3935        region->base = chip->ba1_addr + BA1_SP_REG;
3936        region->size = CS46XX_BA1_REG_SIZE;
3937
3938        /* set up amp and clkrun hack */
3939        pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3940        pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3941
3942        for (cp = &cards[0]; cp->name; cp++) {
3943                if (cp->vendor == ss_vendor && cp->id == ss_card) {
3944                        dev_dbg(chip->card->dev, "hack for %s enabled\n",
3945                                cp->name);
3946
3947                        chip->amplifier_ctrl = cp->amp;
3948                        chip->active_ctrl = cp->active;
3949                        chip->mixer_init = cp->mixer_init;
3950
3951                        if (cp->init)
3952                                cp->init(chip);
3953                        break;
3954                }
3955        }
3956
3957        if (external_amp) {
3958                dev_info(chip->card->dev,
3959                         "Crystal EAPD support forced on.\n");
3960                chip->amplifier_ctrl = amp_voyetra;
3961        }
3962
3963        if (thinkpad) {
3964                dev_info(chip->card->dev,
3965                         "Activating CLKRUN hack for Thinkpad.\n");
3966                chip->active_ctrl = clkrun_hack;
3967                clkrun_init(chip);
3968        }
3969        
3970        if (chip->amplifier_ctrl == NULL)
3971                chip->amplifier_ctrl = amp_none;
3972        if (chip->active_ctrl == NULL)
3973                chip->active_ctrl = amp_none;
3974
3975        chip->active_ctrl(chip, 1); /* enable CLKRUN */
3976
3977        pci_set_master(pci);
3978
3979        for (idx = 0; idx < 5; idx++) {
3980                region = &chip->region.idx[idx];
3981                region->resource = request_mem_region(region->base, region->size,
3982                                                      region->name);
3983                if (!region->resource) {
3984                        dev_err(chip->card->dev,
3985                                "unable to request memory region 0x%lx-0x%lx\n",
3986                                   region->base, region->base + region->size - 1);
3987                        snd_cs46xx_free(chip);
3988                        return -EBUSY;
3989                }
3990                region->remap_addr = ioremap(region->base, region->size);
3991                if (region->remap_addr == NULL) {
3992                        dev_err(chip->card->dev,
3993                                "%s ioremap problem\n", region->name);
3994                        snd_cs46xx_free(chip);
3995                        return -ENOMEM;
3996                }
3997        }
3998
3999        if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
4000                        KBUILD_MODNAME, chip)) {
4001                dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
4002                snd_cs46xx_free(chip);
4003                return -EBUSY;
4004        }
4005        chip->irq = pci->irq;
4006        card->sync_irq = chip->irq;
4007
4008#ifdef CONFIG_SND_CS46XX_NEW_DSP
4009        chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
4010        if (chip->dsp_spos_instance == NULL) {
4011                snd_cs46xx_free(chip);
4012                return -ENOMEM;
4013        }
4014#endif
4015
4016        err = snd_cs46xx_chip_init(chip);
4017        if (err < 0) {
4018                snd_cs46xx_free(chip);
4019                return err;
4020        }
4021
4022        err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
4023        if (err < 0) {
4024                snd_cs46xx_free(chip);
4025                return err;
4026        }
4027        
4028        snd_cs46xx_proc_init(card, chip);
4029
4030#ifdef CONFIG_PM_SLEEP
4031        chip->saved_regs = kmalloc_array(ARRAY_SIZE(saved_regs),
4032                                         sizeof(*chip->saved_regs),
4033                                         GFP_KERNEL);
4034        if (!chip->saved_regs) {
4035                snd_cs46xx_free(chip);
4036                return -ENOMEM;
4037        }
4038#endif
4039
4040        chip->active_ctrl(chip, -1); /* disable CLKRUN */
4041
4042        *rchip = chip;
4043        return 0;
4044}
4045
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