linux/drivers/watchdog/imx2_wdt.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Watchdog driver for IMX2 and later processors
   4 *
   5 *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <kernel@pengutronix.de>
   6 *  Copyright (C) 2014 Freescale Semiconductor, Inc.
   7 *
   8 * some parts adapted by similar drivers from Darius Augulis and Vladimir
   9 * Zapolskiy, additional improvements by Wim Van Sebroeck.
  10 *
  11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
  12 *
  13 *                      MX1:            MX2+:
  14 *                      ----            -----
  15 * Registers:           32-bit          16-bit
  16 * Stopable timer:      Yes             No
  17 * Need to enable clk:  No              Yes
  18 * Halt on suspend:     Manual          Can be automatic
  19 */
  20
  21#include <linux/clk.h>
  22#include <linux/delay.h>
  23#include <linux/init.h>
  24#include <linux/interrupt.h>
  25#include <linux/io.h>
  26#include <linux/kernel.h>
  27#include <linux/module.h>
  28#include <linux/moduleparam.h>
  29#include <linux/of_address.h>
  30#include <linux/platform_device.h>
  31#include <linux/regmap.h>
  32#include <linux/watchdog.h>
  33
  34#define DRIVER_NAME "imx2-wdt"
  35
  36#define IMX2_WDT_WCR            0x00            /* Control Register */
  37#define IMX2_WDT_WCR_WT         (0xFF << 8)     /* -> Watchdog Timeout Field */
  38#define IMX2_WDT_WCR_WDA        BIT(5)          /* -> External Reset WDOG_B */
  39#define IMX2_WDT_WCR_SRS        BIT(4)          /* -> Software Reset Signal */
  40#define IMX2_WDT_WCR_WRE        BIT(3)          /* -> WDOG Reset Enable */
  41#define IMX2_WDT_WCR_WDE        BIT(2)          /* -> Watchdog Enable */
  42#define IMX2_WDT_WCR_WDZST      BIT(0)          /* -> Watchdog timer Suspend */
  43
  44#define IMX2_WDT_WSR            0x02            /* Service Register */
  45#define IMX2_WDT_SEQ1           0x5555          /* -> service sequence 1 */
  46#define IMX2_WDT_SEQ2           0xAAAA          /* -> service sequence 2 */
  47
  48#define IMX2_WDT_WRSR           0x04            /* Reset Status Register */
  49#define IMX2_WDT_WRSR_TOUT      BIT(1)          /* -> Reset due to Timeout */
  50
  51#define IMX2_WDT_WICR           0x06            /* Interrupt Control Register */
  52#define IMX2_WDT_WICR_WIE       BIT(15)         /* -> Interrupt Enable */
  53#define IMX2_WDT_WICR_WTIS      BIT(14)         /* -> Interrupt Status */
  54#define IMX2_WDT_WICR_WICT      0xFF            /* -> Interrupt Count Timeout */
  55
  56#define IMX2_WDT_WMCR           0x08            /* Misc Register */
  57
  58#define IMX2_WDT_MAX_TIME       128U
  59#define IMX2_WDT_DEFAULT_TIME   60              /* in seconds */
  60
  61#define WDOG_SEC_TO_COUNT(s)    ((s * 2 - 1) << 8)
  62
  63struct imx2_wdt_device {
  64        struct clk *clk;
  65        struct regmap *regmap;
  66        struct watchdog_device wdog;
  67        bool ext_reset;
  68        bool clk_is_on;
  69};
  70
  71static bool nowayout = WATCHDOG_NOWAYOUT;
  72module_param(nowayout, bool, 0);
  73MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  74                                __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  75
  76static unsigned timeout;
  77module_param(timeout, uint, 0);
  78MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
  79                                __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
  80
  81static const struct watchdog_info imx2_wdt_info = {
  82        .identity = "imx2+ watchdog",
  83        .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
  84};
  85
  86static const struct watchdog_info imx2_wdt_pretimeout_info = {
  87        .identity = "imx2+ watchdog",
  88        .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
  89                   WDIOF_PRETIMEOUT,
  90};
  91
  92static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
  93                            void *data)
  94{
  95        struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  96        unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
  97
  98        /* Use internal reset or external - not both */
  99        if (wdev->ext_reset)
 100                wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
 101        else
 102                wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
 103
 104        /* Assert SRS signal */
 105        regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 106        /*
 107         * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
 108         * written twice), we add another two writes to ensure there must be at
 109         * least two writes happen in the same one 32kHz clock period.  We save
 110         * the target check here, since the writes shouldn't be a huge burden
 111         * for other platforms.
 112         */
 113        regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 114        regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 115
 116        /* wait for reset to assert... */
 117        mdelay(500);
 118
 119        return 0;
 120}
 121
 122static inline void imx2_wdt_setup(struct watchdog_device *wdog)
 123{
 124        struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 125        u32 val;
 126
 127        regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 128
 129        /* Suspend timer in low power mode, write once-only */
 130        val |= IMX2_WDT_WCR_WDZST;
 131        /* Strip the old watchdog Time-Out value */
 132        val &= ~IMX2_WDT_WCR_WT;
 133        /* Generate internal chip-level reset if WDOG times out */
 134        if (!wdev->ext_reset)
 135                val &= ~IMX2_WDT_WCR_WRE;
 136        /* Or if external-reset assert WDOG_B reset only on time-out */
 137        else
 138                val |= IMX2_WDT_WCR_WRE;
 139        /* Keep Watchdog Disabled */
 140        val &= ~IMX2_WDT_WCR_WDE;
 141        /* Set the watchdog's Time-Out value */
 142        val |= WDOG_SEC_TO_COUNT(wdog->timeout);
 143
 144        regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 145
 146        /* enable the watchdog */
 147        val |= IMX2_WDT_WCR_WDE;
 148        regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 149}
 150
 151static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
 152{
 153        u32 val;
 154
 155        regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 156
 157        return val & IMX2_WDT_WCR_WDE;
 158}
 159
 160static int imx2_wdt_ping(struct watchdog_device *wdog)
 161{
 162        struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 163
 164        if (!wdev->clk_is_on)
 165                return 0;
 166
 167        regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
 168        regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
 169        return 0;
 170}
 171
 172static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
 173                                   unsigned int new_timeout)
 174{
 175        struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 176
 177        regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
 178                           WDOG_SEC_TO_COUNT(new_timeout));
 179}
 180
 181static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
 182                                unsigned int new_timeout)
 183{
 184        unsigned int actual;
 185
 186        actual = min(new_timeout, IMX2_WDT_MAX_TIME);
 187        __imx2_wdt_set_timeout(wdog, actual);
 188        wdog->timeout = new_timeout;
 189        return 0;
 190}
 191
 192static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
 193                                   unsigned int new_pretimeout)
 194{
 195        struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 196
 197        if (new_pretimeout >= IMX2_WDT_MAX_TIME)
 198                return -EINVAL;
 199
 200        wdog->pretimeout = new_pretimeout;
 201
 202        regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
 203                           IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
 204                           IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
 205        return 0;
 206}
 207
 208static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
 209{
 210        struct watchdog_device *wdog = wdog_arg;
 211        struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 212
 213        regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
 214                          IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
 215
 216        watchdog_notify_pretimeout(wdog);
 217
 218        return IRQ_HANDLED;
 219}
 220
 221static int imx2_wdt_start(struct watchdog_device *wdog)
 222{
 223        struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 224
 225        if (imx2_wdt_is_running(wdev))
 226                imx2_wdt_set_timeout(wdog, wdog->timeout);
 227        else
 228                imx2_wdt_setup(wdog);
 229
 230        set_bit(WDOG_HW_RUNNING, &wdog->status);
 231
 232        return imx2_wdt_ping(wdog);
 233}
 234
 235static const struct watchdog_ops imx2_wdt_ops = {
 236        .owner = THIS_MODULE,
 237        .start = imx2_wdt_start,
 238        .ping = imx2_wdt_ping,
 239        .set_timeout = imx2_wdt_set_timeout,
 240        .set_pretimeout = imx2_wdt_set_pretimeout,
 241        .restart = imx2_wdt_restart,
 242};
 243
 244static const struct regmap_config imx2_wdt_regmap_config = {
 245        .reg_bits = 16,
 246        .reg_stride = 2,
 247        .val_bits = 16,
 248        .max_register = 0x8,
 249};
 250
 251static void imx2_wdt_action(void *data)
 252{
 253        clk_disable_unprepare(data);
 254}
 255
 256static int __init imx2_wdt_probe(struct platform_device *pdev)
 257{
 258        struct device *dev = &pdev->dev;
 259        struct imx2_wdt_device *wdev;
 260        struct watchdog_device *wdog;
 261        void __iomem *base;
 262        int ret;
 263        u32 val;
 264
 265        wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
 266        if (!wdev)
 267                return -ENOMEM;
 268
 269        base = devm_platform_ioremap_resource(pdev, 0);
 270        if (IS_ERR(base))
 271                return PTR_ERR(base);
 272
 273        wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
 274                                                 &imx2_wdt_regmap_config);
 275        if (IS_ERR(wdev->regmap)) {
 276                dev_err(dev, "regmap init failed\n");
 277                return PTR_ERR(wdev->regmap);
 278        }
 279
 280        wdev->clk = devm_clk_get(dev, NULL);
 281        if (IS_ERR(wdev->clk)) {
 282                dev_err(dev, "can't get Watchdog clock\n");
 283                return PTR_ERR(wdev->clk);
 284        }
 285
 286        wdog                    = &wdev->wdog;
 287        wdog->info              = &imx2_wdt_info;
 288        wdog->ops               = &imx2_wdt_ops;
 289        wdog->min_timeout       = 1;
 290        wdog->timeout           = IMX2_WDT_DEFAULT_TIME;
 291        wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
 292        wdog->parent            = dev;
 293
 294        ret = platform_get_irq(pdev, 0);
 295        if (ret > 0)
 296                if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0,
 297                                      dev_name(dev), wdog))
 298                        wdog->info = &imx2_wdt_pretimeout_info;
 299
 300        ret = clk_prepare_enable(wdev->clk);
 301        if (ret)
 302                return ret;
 303
 304        ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);
 305        if (ret)
 306                return ret;
 307
 308        wdev->clk_is_on = true;
 309
 310        regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
 311        wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
 312
 313        wdev->ext_reset = of_property_read_bool(dev->of_node,
 314                                                "fsl,ext-reset-output");
 315        platform_set_drvdata(pdev, wdog);
 316        watchdog_set_drvdata(wdog, wdev);
 317        watchdog_set_nowayout(wdog, nowayout);
 318        watchdog_set_restart_priority(wdog, 128);
 319        watchdog_init_timeout(wdog, timeout, dev);
 320
 321        if (imx2_wdt_is_running(wdev)) {
 322                imx2_wdt_set_timeout(wdog, wdog->timeout);
 323                set_bit(WDOG_HW_RUNNING, &wdog->status);
 324        }
 325
 326        /*
 327         * Disable the watchdog power down counter at boot. Otherwise the power
 328         * down counter will pull down the #WDOG interrupt line for one clock
 329         * cycle.
 330         */
 331        regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
 332
 333        return devm_watchdog_register_device(dev, wdog);
 334}
 335
 336static void imx2_wdt_shutdown(struct platform_device *pdev)
 337{
 338        struct watchdog_device *wdog = platform_get_drvdata(pdev);
 339        struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 340
 341        if (imx2_wdt_is_running(wdev)) {
 342                /*
 343                 * We are running, configure max timeout before reboot
 344                 * will take place.
 345                 */
 346                imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 347                imx2_wdt_ping(wdog);
 348                dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
 349        }
 350}
 351
 352/* Disable watchdog if it is active or non-active but still running */
 353static int __maybe_unused imx2_wdt_suspend(struct device *dev)
 354{
 355        struct watchdog_device *wdog = dev_get_drvdata(dev);
 356        struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 357
 358        /* The watchdog IP block is running */
 359        if (imx2_wdt_is_running(wdev)) {
 360                /*
 361                 * Don't update wdog->timeout, we'll restore the current value
 362                 * during resume.
 363                 */
 364                __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 365                imx2_wdt_ping(wdog);
 366        }
 367
 368        clk_disable_unprepare(wdev->clk);
 369
 370        wdev->clk_is_on = false;
 371
 372        return 0;
 373}
 374
 375/* Enable watchdog and configure it if necessary */
 376static int __maybe_unused imx2_wdt_resume(struct device *dev)
 377{
 378        struct watchdog_device *wdog = dev_get_drvdata(dev);
 379        struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 380        int ret;
 381
 382        ret = clk_prepare_enable(wdev->clk);
 383        if (ret)
 384                return ret;
 385
 386        wdev->clk_is_on = true;
 387
 388        if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
 389                /*
 390                 * If the watchdog is still active and resumes
 391                 * from deep sleep state, need to restart the
 392                 * watchdog again.
 393                 */
 394                imx2_wdt_setup(wdog);
 395        }
 396        if (imx2_wdt_is_running(wdev)) {
 397                imx2_wdt_set_timeout(wdog, wdog->timeout);
 398                imx2_wdt_ping(wdog);
 399        }
 400
 401        return 0;
 402}
 403
 404static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
 405                         imx2_wdt_resume);
 406
 407static const struct of_device_id imx2_wdt_dt_ids[] = {
 408        { .compatible = "fsl,imx21-wdt", },
 409        { /* sentinel */ }
 410};
 411MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
 412
 413static struct platform_driver imx2_wdt_driver = {
 414        .shutdown       = imx2_wdt_shutdown,
 415        .driver         = {
 416                .name   = DRIVER_NAME,
 417                .pm     = &imx2_wdt_pm_ops,
 418                .of_match_table = imx2_wdt_dt_ids,
 419        },
 420};
 421
 422module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
 423
 424MODULE_AUTHOR("Wolfram Sang");
 425MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
 426MODULE_LICENSE("GPL v2");
 427MODULE_ALIAS("platform:" DRIVER_NAME);
 428