linux/drivers/scsi/lpfc/lpfc_hw.h
<<
>>
Prefs
   1/*******************************************************************
   2 * This file is part of the Emulex Linux Device Driver for         *
   3 * Fibre Channel Host Bus Adapters.                                *
   4 * Copyright (C) 2017-2020 Broadcom. All Rights Reserved. The term *
   5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.     *
   6 * Copyright (C) 2004-2016 Emulex.  All rights reserved.           *
   7 * EMULEX and SLI are trademarks of Emulex.                        *
   8 * www.broadcom.com                                                *
   9 *                                                                 *
  10 * This program is free software; you can redistribute it and/or   *
  11 * modify it under the terms of version 2 of the GNU General       *
  12 * Public License as published by the Free Software Foundation.    *
  13 * This program is distributed in the hope that it will be useful. *
  14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  18 * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  19 * more details, a copy of which can be found in the file COPYING  *
  20 * included with this package.                                     *
  21 *******************************************************************/
  22
  23#define FDMI_DID        0xfffffaU
  24#define NameServer_DID  0xfffffcU
  25#define Fabric_Cntl_DID 0xfffffdU
  26#define Fabric_DID      0xfffffeU
  27#define Bcast_DID       0xffffffU
  28#define Mask_DID        0xffffffU
  29#define CT_DID_MASK     0xffff00U
  30#define Fabric_DID_MASK 0xfff000U
  31#define WELL_KNOWN_DID_MASK 0xfffff0U
  32
  33#define PT2PT_LocalID   1
  34#define PT2PT_RemoteID  2
  35
  36#define FF_DEF_EDTOV          2000      /* Default E_D_TOV (2000ms) */
  37#define FF_DEF_ALTOV            15      /* Default AL_TIME (15ms) */
  38#define FF_DEF_RATOV            10      /* Default RA_TOV (10s) */
  39#define FF_DEF_ARBTOV         1900      /* Default ARB_TOV (1900ms) */
  40
  41#define LPFC_BUF_RING0        64        /* Number of buffers to post to RING
  42                                           0 */
  43
  44#define FCELSSIZE             1024      /* maximum ELS transfer size */
  45
  46#define LPFC_FCP_RING            0      /* ring 0 for FCP initiator commands */
  47#define LPFC_EXTRA_RING          1      /* ring 1 for other protocols */
  48#define LPFC_ELS_RING            2      /* ring 2 for ELS commands */
  49
  50#define SLI2_IOCB_CMD_R0_ENTRIES    172 /* SLI-2 FCP command ring entries */
  51#define SLI2_IOCB_RSP_R0_ENTRIES    134 /* SLI-2 FCP response ring entries */
  52#define SLI2_IOCB_CMD_R1_ENTRIES      4 /* SLI-2 extra command ring entries */
  53#define SLI2_IOCB_RSP_R1_ENTRIES      4 /* SLI-2 extra response ring entries */
  54#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
  55#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
  56#define SLI2_IOCB_CMD_R2_ENTRIES     20 /* SLI-2 ELS command ring entries */
  57#define SLI2_IOCB_RSP_R2_ENTRIES     20 /* SLI-2 ELS response ring entries */
  58#define SLI2_IOCB_CMD_R3_ENTRIES      0
  59#define SLI2_IOCB_RSP_R3_ENTRIES      0
  60#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
  61#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
  62
  63#define SLI2_IOCB_CMD_SIZE      32
  64#define SLI2_IOCB_RSP_SIZE      32
  65#define SLI3_IOCB_CMD_SIZE      128
  66#define SLI3_IOCB_RSP_SIZE      64
  67
  68#define LPFC_UNREG_ALL_RPIS_VPORT       0xffff
  69#define LPFC_UNREG_ALL_DFLT_RPIS        0xffffffff
  70
  71/* vendor ID used in SCSI netlink calls */
  72#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
  73
  74#define FW_REV_STR_SIZE 32
  75/* Common Transport structures and definitions */
  76
  77union CtRevisionId {
  78        /* Structure is in Big Endian format */
  79        struct {
  80                uint32_t Revision:8;
  81                uint32_t InId:24;
  82        } bits;
  83        uint32_t word;
  84};
  85
  86union CtCommandResponse {
  87        /* Structure is in Big Endian format */
  88        struct {
  89                uint32_t CmdRsp:16;
  90                uint32_t Size:16;
  91        } bits;
  92        uint32_t word;
  93};
  94
  95/* FC4 Feature bits for RFF_ID */
  96#define FC4_FEATURE_TARGET      0x1
  97#define FC4_FEATURE_INIT        0x2
  98#define FC4_FEATURE_NVME_DISC   0x4
  99
 100struct lpfc_sli_ct_request {
 101        /* Structure is in Big Endian format */
 102        union CtRevisionId RevisionId;
 103        uint8_t FsType;
 104        uint8_t FsSubType;
 105        uint8_t Options;
 106        uint8_t Rsrvd1;
 107        union CtCommandResponse CommandResponse;
 108        uint8_t Rsrvd2;
 109        uint8_t ReasonCode;
 110        uint8_t Explanation;
 111        uint8_t VendorUnique;
 112#define LPFC_CT_PREAMBLE        20      /* Size of CTReq + 4 up to here */
 113
 114        union {
 115                uint32_t PortID;
 116                struct gid {
 117                        uint8_t PortType;       /* for GID_PT requests */
 118#define GID_PT_N_PORT   1
 119                        uint8_t DomainScope;
 120                        uint8_t AreaScope;
 121                        uint8_t Fc4Type;        /* for GID_FT requests */
 122                } gid;
 123                struct gid_ff {
 124                        uint8_t Flags;
 125                        uint8_t DomainScope;
 126                        uint8_t AreaScope;
 127                        uint8_t rsvd1;
 128                        uint8_t rsvd2;
 129                        uint8_t rsvd3;
 130                        uint8_t Fc4FBits;
 131                        uint8_t Fc4Type;
 132                } gid_ff;
 133                struct rft {
 134                        uint32_t PortId;        /* For RFT_ID requests */
 135
 136#ifdef __BIG_ENDIAN_BITFIELD
 137                        uint32_t rsvd0:16;
 138                        uint32_t rsvd1:7;
 139                        uint32_t fcpReg:1;      /* Type 8 */
 140                        uint32_t rsvd2:2;
 141                        uint32_t ipReg:1;       /* Type 5 */
 142                        uint32_t rsvd3:5;
 143#else   /*  __LITTLE_ENDIAN_BITFIELD */
 144                        uint32_t rsvd0:16;
 145                        uint32_t fcpReg:1;      /* Type 8 */
 146                        uint32_t rsvd1:7;
 147                        uint32_t rsvd3:5;
 148                        uint32_t ipReg:1;       /* Type 5 */
 149                        uint32_t rsvd2:2;
 150#endif
 151
 152                        uint32_t rsvd[7];
 153                } rft;
 154                struct rnn {
 155                        uint32_t PortId;        /* For RNN_ID requests */
 156                        uint8_t wwnn[8];
 157                } rnn;
 158                struct rsnn {   /* For RSNN_ID requests */
 159                        uint8_t wwnn[8];
 160                        uint8_t len;
 161                        uint8_t symbname[255];
 162                } rsnn;
 163                struct da_id { /* For DA_ID requests */
 164                        uint32_t port_id;
 165                } da_id;
 166                struct rspn {   /* For RSPN_ID requests */
 167                        uint32_t PortId;
 168                        uint8_t len;
 169                        uint8_t symbname[255];
 170                } rspn;
 171                struct gff {
 172                        uint32_t PortId;
 173                } gff;
 174                struct gff_acc {
 175                        uint8_t fbits[128];
 176                } gff_acc;
 177                struct gft {
 178                        uint32_t PortId;
 179                } gft;
 180                struct gft_acc {
 181                        uint32_t fc4_types[8];
 182                } gft_acc;
 183#define FCP_TYPE_FEATURE_OFFSET 7
 184                struct rff {
 185                        uint32_t PortId;
 186                        uint8_t reserved[2];
 187                        uint8_t fbits;
 188                        uint8_t type_code;     /* type=8 for FCP */
 189                } rff;
 190        } un;
 191};
 192
 193#define LPFC_MAX_CT_SIZE        (60 * 4096)
 194
 195#define  SLI_CT_REVISION        1
 196#define  GID_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 197                           sizeof(struct gid))
 198#define  GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
 199                           sizeof(struct gid_ff))
 200#define  GFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 201                           sizeof(struct gff))
 202#define  GFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 203                           sizeof(struct gft))
 204#define  RFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 205                           sizeof(struct rft))
 206#define  RFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 207                           sizeof(struct rff))
 208#define  RNN_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
 209                           sizeof(struct rnn))
 210#define  RSNN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
 211                           sizeof(struct rsnn))
 212#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
 213                          sizeof(struct da_id))
 214#define  RSPN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
 215                           sizeof(struct rspn))
 216
 217/*
 218 * FsType Definitions
 219 */
 220
 221#define  SLI_CT_MANAGEMENT_SERVICE        0xFA
 222#define  SLI_CT_TIME_SERVICE              0xFB
 223#define  SLI_CT_DIRECTORY_SERVICE         0xFC
 224#define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
 225
 226/*
 227 * Directory Service Subtypes
 228 */
 229
 230#define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
 231
 232/*
 233 * Response Codes
 234 */
 235
 236#define  SLI_CT_RESPONSE_FS_RJT           0x8001
 237#define  SLI_CT_RESPONSE_FS_ACC           0x8002
 238
 239/*
 240 * Reason Codes
 241 */
 242
 243#define  SLI_CT_NO_ADDITIONAL_EXPL        0x0
 244#define  SLI_CT_INVALID_COMMAND           0x01
 245#define  SLI_CT_INVALID_VERSION           0x02
 246#define  SLI_CT_LOGICAL_ERROR             0x03
 247#define  SLI_CT_INVALID_IU_SIZE           0x04
 248#define  SLI_CT_LOGICAL_BUSY              0x05
 249#define  SLI_CT_PROTOCOL_ERROR            0x07
 250#define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
 251#define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
 252#define  SLI_CT_HBA_INFO_NOT_REGISTERED   0x10
 253#define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
 254#define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
 255#define  SLI_CT_HBA_ATTR_NOT_PRESENT      0x13
 256#define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
 257#define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
 258#define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
 259#define  SLI_CT_VENDOR_UNIQUE             0xff
 260
 261/*
 262 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
 263 */
 264
 265#define  SLI_CT_NO_PORT_ID                0x01
 266#define  SLI_CT_NO_PORT_NAME              0x02
 267#define  SLI_CT_NO_NODE_NAME              0x03
 268#define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
 269#define  SLI_CT_NO_IP_ADDRESS             0x05
 270#define  SLI_CT_NO_IPA                    0x06
 271#define  SLI_CT_NO_FC4_TYPES              0x07
 272#define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
 273#define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
 274#define  SLI_CT_NO_PORT_TYPE              0x0A
 275#define  SLI_CT_ACCESS_DENIED             0x10
 276#define  SLI_CT_INVALID_PORT_ID           0x11
 277#define  SLI_CT_DATABASE_EMPTY            0x12
 278#define  SLI_CT_APP_ID_NOT_AVAILABLE      0x40
 279
 280/*
 281 * Name Server Command Codes
 282 */
 283
 284#define  SLI_CTNS_GA_NXT      0x0100
 285#define  SLI_CTNS_GPN_ID      0x0112
 286#define  SLI_CTNS_GNN_ID      0x0113
 287#define  SLI_CTNS_GCS_ID      0x0114
 288#define  SLI_CTNS_GFT_ID      0x0117
 289#define  SLI_CTNS_GSPN_ID     0x0118
 290#define  SLI_CTNS_GPT_ID      0x011A
 291#define  SLI_CTNS_GFF_ID      0x011F
 292#define  SLI_CTNS_GID_PN      0x0121
 293#define  SLI_CTNS_GID_NN      0x0131
 294#define  SLI_CTNS_GIP_NN      0x0135
 295#define  SLI_CTNS_GIPA_NN     0x0136
 296#define  SLI_CTNS_GSNN_NN     0x0139
 297#define  SLI_CTNS_GNN_IP      0x0153
 298#define  SLI_CTNS_GIPA_IP     0x0156
 299#define  SLI_CTNS_GID_FT      0x0171
 300#define  SLI_CTNS_GID_FF      0x01F1
 301#define  SLI_CTNS_GID_PT      0x01A1
 302#define  SLI_CTNS_RPN_ID      0x0212
 303#define  SLI_CTNS_RNN_ID      0x0213
 304#define  SLI_CTNS_RCS_ID      0x0214
 305#define  SLI_CTNS_RFT_ID      0x0217
 306#define  SLI_CTNS_RSPN_ID     0x0218
 307#define  SLI_CTNS_RPT_ID      0x021A
 308#define  SLI_CTNS_RFF_ID      0x021F
 309#define  SLI_CTNS_RIP_NN      0x0235
 310#define  SLI_CTNS_RIPA_NN     0x0236
 311#define  SLI_CTNS_RSNN_NN     0x0239
 312#define  SLI_CTNS_DA_ID       0x0300
 313
 314/*
 315 * Port Types
 316 */
 317
 318#define SLI_CTPT_N_PORT         0x01
 319#define SLI_CTPT_NL_PORT        0x02
 320#define SLI_CTPT_FNL_PORT       0x03
 321#define SLI_CTPT_IP             0x04
 322#define SLI_CTPT_FCP            0x08
 323#define SLI_CTPT_NVME           0x28
 324#define SLI_CTPT_NX_PORT        0x7F
 325#define SLI_CTPT_F_PORT         0x81
 326#define SLI_CTPT_FL_PORT        0x82
 327#define SLI_CTPT_E_PORT         0x84
 328
 329#define SLI_CT_LAST_ENTRY     0x80000000
 330
 331/* Fibre Channel Service Parameter definitions */
 332
 333#define FC_PH_4_0   6           /* FC-PH version 4.0 */
 334#define FC_PH_4_1   7           /* FC-PH version 4.1 */
 335#define FC_PH_4_2   8           /* FC-PH version 4.2 */
 336#define FC_PH_4_3   9           /* FC-PH version 4.3 */
 337
 338#define FC_PH_LOW   8           /* Lowest supported FC-PH version */
 339#define FC_PH_HIGH  9           /* Highest supported FC-PH version */
 340#define FC_PH3   0x20           /* FC-PH-3 version */
 341
 342#define FF_FRAME_SIZE     2048
 343
 344struct lpfc_name {
 345        union {
 346                struct {
 347#ifdef __BIG_ENDIAN_BITFIELD
 348                        uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 349                        uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 350                                                   8:11 of IEEE ext */
 351#else   /*  __LITTLE_ENDIAN_BITFIELD */
 352                        uint8_t IEEEextMsn:4;   /* FC Word 0, bit 24:27, bit
 353                                                   8:11 of IEEE ext */
 354                        uint8_t nameType:4;     /* FC Word 0, bit 28:31 */
 355#endif
 356
 357#define NAME_IEEE           0x1 /* IEEE name - nameType */
 358#define NAME_IEEE_EXT       0x2 /* IEEE extended name */
 359#define NAME_FC_TYPE        0x3 /* FC native name type */
 360#define NAME_IP_TYPE        0x4 /* IP address */
 361#define NAME_CCITT_TYPE     0xC
 362#define NAME_CCITT_GR_TYPE  0xE
 363                        uint8_t IEEEextLsb;     /* FC Word 0, bit 16:23, IEEE
 364                                                   extended Lsb */
 365                        uint8_t IEEE[6];        /* FC IEEE address */
 366                } s;
 367                uint8_t wwn[8];
 368                uint64_t name;
 369        } u;
 370};
 371
 372struct csp {
 373        uint8_t fcphHigh;       /* FC Word 0, byte 0 */
 374        uint8_t fcphLow;
 375        uint8_t bbCreditMsb;
 376        uint8_t bbCreditLsb;    /* FC Word 0, byte 3 */
 377
 378/*
 379 * Word 1 Bit 31 in common service parameter is overloaded.
 380 * Word 1 Bit 31 in FLOGI request is multiple NPort request
 381 * Word 1 Bit 31 in FLOGI response is clean address bit
 382 */
 383#define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
 384/*
 385 * Word 1 Bit 30 in common service parameter is overloaded.
 386 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
 387 * Word 1 Bit 30 in PLOGI request is random offset
 388 */
 389#define virtual_fabric_support randomOffset /* Word 1, bit 30 */
 390/*
 391 * Word 1 Bit 29 in common service parameter is overloaded.
 392 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
 393 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
 394 */
 395#define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
 396#ifdef __BIG_ENDIAN_BITFIELD
 397        uint16_t request_multiple_Nport:1;      /* FC Word 1, bit 31 */
 398        uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 399        uint16_t response_multiple_NPort:1;     /* FC Word 1, bit 29 */
 400        uint16_t fPort:1;       /* FC Word 1, bit 28 */
 401        uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 402        uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 403        uint16_t multicast:1;   /* FC Word 1, bit 25 */
 404        uint16_t app_hdr_support:1;     /* FC Word 1, bit 24 */
 405
 406        uint16_t priority_tagging:1;    /* FC Word 1, bit 23 */
 407        uint16_t simplex:1;     /* FC Word 1, bit 22 */
 408        uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 409        uint16_t dhd:1;         /* FC Word 1, bit 18 */
 410        uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 411        uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 412#else   /*  __LITTLE_ENDIAN_BITFIELD */
 413        uint16_t app_hdr_support:1;     /* FC Word 1, bit 24 */
 414        uint16_t multicast:1;   /* FC Word 1, bit 25 */
 415        uint16_t edtovResolution:1;     /* FC Word 1, bit 26 */
 416        uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
 417        uint16_t fPort:1;       /* FC Word 1, bit 28 */
 418        uint16_t response_multiple_NPort:1;     /* FC Word 1, bit 29 */
 419        uint16_t randomOffset:1;        /* FC Word 1, bit 30 */
 420        uint16_t request_multiple_Nport:1;      /* FC Word 1, bit 31 */
 421
 422        uint16_t payloadlength:1;       /* FC Word 1, bit 16 */
 423        uint16_t contIncSeqCnt:1;       /* FC Word 1, bit 17 */
 424        uint16_t dhd:1;         /* FC Word 1, bit 18 */
 425        uint16_t word1Reserved1:3;      /* FC Word 1, bit 21:19 */
 426        uint16_t simplex:1;     /* FC Word 1, bit 22 */
 427        uint16_t priority_tagging:1;    /* FC Word 1, bit 23 */
 428#endif
 429
 430        uint8_t bbRcvSizeMsb;   /* Upper nibble is reserved */
 431        uint8_t bbRcvSizeLsb;   /* FC Word 1, byte 3 */
 432        union {
 433                struct {
 434                        uint8_t word2Reserved1; /* FC Word 2 byte 0 */
 435
 436                        uint8_t totalConcurrSeq;        /* FC Word 2 byte 1 */
 437                        uint8_t roByCategoryMsb;        /* FC Word 2 byte 2 */
 438
 439                        uint8_t roByCategoryLsb;        /* FC Word 2 byte 3 */
 440                } nPort;
 441                uint32_t r_a_tov;       /* R_A_TOV must be in B.E. format */
 442        } w2;
 443
 444        uint32_t e_d_tov;       /* E_D_TOV must be in B.E. format */
 445};
 446
 447struct class_parms {
 448#ifdef __BIG_ENDIAN_BITFIELD
 449        uint8_t classValid:1;   /* FC Word 0, bit 31 */
 450        uint8_t intermix:1;     /* FC Word 0, bit 30 */
 451        uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 452        uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 453        uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 454        uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 455#else   /*  __LITTLE_ENDIAN_BITFIELD */
 456        uint8_t word0Reserved1:3;       /* FC Word 0, bit 24:26 */
 457        uint8_t seqDelivery:1;  /* FC Word 0, bit 27 */
 458        uint8_t stackedLockDown:1;      /* FC Word 0, bit 28 */
 459        uint8_t stackedXparent:1;       /* FC Word 0, bit 29 */
 460        uint8_t intermix:1;     /* FC Word 0, bit 30 */
 461        uint8_t classValid:1;   /* FC Word 0, bit 31 */
 462
 463#endif
 464
 465        uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
 466
 467#ifdef __BIG_ENDIAN_BITFIELD
 468        uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 469        uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 470        uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 471        uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 472        uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 473#else   /*  __LITTLE_ENDIAN_BITFIELD */
 474        uint8_t word0Reserved3:2;       /* FC Word 0, bit  8: 9 */
 475        uint8_t iCtlAckNcapable:1;      /* FC Word 0, bit 10 */
 476        uint8_t iCtlAck0capable:1;      /* FC Word 0, bit 11 */
 477        uint8_t iCtlInitialPa:2;        /* FC Word 0, bit 12:13 */
 478        uint8_t iCtlXidReAssgn:2;       /* FC Word 0, Bit 14:15 */
 479#endif
 480
 481        uint8_t word0Reserved4; /* FC Word 0, bit  0: 7 */
 482
 483#ifdef __BIG_ENDIAN_BITFIELD
 484        uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 485        uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 486        uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 487        uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 488        uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 489        uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 490#else   /*  __LITTLE_ENDIAN_BITFIELD */
 491        uint8_t rCtlCatPerSeq:2;        /* FC Word 1, bit 24:25 */
 492        uint8_t word1Reserved1:1;       /* FC Word 1, bit 26 */
 493        uint8_t rCtlErrorPolicy:2;      /* FC Word 1, bit 27:28 */
 494        uint8_t rCtlXidInterlck:1;      /* FC Word 1, bit 29 */
 495        uint8_t rCtlAckNcapable:1;      /* FC Word 1, bit 30 */
 496        uint8_t rCtlAck0capable:1;      /* FC Word 1, bit 31 */
 497#endif
 498
 499        uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
 500        uint8_t rcvDataSizeMsb; /* FC Word 1, bit  8:15 */
 501        uint8_t rcvDataSizeLsb; /* FC Word 1, bit  0: 7 */
 502
 503        uint8_t concurrentSeqMsb;       /* FC Word 2, bit 24:31 */
 504        uint8_t concurrentSeqLsb;       /* FC Word 2, bit 16:23 */
 505        uint8_t EeCreditSeqMsb; /* FC Word 2, bit  8:15 */
 506        uint8_t EeCreditSeqLsb; /* FC Word 2, bit  0: 7 */
 507
 508        uint8_t openSeqPerXchgMsb;      /* FC Word 3, bit 24:31 */
 509        uint8_t openSeqPerXchgLsb;      /* FC Word 3, bit 16:23 */
 510        uint8_t word3Reserved1; /* Fc Word 3, bit  8:15 */
 511        uint8_t word3Reserved2; /* Fc Word 3, bit  0: 7 */
 512};
 513
 514#define FAPWWN_KEY_VENDOR       0x42524344 /*valid vendor version fawwpn key*/
 515
 516struct serv_parm {      /* Structure is in Big Endian format */
 517        struct csp cmn;
 518        struct lpfc_name portName;
 519        struct lpfc_name nodeName;
 520        struct class_parms cls1;
 521        struct class_parms cls2;
 522        struct class_parms cls3;
 523        struct class_parms cls4;
 524        union {
 525                uint8_t vendorVersion[16];
 526                struct {
 527                        uint32_t vid;
 528#define LPFC_VV_EMLX_ID 0x454d4c58      /* EMLX */
 529                        uint32_t flags;
 530#define LPFC_VV_SUPPRESS_RSP    1
 531                } vv;
 532        } un;
 533};
 534
 535/*
 536 * Virtual Fabric Tagging Header
 537 */
 538struct fc_vft_header {
 539         uint32_t word0;
 540#define fc_vft_hdr_r_ctl_SHIFT          24
 541#define fc_vft_hdr_r_ctl_MASK           0xFF
 542#define fc_vft_hdr_r_ctl_WORD           word0
 543#define fc_vft_hdr_ver_SHIFT            22
 544#define fc_vft_hdr_ver_MASK             0x3
 545#define fc_vft_hdr_ver_WORD             word0
 546#define fc_vft_hdr_type_SHIFT           18
 547#define fc_vft_hdr_type_MASK            0xF
 548#define fc_vft_hdr_type_WORD            word0
 549#define fc_vft_hdr_e_SHIFT              16
 550#define fc_vft_hdr_e_MASK               0x1
 551#define fc_vft_hdr_e_WORD               word0
 552#define fc_vft_hdr_priority_SHIFT       13
 553#define fc_vft_hdr_priority_MASK        0x7
 554#define fc_vft_hdr_priority_WORD        word0
 555#define fc_vft_hdr_vf_id_SHIFT          1
 556#define fc_vft_hdr_vf_id_MASK           0xFFF
 557#define fc_vft_hdr_vf_id_WORD           word0
 558        uint32_t word1;
 559#define fc_vft_hdr_hopct_SHIFT          24
 560#define fc_vft_hdr_hopct_MASK           0xFF
 561#define fc_vft_hdr_hopct_WORD           word1
 562};
 563
 564#include <uapi/scsi/fc/fc_els.h>
 565
 566/*
 567 *  Extended Link Service LS_COMMAND codes (Payload Word 0)
 568 */
 569#ifdef __BIG_ENDIAN_BITFIELD
 570#define ELS_CMD_MASK      0xffff0000
 571#define ELS_RSP_MASK      0xff000000
 572#define ELS_CMD_LS_RJT    0x01000000
 573#define ELS_CMD_ACC       0x02000000
 574#define ELS_CMD_PLOGI     0x03000000
 575#define ELS_CMD_FLOGI     0x04000000
 576#define ELS_CMD_LOGO      0x05000000
 577#define ELS_CMD_ABTX      0x06000000
 578#define ELS_CMD_RCS       0x07000000
 579#define ELS_CMD_RES       0x08000000
 580#define ELS_CMD_RSS       0x09000000
 581#define ELS_CMD_RSI       0x0A000000
 582#define ELS_CMD_ESTS      0x0B000000
 583#define ELS_CMD_ESTC      0x0C000000
 584#define ELS_CMD_ADVC      0x0D000000
 585#define ELS_CMD_RTV       0x0E000000
 586#define ELS_CMD_RLS       0x0F000000
 587#define ELS_CMD_ECHO      0x10000000
 588#define ELS_CMD_TEST      0x11000000
 589#define ELS_CMD_RRQ       0x12000000
 590#define ELS_CMD_REC       0x13000000
 591#define ELS_CMD_RDP       0x18000000
 592#define ELS_CMD_RDF       0x19000000
 593#define ELS_CMD_PRLI      0x20100014
 594#define ELS_CMD_NVMEPRLI  0x20140018
 595#define ELS_CMD_PRLO      0x21100014
 596#define ELS_CMD_PRLO_ACC  0x02100014
 597#define ELS_CMD_PDISC     0x50000000
 598#define ELS_CMD_FDISC     0x51000000
 599#define ELS_CMD_ADISC     0x52000000
 600#define ELS_CMD_FARP      0x54000000
 601#define ELS_CMD_FARPR     0x55000000
 602#define ELS_CMD_RPL       0x57000000
 603#define ELS_CMD_FAN       0x60000000
 604#define ELS_CMD_RSCN      0x61040000
 605#define ELS_CMD_RSCN_XMT  0x61040008
 606#define ELS_CMD_SCR       0x62000000
 607#define ELS_CMD_RNID      0x78000000
 608#define ELS_CMD_LIRR      0x7A000000
 609#define ELS_CMD_LCB       0x81000000
 610#define ELS_CMD_FPIN      0x16000000
 611#define ELS_CMD_QFPA      0xB0000000
 612#define ELS_CMD_UVEM      0xB1000000
 613#else   /*  __LITTLE_ENDIAN_BITFIELD */
 614#define ELS_CMD_MASK      0xffff
 615#define ELS_RSP_MASK      0xff
 616#define ELS_CMD_LS_RJT    0x01
 617#define ELS_CMD_ACC       0x02
 618#define ELS_CMD_PLOGI     0x03
 619#define ELS_CMD_FLOGI     0x04
 620#define ELS_CMD_LOGO      0x05
 621#define ELS_CMD_ABTX      0x06
 622#define ELS_CMD_RCS       0x07
 623#define ELS_CMD_RES       0x08
 624#define ELS_CMD_RSS       0x09
 625#define ELS_CMD_RSI       0x0A
 626#define ELS_CMD_ESTS      0x0B
 627#define ELS_CMD_ESTC      0x0C
 628#define ELS_CMD_ADVC      0x0D
 629#define ELS_CMD_RTV       0x0E
 630#define ELS_CMD_RLS       0x0F
 631#define ELS_CMD_ECHO      0x10
 632#define ELS_CMD_TEST      0x11
 633#define ELS_CMD_RRQ       0x12
 634#define ELS_CMD_REC       0x13
 635#define ELS_CMD_RDP       0x18
 636#define ELS_CMD_RDF       0x19
 637#define ELS_CMD_PRLI      0x14001020
 638#define ELS_CMD_NVMEPRLI  0x18001420
 639#define ELS_CMD_PRLO      0x14001021
 640#define ELS_CMD_PRLO_ACC  0x14001002
 641#define ELS_CMD_PDISC     0x50
 642#define ELS_CMD_FDISC     0x51
 643#define ELS_CMD_ADISC     0x52
 644#define ELS_CMD_FARP      0x54
 645#define ELS_CMD_FARPR     0x55
 646#define ELS_CMD_RPL       0x57
 647#define ELS_CMD_FAN       0x60
 648#define ELS_CMD_RSCN      0x0461
 649#define ELS_CMD_RSCN_XMT  0x08000461
 650#define ELS_CMD_SCR       0x62
 651#define ELS_CMD_RNID      0x78
 652#define ELS_CMD_LIRR      0x7A
 653#define ELS_CMD_LCB       0x81
 654#define ELS_CMD_FPIN      ELS_FPIN
 655#define ELS_CMD_QFPA      0xB0
 656#define ELS_CMD_UVEM      0xB1
 657#endif
 658
 659/*
 660 *  LS_RJT Payload Definition
 661 */
 662
 663struct ls_rjt { /* Structure is in Big Endian format */
 664        union {
 665                uint32_t lsRjtError;
 666                struct {
 667                        uint8_t lsRjtRsvd0;     /* FC Word 0, bit 24:31 */
 668
 669                        uint8_t lsRjtRsnCode;   /* FC Word 0, bit 16:23 */
 670                        /* LS_RJT reason codes */
 671#define LSRJT_INVALID_CMD     0x01
 672#define LSRJT_LOGICAL_ERR     0x03
 673#define LSRJT_LOGICAL_BSY     0x05
 674#define LSRJT_PROTOCOL_ERR    0x07
 675#define LSRJT_UNABLE_TPC      0x09      /* Unable to perform command */
 676#define LSRJT_CMD_UNSUPPORTED 0x0B
 677#define LSRJT_VENDOR_UNIQUE   0xFF      /* See Byte 3 */
 678
 679                        uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
 680                        /* LS_RJT reason explanation */
 681#define LSEXP_NOTHING_MORE      0x00
 682#define LSEXP_SPARM_OPTIONS     0x01
 683#define LSEXP_SPARM_ICTL        0x03
 684#define LSEXP_SPARM_RCTL        0x05
 685#define LSEXP_SPARM_RCV_SIZE    0x07
 686#define LSEXP_SPARM_CONCUR_SEQ  0x09
 687#define LSEXP_SPARM_CREDIT      0x0B
 688#define LSEXP_INVALID_PNAME     0x0D
 689#define LSEXP_INVALID_NNAME     0x0E
 690#define LSEXP_INVALID_CSP       0x0F
 691#define LSEXP_INVALID_ASSOC_HDR 0x11
 692#define LSEXP_ASSOC_HDR_REQ     0x13
 693#define LSEXP_INVALID_O_SID     0x15
 694#define LSEXP_INVALID_OX_RX     0x17
 695#define LSEXP_CMD_IN_PROGRESS   0x19
 696#define LSEXP_PORT_LOGIN_REQ    0x1E
 697#define LSEXP_INVALID_NPORT_ID  0x1F
 698#define LSEXP_INVALID_SEQ_ID    0x21
 699#define LSEXP_INVALID_XCHG      0x23
 700#define LSEXP_INACTIVE_XCHG     0x25
 701#define LSEXP_RQ_REQUIRED       0x27
 702#define LSEXP_OUT_OF_RESOURCE   0x29
 703#define LSEXP_CANT_GIVE_DATA    0x2A
 704#define LSEXP_REQ_UNSUPPORTED   0x2C
 705                        uint8_t vendorUnique;   /* FC Word 0, bit  0: 7 */
 706                } b;
 707        } un;
 708};
 709
 710/*
 711 *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
 712 */
 713
 714typedef struct _LOGO {          /* Structure is in Big Endian format */
 715        union {
 716                uint32_t nPortId32;     /* Access nPortId as a word */
 717                struct {
 718                        uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
 719                        uint8_t nPortIdByte0;   /* N_port  ID bit 16:23 */
 720                        uint8_t nPortIdByte1;   /* N_port  ID bit  8:15 */
 721                        uint8_t nPortIdByte2;   /* N_port  ID bit  0: 7 */
 722                } b;
 723        } un;
 724        struct lpfc_name portName;      /* N_port name field */
 725} LOGO;
 726
 727/*
 728 *  FCP Login (PRLI Request / ACC) Payload Definition
 729 */
 730
 731#define PRLX_PAGE_LEN   0x10
 732#define TPRLO_PAGE_LEN  0x14
 733
 734typedef struct _PRLI {          /* Structure is in Big Endian format */
 735        uint8_t prliType;       /* FC Parm Word 0, bit 24:31 */
 736
 737#define PRLI_FCP_TYPE 0x08
 738#define PRLI_NVME_TYPE 0x28
 739        uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 740
 741#ifdef __BIG_ENDIAN_BITFIELD
 742        uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 743        uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 744        uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 745
 746        /*    ACC = imagePairEstablished */
 747        uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 748        uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 749#else   /*  __LITTLE_ENDIAN_BITFIELD */
 750        uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 751        uint8_t word0Reserved2:1;       /* FC Parm Word 0, bit 12 */
 752        uint8_t estabImagePair:1;       /* FC Parm Word 0, bit 13 */
 753        uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 754        uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 755        /*    ACC = imagePairEstablished */
 756#endif
 757
 758#define PRLI_REQ_EXECUTED     0x1       /* acceptRspCode */
 759#define PRLI_NO_RESOURCES     0x2
 760#define PRLI_INIT_INCOMPLETE  0x3
 761#define PRLI_NO_SUCH_PA       0x4
 762#define PRLI_PREDEF_CONFIG    0x5
 763#define PRLI_PARTIAL_SUCCESS  0x6
 764#define PRLI_INVALID_PAGE_CNT 0x7
 765        uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 766
 767        uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 768
 769        uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 770
 771        uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
 772        uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
 773
 774#ifdef __BIG_ENDIAN_BITFIELD
 775        uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 776        uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 777        uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 778        uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 779        uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 780        uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 781        uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 782        uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 783        uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 784        uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 785        uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 786        uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 787        uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 788        uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 789        uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 790        uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 791#else   /*  __LITTLE_ENDIAN_BITFIELD */
 792        uint16_t Retry:1;       /* FC Parm Word 3, bit  8 */
 793        uint16_t TaskRetryIdReq:1;      /* FC Parm Word 3, bit  9 */
 794        uint16_t Word3bit10Resved:1;    /* FC Parm Word 3, bit 10 */
 795        uint16_t Word3bit11Resved:1;    /* FC Parm Word 3, bit 11 */
 796        uint16_t Word3bit12Resved:1;    /* FC Parm Word 3, bit 12 */
 797        uint16_t Word3bit13Resved:1;    /* FC Parm Word 3, bit 13 */
 798        uint16_t Word3bit14Resved:1;    /* FC Parm Word 3, bit 14 */
 799        uint16_t Word3bit15Resved:1;    /* FC Parm Word 3, bit 15 */
 800        uint16_t writeXferRdyDis:1;     /* FC Parm Word 3, bit  0 */
 801        uint16_t readXferRdyDis:1;      /* FC Parm Word 3, bit  1 */
 802        uint16_t dataRspMixEna:1;       /* FC Parm Word 3, bit  2 */
 803        uint16_t cmdDataMixEna:1;       /* FC Parm Word 3, bit  3 */
 804        uint16_t targetFunc:1;  /* FC Parm Word 3, bit  4 */
 805        uint16_t initiatorFunc:1;       /* FC Parm Word 3, bit  5 */
 806        uint16_t dataOverLay:1; /* FC Parm Word 3, bit  6 */
 807        uint16_t ConfmComplAllowed:1;   /* FC Parm Word 3, bit  7 */
 808#endif
 809} PRLI;
 810
 811/*
 812 *  FCP Logout (PRLO Request / ACC) Payload Definition
 813 */
 814
 815typedef struct _PRLO {          /* Structure is in Big Endian format */
 816        uint8_t prloType;       /* FC Parm Word 0, bit 24:31 */
 817
 818#define PRLO_FCP_TYPE  0x08
 819        uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
 820
 821#ifdef __BIG_ENDIAN_BITFIELD
 822        uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 823        uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 824        uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 825        uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 826#else   /*  __LITTLE_ENDIAN_BITFIELD */
 827        uint8_t acceptRspCode:4;        /* FC Parm Word 0, bit 8:11, ACC ONLY */
 828        uint8_t word0Reserved2:2;       /* FC Parm Word 0, bit 12:13 */
 829        uint8_t respProcAssocV:1;       /* FC Parm Word 0, bit 14 */
 830        uint8_t origProcAssocV:1;       /* FC Parm Word 0, bit 15 */
 831#endif
 832
 833#define PRLO_REQ_EXECUTED     0x1       /* acceptRspCode */
 834#define PRLO_NO_SUCH_IMAGE    0x4
 835#define PRLO_INVALID_PAGE_CNT 0x7
 836
 837        uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
 838
 839        uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
 840
 841        uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
 842
 843        uint32_t word3Reserved1;        /* FC Parm Word 3, bit 0:31 */
 844} PRLO;
 845
 846typedef struct _ADISC {         /* Structure is in Big Endian format */
 847        uint32_t hardAL_PA;
 848        struct lpfc_name portName;
 849        struct lpfc_name nodeName;
 850        uint32_t DID;
 851} __packed ADISC;
 852
 853typedef struct _FARP {          /* Structure is in Big Endian format */
 854        uint32_t Mflags:8;
 855        uint32_t Odid:24;
 856#define FARP_NO_ACTION          0       /* FARP information enclosed, no
 857                                           action */
 858#define FARP_MATCH_PORT         0x1     /* Match on Responder Port Name */
 859#define FARP_MATCH_NODE         0x2     /* Match on Responder Node Name */
 860#define FARP_MATCH_IP           0x4     /* Match on IP address, not supported */
 861#define FARP_MATCH_IPV4         0x5     /* Match on IPV4 address, not
 862                                           supported */
 863#define FARP_MATCH_IPV6         0x6     /* Match on IPV6 address, not
 864                                           supported */
 865        uint32_t Rflags:8;
 866        uint32_t Rdid:24;
 867#define FARP_REQUEST_PLOGI      0x1     /* Request for PLOGI */
 868#define FARP_REQUEST_FARPR      0x2     /* Request for FARP Response */
 869        struct lpfc_name OportName;
 870        struct lpfc_name OnodeName;
 871        struct lpfc_name RportName;
 872        struct lpfc_name RnodeName;
 873        uint8_t Oipaddr[16];
 874        uint8_t Ripaddr[16];
 875} FARP;
 876
 877typedef struct _FAN {           /* Structure is in Big Endian format */
 878        uint32_t Fdid;
 879        struct lpfc_name FportName;
 880        struct lpfc_name FnodeName;
 881} __packed FAN;
 882
 883typedef struct _SCR {           /* Structure is in Big Endian format */
 884        uint8_t resvd1;
 885        uint8_t resvd2;
 886        uint8_t resvd3;
 887        uint8_t Function;
 888#define  SCR_FUNC_FABRIC     0x01
 889#define  SCR_FUNC_NPORT      0x02
 890#define  SCR_FUNC_FULL       0x03
 891#define  SCR_CLEAR           0xff
 892} SCR;
 893
 894typedef struct _RNID_TOP_DISC {
 895        struct lpfc_name portName;
 896        uint8_t resvd[8];
 897        uint32_t unitType;
 898#define RNID_HBA            0x7
 899#define RNID_HOST           0xa
 900#define RNID_DRIVER         0xd
 901        uint32_t physPort;
 902        uint32_t attachedNodes;
 903        uint16_t ipVersion;
 904#define RNID_IPV4           0x1
 905#define RNID_IPV6           0x2
 906        uint16_t UDPport;
 907        uint8_t ipAddr[16];
 908        uint16_t resvd1;
 909        uint16_t flags;
 910#define RNID_TD_SUPPORT     0x1
 911#define RNID_LP_VALID       0x2
 912} RNID_TOP_DISC;
 913
 914typedef struct _RNID {          /* Structure is in Big Endian format */
 915        uint8_t Format;
 916#define RNID_TOPOLOGY_DISC  0xdf
 917        uint8_t CommonLen;
 918        uint8_t resvd1;
 919        uint8_t SpecificLen;
 920        struct lpfc_name portName;
 921        struct lpfc_name nodeName;
 922        union {
 923                RNID_TOP_DISC topologyDisc;     /* topology disc (0xdf) */
 924        } un;
 925} __packed RNID;
 926
 927struct RLS {                    /* Structure is in Big Endian format */
 928        uint32_t rls;
 929#define rls_rsvd_SHIFT          24
 930#define rls_rsvd_MASK           0x000000ff
 931#define rls_rsvd_WORD           rls
 932#define rls_did_SHIFT           0
 933#define rls_did_MASK            0x00ffffff
 934#define rls_did_WORD            rls
 935};
 936
 937struct  RLS_RSP {               /* Structure is in Big Endian format */
 938        uint32_t linkFailureCnt;
 939        uint32_t lossSyncCnt;
 940        uint32_t lossSignalCnt;
 941        uint32_t primSeqErrCnt;
 942        uint32_t invalidXmitWord;
 943        uint32_t crcCnt;
 944};
 945
 946struct RRQ {                    /* Structure is in Big Endian format */
 947        uint32_t rrq;
 948#define rrq_rsvd_SHIFT          24
 949#define rrq_rsvd_MASK           0x000000ff
 950#define rrq_rsvd_WORD           rrq
 951#define rrq_did_SHIFT           0
 952#define rrq_did_MASK            0x00ffffff
 953#define rrq_did_WORD            rrq
 954        uint32_t rrq_exchg;
 955#define rrq_oxid_SHIFT          16
 956#define rrq_oxid_MASK           0xffff
 957#define rrq_oxid_WORD           rrq_exchg
 958#define rrq_rxid_SHIFT          0
 959#define rrq_rxid_MASK           0xffff
 960#define rrq_rxid_WORD           rrq_exchg
 961};
 962
 963#define LPFC_MAX_VFN_PER_PFN    255 /* Maximum VFs allowed per ARI */
 964#define LPFC_DEF_VFN_PER_PFN    0   /* Default VFs due to platform limitation*/
 965
 966struct RTV_RSP {                /* Structure is in Big Endian format */
 967        uint32_t ratov;
 968        uint32_t edtov;
 969        uint32_t qtov;
 970#define qtov_rsvd0_SHIFT        28
 971#define qtov_rsvd0_MASK         0x0000000f
 972#define qtov_rsvd0_WORD         qtov            /* reserved */
 973#define qtov_edtovres_SHIFT     27
 974#define qtov_edtovres_MASK      0x00000001
 975#define qtov_edtovres_WORD      qtov            /* E_D_TOV Resolution */
 976#define qtov__rsvd1_SHIFT       19
 977#define qtov_rsvd1_MASK         0x0000003f
 978#define qtov_rsvd1_WORD         qtov            /* reserved */
 979#define qtov_rttov_SHIFT        18
 980#define qtov_rttov_MASK         0x00000001
 981#define qtov_rttov_WORD         qtov            /* R_T_TOV value */
 982#define qtov_rsvd2_SHIFT        0
 983#define qtov_rsvd2_MASK         0x0003ffff
 984#define qtov_rsvd2_WORD         qtov            /* reserved */
 985};
 986
 987
 988typedef struct  _RPL {          /* Structure is in Big Endian format */
 989        uint32_t maxsize;
 990        uint32_t index;
 991} RPL;
 992
 993typedef struct  _PORT_NUM_BLK {
 994        uint32_t portNum;
 995        uint32_t portID;
 996        struct lpfc_name portName;
 997} PORT_NUM_BLK;
 998
 999typedef struct  _RPL_RSP {      /* Structure is in Big Endian format */
1000        uint32_t listLen;
1001        uint32_t index;
1002        PORT_NUM_BLK port_num_blk;
1003} RPL_RSP;
1004
1005/* This is used for RSCN command */
1006typedef struct _D_ID {          /* Structure is in Big Endian format */
1007        union {
1008                uint32_t word;
1009                struct {
1010#ifdef __BIG_ENDIAN_BITFIELD
1011                        uint8_t resv;
1012                        uint8_t domain;
1013                        uint8_t area;
1014                        uint8_t id;
1015#else   /*  __LITTLE_ENDIAN_BITFIELD */
1016                        uint8_t id;
1017                        uint8_t area;
1018                        uint8_t domain;
1019                        uint8_t resv;
1020#endif
1021                } b;
1022        } un;
1023} D_ID;
1024
1025#define RSCN_ADDRESS_FORMAT_PORT        0x0
1026#define RSCN_ADDRESS_FORMAT_AREA        0x1
1027#define RSCN_ADDRESS_FORMAT_DOMAIN      0x2
1028#define RSCN_ADDRESS_FORMAT_FABRIC      0x3
1029#define RSCN_ADDRESS_FORMAT_MASK        0x3
1030
1031/*
1032 *  Structure to define all ELS Payload types
1033 */
1034
1035typedef struct _ELS_PKT {       /* Structure is in Big Endian format */
1036        uint8_t elsCode;        /* FC Word 0, bit 24:31 */
1037        uint8_t elsByte1;
1038        uint8_t elsByte2;
1039        uint8_t elsByte3;
1040        union {
1041                struct ls_rjt lsRjt;    /* Payload for LS_RJT ELS response */
1042                struct serv_parm logi;  /* Payload for PLOGI/FLOGI/PDISC/ACC */
1043                LOGO logo;      /* Payload for PLOGO/FLOGO/ACC */
1044                PRLI prli;      /* Payload for PRLI/ACC */
1045                PRLO prlo;      /* Payload for PRLO/ACC */
1046                ADISC adisc;    /* Payload for ADISC/ACC */
1047                FARP farp;      /* Payload for FARP/ACC */
1048                FAN fan;        /* Payload for FAN */
1049                SCR scr;        /* Payload for SCR/ACC */
1050                RNID rnid;      /* Payload for RNID */
1051                uint8_t pad[128 - 4];   /* Pad out to payload of 128 bytes */
1052        } un;
1053} ELS_PKT;
1054
1055/*
1056 * Link Cable Beacon (LCB) ELS Frame
1057 */
1058
1059struct fc_lcb_request_frame {
1060        uint32_t      lcb_command;      /* ELS command opcode (0x81)     */
1061        uint8_t       lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1062#define LPFC_LCB_ON             0x1
1063#define LPFC_LCB_OFF            0x2
1064        uint8_t       reserved[2];
1065        uint8_t       capability;       /* LCB Payload Word 1, bit 0:7 */
1066        uint8_t       lcb_type; /* LCB Payload Word 2, bit 24:31 */
1067#define LPFC_LCB_GREEN          0x1
1068#define LPFC_LCB_AMBER          0x2
1069        uint8_t       lcb_frequency;    /* LCB Payload Word 2, bit 16:23 */
1070#define LCB_CAPABILITY_DURATION 1
1071#define BEACON_VERSION_V1       1
1072#define BEACON_VERSION_V0       0
1073        uint16_t      lcb_duration;     /* LCB Payload Word 2, bit 15:0  */
1074};
1075
1076/*
1077 * Link Cable Beacon (LCB) ELS Response Frame
1078 */
1079struct fc_lcb_res_frame {
1080        uint32_t      lcb_ls_acc;       /* Acceptance of LCB request (0x02) */
1081        uint8_t       lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1082        uint8_t       reserved[2];
1083        uint8_t       capability;       /* LCB Payload Word 1, bit 0:7 */
1084        uint8_t       lcb_type; /* LCB Payload Word 2, bit 24:31 */
1085        uint8_t       lcb_frequency;    /* LCB Payload Word 2, bit 16:23 */
1086        uint16_t      lcb_duration;     /* LCB Payload Word 2, bit 15:0  */
1087};
1088
1089/*
1090 * Read Diagnostic Parameters (RDP) ELS frame.
1091 */
1092#define SFF_PG0_IDENT_SFP              0x3
1093
1094#define SFP_FLAG_PT_OPTICAL            0x0
1095#define SFP_FLAG_PT_SWLASER            0x01
1096#define SFP_FLAG_PT_LWLASER_LC1310     0x02
1097#define SFP_FLAG_PT_LWLASER_LL1550     0x03
1098#define SFP_FLAG_PT_MASK               0x0F
1099#define SFP_FLAG_PT_SHIFT              0
1100
1101#define SFP_FLAG_IS_OPTICAL_PORT       0x01
1102#define SFP_FLAG_IS_OPTICAL_MASK       0x010
1103#define SFP_FLAG_IS_OPTICAL_SHIFT      4
1104
1105#define SFP_FLAG_IS_DESC_VALID         0x01
1106#define SFP_FLAG_IS_DESC_VALID_MASK    0x020
1107#define SFP_FLAG_IS_DESC_VALID_SHIFT   5
1108
1109#define SFP_FLAG_CT_UNKNOWN            0x0
1110#define SFP_FLAG_CT_SFP_PLUS           0x01
1111#define SFP_FLAG_CT_MASK               0x3C
1112#define SFP_FLAG_CT_SHIFT              6
1113
1114struct fc_rdp_port_name_info {
1115        uint8_t wwnn[8];
1116        uint8_t wwpn[8];
1117};
1118
1119
1120/*
1121 * Link Error Status Block Structure (FC-FS-3) for RDP
1122 * This similar to RPS ELS
1123 */
1124struct fc_link_status {
1125        uint32_t      link_failure_cnt;
1126        uint32_t      loss_of_synch_cnt;
1127        uint32_t      loss_of_signal_cnt;
1128        uint32_t      primitive_seq_proto_err;
1129        uint32_t      invalid_trans_word;
1130        uint32_t      invalid_crc_cnt;
1131
1132};
1133
1134#define RDP_PORT_NAMES_DESC_TAG  0x00010003
1135struct fc_rdp_port_name_desc {
1136        uint32_t        tag;     /* 0001 0003h */
1137        uint32_t        length;  /* set to size of payload struct */
1138        struct fc_rdp_port_name_info  port_names;
1139};
1140
1141
1142struct fc_rdp_fec_info {
1143        uint32_t CorrectedBlocks;
1144        uint32_t UncorrectableBlocks;
1145};
1146
1147#define RDP_FEC_DESC_TAG  0x00010005
1148struct fc_fec_rdp_desc {
1149        uint32_t tag;
1150        uint32_t length;
1151        struct fc_rdp_fec_info info;
1152};
1153
1154struct fc_rdp_link_error_status_payload_info {
1155        struct fc_link_status link_status; /* 24 bytes */
1156        uint32_t  port_type;             /* bits 31-30 only */
1157};
1158
1159#define RDP_LINK_ERROR_STATUS_DESC_TAG  0x00010002
1160struct fc_rdp_link_error_status_desc {
1161        uint32_t         tag;     /* 0001 0002h */
1162        uint32_t         length;  /* set to size of payload struct */
1163        struct fc_rdp_link_error_status_payload_info info;
1164};
1165
1166#define VN_PT_PHY_UNKNOWN      0x00
1167#define VN_PT_PHY_PF_PORT      0x01
1168#define VN_PT_PHY_ETH_MAC      0x10
1169#define VN_PT_PHY_SHIFT                30
1170
1171#define RDP_PS_1GB             0x8000
1172#define RDP_PS_2GB             0x4000
1173#define RDP_PS_4GB             0x2000
1174#define RDP_PS_10GB            0x1000
1175#define RDP_PS_8GB             0x0800
1176#define RDP_PS_16GB            0x0400
1177#define RDP_PS_32GB            0x0200
1178#define RDP_PS_64GB            0x0100
1179#define RDP_PS_128GB           0x0080
1180#define RDP_PS_256GB           0x0040
1181
1182#define RDP_CAP_USER_CONFIGURED 0x0002
1183#define RDP_CAP_UNKNOWN         0x0001
1184#define RDP_PS_UNKNOWN          0x0002
1185#define RDP_PS_NOT_ESTABLISHED  0x0001
1186
1187struct fc_rdp_port_speed {
1188        uint16_t   capabilities;
1189        uint16_t   speed;
1190};
1191
1192struct fc_rdp_port_speed_info {
1193        struct fc_rdp_port_speed   port_speed;
1194};
1195
1196#define RDP_PORT_SPEED_DESC_TAG  0x00010001
1197struct fc_rdp_port_speed_desc {
1198        uint32_t         tag;            /* 00010001h */
1199        uint32_t         length;         /* set to size of payload struct */
1200        struct fc_rdp_port_speed_info info;
1201};
1202
1203#define RDP_NPORT_ID_SIZE      4
1204#define RDP_N_PORT_DESC_TAG    0x00000003
1205struct fc_rdp_nport_desc {
1206        uint32_t         tag;          /* 0000 0003h, big endian */
1207        uint32_t         length;       /* size of RDP_N_PORT_ID struct */
1208        uint32_t         nport_id : 12;
1209        uint32_t         reserved : 8;
1210};
1211
1212
1213struct fc_rdp_link_service_info {
1214        uint32_t         els_req;    /* Request payload word 0 value.*/
1215};
1216
1217#define RDP_LINK_SERVICE_DESC_TAG  0x00000001
1218struct fc_rdp_link_service_desc {
1219        uint32_t         tag;     /* Descriptor tag  1 */
1220        uint32_t         length;  /* set to size of payload struct. */
1221        struct fc_rdp_link_service_info  payload;
1222                                  /* must be ELS req Word 0(0x18) */
1223};
1224
1225struct fc_rdp_sfp_info {
1226        uint16_t        temperature;
1227        uint16_t        vcc;
1228        uint16_t        tx_bias;
1229        uint16_t        tx_power;
1230        uint16_t        rx_power;
1231        uint16_t        flags;
1232};
1233
1234#define RDP_SFP_DESC_TAG  0x00010000
1235struct fc_rdp_sfp_desc {
1236        uint32_t         tag;
1237        uint32_t         length;  /* set to size of sfp_info struct */
1238        struct fc_rdp_sfp_info sfp_info;
1239};
1240
1241/* Buffer Credit Descriptor */
1242struct fc_rdp_bbc_info {
1243        uint32_t              port_bbc; /* FC_Port buffer-to-buffer credit */
1244        uint32_t              attached_port_bbc;
1245        uint32_t              rtt;      /* Round trip time */
1246};
1247#define RDP_BBC_DESC_TAG  0x00010006
1248struct fc_rdp_bbc_desc {
1249        uint32_t              tag;
1250        uint32_t              length;
1251        struct fc_rdp_bbc_info  bbc_info;
1252};
1253
1254/* Optical Element Type Transgression Flags */
1255#define RDP_OET_LOW_WARNING  0x1
1256#define RDP_OET_HIGH_WARNING 0x2
1257#define RDP_OET_LOW_ALARM    0x4
1258#define RDP_OET_HIGH_ALARM   0x8
1259
1260#define RDP_OED_TEMPERATURE  0x1
1261#define RDP_OED_VOLTAGE      0x2
1262#define RDP_OED_TXBIAS       0x3
1263#define RDP_OED_TXPOWER      0x4
1264#define RDP_OED_RXPOWER      0x5
1265
1266#define RDP_OED_TYPE_SHIFT   28
1267/* Optical Element Data descriptor */
1268struct fc_rdp_oed_info {
1269        uint16_t            hi_alarm;
1270        uint16_t            lo_alarm;
1271        uint16_t            hi_warning;
1272        uint16_t            lo_warning;
1273        uint32_t            function_flags;
1274};
1275#define RDP_OED_DESC_TAG  0x00010007
1276struct fc_rdp_oed_sfp_desc {
1277        uint32_t             tag;
1278        uint32_t             length;
1279        struct fc_rdp_oed_info oed_info;
1280};
1281
1282/* Optical Product Data descriptor */
1283struct fc_rdp_opd_sfp_info {
1284        uint8_t            vendor_name[16];
1285        uint8_t            model_number[16];
1286        uint8_t            serial_number[16];
1287        uint8_t            revision[4];
1288        uint8_t            date[8];
1289};
1290
1291#define RDP_OPD_DESC_TAG  0x00010008
1292struct fc_rdp_opd_sfp_desc {
1293        uint32_t             tag;
1294        uint32_t             length;
1295        struct fc_rdp_opd_sfp_info opd_info;
1296};
1297
1298struct fc_rdp_req_frame {
1299        uint32_t         rdp_command;           /* ELS command opcode (0x18)*/
1300        uint32_t         rdp_des_length;        /* RDP Payload Word 1 */
1301        struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1302};
1303
1304
1305struct fc_rdp_res_frame {
1306        uint32_t    reply_sequence;             /* FC word0 LS_ACC or LS_RJT */
1307        uint32_t   length;                      /* FC Word 1      */
1308        struct fc_rdp_link_service_desc link_service_desc;    /* Word 2 -4   */
1309        struct fc_rdp_sfp_desc sfp_desc;                      /* Word 5 -9   */
1310        struct fc_rdp_port_speed_desc portspeed_desc;         /* Word 10 -12 */
1311        struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1312        struct fc_rdp_port_name_desc diag_port_names_desc;    /* Word 22 -27 */
1313        struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1314        struct fc_fec_rdp_desc fec_desc;                      /* FC word 34-37*/
1315        struct fc_rdp_bbc_desc bbc_desc;                      /* FC Word 38-42*/
1316        struct fc_rdp_oed_sfp_desc oed_temp_desc;             /* FC Word 43-47*/
1317        struct fc_rdp_oed_sfp_desc oed_voltage_desc;          /* FC word 48-52*/
1318        struct fc_rdp_oed_sfp_desc oed_txbias_desc;           /* FC word 53-57*/
1319        struct fc_rdp_oed_sfp_desc oed_txpower_desc;          /* FC word 58-62*/
1320        struct fc_rdp_oed_sfp_desc oed_rxpower_desc;          /* FC word 63-67*/
1321        struct fc_rdp_opd_sfp_desc opd_desc;                  /* FC word 68-84*/
1322};
1323
1324
1325/* UVEM */
1326
1327#define LPFC_UVEM_SIZE 60
1328#define LPFC_UVEM_VEM_ID_DESC_SIZE 16
1329#define LPFC_UVEM_VE_MAP_DESC_SIZE 20
1330
1331#define VEM_ID_DESC_TAG  0x0001000A
1332struct lpfc_vem_id_desc {
1333        uint32_t tag;
1334        uint32_t length;
1335        uint8_t vem_id[16];
1336};
1337
1338#define LPFC_QFPA_SIZE  4
1339
1340#define INSTANTIATED_VE_DESC_TAG  0x0001000B
1341struct instantiated_ve_desc {
1342        uint32_t tag;
1343        uint32_t length;
1344        uint8_t global_vem_id[16];
1345        uint32_t word6;
1346#define lpfc_instantiated_local_id_SHIFT   0
1347#define lpfc_instantiated_local_id_MASK    0x000000ff
1348#define lpfc_instantiated_local_id_WORD    word6
1349#define lpfc_instantiated_nport_id_SHIFT   8
1350#define lpfc_instantiated_nport_id_MASK    0x00ffffff
1351#define lpfc_instantiated_nport_id_WORD    word6
1352};
1353
1354#define DEINSTANTIATED_VE_DESC_TAG  0x0001000C
1355struct deinstantiated_ve_desc {
1356        uint32_t tag;
1357        uint32_t length;
1358        uint8_t global_vem_id[16];
1359        uint32_t word6;
1360#define lpfc_deinstantiated_nport_id_SHIFT   0
1361#define lpfc_deinstantiated_nport_id_MASK    0x000000ff
1362#define lpfc_deinstantiated_nport_id_WORD    word6
1363#define lpfc_deinstantiated_local_id_SHIFT   24
1364#define lpfc_deinstantiated_local_id_MASK    0x00ffffff
1365#define lpfc_deinstantiated_local_id_WORD    word6
1366};
1367
1368/* Query Fabric Priority Allocation Response */
1369#define LPFC_PRIORITY_RANGE_DESC_SIZE 12
1370
1371struct priority_range_desc {
1372        uint32_t tag;
1373        uint32_t length;
1374        uint8_t lo_range;
1375        uint8_t hi_range;
1376        uint8_t qos_priority;
1377        uint8_t local_ve_id;
1378};
1379
1380struct fc_qfpa_res {
1381        uint32_t reply_sequence;        /* LS_ACC or LS_RJT */
1382        uint32_t length;        /* FC Word 1    */
1383        struct priority_range_desc desc[1];
1384};
1385
1386/* Application Server command code */
1387/* VMID               */
1388
1389#define SLI_CT_APP_SEV_Subtypes     0x20        /* Application Server subtype */
1390
1391#define SLI_CTAS_GAPPIA_ENT    0x0100   /* Get Application Identifier */
1392#define SLI_CTAS_GALLAPPIA     0x0101   /* Get All Application Identifier */
1393#define SLI_CTAS_GALLAPPIA_ID  0x0102   /* Get All Application Identifier */
1394                                        /* for Nport */
1395#define SLI_CTAS_GAPPIA_IDAPP  0x0103   /* Get Application Identifier */
1396                                        /* for Nport */
1397#define SLI_CTAS_RAPP_IDENT    0x0200   /* Register Application Identifier */
1398#define SLI_CTAS_DAPP_IDENT    0x0300   /* Deregister Application */
1399                                        /* Identifier */
1400#define SLI_CTAS_DALLAPP_ID    0x0301   /* Deregister All Application */
1401                                        /* Identifier */
1402
1403struct entity_id_object {
1404        uint8_t entity_id_len;
1405        uint8_t entity_id[255]; /* VM UUID */
1406};
1407
1408struct app_id_object {
1409        uint32_t port_id;
1410        uint32_t app_id;
1411        struct entity_id_object obj;
1412};
1413
1414struct lpfc_vmid_rapp_ident_list {
1415        uint32_t no_of_objects;
1416        struct entity_id_object obj[1];
1417};
1418
1419struct lpfc_vmid_dapp_ident_list {
1420        uint32_t no_of_objects;
1421        struct entity_id_object obj[1];
1422};
1423
1424#define GALLAPPIA_ID_LAST  0x80
1425struct lpfc_vmid_gallapp_ident_list {
1426        uint8_t control;
1427        uint8_t reserved[3];
1428        struct app_id_object app_id;
1429};
1430
1431#define RAPP_IDENT_OFFSET  (offsetof(struct lpfc_sli_ct_request, un) + 4)
1432#define DAPP_IDENT_OFFSET  (offsetof(struct lpfc_sli_ct_request, un) + 4)
1433#define GALLAPPIA_ID_SIZE  (offsetof(struct lpfc_sli_ct_request, un) + 4)
1434#define DALLAPP_ID_SIZE    (offsetof(struct lpfc_sli_ct_request, un) + 4)
1435
1436/******** FDMI ********/
1437
1438/* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1439#define  SLI_CT_FDMI_Subtypes     0x10  /* Management Service Subtype */
1440
1441/* Definitions for HBA / Port attribute entries */
1442
1443/* Attribute Entry */
1444struct lpfc_fdmi_attr_entry {
1445        union {
1446                uint32_t AttrInt;
1447                uint8_t  AttrTypes[32];
1448                uint8_t  AttrString[256];
1449                struct lpfc_name AttrWWN;
1450        } un;
1451};
1452
1453struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1454        /* Structure is in Big Endian format */
1455        uint32_t AttrType:16;
1456        uint32_t AttrLen:16;
1457        /* Marks start of Value (ATTRIBUTE_ENTRY) */
1458        struct lpfc_fdmi_attr_entry AttrValue;
1459} __packed;
1460
1461/*
1462 * HBA Attribute Block
1463 */
1464struct lpfc_fdmi_attr_block {
1465        uint32_t EntryCnt;              /* Number of HBA attribute entries */
1466        struct lpfc_fdmi_attr_entry Entry;      /* Variable-length array */
1467};
1468
1469/*
1470 * Port Entry
1471 */
1472struct lpfc_fdmi_port_entry {
1473        struct lpfc_name PortName;
1474};
1475
1476/*
1477 * HBA Identifier
1478 */
1479struct lpfc_fdmi_hba_ident {
1480        struct lpfc_name PortName;
1481};
1482
1483/*
1484 * Registered Port List Format
1485 */
1486struct lpfc_fdmi_reg_port_list {
1487        uint32_t EntryCnt;
1488        struct lpfc_fdmi_port_entry pe;
1489} __packed;
1490
1491/*
1492 * Register HBA(RHBA)
1493 */
1494struct lpfc_fdmi_reg_hba {
1495        struct lpfc_fdmi_hba_ident hi;
1496        struct lpfc_fdmi_reg_port_list rpl;
1497};
1498
1499/******** MI MIB ********/
1500#define SLI_CT_MIB_Subtypes     0x11
1501
1502/*
1503 * Register HBA Attributes (RHAT)
1504 */
1505struct lpfc_fdmi_reg_hbaattr {
1506        struct lpfc_name HBA_PortName;
1507        struct lpfc_fdmi_attr_block ab;
1508};
1509
1510/*
1511 * Register Port Attributes (RPA)
1512 */
1513struct lpfc_fdmi_reg_portattr {
1514        struct lpfc_name PortName;
1515        struct lpfc_fdmi_attr_block ab;
1516};
1517
1518/*
1519 * HBA MAnagement Operations Command Codes
1520 */
1521#define  SLI_MGMT_GRHL     0x100        /* Get registered HBA list */
1522#define  SLI_MGMT_GHAT     0x101        /* Get HBA attributes */
1523#define  SLI_MGMT_GRPL     0x102        /* Get registered Port list */
1524#define  SLI_MGMT_GPAT     0x110        /* Get Port attributes */
1525#define  SLI_MGMT_GPAS     0x120        /* Get Port Statistics */
1526#define  SLI_MGMT_RHBA     0x200        /* Register HBA */
1527#define  SLI_MGMT_RHAT     0x201        /* Register HBA attributes */
1528#define  SLI_MGMT_RPRT     0x210        /* Register Port */
1529#define  SLI_MGMT_RPA      0x211        /* Register Port attributes */
1530#define  SLI_MGMT_DHBA     0x300        /* De-register HBA */
1531#define  SLI_MGMT_DHAT     0x301        /* De-register HBA attributes */
1532#define  SLI_MGMT_DPRT     0x310        /* De-register Port */
1533#define  SLI_MGMT_DPA      0x311        /* De-register Port attributes */
1534
1535#define LPFC_FDMI_MAX_RETRY     3  /* Max retries for a FDMI command */
1536
1537/*
1538 * HBA Attribute Types
1539 */
1540#define  RHBA_NODENAME           0x1 /* 8 byte WWNN */
1541#define  RHBA_MANUFACTURER       0x2 /* 4 to 64 byte ASCII string */
1542#define  RHBA_SERIAL_NUMBER      0x3 /* 4 to 64 byte ASCII string */
1543#define  RHBA_MODEL              0x4 /* 4 to 256 byte ASCII string */
1544#define  RHBA_MODEL_DESCRIPTION  0x5 /* 4 to 256 byte ASCII string */
1545#define  RHBA_HARDWARE_VERSION   0x6 /* 4 to 256 byte ASCII string */
1546#define  RHBA_DRIVER_VERSION     0x7 /* 4 to 256 byte ASCII string */
1547#define  RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1548#define  RHBA_FIRMWARE_VERSION   0x9 /* 4 to 256 byte ASCII string */
1549#define  RHBA_OS_NAME_VERSION    0xa /* 4 to 256 byte ASCII string */
1550#define  RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1551#define  RHBA_SYM_NODENAME       0xc /* 4 to 256 byte ASCII string */
1552#define  RHBA_VENDOR_INFO        0xd  /* 32-bit unsigned int */
1553#define  RHBA_NUM_PORTS          0xe  /* 32-bit unsigned int */
1554#define  RHBA_FABRIC_WWNN        0xf  /* 8 byte WWNN */
1555#define  RHBA_BIOS_VERSION       0x10 /* 4 to 256 byte ASCII string */
1556#define  RHBA_BIOS_STATE         0x11 /* 32-bit unsigned int */
1557#define  RHBA_VENDOR_ID          0xe0 /* 8 byte ASCII string */
1558
1559/* Bit mask for all individual HBA attributes */
1560#define LPFC_FDMI_HBA_ATTR_wwnn                 0x00000001
1561#define LPFC_FDMI_HBA_ATTR_manufacturer         0x00000002
1562#define LPFC_FDMI_HBA_ATTR_sn                   0x00000004
1563#define LPFC_FDMI_HBA_ATTR_model                0x00000008
1564#define LPFC_FDMI_HBA_ATTR_description          0x00000010
1565#define LPFC_FDMI_HBA_ATTR_hdw_ver              0x00000020
1566#define LPFC_FDMI_HBA_ATTR_drvr_ver             0x00000040
1567#define LPFC_FDMI_HBA_ATTR_rom_ver              0x00000080
1568#define LPFC_FDMI_HBA_ATTR_fmw_ver              0x00000100
1569#define LPFC_FDMI_HBA_ATTR_os_ver               0x00000200
1570#define LPFC_FDMI_HBA_ATTR_ct_len               0x00000400
1571#define LPFC_FDMI_HBA_ATTR_symbolic_name        0x00000800
1572#define LPFC_FDMI_HBA_ATTR_vendor_info          0x00001000 /* Not used */
1573#define LPFC_FDMI_HBA_ATTR_num_ports            0x00002000
1574#define LPFC_FDMI_HBA_ATTR_fabric_wwnn          0x00004000
1575#define LPFC_FDMI_HBA_ATTR_bios_ver             0x00008000
1576#define LPFC_FDMI_HBA_ATTR_bios_state           0x00010000 /* Not used */
1577#define LPFC_FDMI_HBA_ATTR_vendor_id            0x00020000
1578
1579/* Bit mask for FDMI-1 defined HBA attributes */
1580#define LPFC_FDMI1_HBA_ATTR                     0x000007ff
1581
1582/* Bit mask for FDMI-2 defined HBA attributes */
1583/* Skip vendor_info and bios_state */
1584#define LPFC_FDMI2_HBA_ATTR                     0x0002efff
1585
1586/*
1587 * Port Attribute Types
1588 */
1589#define  RPRT_SUPPORTED_FC4_TYPES     0x1 /* 32 byte binary array */
1590#define  RPRT_SUPPORTED_SPEED         0x2 /* 32-bit unsigned int */
1591#define  RPRT_PORT_SPEED              0x3 /* 32-bit unsigned int */
1592#define  RPRT_MAX_FRAME_SIZE          0x4 /* 32-bit unsigned int */
1593#define  RPRT_OS_DEVICE_NAME          0x5 /* 4 to 256 byte ASCII string */
1594#define  RPRT_HOST_NAME               0x6 /* 4 to 256 byte ASCII string */
1595#define  RPRT_NODENAME                0x7 /* 8 byte WWNN */
1596#define  RPRT_PORTNAME                0x8 /* 8 byte WWPN */
1597#define  RPRT_SYM_PORTNAME            0x9 /* 4 to 256 byte ASCII string */
1598#define  RPRT_PORT_TYPE               0xa /* 32-bit unsigned int */
1599#define  RPRT_SUPPORTED_CLASS         0xb /* 32-bit unsigned int */
1600#define  RPRT_FABRICNAME              0xc /* 8 byte Fabric WWPN */
1601#define  RPRT_ACTIVE_FC4_TYPES        0xd /* 32 byte binary array */
1602#define  RPRT_PORT_STATE              0x101 /* 32-bit unsigned int */
1603#define  RPRT_DISC_PORT               0x102 /* 32-bit unsigned int */
1604#define  RPRT_PORT_ID                 0x103 /* 32-bit unsigned int */
1605#define  RPRT_VENDOR_MI               0xf047 /* vendor ascii string */
1606#define  RPRT_SMART_SERVICE           0xf100 /* 4 to 256 byte ASCII string */
1607#define  RPRT_SMART_GUID              0xf101 /* 8 byte WWNN + 8 byte WWPN */
1608#define  RPRT_SMART_VERSION           0xf102 /* 4 to 256 byte ASCII string */
1609#define  RPRT_SMART_MODEL             0xf103 /* 4 to 256 byte ASCII string */
1610#define  RPRT_SMART_PORT_INFO         0xf104 /* 32-bit unsigned int */
1611#define  RPRT_SMART_QOS               0xf105 /* 32-bit unsigned int */
1612#define  RPRT_SMART_SECURITY          0xf106 /* 32-bit unsigned int */
1613
1614/* Bit mask for all individual PORT attributes */
1615#define LPFC_FDMI_PORT_ATTR_fc4type             0x00000001
1616#define LPFC_FDMI_PORT_ATTR_support_speed       0x00000002
1617#define LPFC_FDMI_PORT_ATTR_speed               0x00000004
1618#define LPFC_FDMI_PORT_ATTR_max_frame           0x00000008
1619#define LPFC_FDMI_PORT_ATTR_os_devname          0x00000010
1620#define LPFC_FDMI_PORT_ATTR_host_name           0x00000020
1621#define LPFC_FDMI_PORT_ATTR_wwnn                0x00000040
1622#define LPFC_FDMI_PORT_ATTR_wwpn                0x00000080
1623#define LPFC_FDMI_PORT_ATTR_symbolic_name       0x00000100
1624#define LPFC_FDMI_PORT_ATTR_port_type           0x00000200
1625#define LPFC_FDMI_PORT_ATTR_class               0x00000400
1626#define LPFC_FDMI_PORT_ATTR_fabric_wwpn         0x00000800
1627#define LPFC_FDMI_PORT_ATTR_port_state          0x00001000
1628#define LPFC_FDMI_PORT_ATTR_active_fc4type      0x00002000
1629#define LPFC_FDMI_PORT_ATTR_num_disc            0x00004000
1630#define LPFC_FDMI_PORT_ATTR_nportid             0x00008000
1631#define LPFC_FDMI_SMART_ATTR_service            0x00010000 /* Vendor specific */
1632#define LPFC_FDMI_SMART_ATTR_guid               0x00020000 /* Vendor specific */
1633#define LPFC_FDMI_SMART_ATTR_version            0x00040000 /* Vendor specific */
1634#define LPFC_FDMI_SMART_ATTR_model              0x00080000 /* Vendor specific */
1635#define LPFC_FDMI_SMART_ATTR_port_info          0x00100000 /* Vendor specific */
1636#define LPFC_FDMI_SMART_ATTR_qos                0x00200000 /* Vendor specific */
1637#define LPFC_FDMI_SMART_ATTR_security           0x00400000 /* Vendor specific */
1638#define LPFC_FDMI_VENDOR_ATTR_mi                0x00800000 /* Vendor specific */
1639
1640/* Bit mask for FDMI-1 defined PORT attributes */
1641#define LPFC_FDMI1_PORT_ATTR                    0x0000003f
1642
1643/* Bit mask for FDMI-2 defined PORT attributes */
1644#define LPFC_FDMI2_PORT_ATTR                    0x0000ffff
1645
1646/* Bit mask for Smart SAN defined PORT attributes */
1647#define LPFC_FDMI2_SMART_ATTR                   0x007fffff
1648
1649/* Defines for PORT port state attribute */
1650#define LPFC_FDMI_PORTSTATE_UNKNOWN     1
1651#define LPFC_FDMI_PORTSTATE_ONLINE      2
1652
1653/* Defines for PORT port type attribute */
1654#define LPFC_FDMI_PORTTYPE_UNKNOWN      0
1655#define LPFC_FDMI_PORTTYPE_NPORT        1
1656#define LPFC_FDMI_PORTTYPE_NLPORT       2
1657
1658/*
1659 *  Begin HBA configuration parameters.
1660 *  The PCI configuration register BAR assignments are:
1661 *  BAR0, offset 0x10 - SLIM base memory address
1662 *  BAR1, offset 0x14 - SLIM base memory high address
1663 *  BAR2, offset 0x18 - REGISTER base memory address
1664 *  BAR3, offset 0x1c - REGISTER base memory high address
1665 *  BAR4, offset 0x20 - BIU I/O registers
1666 *  BAR5, offset 0x24 - REGISTER base io high address
1667 */
1668
1669/* Number of rings currently used and available. */
1670#define MAX_SLI3_CONFIGURED_RINGS     3
1671#define MAX_SLI3_RINGS                4
1672
1673/* IOCB / Mailbox is owned by FireFly */
1674#define OWN_CHIP        1
1675
1676/* IOCB / Mailbox is owned by Host */
1677#define OWN_HOST        0
1678
1679/* Number of 4-byte words in an IOCB. */
1680#define IOCB_WORD_SZ    8
1681
1682/* network headers for Dfctl field */
1683#define FC_NET_HDR      0x20
1684
1685/* Start FireFly Register definitions */
1686#define PCI_VENDOR_ID_EMULEX        0x10df
1687#define PCI_DEVICE_ID_FIREFLY       0x1ae5
1688#define PCI_DEVICE_ID_PROTEUS_VF    0xe100
1689#define PCI_DEVICE_ID_BALIUS        0xe131
1690#define PCI_DEVICE_ID_PROTEUS_PF    0xe180
1691#define PCI_DEVICE_ID_LANCER_FC     0xe200
1692#define PCI_DEVICE_ID_LANCER_FC_VF  0xe208
1693#define PCI_DEVICE_ID_LANCER_FCOE   0xe260
1694#define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1695#define PCI_DEVICE_ID_LANCER_G6_FC  0xe300
1696#define PCI_DEVICE_ID_LANCER_G7_FC  0xf400
1697#define PCI_DEVICE_ID_SAT_SMB       0xf011
1698#define PCI_DEVICE_ID_SAT_MID       0xf015
1699#define PCI_DEVICE_ID_RFLY          0xf095
1700#define PCI_DEVICE_ID_PFLY          0xf098
1701#define PCI_DEVICE_ID_LP101         0xf0a1
1702#define PCI_DEVICE_ID_TFLY          0xf0a5
1703#define PCI_DEVICE_ID_BSMB          0xf0d1
1704#define PCI_DEVICE_ID_BMID          0xf0d5
1705#define PCI_DEVICE_ID_ZSMB          0xf0e1
1706#define PCI_DEVICE_ID_ZMID          0xf0e5
1707#define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1708#define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1709#define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1710#define PCI_DEVICE_ID_SAT           0xf100
1711#define PCI_DEVICE_ID_SAT_SCSP      0xf111
1712#define PCI_DEVICE_ID_SAT_DCSP      0xf112
1713#define PCI_DEVICE_ID_FALCON        0xf180
1714#define PCI_DEVICE_ID_SUPERFLY      0xf700
1715#define PCI_DEVICE_ID_DRAGONFLY     0xf800
1716#define PCI_DEVICE_ID_CENTAUR       0xf900
1717#define PCI_DEVICE_ID_PEGASUS       0xf980
1718#define PCI_DEVICE_ID_THOR          0xfa00
1719#define PCI_DEVICE_ID_VIPER         0xfb00
1720#define PCI_DEVICE_ID_LP10000S      0xfc00
1721#define PCI_DEVICE_ID_LP11000S      0xfc10
1722#define PCI_DEVICE_ID_LPE11000S     0xfc20
1723#define PCI_DEVICE_ID_SAT_S         0xfc40
1724#define PCI_DEVICE_ID_PROTEUS_S     0xfc50
1725#define PCI_DEVICE_ID_HELIOS        0xfd00
1726#define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1727#define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1728#define PCI_DEVICE_ID_ZEPHYR        0xfe00
1729#define PCI_DEVICE_ID_HORNET        0xfe05
1730#define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1731#define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1732#define PCI_VENDOR_ID_SERVERENGINE  0x19a2
1733#define PCI_DEVICE_ID_TIGERSHARK    0x0704
1734#define PCI_DEVICE_ID_TOMCAT        0x0714
1735#define PCI_DEVICE_ID_SKYHAWK       0x0724
1736#define PCI_DEVICE_ID_SKYHAWK_VF    0x072c
1737
1738#define JEDEC_ID_ADDRESS            0x0080001c
1739#define FIREFLY_JEDEC_ID            0x1ACC
1740#define SUPERFLY_JEDEC_ID           0x0020
1741#define DRAGONFLY_JEDEC_ID          0x0021
1742#define DRAGONFLY_V2_JEDEC_ID       0x0025
1743#define CENTAUR_2G_JEDEC_ID         0x0026
1744#define CENTAUR_1G_JEDEC_ID         0x0028
1745#define PEGASUS_ORION_JEDEC_ID      0x0036
1746#define PEGASUS_JEDEC_ID            0x0038
1747#define THOR_JEDEC_ID               0x0012
1748#define HELIOS_JEDEC_ID             0x0364
1749#define ZEPHYR_JEDEC_ID             0x0577
1750#define VIPER_JEDEC_ID              0x4838
1751#define SATURN_JEDEC_ID             0x1004
1752#define HORNET_JDEC_ID              0x2057706D
1753
1754#define JEDEC_ID_MASK               0x0FFFF000
1755#define JEDEC_ID_SHIFT              12
1756#define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1757
1758typedef struct {                /* FireFly BIU registers */
1759        uint32_t hostAtt;       /* See definitions for Host Attention
1760                                   register */
1761        uint32_t chipAtt;       /* See definitions for Chip Attention
1762                                   register */
1763        uint32_t hostStatus;    /* See definitions for Host Status register */
1764        uint32_t hostControl;   /* See definitions for Host Control register */
1765        uint32_t buiConfig;     /* See definitions for BIU configuration
1766                                   register */
1767} FF_REGS;
1768
1769/* IO Register size in bytes */
1770#define FF_REG_AREA_SIZE       256
1771
1772/* Host Attention Register */
1773
1774#define HA_REG_OFFSET  0        /* Byte offset from register base address */
1775
1776#define HA_R0RE_REQ    0x00000001       /* Bit  0 */
1777#define HA_R0CE_RSP    0x00000002       /* Bit  1 */
1778#define HA_R0ATT       0x00000008       /* Bit  3 */
1779#define HA_R1RE_REQ    0x00000010       /* Bit  4 */
1780#define HA_R1CE_RSP    0x00000020       /* Bit  5 */
1781#define HA_R1ATT       0x00000080       /* Bit  7 */
1782#define HA_R2RE_REQ    0x00000100       /* Bit  8 */
1783#define HA_R2CE_RSP    0x00000200       /* Bit  9 */
1784#define HA_R2ATT       0x00000800       /* Bit 11 */
1785#define HA_R3RE_REQ    0x00001000       /* Bit 12 */
1786#define HA_R3CE_RSP    0x00002000       /* Bit 13 */
1787#define HA_R3ATT       0x00008000       /* Bit 15 */
1788#define HA_LATT        0x20000000       /* Bit 29 */
1789#define HA_MBATT       0x40000000       /* Bit 30 */
1790#define HA_ERATT       0x80000000       /* Bit 31 */
1791
1792#define HA_RXRE_REQ    0x00000001       /* Bit  0 */
1793#define HA_RXCE_RSP    0x00000002       /* Bit  1 */
1794#define HA_RXATT       0x00000008       /* Bit  3 */
1795#define HA_RXMASK      0x0000000f
1796
1797#define HA_R0_CLR_MSK   (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1798#define HA_R1_CLR_MSK   (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1799#define HA_R2_CLR_MSK   (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1800#define HA_R3_CLR_MSK   (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1801
1802#define HA_R0_POS       3
1803#define HA_R1_POS       7
1804#define HA_R2_POS       11
1805#define HA_R3_POS       15
1806#define HA_LE_POS       29
1807#define HA_MB_POS       30
1808#define HA_ER_POS       31
1809/* Chip Attention Register */
1810
1811#define CA_REG_OFFSET  4        /* Byte offset from register base address */
1812
1813#define CA_R0CE_REQ    0x00000001       /* Bit  0 */
1814#define CA_R0RE_RSP    0x00000002       /* Bit  1 */
1815#define CA_R0ATT       0x00000008       /* Bit  3 */
1816#define CA_R1CE_REQ    0x00000010       /* Bit  4 */
1817#define CA_R1RE_RSP    0x00000020       /* Bit  5 */
1818#define CA_R1ATT       0x00000080       /* Bit  7 */
1819#define CA_R2CE_REQ    0x00000100       /* Bit  8 */
1820#define CA_R2RE_RSP    0x00000200       /* Bit  9 */
1821#define CA_R2ATT       0x00000800       /* Bit 11 */
1822#define CA_R3CE_REQ    0x00001000       /* Bit 12 */
1823#define CA_R3RE_RSP    0x00002000       /* Bit 13 */
1824#define CA_R3ATT       0x00008000       /* Bit 15 */
1825#define CA_MBATT       0x40000000       /* Bit 30 */
1826
1827/* Host Status Register */
1828
1829#define HS_REG_OFFSET  8        /* Byte offset from register base address */
1830
1831#define HS_MBRDY       0x00400000       /* Bit 22 */
1832#define HS_FFRDY       0x00800000       /* Bit 23 */
1833#define HS_FFER8       0x01000000       /* Bit 24 */
1834#define HS_FFER7       0x02000000       /* Bit 25 */
1835#define HS_FFER6       0x04000000       /* Bit 26 */
1836#define HS_FFER5       0x08000000       /* Bit 27 */
1837#define HS_FFER4       0x10000000       /* Bit 28 */
1838#define HS_FFER3       0x20000000       /* Bit 29 */
1839#define HS_FFER2       0x40000000       /* Bit 30 */
1840#define HS_FFER1       0x80000000       /* Bit 31 */
1841#define HS_CRIT_TEMP   0x00000100       /* Bit 8  */
1842#define HS_FFERM       0xFF000100       /* Mask for error bits 31:24 and 8 */
1843#define UNPLUG_ERR     0x00000001       /* Indicate pci hot unplug */
1844/* Host Control Register */
1845
1846#define HC_REG_OFFSET  12       /* Byte offset from register base address */
1847
1848#define HC_MBINT_ENA   0x00000001       /* Bit  0 */
1849#define HC_R0INT_ENA   0x00000002       /* Bit  1 */
1850#define HC_R1INT_ENA   0x00000004       /* Bit  2 */
1851#define HC_R2INT_ENA   0x00000008       /* Bit  3 */
1852#define HC_R3INT_ENA   0x00000010       /* Bit  4 */
1853#define HC_INITHBI     0x02000000       /* Bit 25 */
1854#define HC_INITMB      0x04000000       /* Bit 26 */
1855#define HC_INITFF      0x08000000       /* Bit 27 */
1856#define HC_LAINT_ENA   0x20000000       /* Bit 29 */
1857#define HC_ERINT_ENA   0x80000000       /* Bit 31 */
1858
1859/* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1860#define MSIX_DFLT_ID    0
1861#define MSIX_RNG0_ID    0
1862#define MSIX_RNG1_ID    1
1863#define MSIX_RNG2_ID    2
1864#define MSIX_RNG3_ID    3
1865
1866#define MSIX_LINK_ID    4
1867#define MSIX_MBOX_ID    5
1868
1869#define MSIX_SPARE0_ID  6
1870#define MSIX_SPARE1_ID  7
1871
1872/* Mailbox Commands */
1873#define MBX_SHUTDOWN        0x00        /* terminate testing */
1874#define MBX_LOAD_SM         0x01
1875#define MBX_READ_NV         0x02
1876#define MBX_WRITE_NV        0x03
1877#define MBX_RUN_BIU_DIAG    0x04
1878#define MBX_INIT_LINK       0x05
1879#define MBX_DOWN_LINK       0x06
1880#define MBX_CONFIG_LINK     0x07
1881#define MBX_CONFIG_RING     0x09
1882#define MBX_RESET_RING      0x0A
1883#define MBX_READ_CONFIG     0x0B
1884#define MBX_READ_RCONFIG    0x0C
1885#define MBX_READ_SPARM      0x0D
1886#define MBX_READ_STATUS     0x0E
1887#define MBX_READ_RPI        0x0F
1888#define MBX_READ_XRI        0x10
1889#define MBX_READ_REV        0x11
1890#define MBX_READ_LNK_STAT   0x12
1891#define MBX_REG_LOGIN       0x13
1892#define MBX_UNREG_LOGIN     0x14
1893#define MBX_CLEAR_LA        0x16
1894#define MBX_DUMP_MEMORY     0x17
1895#define MBX_DUMP_CONTEXT    0x18
1896#define MBX_RUN_DIAGS       0x19
1897#define MBX_RESTART         0x1A
1898#define MBX_UPDATE_CFG      0x1B
1899#define MBX_DOWN_LOAD       0x1C
1900#define MBX_DEL_LD_ENTRY    0x1D
1901#define MBX_RUN_PROGRAM     0x1E
1902#define MBX_SET_MASK        0x20
1903#define MBX_SET_VARIABLE    0x21
1904#define MBX_UNREG_D_ID      0x23
1905#define MBX_KILL_BOARD      0x24
1906#define MBX_CONFIG_FARP     0x25
1907#define MBX_BEACON          0x2A
1908#define MBX_CONFIG_MSI      0x30
1909#define MBX_HEARTBEAT       0x31
1910#define MBX_WRITE_VPARMS    0x32
1911#define MBX_ASYNCEVT_ENABLE 0x33
1912#define MBX_READ_EVENT_LOG_STATUS 0x37
1913#define MBX_READ_EVENT_LOG  0x38
1914#define MBX_WRITE_EVENT_LOG 0x39
1915
1916#define MBX_PORT_CAPABILITIES 0x3B
1917#define MBX_PORT_IOV_CONTROL 0x3C
1918
1919#define MBX_CONFIG_HBQ      0x7C
1920#define MBX_LOAD_AREA       0x81
1921#define MBX_RUN_BIU_DIAG64  0x84
1922#define MBX_CONFIG_PORT     0x88
1923#define MBX_READ_SPARM64    0x8D
1924#define MBX_READ_RPI64      0x8F
1925#define MBX_REG_LOGIN64     0x93
1926#define MBX_READ_TOPOLOGY   0x95
1927#define MBX_REG_VPI         0x96
1928#define MBX_UNREG_VPI       0x97
1929
1930#define MBX_WRITE_WWN       0x98
1931#define MBX_SET_DEBUG       0x99
1932#define MBX_LOAD_EXP_ROM    0x9C
1933#define MBX_SLI4_CONFIG     0x9B
1934#define MBX_SLI4_REQ_FTRS   0x9D
1935#define MBX_MAX_CMDS        0x9E
1936#define MBX_RESUME_RPI      0x9E
1937#define MBX_SLI2_CMD_MASK   0x80
1938#define MBX_REG_VFI         0x9F
1939#define MBX_REG_FCFI        0xA0
1940#define MBX_UNREG_VFI       0xA1
1941#define MBX_UNREG_FCFI      0xA2
1942#define MBX_INIT_VFI        0xA3
1943#define MBX_INIT_VPI        0xA4
1944#define MBX_ACCESS_VDATA    0xA5
1945#define MBX_REG_FCFI_MRQ    0xAF
1946
1947#define MBX_AUTH_PORT       0xF8
1948#define MBX_SECURITY_MGMT   0xF9
1949
1950/* IOCB Commands */
1951
1952#define CMD_RCV_SEQUENCE_CX     0x01
1953#define CMD_XMIT_SEQUENCE_CR    0x02
1954#define CMD_XMIT_SEQUENCE_CX    0x03
1955#define CMD_XMIT_BCAST_CN       0x04
1956#define CMD_XMIT_BCAST_CX       0x05
1957#define CMD_QUE_RING_BUF_CN     0x06
1958#define CMD_QUE_XRI_BUF_CX      0x07
1959#define CMD_IOCB_CONTINUE_CN    0x08
1960#define CMD_RET_XRI_BUF_CX      0x09
1961#define CMD_ELS_REQUEST_CR      0x0A
1962#define CMD_ELS_REQUEST_CX      0x0B
1963#define CMD_RCV_ELS_REQ_CX      0x0D
1964#define CMD_ABORT_XRI_CN        0x0E
1965#define CMD_ABORT_XRI_CX        0x0F
1966#define CMD_CLOSE_XRI_CN        0x10
1967#define CMD_CLOSE_XRI_CX        0x11
1968#define CMD_CREATE_XRI_CR       0x12
1969#define CMD_CREATE_XRI_CX       0x13
1970#define CMD_GET_RPI_CN          0x14
1971#define CMD_XMIT_ELS_RSP_CX     0x15
1972#define CMD_GET_RPI_CR          0x16
1973#define CMD_XRI_ABORTED_CX      0x17
1974#define CMD_FCP_IWRITE_CR       0x18
1975#define CMD_FCP_IWRITE_CX       0x19
1976#define CMD_FCP_IREAD_CR        0x1A
1977#define CMD_FCP_IREAD_CX        0x1B
1978#define CMD_FCP_ICMND_CR        0x1C
1979#define CMD_FCP_ICMND_CX        0x1D
1980#define CMD_FCP_TSEND_CX        0x1F
1981#define CMD_FCP_TRECEIVE_CX     0x21
1982#define CMD_FCP_TRSP_CX         0x23
1983#define CMD_FCP_AUTO_TRSP_CX    0x29
1984
1985#define CMD_ADAPTER_MSG         0x20
1986#define CMD_ADAPTER_DUMP        0x22
1987
1988/*  SLI_2 IOCB Command Set */
1989
1990#define CMD_ASYNC_STATUS        0x7C
1991#define CMD_RCV_SEQUENCE64_CX   0x81
1992#define CMD_XMIT_SEQUENCE64_CR  0x82
1993#define CMD_XMIT_SEQUENCE64_CX  0x83
1994#define CMD_XMIT_BCAST64_CN     0x84
1995#define CMD_XMIT_BCAST64_CX     0x85
1996#define CMD_QUE_RING_BUF64_CN   0x86
1997#define CMD_QUE_XRI_BUF64_CX    0x87
1998#define CMD_IOCB_CONTINUE64_CN  0x88
1999#define CMD_RET_XRI_BUF64_CX    0x89
2000#define CMD_ELS_REQUEST64_CR    0x8A
2001#define CMD_ELS_REQUEST64_CX    0x8B
2002#define CMD_ABORT_MXRI64_CN     0x8C
2003#define CMD_RCV_ELS_REQ64_CX    0x8D
2004#define CMD_XMIT_ELS_RSP64_CX   0x95
2005#define CMD_XMIT_BLS_RSP64_CX   0x97
2006#define CMD_FCP_IWRITE64_CR     0x98
2007#define CMD_FCP_IWRITE64_CX     0x99
2008#define CMD_FCP_IREAD64_CR      0x9A
2009#define CMD_FCP_IREAD64_CX      0x9B
2010#define CMD_FCP_ICMND64_CR      0x9C
2011#define CMD_FCP_ICMND64_CX      0x9D
2012#define CMD_FCP_TSEND64_CX      0x9F
2013#define CMD_FCP_TRECEIVE64_CX   0xA1
2014#define CMD_FCP_TRSP64_CX       0xA3
2015
2016#define CMD_QUE_XRI64_CX        0xB3
2017#define CMD_IOCB_RCV_SEQ64_CX   0xB5
2018#define CMD_IOCB_RCV_ELS64_CX   0xB7
2019#define CMD_IOCB_RET_XRI64_CX   0xB9
2020#define CMD_IOCB_RCV_CONT64_CX  0xBB
2021
2022#define CMD_GEN_REQUEST64_CR    0xC2
2023#define CMD_GEN_REQUEST64_CX    0xC3
2024
2025/* Unhandled SLI-3 Commands */
2026#define CMD_IOCB_XMIT_MSEQ64_CR         0xB0
2027#define CMD_IOCB_XMIT_MSEQ64_CX         0xB1
2028#define CMD_IOCB_RCV_SEQ_LIST64_CX      0xC1
2029#define CMD_IOCB_RCV_ELS_LIST64_CX      0xCD
2030#define CMD_IOCB_CLOSE_EXTENDED_CN      0xB6
2031#define CMD_IOCB_ABORT_EXTENDED_CN      0xBA
2032#define CMD_IOCB_RET_HBQE64_CN          0xCA
2033#define CMD_IOCB_FCP_IBIDIR64_CR        0xAC
2034#define CMD_IOCB_FCP_IBIDIR64_CX        0xAD
2035#define CMD_IOCB_FCP_ITASKMGT64_CX      0xAF
2036#define CMD_IOCB_LOGENTRY_CN            0x94
2037#define CMD_IOCB_LOGENTRY_ASYNC_CN      0x96
2038
2039/* Data Security SLI Commands */
2040#define DSSCMD_IWRITE64_CR              0xF8
2041#define DSSCMD_IWRITE64_CX              0xF9
2042#define DSSCMD_IREAD64_CR               0xFA
2043#define DSSCMD_IREAD64_CX               0xFB
2044
2045#define CMD_MAX_IOCB_CMD        0xFB
2046#define CMD_IOCB_MASK           0xff
2047
2048#define MAX_MSG_DATA            28      /* max msg data in CMD_ADAPTER_MSG
2049                                           iocb */
2050#define LPFC_MAX_ADPTMSG         32     /* max msg data */
2051/*
2052 *  Define Status
2053 */
2054#define MBX_SUCCESS                 0
2055#define MBXERR_NUM_RINGS            1
2056#define MBXERR_NUM_IOCBS            2
2057#define MBXERR_IOCBS_EXCEEDED       3
2058#define MBXERR_BAD_RING_NUMBER      4
2059#define MBXERR_MASK_ENTRIES_RANGE   5
2060#define MBXERR_MASKS_EXCEEDED       6
2061#define MBXERR_BAD_PROFILE          7
2062#define MBXERR_BAD_DEF_CLASS        8
2063#define MBXERR_BAD_MAX_RESPONDER    9
2064#define MBXERR_BAD_MAX_ORIGINATOR   10
2065#define MBXERR_RPI_REGISTERED       11
2066#define MBXERR_RPI_FULL             12
2067#define MBXERR_NO_RESOURCES         13
2068#define MBXERR_BAD_RCV_LENGTH       14
2069#define MBXERR_DMA_ERROR            15
2070#define MBXERR_ERROR                16
2071#define MBXERR_LINK_DOWN            0x33
2072#define MBXERR_SEC_NO_PERMISSION    0xF02
2073#define MBX_NOT_FINISHED            255
2074
2075#define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
2076#define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
2077
2078#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
2079
2080/*
2081 * return code Fail
2082 */
2083#define FAILURE 1
2084
2085/*
2086 *    Begin Structure Definitions for Mailbox Commands
2087 */
2088
2089typedef struct {
2090#ifdef __BIG_ENDIAN_BITFIELD
2091        uint8_t tval;
2092        uint8_t tmask;
2093        uint8_t rval;
2094        uint8_t rmask;
2095#else   /*  __LITTLE_ENDIAN_BITFIELD */
2096        uint8_t rmask;
2097        uint8_t rval;
2098        uint8_t tmask;
2099        uint8_t tval;
2100#endif
2101} RR_REG;
2102
2103struct ulp_bde {
2104        uint32_t bdeAddress;
2105#ifdef __BIG_ENDIAN_BITFIELD
2106        uint32_t bdeReserved:4;
2107        uint32_t bdeAddrHigh:4;
2108        uint32_t bdeSize:24;
2109#else   /*  __LITTLE_ENDIAN_BITFIELD */
2110        uint32_t bdeSize:24;
2111        uint32_t bdeAddrHigh:4;
2112        uint32_t bdeReserved:4;
2113#endif
2114};
2115
2116typedef struct ULP_BDL {        /* SLI-2 */
2117#ifdef __BIG_ENDIAN_BITFIELD
2118        uint32_t bdeFlags:8;    /* BDL Flags */
2119        uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
2120#else   /*  __LITTLE_ENDIAN_BITFIELD */
2121        uint32_t bdeSize:24;    /* Size of BDL array in host memory (bytes) */
2122        uint32_t bdeFlags:8;    /* BDL Flags */
2123#endif
2124
2125        uint32_t addrLow;       /* Address 0:31 */
2126        uint32_t addrHigh;      /* Address 32:63 */
2127        uint32_t ulpIoTag32;    /* Can be used for 32 bit I/O Tag */
2128} ULP_BDL;
2129
2130/*
2131 * BlockGuard Definitions
2132 */
2133
2134enum lpfc_protgrp_type {
2135        LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors                  */
2136        LPFC_PG_TYPE_NO_DIF,      /* no DIF data pointed to by prot grp       */
2137        LPFC_PG_TYPE_EMBD_DIF,    /* DIF is embedded (inline) with data       */
2138        LPFC_PG_TYPE_DIF_BUF      /* DIF has its own scatter/gather list      */
2139};
2140
2141/* PDE Descriptors */
2142#define LPFC_PDE5_DESCRIPTOR            0x85
2143#define LPFC_PDE6_DESCRIPTOR            0x86
2144#define LPFC_PDE7_DESCRIPTOR            0x87
2145
2146/* BlockGuard Opcodes */
2147#define BG_OP_IN_NODIF_OUT_CRC          0x0
2148#define BG_OP_IN_CRC_OUT_NODIF          0x1
2149#define BG_OP_IN_NODIF_OUT_CSUM         0x2
2150#define BG_OP_IN_CSUM_OUT_NODIF         0x3
2151#define BG_OP_IN_CRC_OUT_CRC            0x4
2152#define BG_OP_IN_CSUM_OUT_CSUM          0x5
2153#define BG_OP_IN_CRC_OUT_CSUM           0x6
2154#define BG_OP_IN_CSUM_OUT_CRC           0x7
2155#define BG_OP_RAW_MODE                  0x8
2156
2157struct lpfc_pde5 {
2158        uint32_t word0;
2159#define pde5_type_SHIFT         24
2160#define pde5_type_MASK          0x000000ff
2161#define pde5_type_WORD          word0
2162#define pde5_rsvd0_SHIFT        0
2163#define pde5_rsvd0_MASK         0x00ffffff
2164#define pde5_rsvd0_WORD         word0
2165        uint32_t reftag;        /* Reference Tag Value                  */
2166        uint32_t reftagtr;      /* Reference Tag Translation Value      */
2167};
2168
2169struct lpfc_pde6 {
2170        uint32_t word0;
2171#define pde6_type_SHIFT         24
2172#define pde6_type_MASK          0x000000ff
2173#define pde6_type_WORD          word0
2174#define pde6_rsvd0_SHIFT        0
2175#define pde6_rsvd0_MASK         0x00ffffff
2176#define pde6_rsvd0_WORD         word0
2177        uint32_t word1;
2178#define pde6_rsvd1_SHIFT        26
2179#define pde6_rsvd1_MASK         0x0000003f
2180#define pde6_rsvd1_WORD         word1
2181#define pde6_na_SHIFT           25
2182#define pde6_na_MASK            0x00000001
2183#define pde6_na_WORD            word1
2184#define pde6_rsvd2_SHIFT        16
2185#define pde6_rsvd2_MASK         0x000001FF
2186#define pde6_rsvd2_WORD         word1
2187#define pde6_apptagtr_SHIFT     0
2188#define pde6_apptagtr_MASK      0x0000ffff
2189#define pde6_apptagtr_WORD      word1
2190        uint32_t word2;
2191#define pde6_optx_SHIFT         28
2192#define pde6_optx_MASK          0x0000000f
2193#define pde6_optx_WORD          word2
2194#define pde6_oprx_SHIFT         24
2195#define pde6_oprx_MASK          0x0000000f
2196#define pde6_oprx_WORD          word2
2197#define pde6_nr_SHIFT           23
2198#define pde6_nr_MASK            0x00000001
2199#define pde6_nr_WORD            word2
2200#define pde6_ce_SHIFT           22
2201#define pde6_ce_MASK            0x00000001
2202#define pde6_ce_WORD            word2
2203#define pde6_re_SHIFT           21
2204#define pde6_re_MASK            0x00000001
2205#define pde6_re_WORD            word2
2206#define pde6_ae_SHIFT           20
2207#define pde6_ae_MASK            0x00000001
2208#define pde6_ae_WORD            word2
2209#define pde6_ai_SHIFT           19
2210#define pde6_ai_MASK            0x00000001
2211#define pde6_ai_WORD            word2
2212#define pde6_bs_SHIFT           16
2213#define pde6_bs_MASK            0x00000007
2214#define pde6_bs_WORD            word2
2215#define pde6_apptagval_SHIFT    0
2216#define pde6_apptagval_MASK     0x0000ffff
2217#define pde6_apptagval_WORD     word2
2218};
2219
2220struct lpfc_pde7 {
2221        uint32_t word0;
2222#define pde7_type_SHIFT         24
2223#define pde7_type_MASK          0x000000ff
2224#define pde7_type_WORD          word0
2225#define pde7_rsvd0_SHIFT        0
2226#define pde7_rsvd0_MASK         0x00ffffff
2227#define pde7_rsvd0_WORD         word0
2228        uint32_t addrHigh;
2229        uint32_t addrLow;
2230};
2231
2232/* Structure for MB Command LOAD_SM and DOWN_LOAD */
2233
2234typedef struct {
2235#ifdef __BIG_ENDIAN_BITFIELD
2236        uint32_t rsvd2:25;
2237        uint32_t acknowledgment:1;
2238        uint32_t version:1;
2239        uint32_t erase_or_prog:1;
2240        uint32_t update_flash:1;
2241        uint32_t update_ram:1;
2242        uint32_t method:1;
2243        uint32_t load_cmplt:1;
2244#else   /*  __LITTLE_ENDIAN_BITFIELD */
2245        uint32_t load_cmplt:1;
2246        uint32_t method:1;
2247        uint32_t update_ram:1;
2248        uint32_t update_flash:1;
2249        uint32_t erase_or_prog:1;
2250        uint32_t version:1;
2251        uint32_t acknowledgment:1;
2252        uint32_t rsvd2:25;
2253#endif
2254
2255        uint32_t dl_to_adr_low;
2256        uint32_t dl_to_adr_high;
2257        uint32_t dl_len;
2258        union {
2259                uint32_t dl_from_mbx_offset;
2260                struct ulp_bde dl_from_bde;
2261                struct ulp_bde64 dl_from_bde64;
2262        } un;
2263
2264} LOAD_SM_VAR;
2265
2266/* Structure for MB Command READ_NVPARM (02) */
2267
2268typedef struct {
2269        uint32_t rsvd1[3];      /* Read as all one's */
2270        uint32_t rsvd2;         /* Read as all zero's */
2271        uint32_t portname[2];   /* N_PORT name */
2272        uint32_t nodename[2];   /* NODE name */
2273
2274#ifdef __BIG_ENDIAN_BITFIELD
2275        uint32_t pref_DID:24;
2276        uint32_t hardAL_PA:8;
2277#else   /*  __LITTLE_ENDIAN_BITFIELD */
2278        uint32_t hardAL_PA:8;
2279        uint32_t pref_DID:24;
2280#endif
2281
2282        uint32_t rsvd3[21];     /* Read as all one's */
2283} READ_NV_VAR;
2284
2285/* Structure for MB Command WRITE_NVPARMS (03) */
2286
2287typedef struct {
2288        uint32_t rsvd1[3];      /* Must be all one's */
2289        uint32_t rsvd2;         /* Must be all zero's */
2290        uint32_t portname[2];   /* N_PORT name */
2291        uint32_t nodename[2];   /* NODE name */
2292
2293#ifdef __BIG_ENDIAN_BITFIELD
2294        uint32_t pref_DID:24;
2295        uint32_t hardAL_PA:8;
2296#else   /*  __LITTLE_ENDIAN_BITFIELD */
2297        uint32_t hardAL_PA:8;
2298        uint32_t pref_DID:24;
2299#endif
2300
2301        uint32_t rsvd3[21];     /* Must be all one's */
2302} WRITE_NV_VAR;
2303
2304/* Structure for MB Command RUN_BIU_DIAG (04) */
2305/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2306
2307typedef struct {
2308        uint32_t rsvd1;
2309        union {
2310                struct {
2311                        struct ulp_bde xmit_bde;
2312                        struct ulp_bde rcv_bde;
2313                } s1;
2314                struct {
2315                        struct ulp_bde64 xmit_bde64;
2316                        struct ulp_bde64 rcv_bde64;
2317                } s2;
2318        } un;
2319} BIU_DIAG_VAR;
2320
2321/* Structure for MB command READ_EVENT_LOG (0x38) */
2322struct READ_EVENT_LOG_VAR {
2323        uint32_t word1;
2324#define lpfc_event_log_SHIFT    29
2325#define lpfc_event_log_MASK     0x00000001
2326#define lpfc_event_log_WORD     word1
2327#define USE_MAILBOX_RESPONSE    1
2328        uint32_t offset;
2329        struct ulp_bde64 rcv_bde64;
2330};
2331
2332/* Structure for MB Command INIT_LINK (05) */
2333
2334typedef struct {
2335#ifdef __BIG_ENDIAN_BITFIELD
2336        uint32_t rsvd1:24;
2337        uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2338#else   /*  __LITTLE_ENDIAN_BITFIELD */
2339        uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2340        uint32_t rsvd1:24;
2341#endif
2342
2343#ifdef __BIG_ENDIAN_BITFIELD
2344        uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
2345        uint8_t rsvd2;
2346        uint16_t link_flags;
2347#else   /*  __LITTLE_ENDIAN_BITFIELD */
2348        uint16_t link_flags;
2349        uint8_t rsvd2;
2350        uint8_t fabric_AL_PA;   /* If using a Fabric Assigned AL_PA */
2351#endif
2352
2353#define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
2354#define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
2355#define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
2356#define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
2357#define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
2358#define FLAGS_UNREG_LOGIN_ALL        0x08 /* UNREG_LOGIN all on link down */
2359#define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
2360
2361#define FLAGS_TOPOLOGY_FAILOVER      0x0400     /* Bit 10 */
2362#define FLAGS_LINK_SPEED             0x0800     /* Bit 11 */
2363#define FLAGS_IMED_ABORT             0x04000    /* Bit 14 */
2364
2365        uint32_t link_speed;
2366#define LINK_SPEED_AUTO 0x0     /* Auto selection */
2367#define LINK_SPEED_1G   0x1     /* 1 Gigabaud */
2368#define LINK_SPEED_2G   0x2     /* 2 Gigabaud */
2369#define LINK_SPEED_4G   0x4     /* 4 Gigabaud */
2370#define LINK_SPEED_8G   0x8     /* 8 Gigabaud */
2371#define LINK_SPEED_10G  0x10    /* 10 Gigabaud */
2372#define LINK_SPEED_16G  0x11    /* 16 Gigabaud */
2373#define LINK_SPEED_32G  0x14    /* 32 Gigabaud */
2374#define LINK_SPEED_64G  0x17    /* 64 Gigabaud */
2375#define LINK_SPEED_128G 0x1A    /* 128 Gigabaud */
2376#define LINK_SPEED_256G 0x1D    /* 256 Gigabaud */
2377
2378} INIT_LINK_VAR;
2379
2380/* Structure for MB Command DOWN_LINK (06) */
2381
2382typedef struct {
2383        uint32_t rsvd1;
2384} DOWN_LINK_VAR;
2385
2386/* Structure for MB Command CONFIG_LINK (07) */
2387
2388typedef struct {
2389#ifdef __BIG_ENDIAN_BITFIELD
2390        uint32_t cr:1;
2391        uint32_t ci:1;
2392        uint32_t cr_delay:6;
2393        uint32_t cr_count:8;
2394        uint32_t rsvd1:8;
2395        uint32_t MaxBBC:8;
2396#else   /*  __LITTLE_ENDIAN_BITFIELD */
2397        uint32_t MaxBBC:8;
2398        uint32_t rsvd1:8;
2399        uint32_t cr_count:8;
2400        uint32_t cr_delay:6;
2401        uint32_t ci:1;
2402        uint32_t cr:1;
2403#endif
2404
2405        uint32_t myId;
2406        uint32_t rsvd2;
2407        uint32_t edtov;
2408        uint32_t arbtov;
2409        uint32_t ratov;
2410        uint32_t rttov;
2411        uint32_t altov;
2412        uint32_t crtov;
2413
2414#ifdef __BIG_ENDIAN_BITFIELD
2415        uint32_t rsvd4:19;
2416        uint32_t cscn:1;
2417        uint32_t bbscn:4;
2418        uint32_t rsvd3:8;
2419#else   /*  __LITTLE_ENDIAN_BITFIELD */
2420        uint32_t rsvd3:8;
2421        uint32_t bbscn:4;
2422        uint32_t cscn:1;
2423        uint32_t rsvd4:19;
2424#endif
2425
2426#ifdef __BIG_ENDIAN_BITFIELD
2427        uint32_t rrq_enable:1;
2428        uint32_t rrq_immed:1;
2429        uint32_t rsvd5:29;
2430        uint32_t ack0_enable:1;
2431#else   /*  __LITTLE_ENDIAN_BITFIELD */
2432        uint32_t ack0_enable:1;
2433        uint32_t rsvd5:29;
2434        uint32_t rrq_immed:1;
2435        uint32_t rrq_enable:1;
2436#endif
2437} CONFIG_LINK;
2438
2439/* Structure for MB Command PART_SLIM (08)
2440 * will be removed since SLI1 is no longer supported!
2441 */
2442typedef struct {
2443#ifdef __BIG_ENDIAN_BITFIELD
2444        uint16_t offCiocb;
2445        uint16_t numCiocb;
2446        uint16_t offRiocb;
2447        uint16_t numRiocb;
2448#else   /*  __LITTLE_ENDIAN_BITFIELD */
2449        uint16_t numCiocb;
2450        uint16_t offCiocb;
2451        uint16_t numRiocb;
2452        uint16_t offRiocb;
2453#endif
2454} RING_DEF;
2455
2456typedef struct {
2457#ifdef __BIG_ENDIAN_BITFIELD
2458        uint32_t unused1:24;
2459        uint32_t numRing:8;
2460#else   /*  __LITTLE_ENDIAN_BITFIELD */
2461        uint32_t numRing:8;
2462        uint32_t unused1:24;
2463#endif
2464
2465        RING_DEF ringdef[4];
2466        uint32_t hbainit;
2467} PART_SLIM_VAR;
2468
2469/* Structure for MB Command CONFIG_RING (09) */
2470
2471typedef struct {
2472#ifdef __BIG_ENDIAN_BITFIELD
2473        uint32_t unused2:6;
2474        uint32_t recvSeq:1;
2475        uint32_t recvNotify:1;
2476        uint32_t numMask:8;
2477        uint32_t profile:8;
2478        uint32_t unused1:4;
2479        uint32_t ring:4;
2480#else   /*  __LITTLE_ENDIAN_BITFIELD */
2481        uint32_t ring:4;
2482        uint32_t unused1:4;
2483        uint32_t profile:8;
2484        uint32_t numMask:8;
2485        uint32_t recvNotify:1;
2486        uint32_t recvSeq:1;
2487        uint32_t unused2:6;
2488#endif
2489
2490#ifdef __BIG_ENDIAN_BITFIELD
2491        uint16_t maxRespXchg;
2492        uint16_t maxOrigXchg;
2493#else   /*  __LITTLE_ENDIAN_BITFIELD */
2494        uint16_t maxOrigXchg;
2495        uint16_t maxRespXchg;
2496#endif
2497
2498        RR_REG rrRegs[6];
2499} CONFIG_RING_VAR;
2500
2501/* Structure for MB Command RESET_RING (10) */
2502
2503typedef struct {
2504        uint32_t ring_no;
2505} RESET_RING_VAR;
2506
2507/* Structure for MB Command READ_CONFIG (11) */
2508
2509typedef struct {
2510#ifdef __BIG_ENDIAN_BITFIELD
2511        uint32_t cr:1;
2512        uint32_t ci:1;
2513        uint32_t cr_delay:6;
2514        uint32_t cr_count:8;
2515        uint32_t InitBBC:8;
2516        uint32_t MaxBBC:8;
2517#else   /*  __LITTLE_ENDIAN_BITFIELD */
2518        uint32_t MaxBBC:8;
2519        uint32_t InitBBC:8;
2520        uint32_t cr_count:8;
2521        uint32_t cr_delay:6;
2522        uint32_t ci:1;
2523        uint32_t cr:1;
2524#endif
2525
2526#ifdef __BIG_ENDIAN_BITFIELD
2527        uint32_t topology:8;
2528        uint32_t myDid:24;
2529#else   /*  __LITTLE_ENDIAN_BITFIELD */
2530        uint32_t myDid:24;
2531        uint32_t topology:8;
2532#endif
2533
2534        /* Defines for topology (defined previously) */
2535#ifdef __BIG_ENDIAN_BITFIELD
2536        uint32_t AR:1;
2537        uint32_t IR:1;
2538        uint32_t rsvd1:29;
2539        uint32_t ack0:1;
2540#else   /*  __LITTLE_ENDIAN_BITFIELD */
2541        uint32_t ack0:1;
2542        uint32_t rsvd1:29;
2543        uint32_t IR:1;
2544        uint32_t AR:1;
2545#endif
2546
2547        uint32_t edtov;
2548        uint32_t arbtov;
2549        uint32_t ratov;
2550        uint32_t rttov;
2551        uint32_t altov;
2552        uint32_t lmt;
2553#define LMT_RESERVED  0x000    /* Not used */
2554#define LMT_1Gb       0x004
2555#define LMT_2Gb       0x008
2556#define LMT_4Gb       0x040
2557#define LMT_8Gb       0x080
2558#define LMT_10Gb      0x100
2559#define LMT_16Gb      0x200
2560#define LMT_32Gb      0x400
2561#define LMT_64Gb      0x800
2562#define LMT_128Gb     0x1000
2563#define LMT_256Gb     0x2000
2564        uint32_t rsvd2;
2565        uint32_t rsvd3;
2566        uint32_t max_xri;
2567        uint32_t max_iocb;
2568        uint32_t max_rpi;
2569        uint32_t avail_xri;
2570        uint32_t avail_iocb;
2571        uint32_t avail_rpi;
2572        uint32_t max_vpi;
2573        uint32_t rsvd4;
2574        uint32_t rsvd5;
2575        uint32_t avail_vpi;
2576} READ_CONFIG_VAR;
2577
2578/* Structure for MB Command READ_RCONFIG (12) */
2579
2580typedef struct {
2581#ifdef __BIG_ENDIAN_BITFIELD
2582        uint32_t rsvd2:7;
2583        uint32_t recvNotify:1;
2584        uint32_t numMask:8;
2585        uint32_t profile:8;
2586        uint32_t rsvd1:4;
2587        uint32_t ring:4;
2588#else   /*  __LITTLE_ENDIAN_BITFIELD */
2589        uint32_t ring:4;
2590        uint32_t rsvd1:4;
2591        uint32_t profile:8;
2592        uint32_t numMask:8;
2593        uint32_t recvNotify:1;
2594        uint32_t rsvd2:7;
2595#endif
2596
2597#ifdef __BIG_ENDIAN_BITFIELD
2598        uint16_t maxResp;
2599        uint16_t maxOrig;
2600#else   /*  __LITTLE_ENDIAN_BITFIELD */
2601        uint16_t maxOrig;
2602        uint16_t maxResp;
2603#endif
2604
2605        RR_REG rrRegs[6];
2606
2607#ifdef __BIG_ENDIAN_BITFIELD
2608        uint16_t cmdRingOffset;
2609        uint16_t cmdEntryCnt;
2610        uint16_t rspRingOffset;
2611        uint16_t rspEntryCnt;
2612        uint16_t nextCmdOffset;
2613        uint16_t rsvd3;
2614        uint16_t nextRspOffset;
2615        uint16_t rsvd4;
2616#else   /*  __LITTLE_ENDIAN_BITFIELD */
2617        uint16_t cmdEntryCnt;
2618        uint16_t cmdRingOffset;
2619        uint16_t rspEntryCnt;
2620        uint16_t rspRingOffset;
2621        uint16_t rsvd3;
2622        uint16_t nextCmdOffset;
2623        uint16_t rsvd4;
2624        uint16_t nextRspOffset;
2625#endif
2626} READ_RCONF_VAR;
2627
2628/* Structure for MB Command READ_SPARM (13) */
2629/* Structure for MB Command READ_SPARM64 (0x8D) */
2630
2631typedef struct {
2632        uint32_t rsvd1;
2633        uint32_t rsvd2;
2634        union {
2635                struct ulp_bde sp; /* This BDE points to struct serv_parm
2636                                      structure */
2637                struct ulp_bde64 sp64;
2638        } un;
2639#ifdef __BIG_ENDIAN_BITFIELD
2640        uint16_t rsvd3;
2641        uint16_t vpi;
2642#else   /*  __LITTLE_ENDIAN_BITFIELD */
2643        uint16_t vpi;
2644        uint16_t rsvd3;
2645#endif
2646} READ_SPARM_VAR;
2647
2648/* Structure for MB Command READ_STATUS (14) */
2649
2650typedef struct {
2651#ifdef __BIG_ENDIAN_BITFIELD
2652        uint32_t rsvd1:31;
2653        uint32_t clrCounters:1;
2654        uint16_t activeXriCnt;
2655        uint16_t activeRpiCnt;
2656#else   /*  __LITTLE_ENDIAN_BITFIELD */
2657        uint32_t clrCounters:1;
2658        uint32_t rsvd1:31;
2659        uint16_t activeRpiCnt;
2660        uint16_t activeXriCnt;
2661#endif
2662
2663        uint32_t xmitByteCnt;
2664        uint32_t rcvByteCnt;
2665        uint32_t xmitFrameCnt;
2666        uint32_t rcvFrameCnt;
2667        uint32_t xmitSeqCnt;
2668        uint32_t rcvSeqCnt;
2669        uint32_t totalOrigExchanges;
2670        uint32_t totalRespExchanges;
2671        uint32_t rcvPbsyCnt;
2672        uint32_t rcvFbsyCnt;
2673} READ_STATUS_VAR;
2674
2675/* Structure for MB Command READ_RPI (15) */
2676/* Structure for MB Command READ_RPI64 (0x8F) */
2677
2678typedef struct {
2679#ifdef __BIG_ENDIAN_BITFIELD
2680        uint16_t nextRpi;
2681        uint16_t reqRpi;
2682        uint32_t rsvd2:8;
2683        uint32_t DID:24;
2684#else   /*  __LITTLE_ENDIAN_BITFIELD */
2685        uint16_t reqRpi;
2686        uint16_t nextRpi;
2687        uint32_t DID:24;
2688        uint32_t rsvd2:8;
2689#endif
2690
2691        union {
2692                struct ulp_bde sp;
2693                struct ulp_bde64 sp64;
2694        } un;
2695
2696} READ_RPI_VAR;
2697
2698/* Structure for MB Command READ_XRI (16) */
2699
2700typedef struct {
2701#ifdef __BIG_ENDIAN_BITFIELD
2702        uint16_t nextXri;
2703        uint16_t reqXri;
2704        uint16_t rsvd1;
2705        uint16_t rpi;
2706        uint32_t rsvd2:8;
2707        uint32_t DID:24;
2708        uint32_t rsvd3:8;
2709        uint32_t SID:24;
2710        uint32_t rsvd4;
2711        uint8_t seqId;
2712        uint8_t rsvd5;
2713        uint16_t seqCount;
2714        uint16_t oxId;
2715        uint16_t rxId;
2716        uint32_t rsvd6:30;
2717        uint32_t si:1;
2718        uint32_t exchOrig:1;
2719#else   /*  __LITTLE_ENDIAN_BITFIELD */
2720        uint16_t reqXri;
2721        uint16_t nextXri;
2722        uint16_t rpi;
2723        uint16_t rsvd1;
2724        uint32_t DID:24;
2725        uint32_t rsvd2:8;
2726        uint32_t SID:24;
2727        uint32_t rsvd3:8;
2728        uint32_t rsvd4;
2729        uint16_t seqCount;
2730        uint8_t rsvd5;
2731        uint8_t seqId;
2732        uint16_t rxId;
2733        uint16_t oxId;
2734        uint32_t exchOrig:1;
2735        uint32_t si:1;
2736        uint32_t rsvd6:30;
2737#endif
2738} READ_XRI_VAR;
2739
2740/* Structure for MB Command READ_REV (17) */
2741
2742typedef struct {
2743#ifdef __BIG_ENDIAN_BITFIELD
2744        uint32_t cv:1;
2745        uint32_t rr:1;
2746        uint32_t rsvd2:2;
2747        uint32_t v3req:1;
2748        uint32_t v3rsp:1;
2749        uint32_t rsvd1:25;
2750        uint32_t rv:1;
2751#else   /*  __LITTLE_ENDIAN_BITFIELD */
2752        uint32_t rv:1;
2753        uint32_t rsvd1:25;
2754        uint32_t v3rsp:1;
2755        uint32_t v3req:1;
2756        uint32_t rsvd2:2;
2757        uint32_t rr:1;
2758        uint32_t cv:1;
2759#endif
2760
2761        uint32_t biuRev;
2762        uint32_t smRev;
2763        union {
2764                uint32_t smFwRev;
2765                struct {
2766#ifdef __BIG_ENDIAN_BITFIELD
2767                        uint8_t ProgType;
2768                        uint8_t ProgId;
2769                        uint16_t ProgVer:4;
2770                        uint16_t ProgRev:4;
2771                        uint16_t ProgFixLvl:2;
2772                        uint16_t ProgDistType:2;
2773                        uint16_t DistCnt:4;
2774#else   /*  __LITTLE_ENDIAN_BITFIELD */
2775                        uint16_t DistCnt:4;
2776                        uint16_t ProgDistType:2;
2777                        uint16_t ProgFixLvl:2;
2778                        uint16_t ProgRev:4;
2779                        uint16_t ProgVer:4;
2780                        uint8_t ProgId;
2781                        uint8_t ProgType;
2782#endif
2783
2784                } b;
2785        } un;
2786        uint32_t endecRev;
2787#ifdef __BIG_ENDIAN_BITFIELD
2788        uint8_t feaLevelHigh;
2789        uint8_t feaLevelLow;
2790        uint8_t fcphHigh;
2791        uint8_t fcphLow;
2792#else   /*  __LITTLE_ENDIAN_BITFIELD */
2793        uint8_t fcphLow;
2794        uint8_t fcphHigh;
2795        uint8_t feaLevelLow;
2796        uint8_t feaLevelHigh;
2797#endif
2798
2799        uint32_t postKernRev;
2800        uint32_t opFwRev;
2801        uint8_t opFwName[16];
2802        uint32_t sli1FwRev;
2803        uint8_t sli1FwName[16];
2804        uint32_t sli2FwRev;
2805        uint8_t sli2FwName[16];
2806        uint32_t sli3Feat;
2807        uint32_t RandomData[6];
2808} READ_REV_VAR;
2809
2810/* Structure for MB Command READ_LINK_STAT (18) */
2811
2812typedef struct {
2813        uint32_t word0;
2814
2815#define lpfc_read_link_stat_rec_SHIFT   0
2816#define lpfc_read_link_stat_rec_MASK   0x1
2817#define lpfc_read_link_stat_rec_WORD   word0
2818
2819#define lpfc_read_link_stat_gec_SHIFT   1
2820#define lpfc_read_link_stat_gec_MASK   0x1
2821#define lpfc_read_link_stat_gec_WORD   word0
2822
2823#define lpfc_read_link_stat_w02oftow23of_SHIFT  2
2824#define lpfc_read_link_stat_w02oftow23of_MASK   0x3FFFFF
2825#define lpfc_read_link_stat_w02oftow23of_WORD   word0
2826
2827#define lpfc_read_link_stat_rsvd_SHIFT  24
2828#define lpfc_read_link_stat_rsvd_MASK   0x1F
2829#define lpfc_read_link_stat_rsvd_WORD   word0
2830
2831#define lpfc_read_link_stat_gec2_SHIFT  29
2832#define lpfc_read_link_stat_gec2_MASK   0x1
2833#define lpfc_read_link_stat_gec2_WORD   word0
2834
2835#define lpfc_read_link_stat_clrc_SHIFT  30
2836#define lpfc_read_link_stat_clrc_MASK   0x1
2837#define lpfc_read_link_stat_clrc_WORD   word0
2838
2839#define lpfc_read_link_stat_clof_SHIFT  31
2840#define lpfc_read_link_stat_clof_MASK   0x1
2841#define lpfc_read_link_stat_clof_WORD   word0
2842
2843        uint32_t linkFailureCnt;
2844        uint32_t lossSyncCnt;
2845        uint32_t lossSignalCnt;
2846        uint32_t primSeqErrCnt;
2847        uint32_t invalidXmitWord;
2848        uint32_t crcCnt;
2849        uint32_t primSeqTimeout;
2850        uint32_t elasticOverrun;
2851        uint32_t arbTimeout;
2852        uint32_t advRecBufCredit;
2853        uint32_t curRecBufCredit;
2854        uint32_t advTransBufCredit;
2855        uint32_t curTransBufCredit;
2856        uint32_t recEofCount;
2857        uint32_t recEofdtiCount;
2858        uint32_t recEofniCount;
2859        uint32_t recSofcount;
2860        uint32_t rsvd1;
2861        uint32_t rsvd2;
2862        uint32_t recDrpXriCount;
2863        uint32_t fecCorrBlkCount;
2864        uint32_t fecUncorrBlkCount;
2865} READ_LNK_VAR;
2866
2867/* Structure for MB Command REG_LOGIN (19) */
2868/* Structure for MB Command REG_LOGIN64 (0x93) */
2869
2870typedef struct {
2871#ifdef __BIG_ENDIAN_BITFIELD
2872        uint16_t rsvd1;
2873        uint16_t rpi;
2874        uint32_t rsvd2:8;
2875        uint32_t did:24;
2876#else   /*  __LITTLE_ENDIAN_BITFIELD */
2877        uint16_t rpi;
2878        uint16_t rsvd1;
2879        uint32_t did:24;
2880        uint32_t rsvd2:8;
2881#endif
2882
2883        union {
2884                struct ulp_bde sp;
2885                struct ulp_bde64 sp64;
2886        } un;
2887
2888#ifdef __BIG_ENDIAN_BITFIELD
2889        uint16_t rsvd6;
2890        uint16_t vpi;
2891#else /* __LITTLE_ENDIAN_BITFIELD */
2892        uint16_t vpi;
2893        uint16_t rsvd6;
2894#endif
2895
2896} REG_LOGIN_VAR;
2897
2898/* Word 30 contents for REG_LOGIN */
2899typedef union {
2900        struct {
2901#ifdef __BIG_ENDIAN_BITFIELD
2902                uint16_t rsvd1:12;
2903                uint16_t wd30_class:4;
2904                uint16_t xri;
2905#else   /*  __LITTLE_ENDIAN_BITFIELD */
2906                uint16_t xri;
2907                uint16_t wd30_class:4;
2908                uint16_t rsvd1:12;
2909#endif
2910        } f;
2911        uint32_t word;
2912} REG_WD30;
2913
2914/* Structure for MB Command UNREG_LOGIN (20) */
2915
2916typedef struct {
2917#ifdef __BIG_ENDIAN_BITFIELD
2918        uint16_t rsvd1;
2919        uint16_t rpi;
2920        uint32_t rsvd2;
2921        uint32_t rsvd3;
2922        uint32_t rsvd4;
2923        uint32_t rsvd5;
2924        uint16_t rsvd6;
2925        uint16_t vpi;
2926#else   /*  __LITTLE_ENDIAN_BITFIELD */
2927        uint16_t rpi;
2928        uint16_t rsvd1;
2929        uint32_t rsvd2;
2930        uint32_t rsvd3;
2931        uint32_t rsvd4;
2932        uint32_t rsvd5;
2933        uint16_t vpi;
2934        uint16_t rsvd6;
2935#endif
2936} UNREG_LOGIN_VAR;
2937
2938/* Structure for MB Command REG_VPI (0x96) */
2939typedef struct {
2940#ifdef __BIG_ENDIAN_BITFIELD
2941        uint32_t rsvd1;
2942        uint32_t rsvd2:7;
2943        uint32_t upd:1;
2944        uint32_t sid:24;
2945        uint32_t wwn[2];
2946        uint32_t rsvd5;
2947        uint16_t vfi;
2948        uint16_t vpi;
2949#else   /*  __LITTLE_ENDIAN */
2950        uint32_t rsvd1;
2951        uint32_t sid:24;
2952        uint32_t upd:1;
2953        uint32_t rsvd2:7;
2954        uint32_t wwn[2];
2955        uint32_t rsvd5;
2956        uint16_t vpi;
2957        uint16_t vfi;
2958#endif
2959} REG_VPI_VAR;
2960
2961/* Structure for MB Command UNREG_VPI (0x97) */
2962typedef struct {
2963        uint32_t rsvd1;
2964#ifdef __BIG_ENDIAN_BITFIELD
2965        uint16_t rsvd2;
2966        uint16_t sli4_vpi;
2967#else   /*  __LITTLE_ENDIAN */
2968        uint16_t sli4_vpi;
2969        uint16_t rsvd2;
2970#endif
2971        uint32_t rsvd3;
2972        uint32_t rsvd4;
2973        uint32_t rsvd5;
2974#ifdef __BIG_ENDIAN_BITFIELD
2975        uint16_t rsvd6;
2976        uint16_t vpi;
2977#else   /*  __LITTLE_ENDIAN */
2978        uint16_t vpi;
2979        uint16_t rsvd6;
2980#endif
2981} UNREG_VPI_VAR;
2982
2983/* Structure for MB Command UNREG_D_ID (0x23) */
2984
2985typedef struct {
2986        uint32_t did;
2987        uint32_t rsvd2;
2988        uint32_t rsvd3;
2989        uint32_t rsvd4;
2990        uint32_t rsvd5;
2991#ifdef __BIG_ENDIAN_BITFIELD
2992        uint16_t rsvd6;
2993        uint16_t vpi;
2994#else
2995        uint16_t vpi;
2996        uint16_t rsvd6;
2997#endif
2998} UNREG_D_ID_VAR;
2999
3000/* Structure for MB Command READ_TOPOLOGY (0x95) */
3001struct lpfc_mbx_read_top {
3002        uint32_t eventTag;      /* Event tag */
3003        uint32_t word2;
3004#define lpfc_mbx_read_top_fa_SHIFT              12
3005#define lpfc_mbx_read_top_fa_MASK               0x00000001
3006#define lpfc_mbx_read_top_fa_WORD               word2
3007#define lpfc_mbx_read_top_mm_SHIFT              11
3008#define lpfc_mbx_read_top_mm_MASK               0x00000001
3009#define lpfc_mbx_read_top_mm_WORD               word2
3010#define lpfc_mbx_read_top_pb_SHIFT              9
3011#define lpfc_mbx_read_top_pb_MASK               0X00000001
3012#define lpfc_mbx_read_top_pb_WORD               word2
3013#define lpfc_mbx_read_top_il_SHIFT              8
3014#define lpfc_mbx_read_top_il_MASK               0x00000001
3015#define lpfc_mbx_read_top_il_WORD               word2
3016#define lpfc_mbx_read_top_att_type_SHIFT        0
3017#define lpfc_mbx_read_top_att_type_MASK         0x000000FF
3018#define lpfc_mbx_read_top_att_type_WORD         word2
3019#define LPFC_ATT_RESERVED    0x00       /* Reserved - attType */
3020#define LPFC_ATT_LINK_UP     0x01       /* Link is up */
3021#define LPFC_ATT_LINK_DOWN   0x02       /* Link is down */
3022#define LPFC_ATT_UNEXP_WWPN  0x06       /* Link is down Unexpected WWWPN */
3023        uint32_t word3;
3024#define lpfc_mbx_read_top_alpa_granted_SHIFT    24
3025#define lpfc_mbx_read_top_alpa_granted_MASK     0x000000FF
3026#define lpfc_mbx_read_top_alpa_granted_WORD     word3
3027#define lpfc_mbx_read_top_lip_alps_SHIFT        16
3028#define lpfc_mbx_read_top_lip_alps_MASK         0x000000FF
3029#define lpfc_mbx_read_top_lip_alps_WORD         word3
3030#define lpfc_mbx_read_top_lip_type_SHIFT        8
3031#define lpfc_mbx_read_top_lip_type_MASK         0x000000FF
3032#define lpfc_mbx_read_top_lip_type_WORD         word3
3033#define lpfc_mbx_read_top_topology_SHIFT        0
3034#define lpfc_mbx_read_top_topology_MASK         0x000000FF
3035#define lpfc_mbx_read_top_topology_WORD         word3
3036#define LPFC_TOPOLOGY_PT_PT 0x01        /* Topology is pt-pt / pt-fabric */
3037#define LPFC_TOPOLOGY_LOOP  0x02        /* Topology is FC-AL */
3038#define LPFC_TOPOLOGY_MM    0x05        /* maint mode zephtr to menlo */
3039        /* store the LILP AL_PA position map into */
3040        struct ulp_bde64 lilpBde64;
3041#define LPFC_ALPA_MAP_SIZE      128
3042        uint32_t word7;
3043#define lpfc_mbx_read_top_ld_lu_SHIFT           31
3044#define lpfc_mbx_read_top_ld_lu_MASK            0x00000001
3045#define lpfc_mbx_read_top_ld_lu_WORD            word7
3046#define lpfc_mbx_read_top_ld_tf_SHIFT           30
3047#define lpfc_mbx_read_top_ld_tf_MASK            0x00000001
3048#define lpfc_mbx_read_top_ld_tf_WORD            word7
3049#define lpfc_mbx_read_top_ld_link_spd_SHIFT     8
3050#define lpfc_mbx_read_top_ld_link_spd_MASK      0x000000FF
3051#define lpfc_mbx_read_top_ld_link_spd_WORD      word7
3052#define lpfc_mbx_read_top_ld_nl_port_SHIFT      4
3053#define lpfc_mbx_read_top_ld_nl_port_MASK       0x0000000F
3054#define lpfc_mbx_read_top_ld_nl_port_WORD       word7
3055#define lpfc_mbx_read_top_ld_tx_SHIFT           2
3056#define lpfc_mbx_read_top_ld_tx_MASK            0x00000003
3057#define lpfc_mbx_read_top_ld_tx_WORD            word7
3058#define lpfc_mbx_read_top_ld_rx_SHIFT           0
3059#define lpfc_mbx_read_top_ld_rx_MASK            0x00000003
3060#define lpfc_mbx_read_top_ld_rx_WORD            word7
3061        uint32_t word8;
3062#define lpfc_mbx_read_top_lu_SHIFT              31
3063#define lpfc_mbx_read_top_lu_MASK               0x00000001
3064#define lpfc_mbx_read_top_lu_WORD               word8
3065#define lpfc_mbx_read_top_tf_SHIFT              30
3066#define lpfc_mbx_read_top_tf_MASK               0x00000001
3067#define lpfc_mbx_read_top_tf_WORD               word8
3068#define lpfc_mbx_read_top_link_spd_SHIFT        8
3069#define lpfc_mbx_read_top_link_spd_MASK         0x000000FF
3070#define lpfc_mbx_read_top_link_spd_WORD         word8
3071#define lpfc_mbx_read_top_nl_port_SHIFT         4
3072#define lpfc_mbx_read_top_nl_port_MASK          0x0000000F
3073#define lpfc_mbx_read_top_nl_port_WORD          word8
3074#define lpfc_mbx_read_top_tx_SHIFT              2
3075#define lpfc_mbx_read_top_tx_MASK               0x00000003
3076#define lpfc_mbx_read_top_tx_WORD               word8
3077#define lpfc_mbx_read_top_rx_SHIFT              0
3078#define lpfc_mbx_read_top_rx_MASK               0x00000003
3079#define lpfc_mbx_read_top_rx_WORD               word8
3080#define LPFC_LINK_SPEED_UNKNOWN 0x0
3081#define LPFC_LINK_SPEED_1GHZ    0x04
3082#define LPFC_LINK_SPEED_2GHZ    0x08
3083#define LPFC_LINK_SPEED_4GHZ    0x10
3084#define LPFC_LINK_SPEED_8GHZ    0x20
3085#define LPFC_LINK_SPEED_10GHZ   0x40
3086#define LPFC_LINK_SPEED_16GHZ   0x80
3087#define LPFC_LINK_SPEED_32GHZ   0x90
3088#define LPFC_LINK_SPEED_64GHZ   0xA0
3089#define LPFC_LINK_SPEED_128GHZ  0xB0
3090#define LPFC_LINK_SPEED_256GHZ  0xC0
3091};
3092
3093/* Structure for MB Command CLEAR_LA (22) */
3094
3095typedef struct {
3096        uint32_t eventTag;      /* Event tag */
3097        uint32_t rsvd1;
3098} CLEAR_LA_VAR;
3099
3100/* Structure for MB Command DUMP */
3101
3102typedef struct {
3103#ifdef __BIG_ENDIAN_BITFIELD
3104        uint32_t rsvd:25;
3105        uint32_t ra:1;
3106        uint32_t co:1;
3107        uint32_t cv:1;
3108        uint32_t type:4;
3109        uint32_t entry_index:16;
3110        uint32_t region_id:16;
3111#else   /*  __LITTLE_ENDIAN_BITFIELD */
3112        uint32_t type:4;
3113        uint32_t cv:1;
3114        uint32_t co:1;
3115        uint32_t ra:1;
3116        uint32_t rsvd:25;
3117        uint32_t region_id:16;
3118        uint32_t entry_index:16;
3119#endif
3120
3121        uint32_t sli4_length;
3122        uint32_t word_cnt;
3123        uint32_t resp_offset;
3124} DUMP_VAR;
3125
3126#define  DMP_MEM_REG             0x1
3127#define  DMP_NV_PARAMS           0x2
3128#define  DMP_LMSD                0x3 /* Link Module Serial Data */
3129#define  DMP_WELL_KNOWN          0x4
3130
3131#define  DMP_REGION_VPD          0xe
3132#define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
3133#define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
3134#define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
3135
3136#define  DMP_REGION_VPORT        0x16   /* VPort info region */
3137#define  DMP_VPORT_REGION_SIZE   0x200
3138#define  DMP_MBOX_OFFSET_WORD    0x5
3139
3140#define  DMP_REGION_23           0x17   /* fcoe param  and port state region */
3141#define  DMP_RGN23_SIZE          0x400
3142
3143#define  WAKE_UP_PARMS_REGION_ID    4
3144#define  WAKE_UP_PARMS_WORD_SIZE   15
3145
3146struct vport_rec {
3147        uint8_t wwpn[8];
3148        uint8_t wwnn[8];
3149};
3150
3151#define VPORT_INFO_SIG 0x32324752
3152#define VPORT_INFO_REV_MASK 0xff
3153#define VPORT_INFO_REV 0x1
3154#define MAX_STATIC_VPORT_COUNT 16
3155struct static_vport_info {
3156        uint32_t                signature;
3157        uint32_t                rev;
3158        struct vport_rec        vport_list[MAX_STATIC_VPORT_COUNT];
3159        uint32_t                resvd[66];
3160};
3161
3162/* Option rom version structure */
3163struct prog_id {
3164#ifdef __BIG_ENDIAN_BITFIELD
3165        uint8_t  type;
3166        uint8_t  id;
3167        uint32_t ver:4;  /* Major Version */
3168        uint32_t rev:4;  /* Revision */
3169        uint32_t lev:2;  /* Level */
3170        uint32_t dist:2; /* Dist Type */
3171        uint32_t num:4;  /* number after dist type */
3172#else /*  __LITTLE_ENDIAN_BITFIELD */
3173        uint32_t num:4;  /* number after dist type */
3174        uint32_t dist:2; /* Dist Type */
3175        uint32_t lev:2;  /* Level */
3176        uint32_t rev:4;  /* Revision */
3177        uint32_t ver:4;  /* Major Version */
3178        uint8_t  id;
3179        uint8_t  type;
3180#endif
3181};
3182
3183/* Structure for MB Command UPDATE_CFG (0x1B) */
3184
3185struct update_cfg_var {
3186#ifdef __BIG_ENDIAN_BITFIELD
3187        uint32_t rsvd2:16;
3188        uint32_t type:8;
3189        uint32_t rsvd:1;
3190        uint32_t ra:1;
3191        uint32_t co:1;
3192        uint32_t cv:1;
3193        uint32_t req:4;
3194        uint32_t entry_length:16;
3195        uint32_t region_id:16;
3196#else  /*  __LITTLE_ENDIAN_BITFIELD */
3197        uint32_t req:4;
3198        uint32_t cv:1;
3199        uint32_t co:1;
3200        uint32_t ra:1;
3201        uint32_t rsvd:1;
3202        uint32_t type:8;
3203        uint32_t rsvd2:16;
3204        uint32_t region_id:16;
3205        uint32_t entry_length:16;
3206#endif
3207
3208        uint32_t resp_info;
3209        uint32_t byte_cnt;
3210        uint32_t data_offset;
3211};
3212
3213struct hbq_mask {
3214#ifdef __BIG_ENDIAN_BITFIELD
3215        uint8_t tmatch;
3216        uint8_t tmask;
3217        uint8_t rctlmatch;
3218        uint8_t rctlmask;
3219#else   /*  __LITTLE_ENDIAN */
3220        uint8_t rctlmask;
3221        uint8_t rctlmatch;
3222        uint8_t tmask;
3223        uint8_t tmatch;
3224#endif
3225};
3226
3227
3228/* Structure for MB Command CONFIG_HBQ (7c) */
3229
3230struct config_hbq_var {
3231#ifdef __BIG_ENDIAN_BITFIELD
3232        uint32_t rsvd1      :7;
3233        uint32_t recvNotify :1;     /* Receive Notification */
3234        uint32_t numMask    :8;     /* # Mask Entries       */
3235        uint32_t profile    :8;     /* Selection Profile    */
3236        uint32_t rsvd2      :8;
3237#else   /*  __LITTLE_ENDIAN */
3238        uint32_t rsvd2      :8;
3239        uint32_t profile    :8;     /* Selection Profile    */
3240        uint32_t numMask    :8;     /* # Mask Entries       */
3241        uint32_t recvNotify :1;     /* Receive Notification */
3242        uint32_t rsvd1      :7;
3243#endif
3244
3245#ifdef __BIG_ENDIAN_BITFIELD
3246        uint32_t hbqId      :16;
3247        uint32_t rsvd3      :12;
3248        uint32_t ringMask   :4;
3249#else   /*  __LITTLE_ENDIAN */
3250        uint32_t ringMask   :4;
3251        uint32_t rsvd3      :12;
3252        uint32_t hbqId      :16;
3253#endif
3254
3255#ifdef __BIG_ENDIAN_BITFIELD
3256        uint32_t entry_count :16;
3257        uint32_t rsvd4        :8;
3258        uint32_t headerLen    :8;
3259#else   /*  __LITTLE_ENDIAN */
3260        uint32_t headerLen    :8;
3261        uint32_t rsvd4        :8;
3262        uint32_t entry_count :16;
3263#endif
3264
3265        uint32_t hbqaddrLow;
3266        uint32_t hbqaddrHigh;
3267
3268#ifdef __BIG_ENDIAN_BITFIELD
3269        uint32_t rsvd5      :31;
3270        uint32_t logEntry   :1;
3271#else   /*  __LITTLE_ENDIAN */
3272        uint32_t logEntry   :1;
3273        uint32_t rsvd5      :31;
3274#endif
3275
3276        uint32_t rsvd6;    /* w7 */
3277        uint32_t rsvd7;    /* w8 */
3278        uint32_t rsvd8;    /* w9 */
3279
3280        struct hbq_mask hbqMasks[6];
3281
3282
3283        union {
3284                uint32_t allprofiles[12];
3285
3286                struct {
3287                        #ifdef __BIG_ENDIAN_BITFIELD
3288                                uint32_t        seqlenoff       :16;
3289                                uint32_t        maxlen          :16;
3290                        #else   /*  __LITTLE_ENDIAN */
3291                                uint32_t        maxlen          :16;
3292                                uint32_t        seqlenoff       :16;
3293                        #endif
3294                        #ifdef __BIG_ENDIAN_BITFIELD
3295                                uint32_t        rsvd1           :28;
3296                                uint32_t        seqlenbcnt      :4;
3297                        #else   /*  __LITTLE_ENDIAN */
3298                                uint32_t        seqlenbcnt      :4;
3299                                uint32_t        rsvd1           :28;
3300                        #endif
3301                        uint32_t rsvd[10];
3302                } profile2;
3303
3304                struct {
3305                        #ifdef __BIG_ENDIAN_BITFIELD
3306                                uint32_t        seqlenoff       :16;
3307                                uint32_t        maxlen          :16;
3308                        #else   /*  __LITTLE_ENDIAN */
3309                                uint32_t        maxlen          :16;
3310                                uint32_t        seqlenoff       :16;
3311                        #endif
3312                        #ifdef __BIG_ENDIAN_BITFIELD
3313                                uint32_t        cmdcodeoff      :28;
3314                                uint32_t        rsvd1           :12;
3315                                uint32_t        seqlenbcnt      :4;
3316                        #else   /*  __LITTLE_ENDIAN */
3317                                uint32_t        seqlenbcnt      :4;
3318                                uint32_t        rsvd1           :12;
3319                                uint32_t        cmdcodeoff      :28;
3320                        #endif
3321                        uint32_t cmdmatch[8];
3322
3323                        uint32_t rsvd[2];
3324                } profile3;
3325
3326                struct {
3327                        #ifdef __BIG_ENDIAN_BITFIELD
3328                                uint32_t        seqlenoff       :16;
3329                                uint32_t        maxlen          :16;
3330                        #else   /*  __LITTLE_ENDIAN */
3331                                uint32_t        maxlen          :16;
3332                                uint32_t        seqlenoff       :16;
3333                        #endif
3334                        #ifdef __BIG_ENDIAN_BITFIELD
3335                                uint32_t        cmdcodeoff      :28;
3336                                uint32_t        rsvd1           :12;
3337                                uint32_t        seqlenbcnt      :4;
3338                        #else   /*  __LITTLE_ENDIAN */
3339                                uint32_t        seqlenbcnt      :4;
3340                                uint32_t        rsvd1           :12;
3341                                uint32_t        cmdcodeoff      :28;
3342                        #endif
3343                        uint32_t cmdmatch[8];
3344
3345                        uint32_t rsvd[2];
3346                } profile5;
3347
3348        } profiles;
3349
3350};
3351
3352
3353
3354/* Structure for MB Command CONFIG_PORT (0x88) */
3355typedef struct {
3356#ifdef __BIG_ENDIAN_BITFIELD
3357        uint32_t cBE       :  1;
3358        uint32_t cET       :  1;
3359        uint32_t cHpcb     :  1;
3360        uint32_t cMA       :  1;
3361        uint32_t sli_mode  :  4;
3362        uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
3363                                        * config block */
3364#else   /*  __LITTLE_ENDIAN */
3365        uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
3366                                        * config block */
3367        uint32_t sli_mode  :  4;
3368        uint32_t cMA       :  1;
3369        uint32_t cHpcb     :  1;
3370        uint32_t cET       :  1;
3371        uint32_t cBE       :  1;
3372#endif
3373
3374        uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
3375        uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
3376        uint32_t hbainit[5];
3377#ifdef __BIG_ENDIAN_BITFIELD
3378        uint32_t hps       :  1; /* bit 31 word9 Host Pointer in slim */
3379        uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
3380#else   /*  __LITTLE_ENDIAN */
3381        uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
3382        uint32_t hps       :  1; /* bit 31 word9 Host Pointer in slim */
3383#endif
3384
3385#ifdef __BIG_ENDIAN_BITFIELD
3386        uint32_t rsvd1     : 20;  /* Reserved                             */
3387        uint32_t casabt    :  1;  /* Configure async abts status notice   */
3388        uint32_t rsvd2     :  2;  /* Reserved                             */
3389        uint32_t cbg       :  1;  /* Configure BlockGuard                 */
3390        uint32_t cmv       :  1;  /* Configure Max VPIs                   */
3391        uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
3392        uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
3393        uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
3394        uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
3395        uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
3396        uint32_t cmx       :  1;  /* Configure Max XRIs                   */
3397        uint32_t cmr       :  1;  /* Configure Max RPIs                   */
3398#else   /*  __LITTLE_ENDIAN */
3399        uint32_t cmr       :  1;  /* Configure Max RPIs                   */
3400        uint32_t cmx       :  1;  /* Configure Max XRIs                   */
3401        uint32_t cerbm     :  1;  /* Configure Enhanced Receive Buf Mgmt  */
3402        uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
3403        uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
3404        uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
3405        uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
3406        uint32_t cmv       :  1;  /* Configure Max VPIs                   */
3407        uint32_t cbg       :  1;  /* Configure BlockGuard                 */
3408        uint32_t rsvd2     :  2;  /* Reserved                             */
3409        uint32_t casabt    :  1;  /* Configure async abts status notice   */
3410        uint32_t rsvd1     : 20;  /* Reserved                             */
3411#endif
3412#ifdef __BIG_ENDIAN_BITFIELD
3413        uint32_t rsvd3     : 20;  /* Reserved                             */
3414        uint32_t gasabt    :  1;  /* Grant async abts status notice       */
3415        uint32_t rsvd4     :  2;  /* Reserved                             */
3416        uint32_t gbg       :  1;  /* Grant BlockGuard                     */
3417        uint32_t gmv       :  1;  /* Grant Max VPIs                       */
3418        uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
3419        uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
3420        uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
3421        uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
3422        uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
3423        uint32_t gmx       :  1;  /* Grant Max XRIs                       */
3424        uint32_t gmr       :  1;  /* Grant Max RPIs                       */
3425#else   /*  __LITTLE_ENDIAN */
3426        uint32_t gmr       :  1;  /* Grant Max RPIs                       */
3427        uint32_t gmx       :  1;  /* Grant Max XRIs                       */
3428        uint32_t gerbm     :  1;  /* Grant ERBM Request                   */
3429        uint32_t ginb      :  1;  /* Grant Interrupt Notification Block   */
3430        uint32_t ghbs      :  1;  /* Grant Host Backing Store             */
3431        uint32_t gsah      :  1;  /* Grant Synchronous Abort Handling     */
3432        uint32_t gcrp      :  1;  /* Grant Command Ring Polling           */
3433        uint32_t gmv       :  1;  /* Grant Max VPIs                       */
3434        uint32_t gbg       :  1;  /* Grant BlockGuard                     */
3435        uint32_t rsvd4     :  2;  /* Reserved                             */
3436        uint32_t gasabt    :  1;  /* Grant async abts status notice       */
3437        uint32_t rsvd3     : 20;  /* Reserved                             */
3438#endif
3439
3440#ifdef __BIG_ENDIAN_BITFIELD
3441        uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
3442        uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
3443#else   /*  __LITTLE_ENDIAN */
3444        uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
3445        uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
3446#endif
3447
3448#ifdef __BIG_ENDIAN_BITFIELD
3449        uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
3450        uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
3451#else   /*  __LITTLE_ENDIAN */
3452        uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
3453        uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
3454#endif
3455
3456        uint32_t rsvd6;           /* Reserved                             */
3457
3458#ifdef __BIG_ENDIAN_BITFIELD
3459        uint32_t rsvd7      : 16;
3460        uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
3461#else   /*  __LITTLE_ENDIAN */
3462        uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
3463        uint32_t rsvd7      : 16;
3464#endif
3465
3466} CONFIG_PORT_VAR;
3467
3468/* Structure for MB Command CONFIG_MSI (0x30) */
3469struct config_msi_var {
3470#ifdef __BIG_ENDIAN_BITFIELD
3471        uint32_t dfltMsgNum:8;  /* Default message number            */
3472        uint32_t rsvd1:11;      /* Reserved                          */
3473        uint32_t NID:5;         /* Number of secondary attention IDs */
3474        uint32_t rsvd2:5;       /* Reserved                          */
3475        uint32_t dfltPresent:1; /* Default message number present    */
3476        uint32_t addFlag:1;     /* Add association flag              */
3477        uint32_t reportFlag:1;  /* Report association flag           */
3478#else   /*  __LITTLE_ENDIAN_BITFIELD */
3479        uint32_t reportFlag:1;  /* Report association flag           */
3480        uint32_t addFlag:1;     /* Add association flag              */
3481        uint32_t dfltPresent:1; /* Default message number present    */
3482        uint32_t rsvd2:5;       /* Reserved                          */
3483        uint32_t NID:5;         /* Number of secondary attention IDs */
3484        uint32_t rsvd1:11;      /* Reserved                          */
3485        uint32_t dfltMsgNum:8;  /* Default message number            */
3486#endif
3487        uint32_t attentionConditions[2];
3488        uint8_t  attentionId[16];
3489        uint8_t  messageNumberByHA[64];
3490        uint8_t  messageNumberByID[16];
3491        uint32_t autoClearHA[2];
3492#ifdef __BIG_ENDIAN_BITFIELD
3493        uint32_t rsvd3:16;
3494        uint32_t autoClearID:16;
3495#else   /*  __LITTLE_ENDIAN_BITFIELD */
3496        uint32_t autoClearID:16;
3497        uint32_t rsvd3:16;
3498#endif
3499        uint32_t rsvd4;
3500};
3501
3502/* SLI-2 Port Control Block */
3503
3504/* SLIM POINTER */
3505#define SLIMOFF 0x30            /* WORD */
3506
3507typedef struct _SLI2_RDSC {
3508        uint32_t cmdEntries;
3509        uint32_t cmdAddrLow;
3510        uint32_t cmdAddrHigh;
3511
3512        uint32_t rspEntries;
3513        uint32_t rspAddrLow;
3514        uint32_t rspAddrHigh;
3515} SLI2_RDSC;
3516
3517typedef struct _PCB {
3518#ifdef __BIG_ENDIAN_BITFIELD
3519        uint32_t type:8;
3520#define TYPE_NATIVE_SLI2       0x01
3521        uint32_t feature:8;
3522#define FEATURE_INITIAL_SLI2   0x01
3523        uint32_t rsvd:12;
3524        uint32_t maxRing:4;
3525#else   /*  __LITTLE_ENDIAN_BITFIELD */
3526        uint32_t maxRing:4;
3527        uint32_t rsvd:12;
3528        uint32_t feature:8;
3529#define FEATURE_INITIAL_SLI2   0x01
3530        uint32_t type:8;
3531#define TYPE_NATIVE_SLI2       0x01
3532#endif
3533
3534        uint32_t mailBoxSize;
3535        uint32_t mbAddrLow;
3536        uint32_t mbAddrHigh;
3537
3538        uint32_t hgpAddrLow;
3539        uint32_t hgpAddrHigh;
3540
3541        uint32_t pgpAddrLow;
3542        uint32_t pgpAddrHigh;
3543        SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3544} PCB_t;
3545
3546/* NEW_FEATURE */
3547typedef struct {
3548#ifdef __BIG_ENDIAN_BITFIELD
3549        uint32_t rsvd0:27;
3550        uint32_t discardFarp:1;
3551        uint32_t IPEnable:1;
3552        uint32_t nodeName:1;
3553        uint32_t portName:1;
3554        uint32_t filterEnable:1;
3555#else   /*  __LITTLE_ENDIAN_BITFIELD */
3556        uint32_t filterEnable:1;
3557        uint32_t portName:1;
3558        uint32_t nodeName:1;
3559        uint32_t IPEnable:1;
3560        uint32_t discardFarp:1;
3561        uint32_t rsvd:27;
3562#endif
3563
3564        uint8_t portname[8];    /* Used to be struct lpfc_name */
3565        uint8_t nodename[8];
3566        uint32_t rsvd1;
3567        uint32_t rsvd2;
3568        uint32_t rsvd3;
3569        uint32_t IPAddress;
3570} CONFIG_FARP_VAR;
3571
3572/* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3573
3574typedef struct {
3575#ifdef __BIG_ENDIAN_BITFIELD
3576        uint32_t rsvd:30;
3577        uint32_t ring:2;        /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3578#else /*  __LITTLE_ENDIAN */
3579        uint32_t ring:2;        /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3580        uint32_t rsvd:30;
3581#endif
3582} ASYNCEVT_ENABLE_VAR;
3583
3584/* Union of all Mailbox Command types */
3585#define MAILBOX_CMD_WSIZE       32
3586#define MAILBOX_CMD_SIZE        (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3587/* ext_wsize times 4 bytes should not be greater than max xmit size */
3588#define MAILBOX_EXT_WSIZE       512
3589#define MAILBOX_EXT_SIZE        (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3590#define MAILBOX_HBA_EXT_OFFSET  0x100
3591/* max mbox xmit size is a page size for sysfs IO operations */
3592#define MAILBOX_SYSFS_MAX       4096
3593
3594typedef union {
3595        uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3596                                                    * feature/max ring number
3597                                                    */
3598        LOAD_SM_VAR varLdSM;            /* cmd =  1 (LOAD_SM)        */
3599        READ_NV_VAR varRDnvp;           /* cmd =  2 (READ_NVPARMS)   */
3600        WRITE_NV_VAR varWTnvp;          /* cmd =  3 (WRITE_NVPARMS)  */
3601        BIU_DIAG_VAR varBIUdiag;        /* cmd =  4 (RUN_BIU_DIAG)   */
3602        INIT_LINK_VAR varInitLnk;       /* cmd =  5 (INIT_LINK)      */
3603        DOWN_LINK_VAR varDwnLnk;        /* cmd =  6 (DOWN_LINK)      */
3604        CONFIG_LINK varCfgLnk;          /* cmd =  7 (CONFIG_LINK)    */
3605        PART_SLIM_VAR varSlim;          /* cmd =  8 (PART_SLIM)      */
3606        CONFIG_RING_VAR varCfgRing;     /* cmd =  9 (CONFIG_RING)    */
3607        RESET_RING_VAR varRstRing;      /* cmd = 10 (RESET_RING)     */
3608        READ_CONFIG_VAR varRdConfig;    /* cmd = 11 (READ_CONFIG)    */
3609        READ_RCONF_VAR varRdRConfig;    /* cmd = 12 (READ_RCONFIG)   */
3610        READ_SPARM_VAR varRdSparm;      /* cmd = 13 (READ_SPARM(64)) */
3611        READ_STATUS_VAR varRdStatus;    /* cmd = 14 (READ_STATUS)    */
3612        READ_RPI_VAR varRdRPI;          /* cmd = 15 (READ_RPI(64))   */
3613        READ_XRI_VAR varRdXRI;          /* cmd = 16 (READ_XRI)       */
3614        READ_REV_VAR varRdRev;          /* cmd = 17 (READ_REV)       */
3615        READ_LNK_VAR varRdLnk;          /* cmd = 18 (READ_LNK_STAT)  */
3616        REG_LOGIN_VAR varRegLogin;      /* cmd = 19 (REG_LOGIN(64))  */
3617        UNREG_LOGIN_VAR varUnregLogin;  /* cmd = 20 (UNREG_LOGIN)    */
3618        CLEAR_LA_VAR varClearLA;        /* cmd = 22 (CLEAR_LA)       */
3619        DUMP_VAR varDmp;                /* Warm Start DUMP mbx cmd   */
3620        UNREG_D_ID_VAR varUnregDID;     /* cmd = 0x23 (UNREG_D_ID)   */
3621        CONFIG_FARP_VAR varCfgFarp;     /* cmd = 0x25 (CONFIG_FARP)
3622                                         * NEW_FEATURE
3623                                         */
3624        struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ)  */
3625        struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3626        CONFIG_PORT_VAR varCfgPort;     /* cmd = 0x88 (CONFIG_PORT)  */
3627        struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3628        REG_VPI_VAR varRegVpi;          /* cmd = 0x96 (REG_VPI) */
3629        UNREG_VPI_VAR varUnregVpi;      /* cmd = 0x97 (UNREG_VPI) */
3630        ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3631        struct READ_EVENT_LOG_VAR varRdEventLog;        /* cmd = 0x38
3632                                                         * (READ_EVENT_LOG)
3633                                                         */
3634        struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI)     */
3635} MAILVARIANTS;
3636
3637/*
3638 * SLI-2 specific structures
3639 */
3640
3641struct lpfc_hgp {
3642        __le32 cmdPutInx;
3643        __le32 rspGetInx;
3644};
3645
3646struct lpfc_pgp {
3647        __le32 cmdGetInx;
3648        __le32 rspPutInx;
3649};
3650
3651struct sli2_desc {
3652        uint32_t unused1[16];
3653        struct lpfc_hgp host[MAX_SLI3_RINGS];
3654        struct lpfc_pgp port[MAX_SLI3_RINGS];
3655};
3656
3657struct sli3_desc {
3658        struct lpfc_hgp host[MAX_SLI3_RINGS];
3659        uint32_t reserved[8];
3660        uint32_t hbq_put[16];
3661};
3662
3663struct sli3_pgp {
3664        struct lpfc_pgp port[MAX_SLI3_RINGS];
3665        uint32_t hbq_get[16];
3666};
3667
3668union sli_var {
3669        struct sli2_desc        s2;
3670        struct sli3_desc        s3;
3671        struct sli3_pgp         s3_pgp;
3672};
3673
3674typedef struct {
3675#ifdef __BIG_ENDIAN_BITFIELD
3676        uint16_t mbxStatus;
3677        uint8_t mbxCommand;
3678        uint8_t mbxReserved:6;
3679        uint8_t mbxHc:1;
3680        uint8_t mbxOwner:1;     /* Low order bit first word */
3681#else   /*  __LITTLE_ENDIAN_BITFIELD */
3682        uint8_t mbxOwner:1;     /* Low order bit first word */
3683        uint8_t mbxHc:1;
3684        uint8_t mbxReserved:6;
3685        uint8_t mbxCommand;
3686        uint16_t mbxStatus;
3687#endif
3688
3689        MAILVARIANTS un;
3690        union sli_var us;
3691} MAILBOX_t;
3692
3693/*
3694 *    Begin Structure Definitions for IOCB Commands
3695 */
3696
3697typedef struct {
3698#ifdef __BIG_ENDIAN_BITFIELD
3699        uint8_t statAction;
3700        uint8_t statRsn;
3701        uint8_t statBaExp;
3702        uint8_t statLocalError;
3703#else   /*  __LITTLE_ENDIAN_BITFIELD */
3704        uint8_t statLocalError;
3705        uint8_t statBaExp;
3706        uint8_t statRsn;
3707        uint8_t statAction;
3708#endif
3709        /* statRsn  P/F_RJT reason codes */
3710#define RJT_BAD_D_ID       0x01 /* Invalid D_ID field */
3711#define RJT_BAD_S_ID       0x02 /* Invalid S_ID field */
3712#define RJT_UNAVAIL_TEMP   0x03 /* N_Port unavailable temp. */
3713#define RJT_UNAVAIL_PERM   0x04 /* N_Port unavailable perm. */
3714#define RJT_UNSUP_CLASS    0x05 /* Class not supported */
3715#define RJT_DELIM_ERR      0x06 /* Delimiter usage error */
3716#define RJT_UNSUP_TYPE     0x07 /* Type not supported */
3717#define RJT_BAD_CONTROL    0x08 /* Invalid link conrtol */
3718#define RJT_BAD_RCTL       0x09 /* R_CTL invalid */
3719#define RJT_BAD_FCTL       0x0A /* F_CTL invalid */
3720#define RJT_BAD_OXID       0x0B /* OX_ID invalid */
3721#define RJT_BAD_RXID       0x0C /* RX_ID invalid */
3722#define RJT_BAD_SEQID      0x0D /* SEQ_ID invalid */
3723#define RJT_BAD_DFCTL      0x0E /* DF_CTL invalid */
3724#define RJT_BAD_SEQCNT     0x0F /* SEQ_CNT invalid */
3725#define RJT_BAD_PARM       0x10 /* Param. field invalid */
3726#define RJT_XCHG_ERR       0x11 /* Exchange error */
3727#define RJT_PROT_ERR       0x12 /* Protocol error */
3728#define RJT_BAD_LENGTH     0x13 /* Invalid Length */
3729#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3730#define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3731#define RJT_TOO_MANY_SEQ   0x17 /* Excessive sequences */
3732#define RJT_XCHG_NOT_STRT  0x18 /* Exchange not started */
3733#define RJT_UNSUP_SEC_HDR  0x19 /* Security hdr not supported */
3734#define RJT_UNAVAIL_PATH   0x1A /* Fabric Path not available */
3735#define RJT_VENDOR_UNIQUE  0xFF /* Vendor unique error */
3736
3737#define IOERR_SUCCESS                 0x00      /* statLocalError */
3738#define IOERR_MISSING_CONTINUE        0x01
3739#define IOERR_SEQUENCE_TIMEOUT        0x02
3740#define IOERR_INTERNAL_ERROR          0x03
3741#define IOERR_INVALID_RPI             0x04
3742#define IOERR_NO_XRI                  0x05
3743#define IOERR_ILLEGAL_COMMAND         0x06
3744#define IOERR_XCHG_DROPPED            0x07
3745#define IOERR_ILLEGAL_FIELD           0x08
3746#define IOERR_BAD_CONTINUE            0x09
3747#define IOERR_TOO_MANY_BUFFERS        0x0A
3748#define IOERR_RCV_BUFFER_WAITING      0x0B
3749#define IOERR_NO_CONNECTION           0x0C
3750#define IOERR_TX_DMA_FAILED           0x0D
3751#define IOERR_RX_DMA_FAILED           0x0E
3752#define IOERR_ILLEGAL_FRAME           0x0F
3753#define IOERR_EXTRA_DATA              0x10
3754#define IOERR_NO_RESOURCES            0x11
3755#define IOERR_RESERVED                0x12
3756#define IOERR_ILLEGAL_LENGTH          0x13
3757#define IOERR_UNSUPPORTED_FEATURE     0x14
3758#define IOERR_ABORT_IN_PROGRESS       0x15
3759#define IOERR_ABORT_REQUESTED         0x16
3760#define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
3761#define IOERR_LOOP_OPEN_FAILURE       0x18
3762#define IOERR_RING_RESET              0x19
3763#define IOERR_LINK_DOWN               0x1A
3764#define IOERR_CORRUPTED_DATA          0x1B
3765#define IOERR_CORRUPTED_RPI           0x1C
3766#define IOERR_OUT_OF_ORDER_DATA       0x1D
3767#define IOERR_OUT_OF_ORDER_ACK        0x1E
3768#define IOERR_DUP_FRAME               0x1F
3769#define IOERR_LINK_CONTROL_FRAME      0x20      /* ACK_N received */
3770#define IOERR_BAD_HOST_ADDRESS        0x21
3771#define IOERR_RCV_HDRBUF_WAITING      0x22
3772#define IOERR_MISSING_HDR_BUFFER      0x23
3773#define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
3774#define IOERR_ABORTMULT_REQUESTED     0x25
3775#define IOERR_BUFFER_SHORTAGE         0x28
3776#define IOERR_DEFAULT                 0x29
3777#define IOERR_CNT                     0x2A
3778#define IOERR_SLER_FAILURE            0x46
3779#define IOERR_SLER_CMD_RCV_FAILURE    0x47
3780#define IOERR_SLER_REC_RJT_ERR        0x48
3781#define IOERR_SLER_REC_SRR_RETRY_ERR  0x49
3782#define IOERR_SLER_SRR_RJT_ERR        0x4A
3783#define IOERR_SLER_RRQ_RJT_ERR        0x4C
3784#define IOERR_SLER_RRQ_RETRY_ERR      0x4D
3785#define IOERR_SLER_ABTS_ERR           0x4E
3786#define IOERR_ELXSEC_KEY_UNWRAP_ERROR           0xF0
3787#define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR   0xF1
3788#define IOERR_ELXSEC_CRYPTO_ERROR               0xF2
3789#define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR       0xF3
3790#define IOERR_DRVR_MASK               0x100
3791#define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
3792#define IOERR_SLI_BRESET              0x102
3793#define IOERR_SLI_ABORTED             0x103
3794#define IOERR_PARAM_MASK              0x1ff
3795} PARM_ERR;
3796
3797typedef union {
3798        struct {
3799#ifdef __BIG_ENDIAN_BITFIELD
3800                uint8_t Rctl;   /* R_CTL field */
3801                uint8_t Type;   /* TYPE field */
3802                uint8_t Dfctl;  /* DF_CTL field */
3803                uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
3804#else   /*  __LITTLE_ENDIAN_BITFIELD */
3805                uint8_t Fctl;   /* Bits 0-7 of IOCB word 5 */
3806                uint8_t Dfctl;  /* DF_CTL field */
3807                uint8_t Type;   /* TYPE field */
3808                uint8_t Rctl;   /* R_CTL field */
3809#endif
3810
3811#define BC      0x02            /* Broadcast Received  - Fctl */
3812#define SI      0x04            /* Sequence Initiative */
3813#define LA      0x08            /* Ignore Link Attention state */
3814#define LS      0x80            /* Last Sequence */
3815        } hcsw;
3816        uint32_t reserved;
3817} WORD5;
3818
3819/* IOCB Command template for a generic response */
3820typedef struct {
3821        uint32_t reserved[4];
3822        PARM_ERR perr;
3823} GENERIC_RSP;
3824
3825/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3826typedef struct {
3827        struct ulp_bde xrsqbde[2];
3828        uint32_t xrsqRo;        /* Starting Relative Offset */
3829        WORD5 w5;               /* Header control/status word */
3830} XR_SEQ_FIELDS;
3831
3832/* IOCB Command template for ELS_REQUEST */
3833typedef struct {
3834        struct ulp_bde elsReq;
3835        struct ulp_bde elsRsp;
3836
3837#ifdef __BIG_ENDIAN_BITFIELD
3838        uint32_t word4Rsvd:7;
3839        uint32_t fl:1;
3840        uint32_t myID:24;
3841        uint32_t word5Rsvd:8;
3842        uint32_t remoteID:24;
3843#else   /*  __LITTLE_ENDIAN_BITFIELD */
3844        uint32_t myID:24;
3845        uint32_t fl:1;
3846        uint32_t word4Rsvd:7;
3847        uint32_t remoteID:24;
3848        uint32_t word5Rsvd:8;
3849#endif
3850} ELS_REQUEST;
3851
3852/* IOCB Command template for RCV_ELS_REQ */
3853typedef struct {
3854        struct ulp_bde elsReq[2];
3855        uint32_t parmRo;
3856
3857#ifdef __BIG_ENDIAN_BITFIELD
3858        uint32_t word5Rsvd:8;
3859        uint32_t remoteID:24;
3860#else   /*  __LITTLE_ENDIAN_BITFIELD */
3861        uint32_t remoteID:24;
3862        uint32_t word5Rsvd:8;
3863#endif
3864} RCV_ELS_REQ;
3865
3866/* IOCB Command template for ABORT / CLOSE_XRI */
3867typedef struct {
3868        uint32_t rsvd[3];
3869        uint32_t abortType;
3870#define ABORT_TYPE_ABTX  0x00000000
3871#define ABORT_TYPE_ABTS  0x00000001
3872        uint32_t parm;
3873#ifdef __BIG_ENDIAN_BITFIELD
3874        uint16_t abortContextTag; /* ulpContext from command to abort/close */
3875        uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
3876#else   /*  __LITTLE_ENDIAN_BITFIELD */
3877        uint16_t abortIoTag;    /* ulpIoTag from command to abort/close */
3878        uint16_t abortContextTag; /* ulpContext from command to abort/close */
3879#endif
3880} AC_XRI;
3881
3882/* IOCB Command template for ABORT_MXRI64 */
3883typedef struct {
3884        uint32_t rsvd[3];
3885        uint32_t abortType;
3886        uint32_t parm;
3887        uint32_t iotag32;
3888} A_MXRI64;
3889
3890/* IOCB Command template for GET_RPI */
3891typedef struct {
3892        uint32_t rsvd[4];
3893        uint32_t parmRo;
3894#ifdef __BIG_ENDIAN_BITFIELD
3895        uint32_t word5Rsvd:8;
3896        uint32_t remoteID:24;
3897#else   /*  __LITTLE_ENDIAN_BITFIELD */
3898        uint32_t remoteID:24;
3899        uint32_t word5Rsvd:8;
3900#endif
3901} GET_RPI;
3902
3903/* IOCB Command template for all FCP Initiator commands */
3904typedef struct {
3905        struct ulp_bde fcpi_cmnd;       /* FCP_CMND payload descriptor */
3906        struct ulp_bde fcpi_rsp;        /* Rcv buffer */
3907        uint32_t fcpi_parm;
3908        uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
3909} FCPI_FIELDS;
3910
3911/* IOCB Command template for all FCP Target commands */
3912typedef struct {
3913        struct ulp_bde fcpt_Buffer[2];  /* FCP_CMND payload descriptor */
3914        uint32_t fcpt_Offset;
3915        uint32_t fcpt_Length;   /* transfer ready for IWRITE */
3916} FCPT_FIELDS;
3917
3918/* SLI-2 IOCB structure definitions */
3919
3920/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3921typedef struct {
3922        ULP_BDL bdl;
3923        uint32_t xrsqRo;        /* Starting Relative Offset */
3924        WORD5 w5;               /* Header control/status word */
3925} XMT_SEQ_FIELDS64;
3926
3927/* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3928#define xmit_els_remoteID xrsqRo
3929
3930/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3931typedef struct {
3932        struct ulp_bde64 rcvBde;
3933        uint32_t rsvd1;
3934        uint32_t xrsqRo;        /* Starting Relative Offset */
3935        WORD5 w5;               /* Header control/status word */
3936} RCV_SEQ_FIELDS64;
3937
3938/* IOCB Command template for ELS_REQUEST64 */
3939typedef struct {
3940        ULP_BDL bdl;
3941#ifdef __BIG_ENDIAN_BITFIELD
3942        uint32_t word4Rsvd:7;
3943        uint32_t fl:1;
3944        uint32_t myID:24;
3945        uint32_t word5Rsvd:8;
3946        uint32_t remoteID:24;
3947#else   /*  __LITTLE_ENDIAN_BITFIELD */
3948        uint32_t myID:24;
3949        uint32_t fl:1;
3950        uint32_t word4Rsvd:7;
3951        uint32_t remoteID:24;
3952        uint32_t word5Rsvd:8;
3953#endif
3954} ELS_REQUEST64;
3955
3956/* IOCB Command template for GEN_REQUEST64 */
3957typedef struct {
3958        ULP_BDL bdl;
3959        uint32_t xrsqRo;        /* Starting Relative Offset */
3960        WORD5 w5;               /* Header control/status word */
3961} GEN_REQUEST64;
3962
3963/* IOCB Command template for RCV_ELS_REQ64 */
3964typedef struct {
3965        struct ulp_bde64 elsReq;
3966        uint32_t rcvd1;
3967        uint32_t parmRo;
3968
3969#ifdef __BIG_ENDIAN_BITFIELD
3970        uint32_t word5Rsvd:8;
3971        uint32_t remoteID:24;
3972#else   /*  __LITTLE_ENDIAN_BITFIELD */
3973        uint32_t remoteID:24;
3974        uint32_t word5Rsvd:8;
3975#endif
3976} RCV_ELS_REQ64;
3977
3978/* IOCB Command template for RCV_SEQ64 */
3979struct rcv_seq64 {
3980        struct ulp_bde64 elsReq;
3981        uint32_t hbq_1;
3982        uint32_t parmRo;
3983#ifdef __BIG_ENDIAN_BITFIELD
3984        uint32_t rctl:8;
3985        uint32_t type:8;
3986        uint32_t dfctl:8;
3987        uint32_t ls:1;
3988        uint32_t fs:1;
3989        uint32_t rsvd2:3;
3990        uint32_t si:1;
3991        uint32_t bc:1;
3992        uint32_t rsvd3:1;
3993#else   /*  __LITTLE_ENDIAN_BITFIELD */
3994        uint32_t rsvd3:1;
3995        uint32_t bc:1;
3996        uint32_t si:1;
3997        uint32_t rsvd2:3;
3998        uint32_t fs:1;
3999        uint32_t ls:1;
4000        uint32_t dfctl:8;
4001        uint32_t type:8;
4002        uint32_t rctl:8;
4003#endif
4004};
4005
4006/* IOCB Command template for all 64 bit FCP Initiator commands */
4007typedef struct {
4008        ULP_BDL bdl;
4009        uint32_t fcpi_parm;
4010        uint32_t fcpi_XRdy;     /* transfer ready for IWRITE */
4011} FCPI_FIELDS64;
4012
4013/* IOCB Command template for all 64 bit FCP Target commands */
4014typedef struct {
4015        ULP_BDL bdl;
4016        uint32_t fcpt_Offset;
4017        uint32_t fcpt_Length;   /* transfer ready for IWRITE */
4018} FCPT_FIELDS64;
4019
4020/* IOCB Command template for Async Status iocb commands */
4021typedef struct {
4022        uint32_t rsvd[4];
4023        uint32_t param;
4024#ifdef __BIG_ENDIAN_BITFIELD
4025        uint16_t evt_code;              /* High order bits word 5 */
4026        uint16_t sub_ctxt_tag;          /* Low  order bits word 5 */
4027#else   /*  __LITTLE_ENDIAN_BITFIELD */
4028        uint16_t sub_ctxt_tag;          /* High order bits word 5 */
4029        uint16_t evt_code;              /* Low  order bits word 5 */
4030#endif
4031} ASYNCSTAT_FIELDS;
4032#define ASYNC_TEMP_WARN         0x100
4033#define ASYNC_TEMP_SAFE         0x101
4034#define ASYNC_STATUS_CN         0x102
4035
4036/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
4037   or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
4038
4039struct rcv_sli3 {
4040#ifdef __BIG_ENDIAN_BITFIELD
4041        uint16_t ox_id;
4042        uint16_t seq_cnt;
4043
4044        uint16_t vpi;
4045        uint16_t word9Rsvd;
4046#else  /*  __LITTLE_ENDIAN */
4047        uint16_t seq_cnt;
4048        uint16_t ox_id;
4049
4050        uint16_t word9Rsvd;
4051        uint16_t vpi;
4052#endif
4053        uint32_t word10Rsvd;
4054        uint32_t acc_len;      /* accumulated length */
4055        struct ulp_bde64 bde2;
4056};
4057
4058/* Structure used for a single HBQ entry */
4059struct lpfc_hbq_entry {
4060        struct ulp_bde64 bde;
4061        uint32_t buffer_tag;
4062};
4063
4064/* IOCB Command template for QUE_XRI64_CX (0xB3) command */
4065typedef struct {
4066        struct lpfc_hbq_entry   buff;
4067        uint32_t                rsvd;
4068        uint32_t                rsvd1;
4069} QUE_XRI64_CX_FIELDS;
4070
4071struct que_xri64cx_ext_fields {
4072        uint32_t        iotag64_low;
4073        uint32_t        iotag64_high;
4074        uint32_t        ebde_count;
4075        uint32_t        rsvd;
4076        struct lpfc_hbq_entry   buff[5];
4077};
4078
4079struct sli3_bg_fields {
4080        uint32_t filler[6];     /* word 8-13 in IOCB */
4081        uint32_t bghm;          /* word 14 - BlockGuard High Water Mark */
4082/* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
4083#define BGS_BIDIR_BG_PROF_MASK          0xff000000
4084#define BGS_BIDIR_BG_PROF_SHIFT         24
4085#define BGS_BIDIR_ERR_COND_FLAGS_MASK   0x003f0000
4086#define BGS_BIDIR_ERR_COND_SHIFT        16
4087#define BGS_BG_PROFILE_MASK             0x0000ff00
4088#define BGS_BG_PROFILE_SHIFT            8
4089#define BGS_INVALID_PROF_MASK           0x00000020
4090#define BGS_INVALID_PROF_SHIFT          5
4091#define BGS_UNINIT_DIF_BLOCK_MASK       0x00000010
4092#define BGS_UNINIT_DIF_BLOCK_SHIFT      4
4093#define BGS_HI_WATER_MARK_PRESENT_MASK  0x00000008
4094#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
4095#define BGS_REFTAG_ERR_MASK             0x00000004
4096#define BGS_REFTAG_ERR_SHIFT            2
4097#define BGS_APPTAG_ERR_MASK             0x00000002
4098#define BGS_APPTAG_ERR_SHIFT            1
4099#define BGS_GUARD_ERR_MASK              0x00000001
4100#define BGS_GUARD_ERR_SHIFT             0
4101        uint32_t bgstat;        /* word 15 - BlockGuard Status */
4102};
4103
4104static inline uint32_t
4105lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
4106{
4107        return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
4108                                BGS_BIDIR_BG_PROF_SHIFT;
4109}
4110
4111static inline uint32_t
4112lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
4113{
4114        return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
4115                                BGS_BIDIR_ERR_COND_SHIFT;
4116}
4117
4118static inline uint32_t
4119lpfc_bgs_get_bg_prof(uint32_t bgstat)
4120{
4121        return (bgstat & BGS_BG_PROFILE_MASK) >>
4122                                BGS_BG_PROFILE_SHIFT;
4123}
4124
4125static inline uint32_t
4126lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4127{
4128        return (bgstat & BGS_INVALID_PROF_MASK) >>
4129                                BGS_INVALID_PROF_SHIFT;
4130}
4131
4132static inline uint32_t
4133lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4134{
4135        return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4136                                BGS_UNINIT_DIF_BLOCK_SHIFT;
4137}
4138
4139static inline uint32_t
4140lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4141{
4142        return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4143                                BGS_HI_WATER_MARK_PRESENT_SHIFT;
4144}
4145
4146static inline uint32_t
4147lpfc_bgs_get_reftag_err(uint32_t bgstat)
4148{
4149        return (bgstat & BGS_REFTAG_ERR_MASK) >>
4150                                BGS_REFTAG_ERR_SHIFT;
4151}
4152
4153static inline uint32_t
4154lpfc_bgs_get_apptag_err(uint32_t bgstat)
4155{
4156        return (bgstat & BGS_APPTAG_ERR_MASK) >>
4157                                BGS_APPTAG_ERR_SHIFT;
4158}
4159
4160static inline uint32_t
4161lpfc_bgs_get_guard_err(uint32_t bgstat)
4162{
4163        return (bgstat & BGS_GUARD_ERR_MASK) >>
4164                                BGS_GUARD_ERR_SHIFT;
4165}
4166
4167#define LPFC_EXT_DATA_BDE_COUNT 3
4168struct fcp_irw_ext {
4169        uint32_t        io_tag64_low;
4170        uint32_t        io_tag64_high;
4171#ifdef __BIG_ENDIAN_BITFIELD
4172        uint8_t         reserved1;
4173        uint8_t         reserved2;
4174        uint8_t         reserved3;
4175        uint8_t         ebde_count;
4176#else  /* __LITTLE_ENDIAN */
4177        uint8_t         ebde_count;
4178        uint8_t         reserved3;
4179        uint8_t         reserved2;
4180        uint8_t         reserved1;
4181#endif
4182        uint32_t        reserved4;
4183        struct ulp_bde64 rbde;          /* response bde */
4184        struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4185        uint8_t icd[32];                /* immediate command data (32 bytes) */
4186};
4187
4188typedef struct _IOCB {  /* IOCB structure */
4189        union {
4190                GENERIC_RSP grsp;       /* Generic response */
4191                XR_SEQ_FIELDS xrseq;    /* XMIT / BCAST / RCV_SEQUENCE cmd */
4192                struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4193                RCV_ELS_REQ rcvels;     /* RCV_ELS_REQ template */
4194                AC_XRI acxri;   /* ABORT / CLOSE_XRI template */
4195                A_MXRI64 amxri; /* abort multiple xri command overlay */
4196                GET_RPI getrpi; /* GET_RPI template */
4197                FCPI_FIELDS fcpi;       /* FCP Initiator template */
4198                FCPT_FIELDS fcpt;       /* FCP target template */
4199
4200                /* SLI-2 structures */
4201
4202                struct ulp_bde64 cont64[2];  /* up to 2 64 bit continuation
4203                                              * bde_64s */
4204                ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4205                GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4206                RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4207                XMT_SEQ_FIELDS64 xseq64;        /* XMIT / BCAST cmd */
4208                FCPI_FIELDS64 fcpi64;   /* FCP 64 bit Initiator template */
4209                FCPT_FIELDS64 fcpt64;   /* FCP 64 bit target template */
4210                ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4211                QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4212                struct rcv_seq64 rcvseq64;      /* RCV_SEQ64 and RCV_CONT64 */
4213                struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4214                uint32_t ulpWord[IOCB_WORD_SZ - 2];     /* generic 6 'words' */
4215        } un;
4216        union {
4217                struct {
4218#ifdef __BIG_ENDIAN_BITFIELD
4219                        uint16_t ulpContext;    /* High order bits word 6 */
4220                        uint16_t ulpIoTag;      /* Low  order bits word 6 */
4221#else   /*  __LITTLE_ENDIAN_BITFIELD */
4222                        uint16_t ulpIoTag;      /* Low  order bits word 6 */
4223                        uint16_t ulpContext;    /* High order bits word 6 */
4224#endif
4225                } t1;
4226                struct {
4227#ifdef __BIG_ENDIAN_BITFIELD
4228                        uint16_t ulpContext;    /* High order bits word 6 */
4229                        uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
4230                        uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
4231#else   /*  __LITTLE_ENDIAN_BITFIELD */
4232                        uint16_t ulpIoTag0:14;  /* Low  order bits word 6 */
4233                        uint16_t ulpIoTag1:2;   /* Low  order bits word 6 */
4234                        uint16_t ulpContext;    /* High order bits word 6 */
4235#endif
4236                } t2;
4237        } un1;
4238#define ulpContext un1.t1.ulpContext
4239#define ulpIoTag   un1.t1.ulpIoTag
4240#define ulpIoTag0  un1.t2.ulpIoTag0
4241
4242#ifdef __BIG_ENDIAN_BITFIELD
4243        uint32_t ulpTimeout:8;
4244        uint32_t ulpXS:1;
4245        uint32_t ulpFCP2Rcvy:1;
4246        uint32_t ulpPU:2;
4247        uint32_t ulpIr:1;
4248        uint32_t ulpClass:3;
4249        uint32_t ulpCommand:8;
4250        uint32_t ulpStatus:4;
4251        uint32_t ulpBdeCount:2;
4252        uint32_t ulpLe:1;
4253        uint32_t ulpOwner:1;    /* Low order bit word 7 */
4254#else   /*  __LITTLE_ENDIAN_BITFIELD */
4255        uint32_t ulpOwner:1;    /* Low order bit word 7 */
4256        uint32_t ulpLe:1;
4257        uint32_t ulpBdeCount:2;
4258        uint32_t ulpStatus:4;
4259        uint32_t ulpCommand:8;
4260        uint32_t ulpClass:3;
4261        uint32_t ulpIr:1;
4262        uint32_t ulpPU:2;
4263        uint32_t ulpFCP2Rcvy:1;
4264        uint32_t ulpXS:1;
4265        uint32_t ulpTimeout:8;
4266#endif
4267
4268        union {
4269                struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4270
4271                /* words 8-31 used for que_xri_cx iocb */
4272                struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4273                struct fcp_irw_ext fcp_ext;
4274                uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4275
4276                /* words 8-15 for BlockGuard */
4277                struct sli3_bg_fields sli3_bg;
4278        } unsli3;
4279
4280#define ulpCt_h ulpXS
4281#define ulpCt_l ulpFCP2Rcvy
4282
4283#define IOCB_FCP           1    /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4284#define IOCB_IP            2    /* IOCB is used for IP ELS cmds */
4285#define PARM_UNUSED        0    /* PU field (Word 4) not used */
4286#define PARM_REL_OFF       1    /* PU field (Word 4) = R. O. */
4287#define PARM_READ_CHECK    2    /* PU field (Word 4) = Data Transfer Length */
4288#define PARM_NPIV_DID      3
4289#define CLASS1             0    /* Class 1 */
4290#define CLASS2             1    /* Class 2 */
4291#define CLASS3             2    /* Class 3 */
4292#define CLASS_FCP_INTERMIX 7    /* FCP Data->Cls 1, all else->Cls 2 */
4293
4294#define IOSTAT_SUCCESS         0x0      /* ulpStatus  - HBA defined */
4295#define IOSTAT_FCP_RSP_ERROR   0x1
4296#define IOSTAT_REMOTE_STOP     0x2
4297#define IOSTAT_LOCAL_REJECT    0x3
4298#define IOSTAT_NPORT_RJT       0x4
4299#define IOSTAT_FABRIC_RJT      0x5
4300#define IOSTAT_NPORT_BSY       0x6
4301#define IOSTAT_FABRIC_BSY      0x7
4302#define IOSTAT_INTERMED_RSP    0x8
4303#define IOSTAT_LS_RJT          0x9
4304#define IOSTAT_BA_RJT          0xA
4305#define IOSTAT_RSVD1           0xB
4306#define IOSTAT_RSVD2           0xC
4307#define IOSTAT_RSVD3           0xD
4308#define IOSTAT_RSVD4           0xE
4309#define IOSTAT_NEED_BUFFER     0xF
4310#define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
4311#define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
4312#define IOSTAT_CNT             0x11
4313
4314} IOCB_t;
4315
4316
4317#define SLI1_SLIM_SIZE   (4 * 1024)
4318
4319/* Up to 498 IOCBs will fit into 16k
4320 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4321 */
4322#define SLI2_SLIM_SIZE   (64 * 1024)
4323
4324/* Maximum IOCBs that will fit in SLI2 slim */
4325#define MAX_SLI2_IOCB    498
4326#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4327                            (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4328                            sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4329
4330/* HBQ entries are 4 words each = 4k */
4331#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) *  \
4332                             lpfc_sli_hbq_count())
4333
4334struct lpfc_sli2_slim {
4335        MAILBOX_t mbx;
4336        uint32_t  mbx_ext_words[MAILBOX_EXT_WSIZE];
4337        PCB_t pcb;
4338        IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4339};
4340
4341/*
4342 * This function checks PCI device to allow special handling for LC HBAs.
4343 *
4344 * Parameters:
4345 * device : struct pci_dev 's device field
4346 *
4347 * return 1 => TRUE
4348 *        0 => FALSE
4349 */
4350static inline int
4351lpfc_is_LC_HBA(unsigned short device)
4352{
4353        if ((device == PCI_DEVICE_ID_TFLY) ||
4354            (device == PCI_DEVICE_ID_PFLY) ||
4355            (device == PCI_DEVICE_ID_LP101) ||
4356            (device == PCI_DEVICE_ID_BMID) ||
4357            (device == PCI_DEVICE_ID_BSMB) ||
4358            (device == PCI_DEVICE_ID_ZMID) ||
4359            (device == PCI_DEVICE_ID_ZSMB) ||
4360            (device == PCI_DEVICE_ID_SAT_MID) ||
4361            (device == PCI_DEVICE_ID_SAT_SMB) ||
4362            (device == PCI_DEVICE_ID_RFLY))
4363                return 1;
4364        else
4365                return 0;
4366}
4367
4368/*
4369 * Determine if an IOCB failed because of a link event or firmware reset.
4370 */
4371
4372static inline int
4373lpfc_error_lost_link(IOCB_t *iocbp)
4374{
4375        return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4376                (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4377                 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4378                 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4379}
4380
4381#define MENLO_TRANSPORT_TYPE 0xfe
4382#define MENLO_CONTEXT 0
4383#define MENLO_PU 3
4384#define MENLO_TIMEOUT 30
4385#define SETVAR_MLOMNT 0x103107
4386#define SETVAR_MLORST 0x103007
4387
4388#define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
4389