linux/drivers/powercap/intel_rapl_msr.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Intel Running Average Power Limit (RAPL) Driver via MSR interface
   4 * Copyright (c) 2019, Intel Corporation.
   5 */
   6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8#include <linux/kernel.h>
   9#include <linux/module.h>
  10#include <linux/list.h>
  11#include <linux/types.h>
  12#include <linux/device.h>
  13#include <linux/slab.h>
  14#include <linux/log2.h>
  15#include <linux/bitmap.h>
  16#include <linux/delay.h>
  17#include <linux/sysfs.h>
  18#include <linux/cpu.h>
  19#include <linux/powercap.h>
  20#include <linux/suspend.h>
  21#include <linux/intel_rapl.h>
  22#include <linux/processor.h>
  23#include <linux/platform_device.h>
  24
  25#include <asm/iosf_mbi.h>
  26#include <asm/cpu_device_id.h>
  27#include <asm/intel-family.h>
  28
  29/* Local defines */
  30#define MSR_PLATFORM_POWER_LIMIT        0x0000065C
  31#define MSR_VR_CURRENT_CONFIG           0x00000601
  32
  33/* private data for RAPL MSR Interface */
  34static struct rapl_if_priv *rapl_msr_priv;
  35
  36static struct rapl_if_priv rapl_msr_priv_intel = {
  37        .reg_unit = MSR_RAPL_POWER_UNIT,
  38        .regs[RAPL_DOMAIN_PACKAGE] = {
  39                MSR_PKG_POWER_LIMIT, MSR_PKG_ENERGY_STATUS, MSR_PKG_PERF_STATUS, 0, MSR_PKG_POWER_INFO },
  40        .regs[RAPL_DOMAIN_PP0] = {
  41                MSR_PP0_POWER_LIMIT, MSR_PP0_ENERGY_STATUS, 0, MSR_PP0_POLICY, 0 },
  42        .regs[RAPL_DOMAIN_PP1] = {
  43                MSR_PP1_POWER_LIMIT, MSR_PP1_ENERGY_STATUS, 0, MSR_PP1_POLICY, 0 },
  44        .regs[RAPL_DOMAIN_DRAM] = {
  45                MSR_DRAM_POWER_LIMIT, MSR_DRAM_ENERGY_STATUS, MSR_DRAM_PERF_STATUS, 0, MSR_DRAM_POWER_INFO },
  46        .regs[RAPL_DOMAIN_PLATFORM] = {
  47                MSR_PLATFORM_POWER_LIMIT, MSR_PLATFORM_ENERGY_STATUS, 0, 0, 0},
  48        .limits[RAPL_DOMAIN_PACKAGE] = 2,
  49        .limits[RAPL_DOMAIN_PLATFORM] = 2,
  50};
  51
  52static struct rapl_if_priv rapl_msr_priv_amd = {
  53        .reg_unit = MSR_AMD_RAPL_POWER_UNIT,
  54        .regs[RAPL_DOMAIN_PACKAGE] = {
  55                0, MSR_AMD_PKG_ENERGY_STATUS, 0, 0, 0 },
  56        .regs[RAPL_DOMAIN_PP0] = {
  57                0, MSR_AMD_CORE_ENERGY_STATUS, 0, 0, 0 },
  58};
  59
  60/* Handles CPU hotplug on multi-socket systems.
  61 * If a CPU goes online as the first CPU of the physical package
  62 * we add the RAPL package to the system. Similarly, when the last
  63 * CPU of the package is removed, we remove the RAPL package and its
  64 * associated domains. Cooling devices are handled accordingly at
  65 * per-domain level.
  66 */
  67static int rapl_cpu_online(unsigned int cpu)
  68{
  69        struct rapl_package *rp;
  70
  71        rp = rapl_find_package_domain(cpu, rapl_msr_priv);
  72        if (!rp) {
  73                rp = rapl_add_package(cpu, rapl_msr_priv);
  74                if (IS_ERR(rp))
  75                        return PTR_ERR(rp);
  76        }
  77        cpumask_set_cpu(cpu, &rp->cpumask);
  78        return 0;
  79}
  80
  81static int rapl_cpu_down_prep(unsigned int cpu)
  82{
  83        struct rapl_package *rp;
  84        int lead_cpu;
  85
  86        rp = rapl_find_package_domain(cpu, rapl_msr_priv);
  87        if (!rp)
  88                return 0;
  89
  90        cpumask_clear_cpu(cpu, &rp->cpumask);
  91        lead_cpu = cpumask_first(&rp->cpumask);
  92        if (lead_cpu >= nr_cpu_ids)
  93                rapl_remove_package(rp);
  94        else if (rp->lead_cpu == cpu)
  95                rp->lead_cpu = lead_cpu;
  96        return 0;
  97}
  98
  99static int rapl_msr_read_raw(int cpu, struct reg_action *ra)
 100{
 101        u32 msr = (u32)ra->reg;
 102
 103        if (rdmsrl_safe_on_cpu(cpu, msr, &ra->value)) {
 104                pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
 105                return -EIO;
 106        }
 107        ra->value &= ra->mask;
 108        return 0;
 109}
 110
 111static void rapl_msr_update_func(void *info)
 112{
 113        struct reg_action *ra = info;
 114        u32 msr = (u32)ra->reg;
 115        u64 val;
 116
 117        ra->err = rdmsrl_safe(msr, &val);
 118        if (ra->err)
 119                return;
 120
 121        val &= ~ra->mask;
 122        val |= ra->value;
 123
 124        ra->err = wrmsrl_safe(msr, val);
 125}
 126
 127static int rapl_msr_write_raw(int cpu, struct reg_action *ra)
 128{
 129        int ret;
 130
 131        ret = smp_call_function_single(cpu, rapl_msr_update_func, ra, 1);
 132        if (WARN_ON_ONCE(ret))
 133                return ret;
 134
 135        return ra->err;
 136}
 137
 138/* List of verified CPUs. */
 139static const struct x86_cpu_id pl4_support_ids[] = {
 140        { X86_VENDOR_INTEL, 6, INTEL_FAM6_TIGERLAKE_L, X86_FEATURE_ANY },
 141        {}
 142};
 143
 144static int rapl_msr_probe(struct platform_device *pdev)
 145{
 146        const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids);
 147        int ret;
 148
 149        switch (boot_cpu_data.x86_vendor) {
 150        case X86_VENDOR_INTEL:
 151                rapl_msr_priv = &rapl_msr_priv_intel;
 152                break;
 153        case X86_VENDOR_HYGON:
 154        case X86_VENDOR_AMD:
 155                rapl_msr_priv = &rapl_msr_priv_amd;
 156                break;
 157        default:
 158                pr_err("intel-rapl does not support CPU vendor %d\n", boot_cpu_data.x86_vendor);
 159                return -ENODEV;
 160        }
 161        rapl_msr_priv->read_raw = rapl_msr_read_raw;
 162        rapl_msr_priv->write_raw = rapl_msr_write_raw;
 163
 164        if (id) {
 165                rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] = 3;
 166                rapl_msr_priv->regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4] =
 167                        MSR_VR_CURRENT_CONFIG;
 168                pr_info("PL4 support detected.\n");
 169        }
 170
 171        rapl_msr_priv->control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
 172        if (IS_ERR(rapl_msr_priv->control_type)) {
 173                pr_debug("failed to register powercap control_type.\n");
 174                return PTR_ERR(rapl_msr_priv->control_type);
 175        }
 176
 177        ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powercap/rapl:online",
 178                                rapl_cpu_online, rapl_cpu_down_prep);
 179        if (ret < 0)
 180                goto out;
 181        rapl_msr_priv->pcap_rapl_online = ret;
 182
 183        return 0;
 184
 185out:
 186        if (ret)
 187                powercap_unregister_control_type(rapl_msr_priv->control_type);
 188        return ret;
 189}
 190
 191static int rapl_msr_remove(struct platform_device *pdev)
 192{
 193        cpuhp_remove_state(rapl_msr_priv->pcap_rapl_online);
 194        powercap_unregister_control_type(rapl_msr_priv->control_type);
 195        return 0;
 196}
 197
 198static const struct platform_device_id rapl_msr_ids[] = {
 199        { .name = "intel_rapl_msr", },
 200        {}
 201};
 202MODULE_DEVICE_TABLE(platform, rapl_msr_ids);
 203
 204static struct platform_driver intel_rapl_msr_driver = {
 205        .probe = rapl_msr_probe,
 206        .remove = rapl_msr_remove,
 207        .id_table = rapl_msr_ids,
 208        .driver = {
 209                .name = "intel_rapl_msr",
 210        },
 211};
 212
 213module_platform_driver(intel_rapl_msr_driver);
 214
 215MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit) control via MSR interface");
 216MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>");
 217MODULE_LICENSE("GPL v2");
 218