linux/drivers/net/wireless/mediatek/mt76/mt7615/mac.c
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   1// SPDX-License-Identifier: ISC
   2/* Copyright (C) 2019 MediaTek Inc.
   3 *
   4 * Author: Ryder Lee <ryder.lee@mediatek.com>
   5 *         Roy Luo <royluo@google.com>
   6 *         Felix Fietkau <nbd@nbd.name>
   7 *         Lorenzo Bianconi <lorenzo@kernel.org>
   8 */
   9
  10#include <linux/devcoredump.h>
  11#include <linux/etherdevice.h>
  12#include <linux/timekeeping.h>
  13#include "mt7615.h"
  14#include "../trace.h"
  15#include "../dma.h"
  16#include "mt7615_trace.h"
  17#include "mac.h"
  18#include "mcu.h"
  19
  20#define to_rssi(field, rxv)             ((FIELD_GET(field, rxv) - 220) / 2)
  21
  22static const struct mt7615_dfs_radar_spec etsi_radar_specs = {
  23        .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
  24        .radar_pattern = {
  25                [5] =  { 1, 0,  6, 32, 28, 0, 17,  990, 5010, 1, 1 },
  26                [6] =  { 1, 0,  9, 32, 28, 0, 27,  615, 5010, 1, 1 },
  27                [7] =  { 1, 0, 15, 32, 28, 0, 27,  240,  445, 1, 1 },
  28                [8] =  { 1, 0, 12, 32, 28, 0, 42,  240,  510, 1, 1 },
  29                [9] =  { 1, 1,  0,  0,  0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 },
  30                [10] = { 1, 1,  0,  0,  0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 },
  31                [11] = { 1, 1,  0,  0,  0, 0, 14,  823, 2510, 0, 0, 18, 32, 28 },
  32                [12] = { 1, 1,  0,  0,  0, 0, 14,  823, 2510, 0, 0, 27, 32, 24 },
  33        },
  34};
  35
  36static const struct mt7615_dfs_radar_spec fcc_radar_specs = {
  37        .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
  38        .radar_pattern = {
  39                [0] = { 1, 0,  9,  32, 28, 0, 13, 508, 3076, 1,  1 },
  40                [1] = { 1, 0, 12,  32, 28, 0, 17, 140,  240, 1,  1 },
  41                [2] = { 1, 0,  8,  32, 28, 0, 22, 190,  510, 1,  1 },
  42                [3] = { 1, 0,  6,  32, 28, 0, 32, 190,  510, 1,  1 },
  43                [4] = { 1, 0,  9, 255, 28, 0, 13, 323,  343, 1, 32 },
  44        },
  45};
  46
  47static const struct mt7615_dfs_radar_spec jp_radar_specs = {
  48        .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
  49        .radar_pattern = {
  50                [0] =  { 1, 0,  8, 32, 28, 0, 13,  508, 3076, 1,  1 },
  51                [1] =  { 1, 0, 12, 32, 28, 0, 17,  140,  240, 1,  1 },
  52                [2] =  { 1, 0,  8, 32, 28, 0, 22,  190,  510, 1,  1 },
  53                [3] =  { 1, 0,  6, 32, 28, 0, 32,  190,  510, 1,  1 },
  54                [4] =  { 1, 0,  9, 32, 28, 0, 13,  323,  343, 1, 32 },
  55                [13] = { 1, 0, 8,  32, 28, 0, 14, 3836, 3856, 1,  1 },
  56                [14] = { 1, 0, 8,  32, 28, 0, 14, 3990, 4010, 1,  1 },
  57        },
  58};
  59
  60static enum mt76_cipher_type
  61mt7615_mac_get_cipher(int cipher)
  62{
  63        switch (cipher) {
  64        case WLAN_CIPHER_SUITE_WEP40:
  65                return MT_CIPHER_WEP40;
  66        case WLAN_CIPHER_SUITE_WEP104:
  67                return MT_CIPHER_WEP104;
  68        case WLAN_CIPHER_SUITE_TKIP:
  69                return MT_CIPHER_TKIP;
  70        case WLAN_CIPHER_SUITE_AES_CMAC:
  71                return MT_CIPHER_BIP_CMAC_128;
  72        case WLAN_CIPHER_SUITE_CCMP:
  73                return MT_CIPHER_AES_CCMP;
  74        case WLAN_CIPHER_SUITE_CCMP_256:
  75                return MT_CIPHER_CCMP_256;
  76        case WLAN_CIPHER_SUITE_GCMP:
  77                return MT_CIPHER_GCMP;
  78        case WLAN_CIPHER_SUITE_GCMP_256:
  79                return MT_CIPHER_GCMP_256;
  80        case WLAN_CIPHER_SUITE_SMS4:
  81                return MT_CIPHER_WAPI;
  82        default:
  83                return MT_CIPHER_NONE;
  84        }
  85}
  86
  87static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
  88                                            u8 idx, bool unicast)
  89{
  90        struct mt7615_sta *sta;
  91        struct mt76_wcid *wcid;
  92
  93        if (idx >= MT7615_WTBL_SIZE)
  94                return NULL;
  95
  96        wcid = rcu_dereference(dev->mt76.wcid[idx]);
  97        if (unicast || !wcid)
  98                return wcid;
  99
 100        if (!wcid->sta)
 101                return NULL;
 102
 103        sta = container_of(wcid, struct mt7615_sta, wcid);
 104        if (!sta->vif)
 105                return NULL;
 106
 107        return &sta->vif->sta.wcid;
 108}
 109
 110void mt7615_mac_reset_counters(struct mt7615_dev *dev)
 111{
 112        int i;
 113
 114        for (i = 0; i < 4; i++) {
 115                mt76_rr(dev, MT_TX_AGG_CNT(0, i));
 116                mt76_rr(dev, MT_TX_AGG_CNT(1, i));
 117        }
 118
 119        memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
 120        dev->mt76.phy.survey_time = ktime_get_boottime();
 121        if (dev->mt76.phy2)
 122                dev->mt76.phy2->survey_time = ktime_get_boottime();
 123
 124        /* reset airtime counters */
 125        mt76_rr(dev, MT_MIB_SDR9(0));
 126        mt76_rr(dev, MT_MIB_SDR9(1));
 127
 128        mt76_rr(dev, MT_MIB_SDR36(0));
 129        mt76_rr(dev, MT_MIB_SDR36(1));
 130
 131        mt76_rr(dev, MT_MIB_SDR37(0));
 132        mt76_rr(dev, MT_MIB_SDR37(1));
 133
 134        mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
 135        mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
 136}
 137
 138void mt7615_mac_set_timing(struct mt7615_phy *phy)
 139{
 140        s16 coverage_class = phy->coverage_class;
 141        struct mt7615_dev *dev = phy->dev;
 142        bool ext_phy = phy != &dev->phy;
 143        u32 val, reg_offset;
 144        u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
 145                  FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
 146        u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
 147                   FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
 148        int sifs, offset;
 149        bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
 150
 151        if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
 152                return;
 153
 154        if (is_5ghz)
 155                sifs = 16;
 156        else
 157                sifs = 10;
 158
 159        if (ext_phy) {
 160                coverage_class = max_t(s16, dev->phy.coverage_class,
 161                                       coverage_class);
 162                mt76_set(dev, MT_ARB_SCR,
 163                         MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
 164        } else {
 165                struct mt7615_phy *phy_ext = mt7615_ext_phy(dev);
 166
 167                if (phy_ext)
 168                        coverage_class = max_t(s16, phy_ext->coverage_class,
 169                                               coverage_class);
 170                mt76_set(dev, MT_ARB_SCR,
 171                         MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
 172        }
 173        udelay(1);
 174
 175        offset = 3 * coverage_class;
 176        reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
 177                     FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
 178        mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);
 179        mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);
 180
 181        mt76_wr(dev, MT_TMAC_ICR(ext_phy),
 182                FIELD_PREP(MT_IFS_EIFS, 360) |
 183                FIELD_PREP(MT_IFS_RIFS, 2) |
 184                FIELD_PREP(MT_IFS_SIFS, sifs) |
 185                FIELD_PREP(MT_IFS_SLOT, phy->slottime));
 186
 187        if (phy->slottime < 20 || is_5ghz)
 188                val = MT7615_CFEND_RATE_DEFAULT;
 189        else
 190                val = MT7615_CFEND_RATE_11B;
 191
 192        mt76_rmw_field(dev, MT_AGG_ACR(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
 193        if (ext_phy)
 194                mt76_clear(dev, MT_ARB_SCR,
 195                           MT_ARB_SCR_TX1_DISABLE | MT_ARB_SCR_RX1_DISABLE);
 196        else
 197                mt76_clear(dev, MT_ARB_SCR,
 198                           MT_ARB_SCR_TX0_DISABLE | MT_ARB_SCR_RX0_DISABLE);
 199
 200}
 201
 202static void
 203mt7615_get_status_freq_info(struct mt7615_dev *dev, struct mt76_phy *mphy,
 204                            struct mt76_rx_status *status, u8 chfreq)
 205{
 206        if (!test_bit(MT76_HW_SCANNING, &mphy->state) &&
 207            !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) &&
 208            !test_bit(MT76_STATE_ROC, &mphy->state)) {
 209                status->freq = mphy->chandef.chan->center_freq;
 210                status->band = mphy->chandef.chan->band;
 211                return;
 212        }
 213
 214        status->band = chfreq <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
 215        status->freq = ieee80211_channel_to_frequency(chfreq, status->band);
 216}
 217
 218static void mt7615_mac_fill_tm_rx(struct mt7615_phy *phy, __le32 *rxv)
 219{
 220#ifdef CONFIG_NL80211_TESTMODE
 221        u32 rxv1 = le32_to_cpu(rxv[0]);
 222        u32 rxv3 = le32_to_cpu(rxv[2]);
 223        u32 rxv4 = le32_to_cpu(rxv[3]);
 224        u32 rxv5 = le32_to_cpu(rxv[4]);
 225        u8 cbw = FIELD_GET(MT_RXV1_FRAME_MODE, rxv1);
 226        u8 mode = FIELD_GET(MT_RXV1_TX_MODE, rxv1);
 227        s16 foe = FIELD_GET(MT_RXV5_FOE, rxv5);
 228        u32 foe_const = (BIT(cbw + 1) & 0xf) * 10000;
 229
 230        if (!mode) {
 231                /* CCK */
 232                foe &= ~BIT(11);
 233                foe *= 1000;
 234                foe >>= 11;
 235        } else {
 236                if (foe > 2048)
 237                        foe -= 4096;
 238
 239                foe = (foe * foe_const) >> 15;
 240        }
 241
 242        phy->test.last_freq_offset = foe;
 243        phy->test.last_rcpi[0] = FIELD_GET(MT_RXV4_RCPI0, rxv4);
 244        phy->test.last_rcpi[1] = FIELD_GET(MT_RXV4_RCPI1, rxv4);
 245        phy->test.last_rcpi[2] = FIELD_GET(MT_RXV4_RCPI2, rxv4);
 246        phy->test.last_rcpi[3] = FIELD_GET(MT_RXV4_RCPI3, rxv4);
 247        phy->test.last_ib_rssi[0] = FIELD_GET(MT_RXV3_IB_RSSI, rxv3);
 248        phy->test.last_wb_rssi[0] = FIELD_GET(MT_RXV3_WB_RSSI, rxv3);
 249#endif
 250}
 251
 252static int mt7615_mac_fill_rx(struct mt7615_dev *dev, struct sk_buff *skb)
 253{
 254        struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
 255        struct mt76_phy *mphy = &dev->mt76.phy;
 256        struct mt7615_phy *phy = &dev->phy;
 257        struct mt7615_phy *phy2 = dev->mt76.phy2 ? dev->mt76.phy2->priv : NULL;
 258        struct ieee80211_supported_band *sband;
 259        struct ieee80211_hdr *hdr;
 260        __le32 *rxd = (__le32 *)skb->data;
 261        u32 rxd0 = le32_to_cpu(rxd[0]);
 262        u32 rxd1 = le32_to_cpu(rxd[1]);
 263        u32 rxd2 = le32_to_cpu(rxd[2]);
 264        u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
 265        bool unicast, hdr_trans, remove_pad, insert_ccmp_hdr = false;
 266        int phy_idx;
 267        int i, idx;
 268        u8 chfreq, amsdu_info, qos_ctl = 0;
 269        u16 seq_ctrl = 0;
 270        __le16 fc = 0;
 271
 272        memset(status, 0, sizeof(*status));
 273
 274        chfreq = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
 275        if (!phy2)
 276                phy_idx = 0;
 277        else if (phy2->chfreq == phy->chfreq)
 278                phy_idx = -1;
 279        else if (phy->chfreq == chfreq)
 280                phy_idx = 0;
 281        else if (phy2->chfreq == chfreq)
 282                phy_idx = 1;
 283        else
 284                phy_idx = -1;
 285
 286        if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR)
 287                return -EINVAL;
 288
 289        unicast = (rxd1 & MT_RXD1_NORMAL_ADDR_TYPE) == MT_RXD1_NORMAL_U2M;
 290        idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
 291        hdr_trans = rxd1 & MT_RXD1_NORMAL_HDR_TRANS;
 292        status->wcid = mt7615_rx_get_wcid(dev, idx, unicast);
 293
 294        if (status->wcid) {
 295                struct mt7615_sta *msta;
 296
 297                msta = container_of(status->wcid, struct mt7615_sta, wcid);
 298                spin_lock_bh(&dev->sta_poll_lock);
 299                if (list_empty(&msta->poll_list))
 300                        list_add_tail(&msta->poll_list, &dev->sta_poll_list);
 301                spin_unlock_bh(&dev->sta_poll_lock);
 302        }
 303
 304        if ((rxd0 & csum_mask) == csum_mask)
 305                skb->ip_summed = CHECKSUM_UNNECESSARY;
 306
 307        if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
 308                status->flag |= RX_FLAG_FAILED_FCS_CRC;
 309
 310        if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
 311                status->flag |= RX_FLAG_MMIC_ERROR;
 312
 313        if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
 314            !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
 315                status->flag |= RX_FLAG_DECRYPTED;
 316                status->flag |= RX_FLAG_IV_STRIPPED;
 317                status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
 318        }
 319
 320        remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
 321
 322        if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
 323                return -EINVAL;
 324
 325        rxd += 4;
 326        if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
 327                u32 v0 = le32_to_cpu(rxd[0]);
 328                u32 v2 = le32_to_cpu(rxd[2]);
 329
 330                fc = cpu_to_le16(FIELD_GET(MT_RXD4_FRAME_CONTROL, v0));
 331                qos_ctl = FIELD_GET(MT_RXD6_QOS_CTL, v2);
 332                seq_ctrl = FIELD_GET(MT_RXD6_SEQ_CTRL, v2);
 333
 334                rxd += 4;
 335                if ((u8 *)rxd - skb->data >= skb->len)
 336                        return -EINVAL;
 337        }
 338
 339        if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
 340                u8 *data = (u8 *)rxd;
 341
 342                if (status->flag & RX_FLAG_DECRYPTED) {
 343                        switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) {
 344                        case MT_CIPHER_AES_CCMP:
 345                        case MT_CIPHER_CCMP_CCX:
 346                        case MT_CIPHER_CCMP_256:
 347                                insert_ccmp_hdr =
 348                                        FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
 349                                fallthrough;
 350                        case MT_CIPHER_TKIP:
 351                        case MT_CIPHER_TKIP_NO_MIC:
 352                        case MT_CIPHER_GCMP:
 353                        case MT_CIPHER_GCMP_256:
 354                                status->iv[0] = data[5];
 355                                status->iv[1] = data[4];
 356                                status->iv[2] = data[3];
 357                                status->iv[3] = data[2];
 358                                status->iv[4] = data[1];
 359                                status->iv[5] = data[0];
 360                                break;
 361                        default:
 362                                break;
 363                        }
 364                }
 365                rxd += 4;
 366                if ((u8 *)rxd - skb->data >= skb->len)
 367                        return -EINVAL;
 368        }
 369
 370        if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
 371                status->timestamp = le32_to_cpu(rxd[0]);
 372                status->flag |= RX_FLAG_MACTIME_START;
 373
 374                if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
 375                              MT_RXD2_NORMAL_NON_AMPDU))) {
 376                        status->flag |= RX_FLAG_AMPDU_DETAILS;
 377
 378                        /* all subframes of an A-MPDU have the same timestamp */
 379                        if (phy->rx_ampdu_ts != status->timestamp) {
 380                                if (!++phy->ampdu_ref)
 381                                        phy->ampdu_ref++;
 382                        }
 383                        phy->rx_ampdu_ts = status->timestamp;
 384
 385                        status->ampdu_ref = phy->ampdu_ref;
 386                }
 387
 388                rxd += 2;
 389                if ((u8 *)rxd - skb->data >= skb->len)
 390                        return -EINVAL;
 391        }
 392
 393        if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
 394                u32 rxdg5 = le32_to_cpu(rxd[5]);
 395
 396                /*
 397                 * If both PHYs are on the same channel and we don't have a WCID,
 398                 * we need to figure out which PHY this packet was received on.
 399                 * On the primary PHY, the noise value for the chains belonging to the
 400                 * second PHY will be set to the noise value of the last packet from
 401                 * that PHY.
 402                 */
 403                if (phy_idx < 0) {
 404                        int first_chain = ffs(phy2->mt76->chainmask) - 1;
 405
 406                        phy_idx = ((rxdg5 >> (first_chain * 8)) & 0xff) == 0;
 407                }
 408        }
 409
 410        if (phy_idx == 1 && phy2) {
 411                mphy = dev->mt76.phy2;
 412                phy = phy2;
 413                status->ext_phy = true;
 414        }
 415
 416        if (!mt7615_firmware_offload(dev) && chfreq != phy->chfreq)
 417                return -EINVAL;
 418
 419        mt7615_get_status_freq_info(dev, mphy, status, chfreq);
 420        if (status->band == NL80211_BAND_5GHZ)
 421                sband = &mphy->sband_5g.sband;
 422        else
 423                sband = &mphy->sband_2g.sband;
 424
 425        if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
 426                return -EINVAL;
 427
 428        if (!sband->channels)
 429                return -EINVAL;
 430
 431        if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
 432                u32 rxdg0 = le32_to_cpu(rxd[0]);
 433                u32 rxdg1 = le32_to_cpu(rxd[1]);
 434                u32 rxdg3 = le32_to_cpu(rxd[3]);
 435                u8 stbc = FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
 436                bool cck = false;
 437
 438                i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
 439                switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
 440                case MT_PHY_TYPE_CCK:
 441                        cck = true;
 442                        fallthrough;
 443                case MT_PHY_TYPE_OFDM:
 444                        i = mt76_get_rate(&dev->mt76, sband, i, cck);
 445                        break;
 446                case MT_PHY_TYPE_HT_GF:
 447                case MT_PHY_TYPE_HT:
 448                        status->encoding = RX_ENC_HT;
 449                        if (i > 31)
 450                                return -EINVAL;
 451                        break;
 452                case MT_PHY_TYPE_VHT:
 453                        status->nss = FIELD_GET(MT_RXV2_NSTS, rxdg1) + 1;
 454                        status->encoding = RX_ENC_VHT;
 455                        break;
 456                default:
 457                        return -EINVAL;
 458                }
 459                status->rate_idx = i;
 460
 461                switch (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0)) {
 462                case MT_PHY_BW_20:
 463                        break;
 464                case MT_PHY_BW_40:
 465                        status->bw = RATE_INFO_BW_40;
 466                        break;
 467                case MT_PHY_BW_80:
 468                        status->bw = RATE_INFO_BW_80;
 469                        break;
 470                case MT_PHY_BW_160:
 471                        status->bw = RATE_INFO_BW_160;
 472                        break;
 473                default:
 474                        return -EINVAL;
 475                }
 476
 477                if (rxdg0 & MT_RXV1_HT_SHORT_GI)
 478                        status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
 479                if (rxdg0 & MT_RXV1_HT_AD_CODE)
 480                        status->enc_flags |= RX_ENC_FLAG_LDPC;
 481
 482                status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
 483
 484                status->chains = mphy->antenna_mask;
 485                status->chain_signal[0] = to_rssi(MT_RXV4_RCPI0, rxdg3);
 486                status->chain_signal[1] = to_rssi(MT_RXV4_RCPI1, rxdg3);
 487                status->chain_signal[2] = to_rssi(MT_RXV4_RCPI2, rxdg3);
 488                status->chain_signal[3] = to_rssi(MT_RXV4_RCPI3, rxdg3);
 489                status->signal = status->chain_signal[0];
 490
 491                for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
 492                        if (!(status->chains & BIT(i)))
 493                                continue;
 494
 495                        status->signal = max(status->signal,
 496                                             status->chain_signal[i]);
 497                }
 498
 499                mt7615_mac_fill_tm_rx(mphy->priv, rxd);
 500
 501                rxd += 6;
 502                if ((u8 *)rxd - skb->data >= skb->len)
 503                        return -EINVAL;
 504        }
 505
 506        skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
 507
 508        amsdu_info = FIELD_GET(MT_RXD1_NORMAL_PAYLOAD_FORMAT, rxd1);
 509        status->amsdu = !!amsdu_info;
 510        if (status->amsdu) {
 511                status->first_amsdu = amsdu_info == MT_RXD1_FIRST_AMSDU_FRAME;
 512                status->last_amsdu = amsdu_info == MT_RXD1_LAST_AMSDU_FRAME;
 513                if (!hdr_trans) {
 514                        memmove(skb->data + 2, skb->data,
 515                                ieee80211_get_hdrlen_from_skb(skb));
 516                        skb_pull(skb, 2);
 517                }
 518        }
 519
 520        if (insert_ccmp_hdr && !hdr_trans) {
 521                u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
 522
 523                mt76_insert_ccmp_hdr(skb, key_id);
 524        }
 525
 526        if (!hdr_trans) {
 527                hdr = (struct ieee80211_hdr *)skb->data;
 528                fc = hdr->frame_control;
 529                if (ieee80211_is_data_qos(fc)) {
 530                        seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
 531                        qos_ctl = *ieee80211_get_qos_ctl(hdr);
 532                }
 533        } else {
 534                status->flag |= RX_FLAG_8023;
 535        }
 536
 537        if (!status->wcid || !ieee80211_is_data_qos(fc))
 538                return 0;
 539
 540        status->aggr = unicast &&
 541                       !ieee80211_is_qos_nullfunc(fc);
 542        status->qos_ctl = qos_ctl;
 543        status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl);
 544
 545        return 0;
 546}
 547
 548void mt7615_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
 549{
 550}
 551EXPORT_SYMBOL_GPL(mt7615_sta_ps);
 552
 553static u16
 554mt7615_mac_tx_rate_val(struct mt7615_dev *dev,
 555                       struct mt76_phy *mphy,
 556                       const struct ieee80211_tx_rate *rate,
 557                       bool stbc, u8 *bw)
 558{
 559        u8 phy, nss, rate_idx;
 560        u16 rateval = 0;
 561
 562        *bw = 0;
 563
 564        if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
 565                rate_idx = ieee80211_rate_get_vht_mcs(rate);
 566                nss = ieee80211_rate_get_vht_nss(rate);
 567                phy = MT_PHY_TYPE_VHT;
 568                if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
 569                        *bw = 1;
 570                else if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
 571                        *bw = 2;
 572                else if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
 573                        *bw = 3;
 574        } else if (rate->flags & IEEE80211_TX_RC_MCS) {
 575                rate_idx = rate->idx;
 576                nss = 1 + (rate->idx >> 3);
 577                phy = MT_PHY_TYPE_HT;
 578                if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
 579                        phy = MT_PHY_TYPE_HT_GF;
 580                if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
 581                        *bw = 1;
 582        } else {
 583                const struct ieee80211_rate *r;
 584                int band = mphy->chandef.chan->band;
 585                u16 val;
 586
 587                nss = 1;
 588                r = &mphy->hw->wiphy->bands[band]->bitrates[rate->idx];
 589                if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
 590                        val = r->hw_value_short;
 591                else
 592                        val = r->hw_value;
 593
 594                phy = val >> 8;
 595                rate_idx = val & 0xff;
 596        }
 597
 598        if (stbc && nss == 1) {
 599                nss++;
 600                rateval |= MT_TX_RATE_STBC;
 601        }
 602
 603        rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
 604                    FIELD_PREP(MT_TX_RATE_MODE, phy) |
 605                    FIELD_PREP(MT_TX_RATE_NSS, nss - 1));
 606
 607        return rateval;
 608}
 609
 610int mt7615_mac_write_txwi(struct mt7615_dev *dev, __le32 *txwi,
 611                          struct sk_buff *skb, struct mt76_wcid *wcid,
 612                          struct ieee80211_sta *sta, int pid,
 613                          struct ieee80211_key_conf *key, bool beacon)
 614{
 615        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
 616        u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
 617        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 618        struct ieee80211_tx_rate *rate = &info->control.rates[0];
 619        bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
 620        bool multicast = is_multicast_ether_addr(hdr->addr1);
 621        struct ieee80211_vif *vif = info->control.vif;
 622        bool is_mmio = mt76_is_mmio(&dev->mt76);
 623        u32 val, sz_txd = is_mmio ? MT_TXD_SIZE : MT_USB_TXD_SIZE;
 624        struct mt76_phy *mphy = &dev->mphy;
 625        __le16 fc = hdr->frame_control;
 626        int tx_count = 8;
 627        u16 seqno = 0;
 628
 629        if (vif) {
 630                struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
 631
 632                omac_idx = mvif->omac_idx;
 633                wmm_idx = mvif->wmm_idx;
 634        }
 635
 636        if (sta) {
 637                struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
 638
 639                tx_count = msta->rate_count;
 640        }
 641
 642        if (ext_phy && dev->mt76.phy2)
 643                mphy = dev->mt76.phy2;
 644
 645        fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
 646        fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
 647
 648        if (beacon) {
 649                p_fmt = MT_TX_TYPE_FW;
 650                q_idx = ext_phy ? MT_LMAC_BCN1 : MT_LMAC_BCN0;
 651        } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) {
 652                p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
 653                q_idx = ext_phy ? MT_LMAC_ALTX1 : MT_LMAC_ALTX0;
 654        } else {
 655                p_fmt = is_mmio ? MT_TX_TYPE_CT : MT_TX_TYPE_SF;
 656                q_idx = wmm_idx * MT7615_MAX_WMM_SETS +
 657                        mt7615_lmac_mapping(dev, skb_get_queue_mapping(skb));
 658        }
 659
 660        val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + sz_txd) |
 661              FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) |
 662              FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
 663        txwi[0] = cpu_to_le32(val);
 664
 665        val = MT_TXD1_LONG_FORMAT |
 666              FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
 667              FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
 668              FIELD_PREP(MT_TXD1_HDR_INFO,
 669                         ieee80211_get_hdrlen_from_skb(skb) / 2) |
 670              FIELD_PREP(MT_TXD1_TID,
 671                         skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
 672              FIELD_PREP(MT_TXD1_PKT_FMT, p_fmt) |
 673              FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
 674        txwi[1] = cpu_to_le32(val);
 675
 676        val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
 677              FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
 678              FIELD_PREP(MT_TXD2_MULTICAST, multicast);
 679        if (key) {
 680                if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
 681                    key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
 682                        val |= MT_TXD2_BIP;
 683                        txwi[3] = 0;
 684                } else {
 685                        txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
 686                }
 687        } else {
 688                txwi[3] = 0;
 689        }
 690        txwi[2] = cpu_to_le32(val);
 691
 692        if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
 693                txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
 694
 695        txwi[4] = 0;
 696        txwi[6] = 0;
 697
 698        if (rate->idx >= 0 && rate->count &&
 699            !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
 700                bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
 701                u8 bw;
 702                u16 rateval = mt7615_mac_tx_rate_val(dev, mphy, rate, stbc,
 703                                                     &bw);
 704
 705                txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
 706
 707                val = MT_TXD6_FIXED_BW |
 708                      FIELD_PREP(MT_TXD6_BW, bw) |
 709                      FIELD_PREP(MT_TXD6_TX_RATE, rateval);
 710                txwi[6] |= cpu_to_le32(val);
 711
 712                if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
 713                        txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
 714
 715                if (info->flags & IEEE80211_TX_CTL_LDPC)
 716                        txwi[6] |= cpu_to_le32(MT_TXD6_LDPC);
 717
 718                if (!(rate->flags & (IEEE80211_TX_RC_MCS |
 719                                     IEEE80211_TX_RC_VHT_MCS)))
 720                        txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
 721
 722                tx_count = rate->count;
 723        }
 724
 725        if (!ieee80211_is_beacon(fc)) {
 726                struct ieee80211_hw *hw = mt76_hw(dev);
 727
 728                val = MT_TXD5_TX_STATUS_HOST | FIELD_PREP(MT_TXD5_PID, pid);
 729                if (!ieee80211_hw_check(hw, SUPPORTS_PS))
 730                        val |= MT_TXD5_SW_POWER_MGMT;
 731                txwi[5] = cpu_to_le32(val);
 732        } else {
 733                txwi[5] = 0;
 734                /* use maximum tx count for beacons */
 735                tx_count = 0x1f;
 736        }
 737
 738        val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
 739        if (info->flags & IEEE80211_TX_CTL_INJECTED) {
 740                seqno = le16_to_cpu(hdr->seq_ctrl);
 741
 742                if (ieee80211_is_back_req(hdr->frame_control)) {
 743                        struct ieee80211_bar *bar;
 744
 745                        bar = (struct ieee80211_bar *)skb->data;
 746                        seqno = le16_to_cpu(bar->start_seq_num);
 747                }
 748
 749                val |= MT_TXD3_SN_VALID |
 750                       FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno));
 751        }
 752
 753        txwi[3] |= cpu_to_le32(val);
 754
 755        if (info->flags & IEEE80211_TX_CTL_NO_ACK)
 756                txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
 757
 758        txwi[7] = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
 759                  FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype) |
 760                  FIELD_PREP(MT_TXD7_SPE_IDX, 0x18);
 761        if (!is_mmio)
 762                txwi[8] = FIELD_PREP(MT_TXD8_L_TYPE, fc_type) |
 763                          FIELD_PREP(MT_TXD8_L_SUB_TYPE, fc_stype);
 764
 765        return 0;
 766}
 767EXPORT_SYMBOL_GPL(mt7615_mac_write_txwi);
 768
 769static void
 770mt7615_txp_skb_unmap_fw(struct mt76_dev *dev, struct mt7615_fw_txp *txp)
 771{
 772        int i;
 773
 774        for (i = 0; i < txp->nbuf; i++)
 775                dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
 776                                 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
 777}
 778
 779static void
 780mt7615_txp_skb_unmap_hw(struct mt76_dev *dev, struct mt7615_hw_txp *txp)
 781{
 782        u32 last_mask;
 783        int i;
 784
 785        last_mask = is_mt7663(dev) ? MT_TXD_LEN_LAST : MT_TXD_LEN_MSDU_LAST;
 786
 787        for (i = 0; i < ARRAY_SIZE(txp->ptr); i++) {
 788                struct mt7615_txp_ptr *ptr = &txp->ptr[i];
 789                bool last;
 790                u16 len;
 791
 792                len = le16_to_cpu(ptr->len0);
 793                last = len & last_mask;
 794                len &= MT_TXD_LEN_MASK;
 795                dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf0), len,
 796                                 DMA_TO_DEVICE);
 797                if (last)
 798                        break;
 799
 800                len = le16_to_cpu(ptr->len1);
 801                last = len & last_mask;
 802                len &= MT_TXD_LEN_MASK;
 803                dma_unmap_single(dev->dev, le32_to_cpu(ptr->buf1), len,
 804                                 DMA_TO_DEVICE);
 805                if (last)
 806                        break;
 807        }
 808}
 809
 810void mt7615_txp_skb_unmap(struct mt76_dev *dev,
 811                          struct mt76_txwi_cache *t)
 812{
 813        struct mt7615_txp_common *txp;
 814
 815        txp = mt7615_txwi_to_txp(dev, t);
 816        if (is_mt7615(dev))
 817                mt7615_txp_skb_unmap_fw(dev, &txp->fw);
 818        else
 819                mt7615_txp_skb_unmap_hw(dev, &txp->hw);
 820}
 821EXPORT_SYMBOL_GPL(mt7615_txp_skb_unmap);
 822
 823bool mt7615_mac_wtbl_update(struct mt7615_dev *dev, int idx, u32 mask)
 824{
 825        mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
 826                 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
 827
 828        return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
 829                         0, 5000);
 830}
 831
 832void mt7615_mac_sta_poll(struct mt7615_dev *dev)
 833{
 834        static const u8 ac_to_tid[4] = {
 835                [IEEE80211_AC_BE] = 0,
 836                [IEEE80211_AC_BK] = 1,
 837                [IEEE80211_AC_VI] = 4,
 838                [IEEE80211_AC_VO] = 6
 839        };
 840        static const u8 hw_queue_map[] = {
 841                [IEEE80211_AC_BK] = 0,
 842                [IEEE80211_AC_BE] = 1,
 843                [IEEE80211_AC_VI] = 2,
 844                [IEEE80211_AC_VO] = 3,
 845        };
 846        struct ieee80211_sta *sta;
 847        struct mt7615_sta *msta;
 848        u32 addr, tx_time[4], rx_time[4];
 849        struct list_head sta_poll_list;
 850        int i;
 851
 852        INIT_LIST_HEAD(&sta_poll_list);
 853        spin_lock_bh(&dev->sta_poll_lock);
 854        list_splice_init(&dev->sta_poll_list, &sta_poll_list);
 855        spin_unlock_bh(&dev->sta_poll_lock);
 856
 857        while (!list_empty(&sta_poll_list)) {
 858                bool clear = false;
 859
 860                msta = list_first_entry(&sta_poll_list, struct mt7615_sta,
 861                                        poll_list);
 862                list_del_init(&msta->poll_list);
 863
 864                addr = mt7615_mac_wtbl_addr(dev, msta->wcid.idx) + 19 * 4;
 865
 866                for (i = 0; i < 4; i++, addr += 8) {
 867                        u32 tx_last = msta->airtime_ac[i];
 868                        u32 rx_last = msta->airtime_ac[i + 4];
 869
 870                        msta->airtime_ac[i] = mt76_rr(dev, addr);
 871                        msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
 872                        tx_time[i] = msta->airtime_ac[i] - tx_last;
 873                        rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
 874
 875                        if ((tx_last | rx_last) & BIT(30))
 876                                clear = true;
 877                }
 878
 879                if (clear) {
 880                        mt7615_mac_wtbl_update(dev, msta->wcid.idx,
 881                                               MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
 882                        memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
 883                }
 884
 885                if (!msta->wcid.sta)
 886                        continue;
 887
 888                sta = container_of((void *)msta, struct ieee80211_sta,
 889                                   drv_priv);
 890                for (i = 0; i < 4; i++) {
 891                        u32 tx_cur = tx_time[i];
 892                        u32 rx_cur = rx_time[hw_queue_map[i]];
 893                        u8 tid = ac_to_tid[i];
 894
 895                        if (!tx_cur && !rx_cur)
 896                                continue;
 897
 898                        ieee80211_sta_register_airtime(sta, tid, tx_cur,
 899                                                       rx_cur);
 900                }
 901        }
 902}
 903EXPORT_SYMBOL_GPL(mt7615_mac_sta_poll);
 904
 905static void
 906mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta,
 907                            struct ieee80211_tx_rate *probe_rate,
 908                            struct ieee80211_tx_rate *rates,
 909                            struct mt7615_rate_desc *rd)
 910{
 911        struct mt7615_dev *dev = phy->dev;
 912        struct mt76_phy *mphy = phy->mt76;
 913        struct ieee80211_tx_rate *ref;
 914        bool rateset, stbc = false;
 915        int n_rates = sta->n_rates;
 916        u8 bw, bw_prev;
 917        int i, j;
 918
 919        for (i = n_rates; i < 4; i++)
 920                rates[i] = rates[n_rates - 1];
 921
 922        rateset = !(sta->rate_set_tsf & BIT(0));
 923        memcpy(sta->rateset[rateset].rates, rates,
 924               sizeof(sta->rateset[rateset].rates));
 925        if (probe_rate) {
 926                sta->rateset[rateset].probe_rate = *probe_rate;
 927                ref = &sta->rateset[rateset].probe_rate;
 928        } else {
 929                sta->rateset[rateset].probe_rate.idx = -1;
 930                ref = &sta->rateset[rateset].rates[0];
 931        }
 932
 933        rates = sta->rateset[rateset].rates;
 934        for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
 935                /*
 936                 * We don't support switching between short and long GI
 937                 * within the rate set. For accurate tx status reporting, we
 938                 * need to make sure that flags match.
 939                 * For improved performance, avoid duplicate entries by
 940                 * decrementing the MCS index if necessary
 941                 */
 942                if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
 943                        rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
 944
 945                for (j = 0; j < i; j++) {
 946                        if (rates[i].idx != rates[j].idx)
 947                                continue;
 948                        if ((rates[i].flags ^ rates[j].flags) &
 949                            (IEEE80211_TX_RC_40_MHZ_WIDTH |
 950                             IEEE80211_TX_RC_80_MHZ_WIDTH |
 951                             IEEE80211_TX_RC_160_MHZ_WIDTH))
 952                                continue;
 953
 954                        if (!rates[i].idx)
 955                                continue;
 956
 957                        rates[i].idx--;
 958                }
 959        }
 960
 961        rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw);
 962        bw_prev = bw;
 963
 964        if (probe_rate) {
 965                rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate,
 966                                                       stbc, &bw);
 967                if (bw)
 968                        rd->bw_idx = 1;
 969                else
 970                        bw_prev = 0;
 971        } else {
 972                rd->probe_val = rd->val[0];
 973        }
 974
 975        rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw);
 976        if (bw_prev) {
 977                rd->bw_idx = 3;
 978                bw_prev = bw;
 979        }
 980
 981        rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw);
 982        if (bw_prev) {
 983                rd->bw_idx = 5;
 984                bw_prev = bw;
 985        }
 986
 987        rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw);
 988        if (bw_prev)
 989                rd->bw_idx = 7;
 990
 991        rd->rateset = rateset;
 992        rd->bw = bw;
 993}
 994
 995static int
 996mt7615_mac_queue_rate_update(struct mt7615_phy *phy, struct mt7615_sta *sta,
 997                             struct ieee80211_tx_rate *probe_rate,
 998                             struct ieee80211_tx_rate *rates)
 999{
1000        struct mt7615_dev *dev = phy->dev;
1001        struct mt7615_wtbl_rate_desc *wrd;
1002
1003        if (work_pending(&dev->rate_work))
1004                return -EBUSY;
1005
1006        wrd = kzalloc(sizeof(*wrd), GFP_ATOMIC);
1007        if (!wrd)
1008                return -ENOMEM;
1009
1010        wrd->sta = sta;
1011        mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates,
1012                                    &wrd->rate);
1013        list_add_tail(&wrd->node, &dev->wrd_head);
1014        queue_work(dev->mt76.wq, &dev->rate_work);
1015
1016        return 0;
1017}
1018
1019u32 mt7615_mac_get_sta_tid_sn(struct mt7615_dev *dev, int wcid, u8 tid)
1020{
1021        u32 addr, val, val2;
1022        u8 offset;
1023
1024        addr = mt7615_mac_wtbl_addr(dev, wcid) + 11 * 4;
1025
1026        offset = tid * 12;
1027        addr += 4 * (offset / 32);
1028        offset %= 32;
1029
1030        val = mt76_rr(dev, addr);
1031        val >>= (tid % 32);
1032
1033        if (offset > 20) {
1034                addr += 4;
1035                val2 = mt76_rr(dev, addr);
1036                val |= val2 << (32 - offset);
1037        }
1038
1039        return val & GENMASK(11, 0);
1040}
1041
1042void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
1043                          struct ieee80211_tx_rate *probe_rate,
1044                          struct ieee80211_tx_rate *rates)
1045{
1046        int wcid = sta->wcid.idx, n_rates = sta->n_rates;
1047        struct mt7615_dev *dev = phy->dev;
1048        struct mt7615_rate_desc rd;
1049        u32 w5, w27, addr;
1050        u16 idx = sta->vif->mt76.omac_idx;
1051
1052        if (!mt76_is_mmio(&dev->mt76)) {
1053                mt7615_mac_queue_rate_update(phy, sta, probe_rate, rates);
1054                return;
1055        }
1056
1057        if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1058                return;
1059
1060        memset(&rd, 0, sizeof(struct mt7615_rate_desc));
1061        mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd);
1062
1063        addr = mt7615_mac_wtbl_addr(dev, wcid);
1064        w27 = mt76_rr(dev, addr + 27 * 4);
1065        w27 &= ~MT_WTBL_W27_CC_BW_SEL;
1066        w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw);
1067
1068        w5 = mt76_rr(dev, addr + 5 * 4);
1069        w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
1070                MT_WTBL_W5_MPDU_OK_COUNT |
1071                MT_WTBL_W5_MPDU_FAIL_COUNT |
1072                MT_WTBL_W5_RATE_IDX);
1073        w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) |
1074              FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE,
1075                         rd.bw_idx ? rd.bw_idx - 1 : 7);
1076
1077        mt76_wr(dev, MT_WTBL_RIUCR0, w5);
1078
1079        mt76_wr(dev, MT_WTBL_RIUCR1,
1080                FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) |
1081                FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) |
1082                FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1]));
1083
1084        mt76_wr(dev, MT_WTBL_RIUCR2,
1085                FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) |
1086                FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) |
1087                FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) |
1088                FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2]));
1089
1090        mt76_wr(dev, MT_WTBL_RIUCR3,
1091                FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) |
1092                FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) |
1093                FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3]));
1094
1095        mt76_wr(dev, MT_WTBL_UPDATE,
1096                FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
1097                MT_WTBL_UPDATE_RATE_UPDATE |
1098                MT_WTBL_UPDATE_TX_COUNT_CLEAR);
1099
1100        mt76_wr(dev, addr + 27 * 4, w27);
1101
1102        idx = idx > HW_BSSID_MAX ? HW_BSSID_0 : idx;
1103        addr = idx > 1 ? MT_LPON_TCR2(idx): MT_LPON_TCR0(idx);
1104
1105        mt76_rmw(dev, addr, MT_LPON_TCR_MODE, MT_LPON_TCR_READ); /* TSF read */
1106        sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0);
1107        sta->rate_set_tsf |= rd.rateset;
1108
1109        if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
1110                mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
1111
1112        sta->rate_count = 2 * MT7615_RATE_RETRY * n_rates;
1113        sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
1114        sta->rate_probe = !!probe_rate;
1115}
1116EXPORT_SYMBOL_GPL(mt7615_mac_set_rates);
1117
1118static int
1119mt7615_mac_wtbl_update_key(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1120                           struct ieee80211_key_conf *key,
1121                           enum mt76_cipher_type cipher, u16 cipher_mask,
1122                           enum set_key_cmd cmd)
1123{
1124        u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx) + 30 * 4;
1125        u8 data[32] = {};
1126
1127        if (key->keylen > sizeof(data))
1128                return -EINVAL;
1129
1130        mt76_rr_copy(dev, addr, data, sizeof(data));
1131        if (cmd == SET_KEY) {
1132                if (cipher == MT_CIPHER_TKIP) {
1133                        /* Rx/Tx MIC keys are swapped */
1134                        memcpy(data, key->key, 16);
1135                        memcpy(data + 16, key->key + 24, 8);
1136                        memcpy(data + 24, key->key + 16, 8);
1137                } else {
1138                        if (cipher_mask == BIT(cipher))
1139                                memcpy(data, key->key, key->keylen);
1140                        else if (cipher != MT_CIPHER_BIP_CMAC_128)
1141                                memcpy(data, key->key, 16);
1142                        if (cipher == MT_CIPHER_BIP_CMAC_128)
1143                                memcpy(data + 16, key->key, 16);
1144                }
1145        } else {
1146                if (cipher == MT_CIPHER_BIP_CMAC_128)
1147                        memset(data + 16, 0, 16);
1148                else if (cipher_mask)
1149                        memset(data, 0, 16);
1150                if (!cipher_mask)
1151                        memset(data, 0, sizeof(data));
1152        }
1153
1154        mt76_wr_copy(dev, addr, data, sizeof(data));
1155
1156        return 0;
1157}
1158
1159static int
1160mt7615_mac_wtbl_update_pk(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1161                          enum mt76_cipher_type cipher, u16 cipher_mask,
1162                          int keyidx, enum set_key_cmd cmd)
1163{
1164        u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx), w0, w1;
1165
1166        if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
1167                return -ETIMEDOUT;
1168
1169        w0 = mt76_rr(dev, addr);
1170        w1 = mt76_rr(dev, addr + 4);
1171
1172        if (cipher_mask)
1173                w0 |= MT_WTBL_W0_RX_KEY_VALID;
1174        else
1175                w0 &= ~(MT_WTBL_W0_RX_KEY_VALID | MT_WTBL_W0_KEY_IDX);
1176        if (cipher_mask & BIT(MT_CIPHER_BIP_CMAC_128))
1177                w0 |= MT_WTBL_W0_RX_IK_VALID;
1178        else
1179                w0 &= ~MT_WTBL_W0_RX_IK_VALID;
1180
1181        if (cmd == SET_KEY &&
1182            (cipher != MT_CIPHER_BIP_CMAC_128 ||
1183             cipher_mask == BIT(cipher))) {
1184                w0 &= ~MT_WTBL_W0_KEY_IDX;
1185                w0 |= FIELD_PREP(MT_WTBL_W0_KEY_IDX, keyidx);
1186        }
1187
1188        mt76_wr(dev, MT_WTBL_RICR0, w0);
1189        mt76_wr(dev, MT_WTBL_RICR1, w1);
1190
1191        if (!mt7615_mac_wtbl_update(dev, wcid->idx,
1192                                    MT_WTBL_UPDATE_RXINFO_UPDATE))
1193                return -ETIMEDOUT;
1194
1195        return 0;
1196}
1197
1198static void
1199mt7615_mac_wtbl_update_cipher(struct mt7615_dev *dev, struct mt76_wcid *wcid,
1200                              enum mt76_cipher_type cipher, u16 cipher_mask,
1201                              enum set_key_cmd cmd)
1202{
1203        u32 addr = mt7615_mac_wtbl_addr(dev, wcid->idx);
1204
1205        if (!cipher_mask) {
1206                mt76_clear(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE);
1207                return;
1208        }
1209
1210        if (cmd != SET_KEY)
1211                return;
1212
1213        if (cipher == MT_CIPHER_BIP_CMAC_128 &&
1214            cipher_mask & ~BIT(MT_CIPHER_BIP_CMAC_128))
1215                return;
1216
1217        mt76_rmw(dev, addr + 2 * 4, MT_WTBL_W2_KEY_TYPE,
1218                 FIELD_PREP(MT_WTBL_W2_KEY_TYPE, cipher));
1219}
1220
1221int __mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1222                              struct mt76_wcid *wcid,
1223                              struct ieee80211_key_conf *key,
1224                              enum set_key_cmd cmd)
1225{
1226        enum mt76_cipher_type cipher;
1227        u16 cipher_mask = wcid->cipher;
1228        int err;
1229
1230        cipher = mt7615_mac_get_cipher(key->cipher);
1231        if (cipher == MT_CIPHER_NONE)
1232                return -EOPNOTSUPP;
1233
1234        if (cmd == SET_KEY)
1235                cipher_mask |= BIT(cipher);
1236        else
1237                cipher_mask &= ~BIT(cipher);
1238
1239        mt7615_mac_wtbl_update_cipher(dev, wcid, cipher, cipher_mask, cmd);
1240        err = mt7615_mac_wtbl_update_key(dev, wcid, key, cipher, cipher_mask,
1241                                         cmd);
1242        if (err < 0)
1243                return err;
1244
1245        err = mt7615_mac_wtbl_update_pk(dev, wcid, cipher, cipher_mask,
1246                                        key->keyidx, cmd);
1247        if (err < 0)
1248                return err;
1249
1250        wcid->cipher = cipher_mask;
1251
1252        return 0;
1253}
1254
1255int mt7615_mac_wtbl_set_key(struct mt7615_dev *dev,
1256                            struct mt76_wcid *wcid,
1257                            struct ieee80211_key_conf *key,
1258                            enum set_key_cmd cmd)
1259{
1260        int err;
1261
1262        spin_lock_bh(&dev->mt76.lock);
1263        err = __mt7615_mac_wtbl_set_key(dev, wcid, key, cmd);
1264        spin_unlock_bh(&dev->mt76.lock);
1265
1266        return err;
1267}
1268
1269static bool mt7615_fill_txs(struct mt7615_dev *dev, struct mt7615_sta *sta,
1270                            struct ieee80211_tx_info *info, __le32 *txs_data)
1271{
1272        struct ieee80211_supported_band *sband;
1273        struct mt7615_rate_set *rs;
1274        struct mt76_phy *mphy;
1275        int first_idx = 0, last_idx;
1276        int i, idx, count;
1277        bool fixed_rate, ack_timeout;
1278        bool ampdu, cck = false;
1279        bool rs_idx;
1280        u32 rate_set_tsf;
1281        u32 final_rate, final_rate_flags, final_nss, txs;
1282
1283        txs = le32_to_cpu(txs_data[1]);
1284        ampdu = txs & MT_TXS1_AMPDU;
1285
1286        txs = le32_to_cpu(txs_data[3]);
1287        count = FIELD_GET(MT_TXS3_TX_COUNT, txs);
1288        last_idx = FIELD_GET(MT_TXS3_LAST_TX_RATE, txs);
1289
1290        txs = le32_to_cpu(txs_data[0]);
1291        fixed_rate = txs & MT_TXS0_FIXED_RATE;
1292        final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1293        ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1294
1295        if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1296                return false;
1297
1298        if (txs & MT_TXS0_QUEUE_TIMEOUT)
1299                return false;
1300
1301        if (!ack_timeout)
1302                info->flags |= IEEE80211_TX_STAT_ACK;
1303
1304        info->status.ampdu_len = 1;
1305        info->status.ampdu_ack_len = !!(info->flags &
1306                                        IEEE80211_TX_STAT_ACK);
1307
1308        if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1309                info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1310
1311        first_idx = max_t(int, 0, last_idx - (count - 1) / MT7615_RATE_RETRY);
1312
1313        if (fixed_rate) {
1314                info->status.rates[0].count = count;
1315                i = 0;
1316                goto out;
1317        }
1318
1319        rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1320        rs_idx = !((u32)(FIELD_GET(MT_TXS4_F0_TIMESTAMP, le32_to_cpu(txs_data[4])) -
1321                         rate_set_tsf) < 1000000);
1322        rs_idx ^= rate_set_tsf & BIT(0);
1323        rs = &sta->rateset[rs_idx];
1324
1325        if (!first_idx && rs->probe_rate.idx >= 0) {
1326                info->status.rates[0] = rs->probe_rate;
1327
1328                spin_lock_bh(&dev->mt76.lock);
1329                if (sta->rate_probe) {
1330                        struct mt7615_phy *phy = &dev->phy;
1331
1332                        if (sta->wcid.ext_phy && dev->mt76.phy2)
1333                                phy = dev->mt76.phy2->priv;
1334
1335                        mt7615_mac_set_rates(phy, sta, NULL, sta->rates);
1336                }
1337                spin_unlock_bh(&dev->mt76.lock);
1338        } else {
1339                info->status.rates[0] = rs->rates[first_idx / 2];
1340        }
1341        info->status.rates[0].count = 0;
1342
1343        for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1344                struct ieee80211_tx_rate *cur_rate;
1345                int cur_count;
1346
1347                cur_rate = &rs->rates[idx / 2];
1348                cur_count = min_t(int, MT7615_RATE_RETRY, count);
1349                count -= cur_count;
1350
1351                if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1352                            cur_rate->flags != info->status.rates[i].flags)) {
1353                        i++;
1354                        if (i == ARRAY_SIZE(info->status.rates)) {
1355                                i--;
1356                                break;
1357                        }
1358
1359                        info->status.rates[i] = *cur_rate;
1360                        info->status.rates[i].count = 0;
1361                }
1362
1363                info->status.rates[i].count += cur_count;
1364        }
1365
1366out:
1367        final_rate_flags = info->status.rates[i].flags;
1368
1369        switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1370        case MT_PHY_TYPE_CCK:
1371                cck = true;
1372                fallthrough;
1373        case MT_PHY_TYPE_OFDM:
1374                mphy = &dev->mphy;
1375                if (sta->wcid.ext_phy && dev->mt76.phy2)
1376                        mphy = dev->mt76.phy2;
1377
1378                if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
1379                        sband = &mphy->sband_5g.sband;
1380                else
1381                        sband = &mphy->sband_2g.sband;
1382                final_rate &= MT_TX_RATE_IDX;
1383                final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1384                                           cck);
1385                final_rate_flags = 0;
1386                break;
1387        case MT_PHY_TYPE_HT_GF:
1388        case MT_PHY_TYPE_HT:
1389                final_rate_flags |= IEEE80211_TX_RC_MCS;
1390                final_rate &= MT_TX_RATE_IDX;
1391                if (final_rate > 31)
1392                        return false;
1393                break;
1394        case MT_PHY_TYPE_VHT:
1395                final_nss = FIELD_GET(MT_TX_RATE_NSS, final_rate);
1396
1397                if ((final_rate & MT_TX_RATE_STBC) && final_nss)
1398                        final_nss--;
1399
1400                final_rate_flags |= IEEE80211_TX_RC_VHT_MCS;
1401                final_rate = (final_rate & MT_TX_RATE_IDX) | (final_nss << 4);
1402                break;
1403        default:
1404                return false;
1405        }
1406
1407        info->status.rates[i].idx = final_rate;
1408        info->status.rates[i].flags = final_rate_flags;
1409
1410        return true;
1411}
1412
1413static bool mt7615_mac_add_txs_skb(struct mt7615_dev *dev,
1414                                   struct mt7615_sta *sta, int pid,
1415                                   __le32 *txs_data)
1416{
1417        struct mt76_dev *mdev = &dev->mt76;
1418        struct sk_buff_head list;
1419        struct sk_buff *skb;
1420
1421        if (pid < MT_PACKET_ID_FIRST)
1422                return false;
1423
1424        trace_mac_txdone(mdev, sta->wcid.idx, pid);
1425
1426        mt76_tx_status_lock(mdev, &list);
1427        skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1428        if (skb) {
1429                struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1430
1431                if (!mt7615_fill_txs(dev, sta, info, txs_data)) {
1432                        info->status.rates[0].count = 0;
1433                        info->status.rates[0].idx = -1;
1434                }
1435
1436                mt76_tx_status_skb_done(mdev, skb, &list);
1437        }
1438        mt76_tx_status_unlock(mdev, &list);
1439
1440        return !!skb;
1441}
1442
1443static void mt7615_mac_add_txs(struct mt7615_dev *dev, void *data)
1444{
1445        struct ieee80211_tx_info info = {};
1446        struct ieee80211_sta *sta = NULL;
1447        struct mt7615_sta *msta = NULL;
1448        struct mt76_wcid *wcid;
1449        struct mt76_phy *mphy = &dev->mt76.phy;
1450        __le32 *txs_data = data;
1451        u32 txs;
1452        u8 wcidx;
1453        u8 pid;
1454
1455        txs = le32_to_cpu(txs_data[0]);
1456        pid = FIELD_GET(MT_TXS0_PID, txs);
1457        txs = le32_to_cpu(txs_data[2]);
1458        wcidx = FIELD_GET(MT_TXS2_WCID, txs);
1459
1460        if (pid == MT_PACKET_ID_NO_ACK)
1461                return;
1462
1463        if (wcidx >= MT7615_WTBL_SIZE)
1464                return;
1465
1466        rcu_read_lock();
1467
1468        wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1469        if (!wcid)
1470                goto out;
1471
1472        msta = container_of(wcid, struct mt7615_sta, wcid);
1473        sta = wcid_to_sta(wcid);
1474
1475        spin_lock_bh(&dev->sta_poll_lock);
1476        if (list_empty(&msta->poll_list))
1477                list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1478        spin_unlock_bh(&dev->sta_poll_lock);
1479
1480        if (mt7615_mac_add_txs_skb(dev, msta, pid, txs_data))
1481                goto out;
1482
1483        if (wcidx >= MT7615_WTBL_STA || !sta)
1484                goto out;
1485
1486        if (wcid->ext_phy && dev->mt76.phy2)
1487                mphy = dev->mt76.phy2;
1488
1489        if (mt7615_fill_txs(dev, msta, &info, txs_data))
1490                ieee80211_tx_status_noskb(mphy->hw, sta, &info);
1491
1492out:
1493        rcu_read_unlock();
1494}
1495
1496static void
1497mt7615_mac_tx_free_token(struct mt7615_dev *dev, u16 token)
1498{
1499        struct mt76_dev *mdev = &dev->mt76;
1500        struct mt76_txwi_cache *txwi;
1501        __le32 *txwi_data;
1502        u32 val;
1503        u8 wcid;
1504
1505        trace_mac_tx_free(dev, token);
1506        txwi = mt76_token_put(mdev, token);
1507        if (!txwi)
1508                return;
1509
1510        txwi_data = (__le32 *)mt76_get_txwi_ptr(mdev, txwi);
1511        val = le32_to_cpu(txwi_data[1]);
1512        wcid = FIELD_GET(MT_TXD1_WLAN_IDX, val);
1513
1514        mt7615_txp_skb_unmap(mdev, txwi);
1515        if (txwi->skb) {
1516                mt76_tx_complete_skb(mdev, wcid, txwi->skb);
1517                txwi->skb = NULL;
1518        }
1519
1520        mt76_put_txwi(mdev, txwi);
1521}
1522
1523static void mt7615_mac_tx_free(struct mt7615_dev *dev, struct sk_buff *skb)
1524{
1525        struct mt7615_tx_free *free = (struct mt7615_tx_free *)skb->data;
1526        u8 i, count;
1527
1528        mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
1529        if (is_mt7615(&dev->mt76)) {
1530                mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
1531        } else {
1532                for (i = 0; i < IEEE80211_NUM_ACS; i++)
1533                        mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
1534        }
1535
1536        count = FIELD_GET(MT_TX_FREE_MSDU_ID_CNT, le16_to_cpu(free->ctrl));
1537        if (is_mt7615(&dev->mt76)) {
1538                __le16 *token = &free->token[0];
1539
1540                for (i = 0; i < count; i++)
1541                        mt7615_mac_tx_free_token(dev, le16_to_cpu(token[i]));
1542        } else {
1543                __le32 *token = (__le32 *)&free->token[0];
1544
1545                for (i = 0; i < count; i++)
1546                        mt7615_mac_tx_free_token(dev, le32_to_cpu(token[i]));
1547        }
1548
1549        dev_kfree_skb(skb);
1550
1551        rcu_read_lock();
1552        mt7615_mac_sta_poll(dev);
1553        rcu_read_unlock();
1554
1555        mt76_worker_schedule(&dev->mt76.tx_worker);
1556}
1557
1558void mt7615_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1559                         struct sk_buff *skb)
1560{
1561        struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
1562        __le32 *rxd = (__le32 *)skb->data;
1563        __le32 *end = (__le32 *)&skb->data[skb->len];
1564        enum rx_pkt_type type;
1565        u16 flag;
1566
1567        type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
1568        flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0]));
1569        if (type == PKT_TYPE_RX_EVENT && flag == 0x1)
1570                type = PKT_TYPE_NORMAL_MCU;
1571
1572        switch (type) {
1573        case PKT_TYPE_TXS:
1574                for (rxd++; rxd + 7 <= end; rxd += 7)
1575                        mt7615_mac_add_txs(dev, rxd);
1576                dev_kfree_skb(skb);
1577                break;
1578        case PKT_TYPE_TXRX_NOTIFY:
1579                mt7615_mac_tx_free(dev, skb);
1580                break;
1581        case PKT_TYPE_RX_EVENT:
1582                mt7615_mcu_rx_event(dev, skb);
1583                break;
1584        case PKT_TYPE_NORMAL_MCU:
1585        case PKT_TYPE_NORMAL:
1586                if (!mt7615_mac_fill_rx(dev, skb)) {
1587                        mt76_rx(&dev->mt76, q, skb);
1588                        return;
1589                }
1590                fallthrough;
1591        default:
1592                dev_kfree_skb(skb);
1593                break;
1594        }
1595}
1596EXPORT_SYMBOL_GPL(mt7615_queue_rx_skb);
1597
1598static void
1599mt7615_mac_set_sensitivity(struct mt7615_phy *phy, int val, bool ofdm)
1600{
1601        struct mt7615_dev *dev = phy->dev;
1602        bool ext_phy = phy != &dev->phy;
1603
1604        if (is_mt7663(&dev->mt76)) {
1605                if (ofdm)
1606                        mt76_rmw(dev, MT7663_WF_PHY_MIN_PRI_PWR(ext_phy),
1607                                 MT_WF_PHY_PD_OFDM_MASK(0),
1608                                 MT_WF_PHY_PD_OFDM(0, val));
1609                else
1610                        mt76_rmw(dev, MT7663_WF_PHY_RXTD_CCK_PD(ext_phy),
1611                                 MT_WF_PHY_PD_CCK_MASK(ext_phy),
1612                                 MT_WF_PHY_PD_CCK(ext_phy, val));
1613                return;
1614        }
1615
1616        if (ofdm)
1617                mt76_rmw(dev, MT_WF_PHY_MIN_PRI_PWR(ext_phy),
1618                         MT_WF_PHY_PD_OFDM_MASK(ext_phy),
1619                         MT_WF_PHY_PD_OFDM(ext_phy, val));
1620        else
1621                mt76_rmw(dev, MT_WF_PHY_RXTD_CCK_PD(ext_phy),
1622                         MT_WF_PHY_PD_CCK_MASK(ext_phy),
1623                         MT_WF_PHY_PD_CCK(ext_phy, val));
1624}
1625
1626static void
1627mt7615_mac_set_default_sensitivity(struct mt7615_phy *phy)
1628{
1629        /* ofdm */
1630        mt7615_mac_set_sensitivity(phy, 0x13c, true);
1631        /* cck */
1632        mt7615_mac_set_sensitivity(phy, 0x92, false);
1633
1634        phy->ofdm_sensitivity = -98;
1635        phy->cck_sensitivity = -110;
1636        phy->last_cca_adj = jiffies;
1637}
1638
1639void mt7615_mac_set_scs(struct mt7615_phy *phy, bool enable)
1640{
1641        struct mt7615_dev *dev = phy->dev;
1642        bool ext_phy = phy != &dev->phy;
1643        u32 reg, mask;
1644
1645        mt7615_mutex_acquire(dev);
1646
1647        if (phy->scs_en == enable)
1648                goto out;
1649
1650        if (is_mt7663(&dev->mt76)) {
1651                reg = MT7663_WF_PHY_MIN_PRI_PWR(ext_phy);
1652                mask = MT_WF_PHY_PD_BLK(0);
1653        } else {
1654                reg = MT_WF_PHY_MIN_PRI_PWR(ext_phy);
1655                mask = MT_WF_PHY_PD_BLK(ext_phy);
1656        }
1657
1658        if (enable) {
1659                mt76_set(dev, reg, mask);
1660                if (is_mt7622(&dev->mt76)) {
1661                        mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7 << 8);
1662                        mt76_set(dev, MT_MIB_M0_MISC_CR(0), 0x7);
1663                }
1664        } else {
1665                mt76_clear(dev, reg, mask);
1666        }
1667
1668        mt7615_mac_set_default_sensitivity(phy);
1669        phy->scs_en = enable;
1670
1671out:
1672        mt7615_mutex_release(dev);
1673}
1674
1675void mt7615_mac_enable_nf(struct mt7615_dev *dev, bool ext_phy)
1676{
1677        u32 rxtd, reg;
1678
1679        if (is_mt7663(&dev->mt76))
1680                reg = MT7663_WF_PHY_R0_PHYMUX_5;
1681        else
1682                reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1683
1684        if (ext_phy)
1685                rxtd = MT_WF_PHY_RXTD2(10);
1686        else
1687                rxtd = MT_WF_PHY_RXTD(12);
1688
1689        mt76_set(dev, rxtd, BIT(18) | BIT(29));
1690        mt76_set(dev, reg, 0x5 << 12);
1691}
1692
1693void mt7615_mac_cca_stats_reset(struct mt7615_phy *phy)
1694{
1695        struct mt7615_dev *dev = phy->dev;
1696        bool ext_phy = phy != &dev->phy;
1697        u32 reg;
1698
1699        if (is_mt7663(&dev->mt76))
1700                reg = MT7663_WF_PHY_R0_PHYMUX_5;
1701        else
1702                reg = MT_WF_PHY_R0_PHYMUX_5(ext_phy);
1703
1704        /* reset PD and MDRDY counters */
1705        mt76_clear(dev, reg, GENMASK(22, 20));
1706        mt76_set(dev, reg, BIT(22) | BIT(20));
1707}
1708
1709static void
1710mt7615_mac_adjust_sensitivity(struct mt7615_phy *phy,
1711                              u32 rts_err_rate, bool ofdm)
1712{
1713        struct mt7615_dev *dev = phy->dev;
1714        int false_cca = ofdm ? phy->false_cca_ofdm : phy->false_cca_cck;
1715        bool ext_phy = phy != &dev->phy;
1716        u16 def_th = ofdm ? -98 : -110;
1717        bool update = false;
1718        s8 *sensitivity;
1719        int signal;
1720
1721        sensitivity = ofdm ? &phy->ofdm_sensitivity : &phy->cck_sensitivity;
1722        signal = mt76_get_min_avg_rssi(&dev->mt76, ext_phy);
1723        if (!signal) {
1724                mt7615_mac_set_default_sensitivity(phy);
1725                return;
1726        }
1727
1728        signal = min(signal, -72);
1729        if (false_cca > 500) {
1730                if (rts_err_rate > MT_FRAC(40, 100))
1731                        return;
1732
1733                /* decrease coverage */
1734                if (*sensitivity == def_th && signal > -90) {
1735                        *sensitivity = -90;
1736                        update = true;
1737                } else if (*sensitivity + 2 < signal) {
1738                        *sensitivity += 2;
1739                        update = true;
1740                }
1741        } else if ((false_cca > 0 && false_cca < 50) ||
1742                   rts_err_rate > MT_FRAC(60, 100)) {
1743                /* increase coverage */
1744                if (*sensitivity - 2 >= def_th) {
1745                        *sensitivity -= 2;
1746                        update = true;
1747                }
1748        }
1749
1750        if (*sensitivity > signal) {
1751                *sensitivity = signal;
1752                update = true;
1753        }
1754
1755        if (update) {
1756                u16 val = ofdm ? *sensitivity * 2 + 512 : *sensitivity + 256;
1757
1758                mt7615_mac_set_sensitivity(phy, val, ofdm);
1759                phy->last_cca_adj = jiffies;
1760        }
1761}
1762
1763static void
1764mt7615_mac_scs_check(struct mt7615_phy *phy)
1765{
1766        struct mt7615_dev *dev = phy->dev;
1767        struct mib_stats *mib = &phy->mib;
1768        u32 val, rts_err_rate = 0;
1769        u32 mdrdy_cck, mdrdy_ofdm, pd_cck, pd_ofdm;
1770        bool ext_phy = phy != &dev->phy;
1771
1772        if (!phy->scs_en)
1773                return;
1774
1775        if (is_mt7663(&dev->mt76))
1776                val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1777        else
1778                val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS0(ext_phy));
1779        pd_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_CCK, val);
1780        pd_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_PD_OFDM, val);
1781
1782        if (is_mt7663(&dev->mt76))
1783                val = mt76_rr(dev, MT7663_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1784        else
1785                val = mt76_rr(dev, MT_WF_PHY_R0_PHYCTRL_STS5(ext_phy));
1786        mdrdy_cck = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_CCK, val);
1787        mdrdy_ofdm = FIELD_GET(MT_WF_PHYCTRL_STAT_MDRDY_OFDM, val);
1788
1789        phy->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1790        phy->false_cca_cck = pd_cck - mdrdy_cck;
1791        mt7615_mac_cca_stats_reset(phy);
1792
1793        if (mib->rts_cnt + mib->rts_retries_cnt)
1794                rts_err_rate = MT_FRAC(mib->rts_retries_cnt,
1795                                       mib->rts_cnt + mib->rts_retries_cnt);
1796
1797        /* cck */
1798        mt7615_mac_adjust_sensitivity(phy, rts_err_rate, false);
1799        /* ofdm */
1800        mt7615_mac_adjust_sensitivity(phy, rts_err_rate, true);
1801
1802        if (time_after(jiffies, phy->last_cca_adj + 10 * HZ))
1803                mt7615_mac_set_default_sensitivity(phy);
1804}
1805
1806static u8
1807mt7615_phy_get_nf(struct mt7615_dev *dev, int idx)
1808{
1809        static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1810        u32 reg, val, sum = 0, n = 0;
1811        int i;
1812
1813        if (is_mt7663(&dev->mt76))
1814                reg = MT7663_WF_PHY_RXTD(20);
1815        else
1816                reg = idx ? MT_WF_PHY_RXTD2(17) : MT_WF_PHY_RXTD(20);
1817
1818        for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1819                val = mt76_rr(dev, reg);
1820                sum += val * nf_power[i];
1821                n += val;
1822        }
1823
1824        if (!n)
1825                return 0;
1826
1827        return sum / n;
1828}
1829
1830static void
1831mt7615_phy_update_channel(struct mt76_phy *mphy, int idx)
1832{
1833        struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1834        struct mt7615_phy *phy = mphy->priv;
1835        struct mt76_channel_state *state;
1836        u64 busy_time, tx_time, rx_time, obss_time;
1837        u32 obss_reg = idx ? MT_WF_RMAC_MIB_TIME6 : MT_WF_RMAC_MIB_TIME5;
1838        int nf;
1839
1840        busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1841                                   MT_MIB_SDR9_BUSY_MASK);
1842        tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1843                                 MT_MIB_SDR36_TXTIME_MASK);
1844        rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1845                                 MT_MIB_SDR37_RXTIME_MASK);
1846        obss_time = mt76_get_field(dev, obss_reg, MT_MIB_OBSSTIME_MASK);
1847
1848        nf = mt7615_phy_get_nf(dev, idx);
1849        if (!phy->noise)
1850                phy->noise = nf << 4;
1851        else if (nf)
1852                phy->noise += nf - (phy->noise >> 4);
1853
1854        state = mphy->chan_state;
1855        state->cc_busy += busy_time;
1856        state->cc_tx += tx_time;
1857        state->cc_rx += rx_time + obss_time;
1858        state->cc_bss_rx += rx_time;
1859        state->noise = -(phy->noise >> 4);
1860}
1861
1862static void mt7615_update_survey(struct mt7615_dev *dev)
1863{
1864        struct mt76_dev *mdev = &dev->mt76;
1865        ktime_t cur_time;
1866
1867        /* MT7615 can only update both phys simultaneously
1868         * since some reisters are shared across bands.
1869         */
1870
1871        mt7615_phy_update_channel(&mdev->phy, 0);
1872        if (mdev->phy2)
1873                mt7615_phy_update_channel(mdev->phy2, 1);
1874
1875        cur_time = ktime_get_boottime();
1876
1877        mt76_update_survey_active_time(&mdev->phy, cur_time);
1878        if (mdev->phy2)
1879                mt76_update_survey_active_time(mdev->phy2, cur_time);
1880
1881        /* reset obss airtime */
1882        mt76_set(dev, MT_WF_RMAC_MIB_TIME0, MT_WF_RMAC_MIB_RXTIME_CLR);
1883}
1884
1885void mt7615_update_channel(struct mt76_phy *mphy)
1886{
1887        struct mt7615_dev *dev = container_of(mphy->dev, struct mt7615_dev, mt76);
1888
1889        if (mt76_connac_pm_wake(&dev->mphy, &dev->pm))
1890                return;
1891
1892        mt7615_update_survey(dev);
1893        mt76_connac_power_save_sched(&dev->mphy, &dev->pm);
1894}
1895EXPORT_SYMBOL_GPL(mt7615_update_channel);
1896
1897static void
1898mt7615_mac_update_mib_stats(struct mt7615_phy *phy)
1899{
1900        struct mt7615_dev *dev = phy->dev;
1901        struct mib_stats *mib = &phy->mib;
1902        bool ext_phy = phy != &dev->phy;
1903        int i, aggr;
1904        u32 val, val2;
1905
1906        mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1907                                           MT_MIB_SDR3_FCS_ERR_MASK);
1908
1909        val = mt76_get_field(dev, MT_MIB_SDR14(ext_phy),
1910                             MT_MIB_AMPDU_MPDU_COUNT);
1911        if (val) {
1912                val2 = mt76_get_field(dev, MT_MIB_SDR15(ext_phy),
1913                                      MT_MIB_AMPDU_ACK_COUNT);
1914                mib->aggr_per = 1000 * (val - val2) / val;
1915        }
1916
1917        aggr = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1918        for (i = 0; i < 4; i++) {
1919                val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
1920                mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1921                mib->ack_fail_cnt += FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK,
1922                                               val);
1923
1924                val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
1925                mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1926                mib->rts_retries_cnt += FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK,
1927                                                  val);
1928
1929                val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1930                dev->mt76.aggr_stats[aggr++] += val & 0xffff;
1931                dev->mt76.aggr_stats[aggr++] += val >> 16;
1932        }
1933}
1934
1935void mt7615_pm_wake_work(struct work_struct *work)
1936{
1937        struct mt7615_dev *dev;
1938        struct mt76_phy *mphy;
1939
1940        dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
1941                                                pm.wake_work);
1942        mphy = dev->phy.mt76;
1943
1944        if (!mt7615_mcu_set_drv_ctrl(dev)) {
1945                struct mt76_dev *mdev = &dev->mt76;
1946                int i;
1947
1948                if (mt76_is_sdio(mdev)) {
1949                        mt76_worker_schedule(&mdev->sdio.txrx_worker);
1950                } else {
1951                        mt76_for_each_q_rx(mdev, i)
1952                                napi_schedule(&mdev->napi[i]);
1953                        mt76_connac_pm_dequeue_skbs(mphy, &dev->pm);
1954                        mt76_queue_tx_cleanup(dev, mdev->q_mcu[MT_MCUQ_WM],
1955                                              false);
1956                }
1957
1958                if (test_bit(MT76_STATE_RUNNING, &mphy->state)) {
1959                        unsigned long timeout;
1960
1961                        timeout = mt7615_get_macwork_timeout(dev);
1962                        ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
1963                                                     timeout);
1964                }
1965        }
1966
1967        ieee80211_wake_queues(mphy->hw);
1968        wake_up(&dev->pm.wait);
1969}
1970
1971void mt7615_pm_power_save_work(struct work_struct *work)
1972{
1973        struct mt7615_dev *dev;
1974        unsigned long delta;
1975
1976        dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
1977                                                pm.ps_work.work);
1978
1979        delta = dev->pm.idle_timeout;
1980        if (test_bit(MT76_HW_SCANNING, &dev->mphy.state) ||
1981            test_bit(MT76_HW_SCHED_SCANNING, &dev->mphy.state))
1982                goto out;
1983
1984        if (time_is_after_jiffies(dev->pm.last_activity + delta)) {
1985                delta = dev->pm.last_activity + delta - jiffies;
1986                goto out;
1987        }
1988
1989        if (!mt7615_mcu_set_fw_ctrl(dev))
1990                return;
1991out:
1992        queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta);
1993}
1994
1995void mt7615_mac_work(struct work_struct *work)
1996{
1997        struct mt7615_phy *phy;
1998        struct mt76_phy *mphy;
1999        unsigned long timeout;
2000
2001        mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
2002                                               mac_work.work);
2003        phy = mphy->priv;
2004
2005        mt7615_mutex_acquire(phy->dev);
2006
2007        mt7615_update_survey(phy->dev);
2008        if (++mphy->mac_work_count == 5) {
2009                mphy->mac_work_count = 0;
2010
2011                mt7615_mac_update_mib_stats(phy);
2012                mt7615_mac_scs_check(phy);
2013        }
2014
2015        mt7615_mutex_release(phy->dev);
2016
2017        mt76_tx_status_check(mphy->dev, NULL, false);
2018
2019        timeout = mt7615_get_macwork_timeout(phy->dev);
2020        ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, timeout);
2021}
2022
2023void mt7615_tx_token_put(struct mt7615_dev *dev)
2024{
2025        struct mt76_txwi_cache *txwi;
2026        int id;
2027
2028        spin_lock_bh(&dev->mt76.token_lock);
2029        idr_for_each_entry(&dev->mt76.token, txwi, id) {
2030                mt7615_txp_skb_unmap(&dev->mt76, txwi);
2031                if (txwi->skb) {
2032                        struct ieee80211_hw *hw;
2033
2034                        hw = mt76_tx_status_get_hw(&dev->mt76, txwi->skb);
2035                        ieee80211_free_txskb(hw, txwi->skb);
2036                }
2037                mt76_put_txwi(&dev->mt76, txwi);
2038        }
2039        spin_unlock_bh(&dev->mt76.token_lock);
2040        idr_destroy(&dev->mt76.token);
2041}
2042EXPORT_SYMBOL_GPL(mt7615_tx_token_put);
2043
2044static void mt7615_dfs_stop_radar_detector(struct mt7615_phy *phy)
2045{
2046        struct mt7615_dev *dev = phy->dev;
2047
2048        if (phy->rdd_state & BIT(0))
2049                mt7615_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0);
2050        if (phy->rdd_state & BIT(1))
2051                mt7615_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0);
2052}
2053
2054static int mt7615_dfs_start_rdd(struct mt7615_dev *dev, int chain)
2055{
2056        int err;
2057
2058        err = mt7615_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
2059        if (err < 0)
2060                return err;
2061
2062        return mt7615_mcu_rdd_cmd(dev, RDD_DET_MODE, chain,
2063                                  MT_RX_SEL0, 1);
2064}
2065
2066static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy)
2067{
2068        struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2069        struct mt7615_dev *dev = phy->dev;
2070        bool ext_phy = phy != &dev->phy;
2071        int err;
2072
2073        /* start CAC */
2074        err = mt7615_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0);
2075        if (err < 0)
2076                return err;
2077
2078        err = mt7615_dfs_start_rdd(dev, ext_phy);
2079        if (err < 0)
2080                return err;
2081
2082        phy->rdd_state |= BIT(ext_phy);
2083
2084        if (chandef->width == NL80211_CHAN_WIDTH_160 ||
2085            chandef->width == NL80211_CHAN_WIDTH_80P80) {
2086                err = mt7615_dfs_start_rdd(dev, 1);
2087                if (err < 0)
2088                        return err;
2089
2090                phy->rdd_state |= BIT(1);
2091        }
2092
2093        return 0;
2094}
2095
2096static int
2097mt7615_dfs_init_radar_specs(struct mt7615_phy *phy)
2098{
2099        const struct mt7615_dfs_radar_spec *radar_specs;
2100        struct mt7615_dev *dev = phy->dev;
2101        int err, i, lpn = 500;
2102
2103        switch (dev->mt76.region) {
2104        case NL80211_DFS_FCC:
2105                radar_specs = &fcc_radar_specs;
2106                lpn = 8;
2107                break;
2108        case NL80211_DFS_ETSI:
2109                radar_specs = &etsi_radar_specs;
2110                break;
2111        case NL80211_DFS_JP:
2112                radar_specs = &jp_radar_specs;
2113                break;
2114        default:
2115                return -EINVAL;
2116        }
2117
2118        /* avoid FCC radar detection in non-FCC region */
2119        err = mt7615_mcu_set_fcc5_lpn(dev, lpn);
2120        if (err < 0)
2121                return err;
2122
2123        for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
2124                err = mt7615_mcu_set_radar_th(dev, i,
2125                                              &radar_specs->radar_pattern[i]);
2126                if (err < 0)
2127                        return err;
2128        }
2129
2130        return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
2131}
2132
2133int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy)
2134{
2135        struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2136        struct mt7615_dev *dev = phy->dev;
2137        bool ext_phy = phy != &dev->phy;
2138        int err;
2139
2140        if (is_mt7663(&dev->mt76))
2141                return 0;
2142
2143        if (dev->mt76.region == NL80211_DFS_UNSET) {
2144                phy->dfs_state = -1;
2145                if (phy->rdd_state)
2146                        goto stop;
2147
2148                return 0;
2149        }
2150
2151        if (test_bit(MT76_SCANNING, &phy->mt76->state))
2152                return 0;
2153
2154        if (phy->dfs_state == chandef->chan->dfs_state)
2155                return 0;
2156
2157        err = mt7615_dfs_init_radar_specs(phy);
2158        if (err < 0) {
2159                phy->dfs_state = -1;
2160                goto stop;
2161        }
2162
2163        phy->dfs_state = chandef->chan->dfs_state;
2164
2165        if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
2166                if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
2167                        return mt7615_dfs_start_radar_detector(phy);
2168
2169                return mt7615_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy,
2170                                          MT_RX_SEL0, 0);
2171        }
2172
2173stop:
2174        err = mt7615_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy, MT_RX_SEL0, 0);
2175        if (err < 0)
2176                return err;
2177
2178        mt7615_dfs_stop_radar_detector(phy);
2179        return 0;
2180}
2181
2182int mt7615_mac_set_beacon_filter(struct mt7615_phy *phy,
2183                                 struct ieee80211_vif *vif,
2184                                 bool enable)
2185{
2186        struct mt7615_dev *dev = phy->dev;
2187        bool ext_phy = phy != &dev->phy;
2188        int err;
2189
2190        if (!mt7615_firmware_offload(dev))
2191                return -EOPNOTSUPP;
2192
2193        switch (vif->type) {
2194        case NL80211_IFTYPE_MONITOR:
2195                return 0;
2196        case NL80211_IFTYPE_MESH_POINT:
2197        case NL80211_IFTYPE_ADHOC:
2198        case NL80211_IFTYPE_AP:
2199                if (enable)
2200                        phy->n_beacon_vif++;
2201                else
2202                        phy->n_beacon_vif--;
2203                fallthrough;
2204        default:
2205                break;
2206        }
2207
2208        err = mt7615_mcu_set_bss_pm(dev, vif, !phy->n_beacon_vif);
2209        if (err)
2210                return err;
2211
2212        if (phy->n_beacon_vif) {
2213                vif->driver_flags &= ~IEEE80211_VIF_BEACON_FILTER;
2214                mt76_clear(dev, MT_WF_RFCR(ext_phy),
2215                           MT_WF_RFCR_DROP_OTHER_BEACON);
2216        } else {
2217                vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER;
2218                mt76_set(dev, MT_WF_RFCR(ext_phy),
2219                         MT_WF_RFCR_DROP_OTHER_BEACON);
2220        }
2221
2222        return 0;
2223}
2224
2225void mt7615_coredump_work(struct work_struct *work)
2226{
2227        struct mt7615_dev *dev;
2228        char *dump, *data;
2229
2230        dev = (struct mt7615_dev *)container_of(work, struct mt7615_dev,
2231                                                coredump.work.work);
2232
2233        if (time_is_after_jiffies(dev->coredump.last_activity +
2234                                  4 * MT76_CONNAC_COREDUMP_TIMEOUT)) {
2235                queue_delayed_work(dev->mt76.wq, &dev->coredump.work,
2236                                   MT76_CONNAC_COREDUMP_TIMEOUT);
2237                return;
2238        }
2239
2240        dump = vzalloc(MT76_CONNAC_COREDUMP_SZ);
2241        data = dump;
2242
2243        while (true) {
2244                struct sk_buff *skb;
2245
2246                spin_lock_bh(&dev->mt76.lock);
2247                skb = __skb_dequeue(&dev->coredump.msg_list);
2248                spin_unlock_bh(&dev->mt76.lock);
2249
2250                if (!skb)
2251                        break;
2252
2253                skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
2254                if (data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) {
2255                        dev_kfree_skb(skb);
2256                        continue;
2257                }
2258
2259                memcpy(data, skb->data, skb->len);
2260                data += skb->len;
2261
2262                dev_kfree_skb(skb);
2263        }
2264        dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ,
2265                      GFP_KERNEL);
2266}
2267
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