linux/drivers/net/wireless/mediatek/mt76/mt7603/mac.c
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   1// SPDX-License-Identifier: ISC
   2
   3#include <linux/etherdevice.h>
   4#include <linux/timekeeping.h>
   5#include "mt7603.h"
   6#include "mac.h"
   7#include "../trace.h"
   8
   9#define MT_PSE_PAGE_SIZE        128
  10
  11static u32
  12mt7603_ac_queue_mask0(u32 mask)
  13{
  14        u32 ret = 0;
  15
  16        ret |= GENMASK(3, 0) * !!(mask & BIT(0));
  17        ret |= GENMASK(8, 5) * !!(mask & BIT(1));
  18        ret |= GENMASK(13, 10) * !!(mask & BIT(2));
  19        ret |= GENMASK(19, 16) * !!(mask & BIT(3));
  20        return ret;
  21}
  22
  23static void
  24mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask)
  25{
  26        mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask));
  27}
  28
  29static void
  30mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask)
  31{
  32        mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask));
  33}
  34
  35void mt7603_mac_reset_counters(struct mt7603_dev *dev)
  36{
  37        int i;
  38
  39        for (i = 0; i < 2; i++)
  40                mt76_rr(dev, MT_TX_AGG_CNT(i));
  41
  42        memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
  43}
  44
  45void mt7603_mac_set_timing(struct mt7603_dev *dev)
  46{
  47        u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
  48                  FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
  49        u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
  50                   FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24);
  51        int offset = 3 * dev->coverage_class;
  52        u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
  53                         FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
  54        bool is_5ghz = dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ;
  55        int sifs;
  56        u32 val;
  57
  58        if (is_5ghz)
  59                sifs = 16;
  60        else
  61                sifs = 10;
  62
  63        mt76_set(dev, MT_ARB_SCR,
  64                 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
  65        udelay(1);
  66
  67        mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset);
  68        mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset);
  69        mt76_wr(dev, MT_IFS,
  70                FIELD_PREP(MT_IFS_EIFS, 360) |
  71                FIELD_PREP(MT_IFS_RIFS, 2) |
  72                FIELD_PREP(MT_IFS_SIFS, sifs) |
  73                FIELD_PREP(MT_IFS_SLOT, dev->slottime));
  74
  75        if (dev->slottime < 20 || is_5ghz)
  76                val = MT7603_CFEND_RATE_DEFAULT;
  77        else
  78                val = MT7603_CFEND_RATE_11B;
  79
  80        mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val);
  81
  82        mt76_clear(dev, MT_ARB_SCR,
  83                   MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
  84}
  85
  86static void
  87mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask)
  88{
  89        mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
  90                 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
  91
  92        mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
  93}
  94
  95static u32
  96mt7603_wtbl1_addr(int idx)
  97{
  98        return MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
  99}
 100
 101static u32
 102mt7603_wtbl2_addr(int idx)
 103{
 104        /* Mapped to WTBL2 */
 105        return MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE;
 106}
 107
 108static u32
 109mt7603_wtbl3_addr(int idx)
 110{
 111        u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE);
 112
 113        return base + idx * MT_WTBL3_SIZE;
 114}
 115
 116static u32
 117mt7603_wtbl4_addr(int idx)
 118{
 119        u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE);
 120
 121        return base + idx * MT_WTBL4_SIZE;
 122}
 123
 124void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,
 125                      const u8 *mac_addr)
 126{
 127        const void *_mac = mac_addr;
 128        u32 addr = mt7603_wtbl1_addr(idx);
 129        u32 w0 = 0, w1 = 0;
 130        int i;
 131
 132        if (_mac) {
 133                w0 = FIELD_PREP(MT_WTBL1_W0_ADDR_HI,
 134                                get_unaligned_le16(_mac + 4));
 135                w1 = FIELD_PREP(MT_WTBL1_W1_ADDR_LO,
 136                                get_unaligned_le32(_mac));
 137        }
 138
 139        if (vif < 0)
 140                vif = 0;
 141        else
 142                w0 |= MT_WTBL1_W0_RX_CHECK_A1;
 143        w0 |= FIELD_PREP(MT_WTBL1_W0_MUAR_IDX, vif);
 144
 145        mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
 146
 147        mt76_set(dev, addr + 0 * 4, w0);
 148        mt76_set(dev, addr + 1 * 4, w1);
 149        mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL);
 150
 151        mt76_stop_tx_ac(dev, GENMASK(3, 0));
 152        addr = mt7603_wtbl2_addr(idx);
 153        for (i = 0; i < MT_WTBL2_SIZE; i += 4)
 154                mt76_wr(dev, addr + i, 0);
 155        mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
 156        mt76_start_tx_ac(dev, GENMASK(3, 0));
 157
 158        addr = mt7603_wtbl3_addr(idx);
 159        for (i = 0; i < MT_WTBL3_SIZE; i += 4)
 160                mt76_wr(dev, addr + i, 0);
 161
 162        addr = mt7603_wtbl4_addr(idx);
 163        for (i = 0; i < MT_WTBL4_SIZE; i += 4)
 164                mt76_wr(dev, addr + i, 0);
 165
 166        mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
 167}
 168
 169static void
 170mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled)
 171{
 172        u32 addr = mt7603_wtbl1_addr(idx);
 173        u32 val = mt76_rr(dev, addr + 3 * 4);
 174
 175        val &= ~MT_WTBL1_W3_SKIP_TX;
 176        val |= enabled * MT_WTBL1_W3_SKIP_TX;
 177
 178        mt76_wr(dev, addr + 3 * 4, val);
 179}
 180
 181void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort)
 182{
 183        int i, port, queue;
 184
 185        if (abort) {
 186                port = 3; /* PSE */
 187                queue = 8; /* free queue */
 188        } else {
 189                port = 0; /* HIF */
 190                queue = 1; /* MCU queue */
 191        }
 192
 193        mt7603_wtbl_set_skip_tx(dev, idx, true);
 194
 195        mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN |
 196                        FIELD_PREP(MT_TX_ABORT_WCID, idx));
 197
 198        for (i = 0; i < 4; i++) {
 199                mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY |
 200                        FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) |
 201                        FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, i) |
 202                        FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) |
 203                        FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue));
 204
 205                WARN_ON_ONCE(!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY,
 206                                        0, 5000));
 207        }
 208
 209        mt76_wr(dev, MT_TX_ABORT, 0);
 210
 211        mt7603_wtbl_set_skip_tx(dev, idx, false);
 212}
 213
 214void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,
 215                          bool enabled)
 216{
 217        u32 addr = mt7603_wtbl1_addr(sta->wcid.idx);
 218
 219        if (sta->smps == enabled)
 220                return;
 221
 222        mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled);
 223        sta->smps = enabled;
 224}
 225
 226void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
 227                        bool enabled)
 228{
 229        int idx = sta->wcid.idx;
 230        u32 addr;
 231
 232        spin_lock_bh(&dev->ps_lock);
 233
 234        if (sta->ps == enabled)
 235                goto out;
 236
 237        mt76_wr(dev, MT_PSE_RTA,
 238                FIELD_PREP(MT_PSE_RTA_TAG_ID, idx) |
 239                FIELD_PREP(MT_PSE_RTA_PORT_ID, 0) |
 240                FIELD_PREP(MT_PSE_RTA_QUEUE_ID, 1) |
 241                FIELD_PREP(MT_PSE_RTA_REDIRECT_EN, enabled) |
 242                MT_PSE_RTA_WRITE | MT_PSE_RTA_BUSY);
 243
 244        mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);
 245
 246        if (enabled)
 247                mt7603_filter_tx(dev, idx, false);
 248
 249        addr = mt7603_wtbl1_addr(idx);
 250        mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
 251        mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE,
 252                 enabled * MT_WTBL1_W3_POWER_SAVE);
 253        mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
 254        sta->ps = enabled;
 255
 256out:
 257        spin_unlock_bh(&dev->ps_lock);
 258}
 259
 260void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
 261{
 262        int wtbl2_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL2_SIZE;
 263        int wtbl2_frame = idx / wtbl2_frame_size;
 264        int wtbl2_entry = idx % wtbl2_frame_size;
 265
 266        int wtbl3_base_frame = MT_WTBL3_OFFSET / MT_PSE_PAGE_SIZE;
 267        int wtbl3_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL3_SIZE;
 268        int wtbl3_frame = wtbl3_base_frame + idx / wtbl3_frame_size;
 269        int wtbl3_entry = (idx % wtbl3_frame_size) * 2;
 270
 271        int wtbl4_base_frame = MT_WTBL4_OFFSET / MT_PSE_PAGE_SIZE;
 272        int wtbl4_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL4_SIZE;
 273        int wtbl4_frame = wtbl4_base_frame + idx / wtbl4_frame_size;
 274        int wtbl4_entry = idx % wtbl4_frame_size;
 275
 276        u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
 277        int i;
 278
 279        mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
 280
 281        mt76_wr(dev, addr + 0 * 4,
 282                MT_WTBL1_W0_RX_CHECK_A1 |
 283                MT_WTBL1_W0_RX_CHECK_A2 |
 284                MT_WTBL1_W0_RX_VALID);
 285        mt76_wr(dev, addr + 1 * 4, 0);
 286        mt76_wr(dev, addr + 2 * 4, 0);
 287
 288        mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
 289
 290        mt76_wr(dev, addr + 3 * 4,
 291                FIELD_PREP(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) |
 292                FIELD_PREP(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) |
 293                FIELD_PREP(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) |
 294                MT_WTBL1_W3_I_PSM | MT_WTBL1_W3_KEEP_I_PSM);
 295        mt76_wr(dev, addr + 4 * 4,
 296                FIELD_PREP(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) |
 297                FIELD_PREP(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) |
 298                FIELD_PREP(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry));
 299
 300        mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
 301
 302        addr = mt7603_wtbl2_addr(idx);
 303
 304        /* Clear BA information */
 305        mt76_wr(dev, addr + (15 * 4), 0);
 306
 307        mt76_stop_tx_ac(dev, GENMASK(3, 0));
 308        for (i = 2; i <= 4; i++)
 309                mt76_wr(dev, addr + (i * 4), 0);
 310        mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
 311        mt76_start_tx_ac(dev, GENMASK(3, 0));
 312
 313        mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR);
 314        mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR);
 315        mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
 316}
 317
 318void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta)
 319{
 320        struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
 321        int idx = msta->wcid.idx;
 322        u8 ampdu_density;
 323        u32 addr;
 324        u32 val;
 325
 326        addr = mt7603_wtbl1_addr(idx);
 327
 328        ampdu_density = sta->ht_cap.ampdu_density;
 329        if (ampdu_density < IEEE80211_HT_MPDU_DENSITY_4)
 330                ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
 331
 332        val = mt76_rr(dev, addr + 2 * 4);
 333        val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL;
 334        val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR, sta->ht_cap.ampdu_factor) |
 335               FIELD_PREP(MT_WTBL1_W2_MPDU_DENSITY, sta->ht_cap.ampdu_density) |
 336               MT_WTBL1_W2_TXS_BAF_REPORT;
 337
 338        if (sta->ht_cap.cap)
 339                val |= MT_WTBL1_W2_HT;
 340        if (sta->vht_cap.cap)
 341                val |= MT_WTBL1_W2_VHT;
 342
 343        mt76_wr(dev, addr + 2 * 4, val);
 344
 345        addr = mt7603_wtbl2_addr(idx);
 346        val = mt76_rr(dev, addr + 9 * 4);
 347        val &= ~(MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
 348                 MT_WTBL2_W9_SHORT_GI_80);
 349        if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20)
 350                val |= MT_WTBL2_W9_SHORT_GI_20;
 351        if (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40)
 352                val |= MT_WTBL2_W9_SHORT_GI_40;
 353        mt76_wr(dev, addr + 9 * 4, val);
 354}
 355
 356void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid)
 357{
 358        mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr));
 359        mt76_wr(dev, MT_BA_CONTROL_1,
 360                (get_unaligned_le16(addr + 4) |
 361                 FIELD_PREP(MT_BA_CONTROL_1_TID, tid) |
 362                 MT_BA_CONTROL_1_RESET));
 363}
 364
 365void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid,
 366                            int ba_size)
 367{
 368        u32 addr = mt7603_wtbl2_addr(wcid);
 369        u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
 370                       (MT_WTBL2_W15_BA_WIN_SIZE <<
 371                        (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT));
 372        u32 tid_val;
 373        int i;
 374
 375        if (ba_size < 0) {
 376                /* disable */
 377                mt76_clear(dev, addr + (15 * 4), tid_mask);
 378                return;
 379        }
 380
 381        for (i = 7; i > 0; i--) {
 382                if (ba_size >= MT_AGG_SIZE_LIMIT(i))
 383                        break;
 384        }
 385
 386        tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
 387                  i << (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT);
 388
 389        mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val);
 390}
 391
 392void mt7603_mac_sta_poll(struct mt7603_dev *dev)
 393{
 394        static const u8 ac_to_tid[4] = {
 395                [IEEE80211_AC_BE] = 0,
 396                [IEEE80211_AC_BK] = 1,
 397                [IEEE80211_AC_VI] = 4,
 398                [IEEE80211_AC_VO] = 6
 399        };
 400        struct ieee80211_sta *sta;
 401        struct mt7603_sta *msta;
 402        u32 total_airtime = 0;
 403        u32 airtime[4];
 404        u32 addr;
 405        int i;
 406
 407        rcu_read_lock();
 408
 409        while (1) {
 410                bool clear = false;
 411
 412                spin_lock_bh(&dev->sta_poll_lock);
 413                if (list_empty(&dev->sta_poll_list)) {
 414                        spin_unlock_bh(&dev->sta_poll_lock);
 415                        break;
 416                }
 417
 418                msta = list_first_entry(&dev->sta_poll_list, struct mt7603_sta,
 419                                        poll_list);
 420                list_del_init(&msta->poll_list);
 421                spin_unlock_bh(&dev->sta_poll_lock);
 422
 423                addr = mt7603_wtbl4_addr(msta->wcid.idx);
 424                for (i = 0; i < 4; i++) {
 425                        u32 airtime_last = msta->tx_airtime_ac[i];
 426
 427                        msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8);
 428                        airtime[i] = msta->tx_airtime_ac[i] - airtime_last;
 429                        airtime[i] *= 32;
 430                        total_airtime += airtime[i];
 431
 432                        if (msta->tx_airtime_ac[i] & BIT(22))
 433                                clear = true;
 434                }
 435
 436                if (clear) {
 437                        mt7603_wtbl_update(dev, msta->wcid.idx,
 438                                           MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
 439                        memset(msta->tx_airtime_ac, 0,
 440                               sizeof(msta->tx_airtime_ac));
 441                }
 442
 443                if (!msta->wcid.sta)
 444                        continue;
 445
 446                sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
 447                for (i = 0; i < 4; i++) {
 448                        struct mt76_queue *q = dev->mphy.q_tx[i];
 449                        u8 qidx = q->hw_idx;
 450                        u8 tid = ac_to_tid[i];
 451                        u32 txtime = airtime[qidx];
 452
 453                        if (!txtime)
 454                                continue;
 455
 456                        ieee80211_sta_register_airtime(sta, tid, txtime, 0);
 457                }
 458        }
 459
 460        rcu_read_unlock();
 461
 462        if (!total_airtime)
 463                return;
 464
 465        spin_lock_bh(&dev->mt76.cc_lock);
 466        dev->mphy.chan_state->cc_tx += total_airtime;
 467        spin_unlock_bh(&dev->mt76.cc_lock);
 468}
 469
 470static struct mt76_wcid *
 471mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast)
 472{
 473        struct mt7603_sta *sta;
 474        struct mt76_wcid *wcid;
 475
 476        if (idx >= MT7603_WTBL_SIZE)
 477                return NULL;
 478
 479        wcid = rcu_dereference(dev->mt76.wcid[idx]);
 480        if (unicast || !wcid)
 481                return wcid;
 482
 483        if (!wcid->sta)
 484                return NULL;
 485
 486        sta = container_of(wcid, struct mt7603_sta, wcid);
 487        if (!sta->vif)
 488                return NULL;
 489
 490        return &sta->vif->sta.wcid;
 491}
 492
 493int
 494mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
 495{
 496        struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
 497        struct ieee80211_supported_band *sband;
 498        struct ieee80211_hdr *hdr;
 499        __le32 *rxd = (__le32 *)skb->data;
 500        u32 rxd0 = le32_to_cpu(rxd[0]);
 501        u32 rxd1 = le32_to_cpu(rxd[1]);
 502        u32 rxd2 = le32_to_cpu(rxd[2]);
 503        bool unicast = rxd1 & MT_RXD1_NORMAL_U2M;
 504        bool insert_ccmp_hdr = false;
 505        bool remove_pad;
 506        int idx;
 507        int i;
 508
 509        memset(status, 0, sizeof(*status));
 510
 511        i = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
 512        sband = (i & 1) ? &dev->mphy.sband_5g.sband : &dev->mphy.sband_2g.sband;
 513        i >>= 1;
 514
 515        idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
 516        status->wcid = mt7603_rx_get_wcid(dev, idx, unicast);
 517
 518        status->band = sband->band;
 519        if (i < sband->n_channels)
 520                status->freq = sband->channels[i].center_freq;
 521
 522        if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
 523                status->flag |= RX_FLAG_FAILED_FCS_CRC;
 524
 525        if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
 526                status->flag |= RX_FLAG_MMIC_ERROR;
 527
 528        if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
 529            !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
 530                status->flag |= RX_FLAG_DECRYPTED;
 531                status->flag |= RX_FLAG_IV_STRIPPED;
 532                status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
 533        }
 534
 535        remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
 536
 537        if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
 538                return -EINVAL;
 539
 540        if (!sband->channels)
 541                return -EINVAL;
 542
 543        rxd += 4;
 544        if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
 545                rxd += 4;
 546                if ((u8 *)rxd - skb->data >= skb->len)
 547                        return -EINVAL;
 548        }
 549        if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
 550                u8 *data = (u8 *)rxd;
 551
 552                if (status->flag & RX_FLAG_DECRYPTED) {
 553                        switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) {
 554                        case MT_CIPHER_AES_CCMP:
 555                        case MT_CIPHER_CCMP_CCX:
 556                        case MT_CIPHER_CCMP_256:
 557                                insert_ccmp_hdr =
 558                                        FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
 559                                fallthrough;
 560                        case MT_CIPHER_TKIP:
 561                        case MT_CIPHER_TKIP_NO_MIC:
 562                        case MT_CIPHER_GCMP:
 563                        case MT_CIPHER_GCMP_256:
 564                                status->iv[0] = data[5];
 565                                status->iv[1] = data[4];
 566                                status->iv[2] = data[3];
 567                                status->iv[3] = data[2];
 568                                status->iv[4] = data[1];
 569                                status->iv[5] = data[0];
 570                                break;
 571                        default:
 572                                break;
 573                        }
 574                }
 575
 576                rxd += 4;
 577                if ((u8 *)rxd - skb->data >= skb->len)
 578                        return -EINVAL;
 579        }
 580        if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
 581                status->timestamp = le32_to_cpu(rxd[0]);
 582                status->flag |= RX_FLAG_MACTIME_START;
 583
 584                if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
 585                              MT_RXD2_NORMAL_NON_AMPDU))) {
 586                        status->flag |= RX_FLAG_AMPDU_DETAILS;
 587
 588                        /* all subframes of an A-MPDU have the same timestamp */
 589                        if (dev->rx_ampdu_ts != status->timestamp) {
 590                                if (!++dev->ampdu_ref)
 591                                        dev->ampdu_ref++;
 592                        }
 593                        dev->rx_ampdu_ts = status->timestamp;
 594
 595                        status->ampdu_ref = dev->ampdu_ref;
 596                }
 597
 598                rxd += 2;
 599                if ((u8 *)rxd - skb->data >= skb->len)
 600                        return -EINVAL;
 601        }
 602        if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
 603                u32 rxdg0 = le32_to_cpu(rxd[0]);
 604                u32 rxdg3 = le32_to_cpu(rxd[3]);
 605                bool cck = false;
 606
 607                i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
 608                switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
 609                case MT_PHY_TYPE_CCK:
 610                        cck = true;
 611                        fallthrough;
 612                case MT_PHY_TYPE_OFDM:
 613                        i = mt76_get_rate(&dev->mt76, sband, i, cck);
 614                        break;
 615                case MT_PHY_TYPE_HT_GF:
 616                case MT_PHY_TYPE_HT:
 617                        status->encoding = RX_ENC_HT;
 618                        if (i > 15)
 619                                return -EINVAL;
 620                        break;
 621                default:
 622                        return -EINVAL;
 623                }
 624
 625                if (rxdg0 & MT_RXV1_HT_SHORT_GI)
 626                        status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
 627                if (rxdg0 & MT_RXV1_HT_AD_CODE)
 628                        status->enc_flags |= RX_ENC_FLAG_LDPC;
 629
 630                status->enc_flags |= RX_ENC_FLAG_STBC_MASK *
 631                                    FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
 632
 633                status->rate_idx = i;
 634
 635                status->chains = dev->mphy.antenna_mask;
 636                status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) +
 637                                          dev->rssi_offset[0];
 638                status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) +
 639                                          dev->rssi_offset[1];
 640
 641                status->signal = status->chain_signal[0];
 642                if (status->chains & BIT(1))
 643                        status->signal = max(status->signal,
 644                                             status->chain_signal[1]);
 645
 646                if (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0) == 1)
 647                        status->bw = RATE_INFO_BW_40;
 648
 649                rxd += 6;
 650                if ((u8 *)rxd - skb->data >= skb->len)
 651                        return -EINVAL;
 652        } else {
 653                return -EINVAL;
 654        }
 655
 656        skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
 657
 658        if (insert_ccmp_hdr) {
 659                u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
 660
 661                mt76_insert_ccmp_hdr(skb, key_id);
 662        }
 663
 664        hdr = (struct ieee80211_hdr *)skb->data;
 665        if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
 666                return 0;
 667
 668        status->aggr = unicast &&
 669                       !ieee80211_is_qos_nullfunc(hdr->frame_control);
 670        status->qos_ctl = *ieee80211_get_qos_ctl(hdr);
 671        status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
 672
 673        return 0;
 674}
 675
 676static u16
 677mt7603_mac_tx_rate_val(struct mt7603_dev *dev,
 678                       const struct ieee80211_tx_rate *rate, bool stbc, u8 *bw)
 679{
 680        u8 phy, nss, rate_idx;
 681        u16 rateval;
 682
 683        *bw = 0;
 684        if (rate->flags & IEEE80211_TX_RC_MCS) {
 685                rate_idx = rate->idx;
 686                nss = 1 + (rate->idx >> 3);
 687                phy = MT_PHY_TYPE_HT;
 688                if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
 689                        phy = MT_PHY_TYPE_HT_GF;
 690                if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
 691                        *bw = 1;
 692        } else {
 693                const struct ieee80211_rate *r;
 694                int band = dev->mphy.chandef.chan->band;
 695                u16 val;
 696
 697                nss = 1;
 698                r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
 699                if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
 700                        val = r->hw_value_short;
 701                else
 702                        val = r->hw_value;
 703
 704                phy = val >> 8;
 705                rate_idx = val & 0xff;
 706        }
 707
 708        rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
 709                   FIELD_PREP(MT_TX_RATE_MODE, phy));
 710
 711        if (stbc && nss == 1)
 712                rateval |= MT_TX_RATE_STBC;
 713
 714        return rateval;
 715}
 716
 717void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,
 718                           struct ieee80211_tx_rate *probe_rate,
 719                           struct ieee80211_tx_rate *rates)
 720{
 721        struct ieee80211_tx_rate *ref;
 722        int wcid = sta->wcid.idx;
 723        u32 addr = mt7603_wtbl2_addr(wcid);
 724        bool stbc = false;
 725        int n_rates = sta->n_rates;
 726        u8 bw, bw_prev, bw_idx = 0;
 727        u16 val[4];
 728        u16 probe_val;
 729        u32 w9 = mt76_rr(dev, addr + 9 * 4);
 730        bool rateset;
 731        int i, k;
 732
 733        if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
 734                return;
 735
 736        for (i = n_rates; i < 4; i++)
 737                rates[i] = rates[n_rates - 1];
 738
 739        rateset = !(sta->rate_set_tsf & BIT(0));
 740        memcpy(sta->rateset[rateset].rates, rates,
 741               sizeof(sta->rateset[rateset].rates));
 742        if (probe_rate) {
 743                sta->rateset[rateset].probe_rate = *probe_rate;
 744                ref = &sta->rateset[rateset].probe_rate;
 745        } else {
 746                sta->rateset[rateset].probe_rate.idx = -1;
 747                ref = &sta->rateset[rateset].rates[0];
 748        }
 749
 750        rates = sta->rateset[rateset].rates;
 751        for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
 752                /*
 753                 * We don't support switching between short and long GI
 754                 * within the rate set. For accurate tx status reporting, we
 755                 * need to make sure that flags match.
 756                 * For improved performance, avoid duplicate entries by
 757                 * decrementing the MCS index if necessary
 758                 */
 759                if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
 760                        rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
 761
 762                for (k = 0; k < i; k++) {
 763                        if (rates[i].idx != rates[k].idx)
 764                                continue;
 765                        if ((rates[i].flags ^ rates[k].flags) &
 766                            IEEE80211_TX_RC_40_MHZ_WIDTH)
 767                                continue;
 768
 769                        if (!rates[i].idx)
 770                                continue;
 771
 772                        rates[i].idx--;
 773                }
 774        }
 775
 776        w9 &= MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
 777              MT_WTBL2_W9_SHORT_GI_80;
 778
 779        val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
 780        bw_prev = bw;
 781
 782        if (probe_rate) {
 783                probe_val = mt7603_mac_tx_rate_val(dev, probe_rate, stbc, &bw);
 784                if (bw)
 785                        bw_idx = 1;
 786                else
 787                        bw_prev = 0;
 788        } else {
 789                probe_val = val[0];
 790        }
 791
 792        w9 |= FIELD_PREP(MT_WTBL2_W9_CC_BW_SEL, bw);
 793        w9 |= FIELD_PREP(MT_WTBL2_W9_BW_CAP, bw);
 794
 795        val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
 796        if (bw_prev) {
 797                bw_idx = 3;
 798                bw_prev = bw;
 799        }
 800
 801        val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
 802        if (bw_prev) {
 803                bw_idx = 5;
 804                bw_prev = bw;
 805        }
 806
 807        val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
 808        if (bw_prev)
 809                bw_idx = 7;
 810
 811        w9 |= FIELD_PREP(MT_WTBL2_W9_CHANGE_BW_RATE,
 812                       bw_idx ? bw_idx - 1 : 7);
 813
 814        mt76_wr(dev, MT_WTBL_RIUCR0, w9);
 815
 816        mt76_wr(dev, MT_WTBL_RIUCR1,
 817                FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
 818                FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
 819                FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1]));
 820
 821        mt76_wr(dev, MT_WTBL_RIUCR2,
 822                FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) |
 823                FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
 824                FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) |
 825                FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
 826
 827        mt76_wr(dev, MT_WTBL_RIUCR3,
 828                FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
 829                FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) |
 830                FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
 831
 832        mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
 833        sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset;
 834
 835        mt76_wr(dev, MT_WTBL_UPDATE,
 836                FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
 837                MT_WTBL_UPDATE_RATE_UPDATE |
 838                MT_WTBL_UPDATE_TX_COUNT_CLEAR);
 839
 840        if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
 841                mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
 842
 843        sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates;
 844        sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
 845}
 846
 847static enum mt76_cipher_type
 848mt7603_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
 849{
 850        memset(key_data, 0, 32);
 851        if (!key)
 852                return MT_CIPHER_NONE;
 853
 854        if (key->keylen > 32)
 855                return MT_CIPHER_NONE;
 856
 857        memcpy(key_data, key->key, key->keylen);
 858
 859        switch (key->cipher) {
 860        case WLAN_CIPHER_SUITE_WEP40:
 861                return MT_CIPHER_WEP40;
 862        case WLAN_CIPHER_SUITE_WEP104:
 863                return MT_CIPHER_WEP104;
 864        case WLAN_CIPHER_SUITE_TKIP:
 865                /* Rx/Tx MIC keys are swapped */
 866                memcpy(key_data + 16, key->key + 24, 8);
 867                memcpy(key_data + 24, key->key + 16, 8);
 868                return MT_CIPHER_TKIP;
 869        case WLAN_CIPHER_SUITE_CCMP:
 870                return MT_CIPHER_AES_CCMP;
 871        default:
 872                return MT_CIPHER_NONE;
 873        }
 874}
 875
 876int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid,
 877                        struct ieee80211_key_conf *key)
 878{
 879        enum mt76_cipher_type cipher;
 880        u32 addr = mt7603_wtbl3_addr(wcid);
 881        u8 key_data[32];
 882        int key_len = sizeof(key_data);
 883
 884        cipher = mt7603_mac_get_key_info(key, key_data);
 885        if (cipher == MT_CIPHER_NONE && key)
 886                return -EOPNOTSUPP;
 887
 888        if (key && (cipher == MT_CIPHER_WEP40 || cipher == MT_CIPHER_WEP104)) {
 889                addr += key->keyidx * 16;
 890                key_len = 16;
 891        }
 892
 893        mt76_wr_copy(dev, addr, key_data, key_len);
 894
 895        addr = mt7603_wtbl1_addr(wcid);
 896        mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher);
 897        if (key)
 898                mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx);
 899        mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key);
 900
 901        return 0;
 902}
 903
 904static int
 905mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
 906                      struct sk_buff *skb, enum mt76_txq_id qid,
 907                      struct mt76_wcid *wcid, struct ieee80211_sta *sta,
 908                      int pid, struct ieee80211_key_conf *key)
 909{
 910        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 911        struct ieee80211_tx_rate *rate = &info->control.rates[0];
 912        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
 913        struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
 914        struct ieee80211_vif *vif = info->control.vif;
 915        struct mt76_queue *q = dev->mphy.q_tx[qid];
 916        struct mt7603_vif *mvif;
 917        int wlan_idx;
 918        int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
 919        int tx_count = 8;
 920        u8 frame_type, frame_subtype;
 921        u16 fc = le16_to_cpu(hdr->frame_control);
 922        u16 seqno = 0;
 923        u8 vif_idx = 0;
 924        u32 val;
 925        u8 bw;
 926
 927        if (vif) {
 928                mvif = (struct mt7603_vif *)vif->drv_priv;
 929                vif_idx = mvif->idx;
 930                if (vif_idx && qid >= MT_TXQ_BEACON)
 931                        vif_idx += 0x10;
 932        }
 933
 934        if (sta) {
 935                struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
 936
 937                tx_count = msta->rate_count;
 938        }
 939
 940        if (wcid)
 941                wlan_idx = wcid->idx;
 942        else
 943                wlan_idx = MT7603_WTBL_RESERVED;
 944
 945        frame_type = (fc & IEEE80211_FCTL_FTYPE) >> 2;
 946        frame_subtype = (fc & IEEE80211_FCTL_STYPE) >> 4;
 947
 948        val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
 949              FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx);
 950        txwi[0] = cpu_to_le32(val);
 951
 952        val = MT_TXD1_LONG_FORMAT |
 953              FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) |
 954              FIELD_PREP(MT_TXD1_TID,
 955                         skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
 956              FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
 957              FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) |
 958              FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) |
 959              FIELD_PREP(MT_TXD1_PROTECTED, !!key);
 960        txwi[1] = cpu_to_le32(val);
 961
 962        if (info->flags & IEEE80211_TX_CTL_NO_ACK)
 963                txwi[1] |= cpu_to_le32(MT_TXD1_NO_ACK);
 964
 965        val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) |
 966              FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) |
 967              FIELD_PREP(MT_TXD2_MULTICAST,
 968                         is_multicast_ether_addr(hdr->addr1));
 969        txwi[2] = cpu_to_le32(val);
 970
 971        if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
 972                txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
 973
 974        txwi[4] = 0;
 975
 976        val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
 977              FIELD_PREP(MT_TXD5_PID, pid);
 978        txwi[5] = cpu_to_le32(val);
 979
 980        txwi[6] = 0;
 981
 982        if (rate->idx >= 0 && rate->count &&
 983            !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
 984                bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
 985                u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw);
 986
 987                txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
 988
 989                val = MT_TXD6_FIXED_BW |
 990                      FIELD_PREP(MT_TXD6_BW, bw) |
 991                      FIELD_PREP(MT_TXD6_TX_RATE, rateval);
 992                txwi[6] |= cpu_to_le32(val);
 993
 994                if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
 995                        txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
 996
 997                if (!(rate->flags & IEEE80211_TX_RC_MCS))
 998                        txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
 999
1000                tx_count = rate->count;
1001        }
1002
1003        /* use maximum tx count for beacons and buffered multicast */
1004        if (qid >= MT_TXQ_BEACON)
1005                tx_count = 0x1f;
1006
1007        val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) |
1008                  MT_TXD3_SN_VALID;
1009
1010        if (ieee80211_is_data_qos(hdr->frame_control))
1011                seqno = le16_to_cpu(hdr->seq_ctrl);
1012        else if (ieee80211_is_back_req(hdr->frame_control))
1013                seqno = le16_to_cpu(bar->start_seq_num);
1014        else
1015                val &= ~MT_TXD3_SN_VALID;
1016
1017        val |= FIELD_PREP(MT_TXD3_SEQ, seqno >> 4);
1018
1019        txwi[3] = cpu_to_le32(val);
1020
1021        if (key) {
1022                u64 pn = atomic64_inc_return(&key->tx_pn);
1023
1024                txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID);
1025                txwi[4] = cpu_to_le32(pn & GENMASK(31, 0));
1026                txwi[5] |= cpu_to_le32(FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32));
1027        }
1028
1029        txwi[7] = 0;
1030
1031        return 0;
1032}
1033
1034int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1035                          enum mt76_txq_id qid, struct mt76_wcid *wcid,
1036                          struct ieee80211_sta *sta,
1037                          struct mt76_tx_info *tx_info)
1038{
1039        struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
1040        struct mt7603_sta *msta = container_of(wcid, struct mt7603_sta, wcid);
1041        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
1042        struct ieee80211_key_conf *key = info->control.hw_key;
1043        int pid;
1044
1045        if (!wcid)
1046                wcid = &dev->global_sta.wcid;
1047
1048        if (sta) {
1049                msta = (struct mt7603_sta *)sta->drv_priv;
1050
1051                if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER |
1052                                    IEEE80211_TX_CTL_CLEAR_PS_FILT)) ||
1053                    (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE))
1054                        mt7603_wtbl_set_ps(dev, msta, false);
1055
1056                mt76_tx_check_agg_ssn(sta, tx_info->skb);
1057        }
1058
1059        pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
1060
1061        if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
1062                spin_lock_bh(&dev->mt76.lock);
1063                mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0],
1064                                      msta->rates);
1065                msta->rate_probe = true;
1066                spin_unlock_bh(&dev->mt76.lock);
1067        }
1068
1069        mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid,
1070                              sta, pid, key);
1071
1072        return 0;
1073}
1074
1075static bool
1076mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta,
1077                struct ieee80211_tx_info *info, __le32 *txs_data)
1078{
1079        struct ieee80211_supported_band *sband;
1080        struct mt7603_rate_set *rs;
1081        int first_idx = 0, last_idx;
1082        u32 rate_set_tsf;
1083        u32 final_rate;
1084        u32 final_rate_flags;
1085        bool rs_idx;
1086        bool ack_timeout;
1087        bool fixed_rate;
1088        bool probe;
1089        bool ampdu;
1090        bool cck = false;
1091        int count;
1092        u32 txs;
1093        int idx;
1094        int i;
1095
1096        fixed_rate = info->status.rates[0].count;
1097        probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1098
1099        txs = le32_to_cpu(txs_data[4]);
1100        ampdu = !fixed_rate && (txs & MT_TXS4_AMPDU);
1101        count = FIELD_GET(MT_TXS4_TX_COUNT, txs);
1102        last_idx = FIELD_GET(MT_TXS4_LAST_TX_RATE, txs);
1103
1104        txs = le32_to_cpu(txs_data[0]);
1105        final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1106        ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1107
1108        if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1109                return false;
1110
1111        if (txs & MT_TXS0_QUEUE_TIMEOUT)
1112                return false;
1113
1114        if (!ack_timeout)
1115                info->flags |= IEEE80211_TX_STAT_ACK;
1116
1117        info->status.ampdu_len = 1;
1118        info->status.ampdu_ack_len = !!(info->flags &
1119                                        IEEE80211_TX_STAT_ACK);
1120
1121        if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1122                info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1123
1124        first_idx = max_t(int, 0, last_idx - (count - 1) / MT7603_RATE_RETRY);
1125
1126        if (fixed_rate && !probe) {
1127                info->status.rates[0].count = count;
1128                i = 0;
1129                goto out;
1130        }
1131
1132        rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1133        rs_idx = !((u32)(FIELD_GET(MT_TXS1_F0_TIMESTAMP, le32_to_cpu(txs_data[1])) -
1134                         rate_set_tsf) < 1000000);
1135        rs_idx ^= rate_set_tsf & BIT(0);
1136        rs = &sta->rateset[rs_idx];
1137
1138        if (!first_idx && rs->probe_rate.idx >= 0) {
1139                info->status.rates[0] = rs->probe_rate;
1140
1141                spin_lock_bh(&dev->mt76.lock);
1142                if (sta->rate_probe) {
1143                        mt7603_wtbl_set_rates(dev, sta, NULL,
1144                                              sta->rates);
1145                        sta->rate_probe = false;
1146                }
1147                spin_unlock_bh(&dev->mt76.lock);
1148        } else {
1149                info->status.rates[0] = rs->rates[first_idx / 2];
1150        }
1151        info->status.rates[0].count = 0;
1152
1153        for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1154                struct ieee80211_tx_rate *cur_rate;
1155                int cur_count;
1156
1157                cur_rate = &rs->rates[idx / 2];
1158                cur_count = min_t(int, MT7603_RATE_RETRY, count);
1159                count -= cur_count;
1160
1161                if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1162                            cur_rate->flags != info->status.rates[i].flags)) {
1163                        i++;
1164                        if (i == ARRAY_SIZE(info->status.rates)) {
1165                                i--;
1166                                break;
1167                        }
1168
1169                        info->status.rates[i] = *cur_rate;
1170                        info->status.rates[i].count = 0;
1171                }
1172
1173                info->status.rates[i].count += cur_count;
1174        }
1175
1176out:
1177        final_rate_flags = info->status.rates[i].flags;
1178
1179        switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1180        case MT_PHY_TYPE_CCK:
1181                cck = true;
1182                fallthrough;
1183        case MT_PHY_TYPE_OFDM:
1184                if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ)
1185                        sband = &dev->mphy.sband_5g.sband;
1186                else
1187                        sband = &dev->mphy.sband_2g.sband;
1188                final_rate &= GENMASK(5, 0);
1189                final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1190                                           cck);
1191                final_rate_flags = 0;
1192                break;
1193        case MT_PHY_TYPE_HT_GF:
1194        case MT_PHY_TYPE_HT:
1195                final_rate_flags |= IEEE80211_TX_RC_MCS;
1196                final_rate &= GENMASK(5, 0);
1197                if (final_rate > 15)
1198                        return false;
1199                break;
1200        default:
1201                return false;
1202        }
1203
1204        info->status.rates[i].idx = final_rate;
1205        info->status.rates[i].flags = final_rate_flags;
1206
1207        return true;
1208}
1209
1210static bool
1211mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid,
1212                       __le32 *txs_data)
1213{
1214        struct mt76_dev *mdev = &dev->mt76;
1215        struct sk_buff_head list;
1216        struct sk_buff *skb;
1217
1218        if (pid < MT_PACKET_ID_FIRST)
1219                return false;
1220
1221        trace_mac_txdone(mdev, sta->wcid.idx, pid);
1222
1223        mt76_tx_status_lock(mdev, &list);
1224        skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1225        if (skb) {
1226                struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1227
1228                if (!mt7603_fill_txs(dev, sta, info, txs_data)) {
1229                        info->status.rates[0].count = 0;
1230                        info->status.rates[0].idx = -1;
1231                }
1232
1233                mt76_tx_status_skb_done(mdev, skb, &list);
1234        }
1235        mt76_tx_status_unlock(mdev, &list);
1236
1237        return !!skb;
1238}
1239
1240void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data)
1241{
1242        struct ieee80211_tx_info info = {};
1243        struct ieee80211_sta *sta = NULL;
1244        struct mt7603_sta *msta = NULL;
1245        struct mt76_wcid *wcid;
1246        __le32 *txs_data = data;
1247        u32 txs;
1248        u8 wcidx;
1249        u8 pid;
1250
1251        txs = le32_to_cpu(txs_data[4]);
1252        pid = FIELD_GET(MT_TXS4_PID, txs);
1253        txs = le32_to_cpu(txs_data[3]);
1254        wcidx = FIELD_GET(MT_TXS3_WCID, txs);
1255
1256        if (pid == MT_PACKET_ID_NO_ACK)
1257                return;
1258
1259        if (wcidx >= MT7603_WTBL_SIZE)
1260                return;
1261
1262        rcu_read_lock();
1263
1264        wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1265        if (!wcid)
1266                goto out;
1267
1268        msta = container_of(wcid, struct mt7603_sta, wcid);
1269        sta = wcid_to_sta(wcid);
1270
1271        if (list_empty(&msta->poll_list)) {
1272                spin_lock_bh(&dev->sta_poll_lock);
1273                list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1274                spin_unlock_bh(&dev->sta_poll_lock);
1275        }
1276
1277        if (mt7603_mac_add_txs_skb(dev, msta, pid, txs_data))
1278                goto out;
1279
1280        if (wcidx >= MT7603_WTBL_STA || !sta)
1281                goto out;
1282
1283        if (mt7603_fill_txs(dev, msta, &info, txs_data))
1284                ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info);
1285
1286out:
1287        rcu_read_unlock();
1288}
1289
1290void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e)
1291{
1292        struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
1293        struct sk_buff *skb = e->skb;
1294
1295        if (!e->txwi) {
1296                dev_kfree_skb_any(skb);
1297                return;
1298        }
1299
1300        dev->tx_hang_check = 0;
1301        mt76_tx_complete_skb(mdev, e->wcid, skb);
1302}
1303
1304static bool
1305wait_for_wpdma(struct mt7603_dev *dev)
1306{
1307        return mt76_poll(dev, MT_WPDMA_GLO_CFG,
1308                         MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
1309                         MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
1310                         0, 1000);
1311}
1312
1313static void mt7603_pse_reset(struct mt7603_dev *dev)
1314{
1315        /* Clear previous reset result */
1316        if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED])
1317                mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S);
1318
1319        /* Reset PSE */
1320        mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
1321
1322        if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET,
1323                            MT_MCU_DEBUG_RESET_PSE_S,
1324                            MT_MCU_DEBUG_RESET_PSE_S, 500)) {
1325                dev->reset_cause[RESET_CAUSE_RESET_FAILED]++;
1326                mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
1327        } else {
1328                dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;
1329                mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES);
1330        }
1331
1332        if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3)
1333                dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;
1334}
1335
1336void mt7603_mac_dma_start(struct mt7603_dev *dev)
1337{
1338        mt7603_mac_start(dev);
1339
1340        wait_for_wpdma(dev);
1341        usleep_range(50, 100);
1342
1343        mt76_set(dev, MT_WPDMA_GLO_CFG,
1344                 (MT_WPDMA_GLO_CFG_TX_DMA_EN |
1345                  MT_WPDMA_GLO_CFG_RX_DMA_EN |
1346                  FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
1347                  MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE));
1348
1349        mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL);
1350}
1351
1352void mt7603_mac_start(struct mt7603_dev *dev)
1353{
1354        mt76_clear(dev, MT_ARB_SCR,
1355                   MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1356        mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0);
1357        mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
1358}
1359
1360void mt7603_mac_stop(struct mt7603_dev *dev)
1361{
1362        mt76_set(dev, MT_ARB_SCR,
1363                 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1364        mt76_wr(dev, MT_WF_ARB_TX_START_0, 0);
1365        mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
1366}
1367
1368void mt7603_pse_client_reset(struct mt7603_dev *dev)
1369{
1370        u32 addr;
1371
1372        addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR +
1373                                   MT_CLIENT_RESET_TX);
1374
1375        /* Clear previous reset state */
1376        mt76_clear(dev, addr,
1377                   MT_CLIENT_RESET_TX_R_E_1 |
1378                   MT_CLIENT_RESET_TX_R_E_2 |
1379                   MT_CLIENT_RESET_TX_R_E_1_S |
1380                   MT_CLIENT_RESET_TX_R_E_2_S);
1381
1382        /* Start PSE client TX abort */
1383        mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1);
1384        mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S,
1385                       MT_CLIENT_RESET_TX_R_E_1_S, 500);
1386
1387        mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2);
1388        mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
1389
1390        /* Wait for PSE client to clear TX FIFO */
1391        mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S,
1392                       MT_CLIENT_RESET_TX_R_E_2_S, 500);
1393
1394        /* Clear PSE client TX abort state */
1395        mt76_clear(dev, addr,
1396                   MT_CLIENT_RESET_TX_R_E_1 |
1397                   MT_CLIENT_RESET_TX_R_E_2);
1398}
1399
1400static void mt7603_dma_sched_reset(struct mt7603_dev *dev)
1401{
1402        if (!is_mt7628(dev))
1403                return;
1404
1405        mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET);
1406        mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET);
1407}
1408
1409static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
1410{
1411        int beacon_int = dev->mt76.beacon_int;
1412        u32 mask = dev->mt76.mmio.irqmask;
1413        int i;
1414
1415        ieee80211_stop_queues(dev->mt76.hw);
1416        set_bit(MT76_RESET, &dev->mphy.state);
1417
1418        /* lock/unlock all queues to ensure that no tx is pending */
1419        mt76_txq_schedule_all(&dev->mphy);
1420
1421        mt76_worker_disable(&dev->mt76.tx_worker);
1422        tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
1423        napi_disable(&dev->mt76.napi[0]);
1424        napi_disable(&dev->mt76.napi[1]);
1425        napi_disable(&dev->mt76.tx_napi);
1426
1427        mutex_lock(&dev->mt76.mutex);
1428
1429        mt7603_beacon_set_timer(dev, -1, 0);
1430
1431        if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] ||
1432            dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY ||
1433            dev->cur_reset_cause == RESET_CAUSE_BEACON_STUCK ||
1434            dev->cur_reset_cause == RESET_CAUSE_TX_HANG)
1435                mt7603_pse_reset(dev);
1436
1437        if (dev->reset_cause[RESET_CAUSE_RESET_FAILED])
1438                goto skip_dma_reset;
1439
1440        mt7603_mac_stop(dev);
1441
1442        mt76_clear(dev, MT_WPDMA_GLO_CFG,
1443                   MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
1444                   MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
1445        usleep_range(1000, 2000);
1446
1447        mt7603_irq_disable(dev, mask);
1448
1449        mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF);
1450
1451        mt7603_pse_client_reset(dev);
1452
1453        mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
1454        for (i = 0; i < __MT_TXQ_MAX; i++)
1455                mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
1456
1457        mt76_for_each_q_rx(&dev->mt76, i) {
1458                mt76_queue_rx_reset(dev, i);
1459        }
1460
1461        mt76_tx_status_check(&dev->mt76, NULL, true);
1462
1463        mt7603_dma_sched_reset(dev);
1464
1465        mt7603_mac_dma_start(dev);
1466
1467        mt7603_irq_enable(dev, mask);
1468
1469skip_dma_reset:
1470        clear_bit(MT76_RESET, &dev->mphy.state);
1471        mutex_unlock(&dev->mt76.mutex);
1472
1473        mt76_worker_enable(&dev->mt76.tx_worker);
1474        napi_enable(&dev->mt76.tx_napi);
1475        napi_schedule(&dev->mt76.tx_napi);
1476
1477        tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
1478        mt7603_beacon_set_timer(dev, -1, beacon_int);
1479
1480        napi_enable(&dev->mt76.napi[0]);
1481        napi_schedule(&dev->mt76.napi[0]);
1482
1483        napi_enable(&dev->mt76.napi[1]);
1484        napi_schedule(&dev->mt76.napi[1]);
1485
1486        ieee80211_wake_queues(dev->mt76.hw);
1487        mt76_txq_schedule_all(&dev->mphy);
1488}
1489
1490static u32 mt7603_dma_debug(struct mt7603_dev *dev, u8 index)
1491{
1492        u32 val;
1493
1494        mt76_wr(dev, MT_WPDMA_DEBUG,
1495                FIELD_PREP(MT_WPDMA_DEBUG_IDX, index) |
1496                MT_WPDMA_DEBUG_SEL);
1497
1498        val = mt76_rr(dev, MT_WPDMA_DEBUG);
1499        return FIELD_GET(MT_WPDMA_DEBUG_VALUE, val);
1500}
1501
1502static bool mt7603_rx_fifo_busy(struct mt7603_dev *dev)
1503{
1504        if (is_mt7628(dev))
1505                return mt7603_dma_debug(dev, 9) & BIT(9);
1506
1507        return mt7603_dma_debug(dev, 2) & BIT(8);
1508}
1509
1510static bool mt7603_rx_dma_busy(struct mt7603_dev *dev)
1511{
1512        if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY))
1513                return false;
1514
1515        return mt7603_rx_fifo_busy(dev);
1516}
1517
1518static bool mt7603_tx_dma_busy(struct mt7603_dev *dev)
1519{
1520        u32 val;
1521
1522        if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_TX_DMA_BUSY))
1523                return false;
1524
1525        val = mt7603_dma_debug(dev, 9);
1526        return (val & BIT(8)) && (val & 0xf) != 0xf;
1527}
1528
1529static bool mt7603_tx_hang(struct mt7603_dev *dev)
1530{
1531        struct mt76_queue *q;
1532        u32 dma_idx, prev_dma_idx;
1533        int i;
1534
1535        for (i = 0; i < 4; i++) {
1536                q = dev->mphy.q_tx[i];
1537
1538                if (!q->queued)
1539                        continue;
1540
1541                prev_dma_idx = dev->tx_dma_idx[i];
1542                dma_idx = readl(&q->regs->dma_idx);
1543                dev->tx_dma_idx[i] = dma_idx;
1544
1545                if (dma_idx == prev_dma_idx &&
1546                    dma_idx != readl(&q->regs->cpu_idx))
1547                        break;
1548        }
1549
1550        return i < 4;
1551}
1552
1553static bool mt7603_rx_pse_busy(struct mt7603_dev *dev)
1554{
1555        u32 addr, val;
1556
1557        if (mt76_rr(dev, MT_MCU_DEBUG_RESET) & MT_MCU_DEBUG_RESET_QUEUES)
1558                return true;
1559
1560        if (mt7603_rx_fifo_busy(dev))
1561                return false;
1562
1563        addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS);
1564        mt76_wr(dev, addr, 3);
1565        val = mt76_rr(dev, addr) >> 16;
1566
1567        if (is_mt7628(dev) && (val & 0x4001) == 0x4001)
1568                return true;
1569
1570        return (val & 0x8001) == 0x8001 || (val & 0xe001) == 0xe001;
1571}
1572
1573static bool
1574mt7603_watchdog_check(struct mt7603_dev *dev, u8 *counter,
1575                      enum mt7603_reset_cause cause,
1576                      bool (*check)(struct mt7603_dev *dev))
1577{
1578        if (dev->reset_test == cause + 1) {
1579                dev->reset_test = 0;
1580                goto trigger;
1581        }
1582
1583        if (check) {
1584                if (!check(dev) && *counter < MT7603_WATCHDOG_TIMEOUT) {
1585                        *counter = 0;
1586                        return false;
1587                }
1588
1589                (*counter)++;
1590        }
1591
1592        if (*counter < MT7603_WATCHDOG_TIMEOUT)
1593                return false;
1594trigger:
1595        dev->cur_reset_cause = cause;
1596        dev->reset_cause[cause]++;
1597        return true;
1598}
1599
1600void mt7603_update_channel(struct mt76_phy *mphy)
1601{
1602        struct mt7603_dev *dev = container_of(mphy->dev, struct mt7603_dev, mt76);
1603        struct mt76_channel_state *state;
1604
1605        state = mphy->chan_state;
1606        state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA);
1607}
1608
1609void
1610mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val)
1611{
1612        u32 rxtd_6 = 0xd7c80000;
1613
1614        if (val == dev->ed_strict_mode)
1615                return;
1616
1617        dev->ed_strict_mode = val;
1618
1619        /* Ensure that ED/CCA does not trigger if disabled */
1620        if (!dev->ed_monitor)
1621                rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x34);
1622        else
1623                rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x7d);
1624
1625        if (dev->ed_monitor && !dev->ed_strict_mode)
1626                rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x0f);
1627        else
1628                rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x10);
1629
1630        mt76_wr(dev, MT_RXTD(6), rxtd_6);
1631
1632        mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN,
1633                       dev->ed_monitor && !dev->ed_strict_mode);
1634}
1635
1636static void
1637mt7603_edcca_check(struct mt7603_dev *dev)
1638{
1639        u32 val = mt76_rr(dev, MT_AGC(41));
1640        ktime_t cur_time;
1641        int rssi0, rssi1;
1642        u32 active;
1643        u32 ed_busy;
1644
1645        if (!dev->ed_monitor)
1646                return;
1647
1648        rssi0 = FIELD_GET(MT_AGC_41_RSSI_0, val);
1649        if (rssi0 > 128)
1650                rssi0 -= 256;
1651
1652        if (dev->mphy.antenna_mask & BIT(1)) {
1653                rssi1 = FIELD_GET(MT_AGC_41_RSSI_1, val);
1654                if (rssi1 > 128)
1655                        rssi1 -= 256;
1656        } else {
1657                rssi1 = rssi0;
1658        }
1659
1660        if (max(rssi0, rssi1) >= -40 &&
1661            dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH)
1662                dev->ed_strong_signal++;
1663        else if (dev->ed_strong_signal > 0)
1664                dev->ed_strong_signal--;
1665
1666        cur_time = ktime_get_boottime();
1667        ed_busy = mt76_rr(dev, MT_MIB_STAT_ED) & MT_MIB_STAT_ED_MASK;
1668
1669        active = ktime_to_us(ktime_sub(cur_time, dev->ed_time));
1670        dev->ed_time = cur_time;
1671
1672        if (!active)
1673                return;
1674
1675        if (100 * ed_busy / active > 90) {
1676                if (dev->ed_trigger < 0)
1677                        dev->ed_trigger = 0;
1678                dev->ed_trigger++;
1679        } else {
1680                if (dev->ed_trigger > 0)
1681                        dev->ed_trigger = 0;
1682                dev->ed_trigger--;
1683        }
1684
1685        if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH ||
1686            dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) {
1687                mt7603_edcca_set_strict(dev, true);
1688        } else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) {
1689                mt7603_edcca_set_strict(dev, false);
1690        }
1691
1692        if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH)
1693                dev->ed_trigger = MT7603_EDCCA_BLOCK_TH;
1694        else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH)
1695                dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH;
1696}
1697
1698void mt7603_cca_stats_reset(struct mt7603_dev *dev)
1699{
1700        mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);
1701        mt76_clear(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);
1702        mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN);
1703}
1704
1705static void
1706mt7603_adjust_sensitivity(struct mt7603_dev *dev)
1707{
1708        u32 agc0 = dev->agc0, agc3 = dev->agc3;
1709        u32 adj;
1710
1711        if (!dev->sensitivity || dev->sensitivity < -100) {
1712                dev->sensitivity = 0;
1713        } else if (dev->sensitivity <= -84) {
1714                adj = 7 + (dev->sensitivity + 92) / 2;
1715
1716                agc0 = 0x56f0076f;
1717                agc0 |= adj << 12;
1718                agc0 |= adj << 16;
1719                agc3 = 0x81d0d5e3;
1720        } else if (dev->sensitivity <= -72) {
1721                adj = 7 + (dev->sensitivity + 80) / 2;
1722
1723                agc0 = 0x6af0006f;
1724                agc0 |= adj << 8;
1725                agc0 |= adj << 12;
1726                agc0 |= adj << 16;
1727
1728                agc3 = 0x8181d5e3;
1729        } else {
1730                if (dev->sensitivity > -54)
1731                        dev->sensitivity = -54;
1732
1733                adj = 7 + (dev->sensitivity + 80) / 2;
1734
1735                agc0 = 0x7ff0000f;
1736                agc0 |= adj << 4;
1737                agc0 |= adj << 8;
1738                agc0 |= adj << 12;
1739                agc0 |= adj << 16;
1740
1741                agc3 = 0x818181e3;
1742        }
1743
1744        mt76_wr(dev, MT_AGC(0), agc0);
1745        mt76_wr(dev, MT_AGC1(0), agc0);
1746
1747        mt76_wr(dev, MT_AGC(3), agc3);
1748        mt76_wr(dev, MT_AGC1(3), agc3);
1749}
1750
1751static void
1752mt7603_false_cca_check(struct mt7603_dev *dev)
1753{
1754        int pd_cck, pd_ofdm, mdrdy_cck, mdrdy_ofdm;
1755        int false_cca;
1756        int min_signal;
1757        u32 val;
1758
1759        if (!dev->dynamic_sensitivity)
1760                return;
1761
1762        val = mt76_rr(dev, MT_PHYCTRL_STAT_PD);
1763        pd_cck = FIELD_GET(MT_PHYCTRL_STAT_PD_CCK, val);
1764        pd_ofdm = FIELD_GET(MT_PHYCTRL_STAT_PD_OFDM, val);
1765
1766        val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY);
1767        mdrdy_cck = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_CCK, val);
1768        mdrdy_ofdm = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_OFDM, val);
1769
1770        dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1771        dev->false_cca_cck = pd_cck - mdrdy_cck;
1772
1773        mt7603_cca_stats_reset(dev);
1774
1775        min_signal = mt76_get_min_avg_rssi(&dev->mt76, false);
1776        if (!min_signal) {
1777                dev->sensitivity = 0;
1778                dev->last_cca_adj = jiffies;
1779                goto out;
1780        }
1781
1782        min_signal -= 15;
1783
1784        false_cca = dev->false_cca_ofdm + dev->false_cca_cck;
1785        if (false_cca > 600 &&
1786            dev->sensitivity < -100 + dev->sensitivity_limit) {
1787                if (!dev->sensitivity)
1788                        dev->sensitivity = -92;
1789                else
1790                        dev->sensitivity += 2;
1791                dev->last_cca_adj = jiffies;
1792        } else if (false_cca < 100 ||
1793                   time_after(jiffies, dev->last_cca_adj + 10 * HZ)) {
1794                dev->last_cca_adj = jiffies;
1795                if (!dev->sensitivity)
1796                        goto out;
1797
1798                dev->sensitivity -= 2;
1799        }
1800
1801        if (dev->sensitivity && dev->sensitivity > min_signal) {
1802                dev->sensitivity = min_signal;
1803                dev->last_cca_adj = jiffies;
1804        }
1805
1806out:
1807        mt7603_adjust_sensitivity(dev);
1808}
1809
1810void mt7603_mac_work(struct work_struct *work)
1811{
1812        struct mt7603_dev *dev = container_of(work, struct mt7603_dev,
1813                                              mphy.mac_work.work);
1814        bool reset = false;
1815        int i, idx;
1816
1817        mt76_tx_status_check(&dev->mt76, NULL, false);
1818
1819        mutex_lock(&dev->mt76.mutex);
1820
1821        dev->mphy.mac_work_count++;
1822        mt76_update_survey(&dev->mphy);
1823        mt7603_edcca_check(dev);
1824
1825        for (i = 0, idx = 0; i < 2; i++) {
1826                u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i));
1827
1828                dev->mt76.aggr_stats[idx++] += val & 0xffff;
1829                dev->mt76.aggr_stats[idx++] += val >> 16;
1830        }
1831
1832        if (dev->mphy.mac_work_count == 10)
1833                mt7603_false_cca_check(dev);
1834
1835        if (mt7603_watchdog_check(dev, &dev->rx_pse_check,
1836                                  RESET_CAUSE_RX_PSE_BUSY,
1837                                  mt7603_rx_pse_busy) ||
1838            mt7603_watchdog_check(dev, &dev->beacon_check,
1839                                  RESET_CAUSE_BEACON_STUCK,
1840                                  NULL) ||
1841            mt7603_watchdog_check(dev, &dev->tx_hang_check,
1842                                  RESET_CAUSE_TX_HANG,
1843                                  mt7603_tx_hang) ||
1844            mt7603_watchdog_check(dev, &dev->tx_dma_check,
1845                                  RESET_CAUSE_TX_BUSY,
1846                                  mt7603_tx_dma_busy) ||
1847            mt7603_watchdog_check(dev, &dev->rx_dma_check,
1848                                  RESET_CAUSE_RX_BUSY,
1849                                  mt7603_rx_dma_busy) ||
1850            mt7603_watchdog_check(dev, &dev->mcu_hang,
1851                                  RESET_CAUSE_MCU_HANG,
1852                                  NULL) ||
1853            dev->reset_cause[RESET_CAUSE_RESET_FAILED]) {
1854                dev->beacon_check = 0;
1855                dev->tx_dma_check = 0;
1856                dev->tx_hang_check = 0;
1857                dev->rx_dma_check = 0;
1858                dev->rx_pse_check = 0;
1859                dev->mcu_hang = 0;
1860                dev->rx_dma_idx = ~0;
1861                memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx));
1862                reset = true;
1863                dev->mphy.mac_work_count = 0;
1864        }
1865
1866        if (dev->mphy.mac_work_count >= 10)
1867                dev->mphy.mac_work_count = 0;
1868
1869        mutex_unlock(&dev->mt76.mutex);
1870
1871        if (reset)
1872                mt7603_mac_watchdog_reset(dev);
1873
1874        ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
1875                                     msecs_to_jiffies(MT7603_WATCHDOG_TIME));
1876}
1877
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