linux/drivers/net/phy/phy-c45.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Clause 45 PHY support
   4 */
   5#include <linux/ethtool.h>
   6#include <linux/export.h>
   7#include <linux/mdio.h>
   8#include <linux/mii.h>
   9#include <linux/phy.h>
  10
  11/**
  12 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
  13 * @phydev: target phy_device struct
  14 */
  15static bool genphy_c45_pma_can_sleep(struct phy_device *phydev)
  16{
  17        int stat1;
  18
  19        stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
  20        if (stat1 < 0)
  21                return false;
  22
  23        return !!(stat1 & MDIO_STAT1_LPOWERABLE);
  24}
  25
  26/**
  27 * genphy_c45_pma_resume - wakes up the PMA module
  28 * @phydev: target phy_device struct
  29 */
  30int genphy_c45_pma_resume(struct phy_device *phydev)
  31{
  32        if (!genphy_c45_pma_can_sleep(phydev))
  33                return -EOPNOTSUPP;
  34
  35        return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
  36                                  MDIO_CTRL1_LPOWER);
  37}
  38EXPORT_SYMBOL_GPL(genphy_c45_pma_resume);
  39
  40/**
  41 * genphy_c45_pma_suspend - suspends the PMA module
  42 * @phydev: target phy_device struct
  43 */
  44int genphy_c45_pma_suspend(struct phy_device *phydev)
  45{
  46        if (!genphy_c45_pma_can_sleep(phydev))
  47                return -EOPNOTSUPP;
  48
  49        return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
  50                                MDIO_CTRL1_LPOWER);
  51}
  52EXPORT_SYMBOL_GPL(genphy_c45_pma_suspend);
  53
  54/**
  55 * genphy_c45_pma_setup_forced - configures a forced speed
  56 * @phydev: target phy_device struct
  57 */
  58int genphy_c45_pma_setup_forced(struct phy_device *phydev)
  59{
  60        int ctrl1, ctrl2, ret;
  61
  62        /* Half duplex is not supported */
  63        if (phydev->duplex != DUPLEX_FULL)
  64                return -EINVAL;
  65
  66        ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
  67        if (ctrl1 < 0)
  68                return ctrl1;
  69
  70        ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
  71        if (ctrl2 < 0)
  72                return ctrl2;
  73
  74        ctrl1 &= ~MDIO_CTRL1_SPEEDSEL;
  75        /*
  76         * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0.  See 45.2.1.6.1
  77         * in 802.3-2012 and 802.3-2015.
  78         */
  79        ctrl2 &= ~(MDIO_PMA_CTRL2_TYPE | 0x30);
  80
  81        switch (phydev->speed) {
  82        case SPEED_10:
  83                ctrl2 |= MDIO_PMA_CTRL2_10BT;
  84                break;
  85        case SPEED_100:
  86                ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
  87                ctrl2 |= MDIO_PMA_CTRL2_100BTX;
  88                break;
  89        case SPEED_1000:
  90                ctrl1 |= MDIO_PMA_CTRL1_SPEED1000;
  91                /* Assume 1000base-T */
  92                ctrl2 |= MDIO_PMA_CTRL2_1000BT;
  93                break;
  94        case SPEED_2500:
  95                ctrl1 |= MDIO_CTRL1_SPEED2_5G;
  96                /* Assume 2.5Gbase-T */
  97                ctrl2 |= MDIO_PMA_CTRL2_2_5GBT;
  98                break;
  99        case SPEED_5000:
 100                ctrl1 |= MDIO_CTRL1_SPEED5G;
 101                /* Assume 5Gbase-T */
 102                ctrl2 |= MDIO_PMA_CTRL2_5GBT;
 103                break;
 104        case SPEED_10000:
 105                ctrl1 |= MDIO_CTRL1_SPEED10G;
 106                /* Assume 10Gbase-T */
 107                ctrl2 |= MDIO_PMA_CTRL2_10GBT;
 108                break;
 109        default:
 110                return -EINVAL;
 111        }
 112
 113        ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
 114        if (ret < 0)
 115                return ret;
 116
 117        ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
 118        if (ret < 0)
 119                return ret;
 120
 121        return genphy_c45_an_disable_aneg(phydev);
 122}
 123EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
 124
 125/**
 126 * genphy_c45_an_config_aneg - configure advertisement registers
 127 * @phydev: target phy_device struct
 128 *
 129 * Configure advertisement registers based on modes set in phydev->advertising
 130 *
 131 * Returns negative errno code on failure, 0 if advertisement didn't change,
 132 * or 1 if advertised modes changed.
 133 */
 134int genphy_c45_an_config_aneg(struct phy_device *phydev)
 135{
 136        int changed, ret;
 137        u32 adv;
 138
 139        linkmode_and(phydev->advertising, phydev->advertising,
 140                     phydev->supported);
 141
 142        changed = genphy_config_eee_advert(phydev);
 143
 144        adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
 145
 146        ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
 147                                     ADVERTISE_ALL | ADVERTISE_100BASE4 |
 148                                     ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
 149                                     adv);
 150        if (ret < 0)
 151                return ret;
 152        if (ret > 0)
 153                changed = 1;
 154
 155        adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
 156
 157        ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
 158                                     MDIO_AN_10GBT_CTRL_ADV10G |
 159                                     MDIO_AN_10GBT_CTRL_ADV5G |
 160                                     MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
 161        if (ret < 0)
 162                return ret;
 163        if (ret > 0)
 164                changed = 1;
 165
 166        return changed;
 167}
 168EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
 169
 170/**
 171 * genphy_c45_an_disable_aneg - disable auto-negotiation
 172 * @phydev: target phy_device struct
 173 *
 174 * Disable auto-negotiation in the Clause 45 PHY. The link parameters
 175 * are controlled through the PMA/PMD MMD registers.
 176 *
 177 * Returns zero on success, negative errno code on failure.
 178 */
 179int genphy_c45_an_disable_aneg(struct phy_device *phydev)
 180{
 181
 182        return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
 183                                  MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 184}
 185EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
 186
 187/**
 188 * genphy_c45_restart_aneg - Enable and restart auto-negotiation
 189 * @phydev: target phy_device struct
 190 *
 191 * This assumes that the auto-negotiation MMD is present.
 192 *
 193 * Enable and restart auto-negotiation.
 194 */
 195int genphy_c45_restart_aneg(struct phy_device *phydev)
 196{
 197        return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
 198                                MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
 199}
 200EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
 201
 202/**
 203 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
 204 * @phydev: target phy_device struct
 205 * @restart: whether aneg restart is requested
 206 *
 207 * This assumes that the auto-negotiation MMD is present.
 208 *
 209 * Check, and restart auto-negotiation if needed.
 210 */
 211int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
 212{
 213        int ret;
 214
 215        if (!restart) {
 216                /* Configure and restart aneg if it wasn't set before */
 217                ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
 218                if (ret < 0)
 219                        return ret;
 220
 221                if (!(ret & MDIO_AN_CTRL1_ENABLE))
 222                        restart = true;
 223        }
 224
 225        if (restart)
 226                return genphy_c45_restart_aneg(phydev);
 227
 228        return 0;
 229}
 230EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
 231
 232/**
 233 * genphy_c45_aneg_done - return auto-negotiation complete status
 234 * @phydev: target phy_device struct
 235 *
 236 * This assumes that the auto-negotiation MMD is present.
 237 *
 238 * Reads the status register from the auto-negotiation MMD, returning:
 239 * - positive if auto-negotiation is complete
 240 * - negative errno code on error
 241 * - zero otherwise
 242 */
 243int genphy_c45_aneg_done(struct phy_device *phydev)
 244{
 245        int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 246
 247        return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
 248}
 249EXPORT_SYMBOL_GPL(genphy_c45_aneg_done);
 250
 251/**
 252 * genphy_c45_read_link - read the overall link status from the MMDs
 253 * @phydev: target phy_device struct
 254 *
 255 * Read the link status from the specified MMDs, and if they all indicate
 256 * that the link is up, set phydev->link to 1.  If an error is encountered,
 257 * a negative errno will be returned, otherwise zero.
 258 */
 259int genphy_c45_read_link(struct phy_device *phydev)
 260{
 261        u32 mmd_mask = MDIO_DEVS_PMAPMD;
 262        int val, devad;
 263        bool link = true;
 264
 265        if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
 266                val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
 267                if (val < 0)
 268                        return val;
 269
 270                /* Autoneg is being started, therefore disregard current
 271                 * link status and report link as down.
 272                 */
 273                if (val & MDIO_AN_CTRL1_RESTART) {
 274                        phydev->link = 0;
 275                        return 0;
 276                }
 277        }
 278
 279        while (mmd_mask && link) {
 280                devad = __ffs(mmd_mask);
 281                mmd_mask &= ~BIT(devad);
 282
 283                /* The link state is latched low so that momentary link
 284                 * drops can be detected. Do not double-read the status
 285                 * in polling mode to detect such short link drops except
 286                 * the link was already down.
 287                 */
 288                if (!phy_polling_mode(phydev) || !phydev->link) {
 289                        val = phy_read_mmd(phydev, devad, MDIO_STAT1);
 290                        if (val < 0)
 291                                return val;
 292                        else if (val & MDIO_STAT1_LSTATUS)
 293                                continue;
 294                }
 295
 296                val = phy_read_mmd(phydev, devad, MDIO_STAT1);
 297                if (val < 0)
 298                        return val;
 299
 300                if (!(val & MDIO_STAT1_LSTATUS))
 301                        link = false;
 302        }
 303
 304        phydev->link = link;
 305
 306        return 0;
 307}
 308EXPORT_SYMBOL_GPL(genphy_c45_read_link);
 309
 310/**
 311 * genphy_c45_read_lpa - read the link partner advertisement and pause
 312 * @phydev: target phy_device struct
 313 *
 314 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
 315 * filling in the link partner advertisement, pause and asym_pause members
 316 * in @phydev.  This assumes that the auto-negotiation MMD is present, and
 317 * the backplane bit (7.48.0) is clear.  Clause 45 PHY drivers are expected
 318 * to fill in the remainder of the link partner advert from vendor registers.
 319 */
 320int genphy_c45_read_lpa(struct phy_device *phydev)
 321{
 322        int val;
 323
 324        val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 325        if (val < 0)
 326                return val;
 327
 328        if (!(val & MDIO_AN_STAT1_COMPLETE)) {
 329                linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 330                                   phydev->lp_advertising);
 331                mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
 332                mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
 333                phydev->pause = 0;
 334                phydev->asym_pause = 0;
 335
 336                return 0;
 337        }
 338
 339        linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
 340                         val & MDIO_AN_STAT1_LPABLE);
 341
 342        /* Read the link partner's base page advertisement */
 343        val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
 344        if (val < 0)
 345                return val;
 346
 347        mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
 348        phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
 349        phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
 350
 351        /* Read the link partner's 10G advertisement */
 352        val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
 353        if (val < 0)
 354                return val;
 355
 356        mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
 357
 358        return 0;
 359}
 360EXPORT_SYMBOL_GPL(genphy_c45_read_lpa);
 361
 362/**
 363 * genphy_c45_read_pma - read link speed etc from PMA
 364 * @phydev: target phy_device struct
 365 */
 366int genphy_c45_read_pma(struct phy_device *phydev)
 367{
 368        int val;
 369
 370        linkmode_zero(phydev->lp_advertising);
 371
 372        val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
 373        if (val < 0)
 374                return val;
 375
 376        switch (val & MDIO_CTRL1_SPEEDSEL) {
 377        case 0:
 378                phydev->speed = SPEED_10;
 379                break;
 380        case MDIO_PMA_CTRL1_SPEED100:
 381                phydev->speed = SPEED_100;
 382                break;
 383        case MDIO_PMA_CTRL1_SPEED1000:
 384                phydev->speed = SPEED_1000;
 385                break;
 386        case MDIO_CTRL1_SPEED2_5G:
 387                phydev->speed = SPEED_2500;
 388                break;
 389        case MDIO_CTRL1_SPEED5G:
 390                phydev->speed = SPEED_5000;
 391                break;
 392        case MDIO_CTRL1_SPEED10G:
 393                phydev->speed = SPEED_10000;
 394                break;
 395        default:
 396                phydev->speed = SPEED_UNKNOWN;
 397                break;
 398        }
 399
 400        phydev->duplex = DUPLEX_FULL;
 401
 402        return 0;
 403}
 404EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
 405
 406/**
 407 * genphy_c45_read_mdix - read mdix status from PMA
 408 * @phydev: target phy_device struct
 409 */
 410int genphy_c45_read_mdix(struct phy_device *phydev)
 411{
 412        int val;
 413
 414        if (phydev->speed == SPEED_10000) {
 415                val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
 416                                   MDIO_PMA_10GBT_SWAPPOL);
 417                if (val < 0)
 418                        return val;
 419
 420                switch (val) {
 421                case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
 422                        phydev->mdix = ETH_TP_MDI;
 423                        break;
 424
 425                case 0:
 426                        phydev->mdix = ETH_TP_MDI_X;
 427                        break;
 428
 429                default:
 430                        phydev->mdix = ETH_TP_MDI_INVALID;
 431                        break;
 432                }
 433        }
 434
 435        return 0;
 436}
 437EXPORT_SYMBOL_GPL(genphy_c45_read_mdix);
 438
 439/**
 440 * genphy_c45_pma_read_abilities - read supported link modes from PMA
 441 * @phydev: target phy_device struct
 442 *
 443 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
 444 * 1.8.9 is set, the list of supported modes is build using the values in the
 445 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
 446 * modes. If bit 1.11.14 is set, then the list is also extended with the modes
 447 * in the 2.5G/5G PMA Extended register (1.21), indicating if 2.5GBASET and
 448 * 5GBASET are supported.
 449 */
 450int genphy_c45_pma_read_abilities(struct phy_device *phydev)
 451{
 452        int val;
 453
 454        linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
 455        if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
 456                val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
 457                if (val < 0)
 458                        return val;
 459
 460                if (val & MDIO_AN_STAT1_ABLE)
 461                        linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
 462                                         phydev->supported);
 463        }
 464
 465        val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
 466        if (val < 0)
 467                return val;
 468
 469        linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 470                         phydev->supported,
 471                         val & MDIO_PMA_STAT2_10GBSR);
 472
 473        linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
 474                         phydev->supported,
 475                         val & MDIO_PMA_STAT2_10GBLR);
 476
 477        linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
 478                         phydev->supported,
 479                         val & MDIO_PMA_STAT2_10GBER);
 480
 481        if (val & MDIO_PMA_STAT2_EXTABLE) {
 482                val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
 483                if (val < 0)
 484                        return val;
 485
 486                linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
 487                                 phydev->supported,
 488                                 val & MDIO_PMA_EXTABLE_10GBLRM);
 489                linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 490                                 phydev->supported,
 491                                 val & MDIO_PMA_EXTABLE_10GBT);
 492                linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
 493                                 phydev->supported,
 494                                 val & MDIO_PMA_EXTABLE_10GBKX4);
 495                linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
 496                                 phydev->supported,
 497                                 val & MDIO_PMA_EXTABLE_10GBKR);
 498                linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 499                                 phydev->supported,
 500                                 val & MDIO_PMA_EXTABLE_1000BT);
 501                linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
 502                                 phydev->supported,
 503                                 val & MDIO_PMA_EXTABLE_1000BKX);
 504
 505                linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
 506                                 phydev->supported,
 507                                 val & MDIO_PMA_EXTABLE_100BTX);
 508                linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
 509                                 phydev->supported,
 510                                 val & MDIO_PMA_EXTABLE_100BTX);
 511
 512                linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
 513                                 phydev->supported,
 514                                 val & MDIO_PMA_EXTABLE_10BT);
 515                linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
 516                                 phydev->supported,
 517                                 val & MDIO_PMA_EXTABLE_10BT);
 518
 519                if (val & MDIO_PMA_EXTABLE_NBT) {
 520                        val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
 521                                           MDIO_PMA_NG_EXTABLE);
 522                        if (val < 0)
 523                                return val;
 524
 525                        linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 526                                         phydev->supported,
 527                                         val & MDIO_PMA_NG_EXTABLE_2_5GBT);
 528
 529                        linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 530                                         phydev->supported,
 531                                         val & MDIO_PMA_NG_EXTABLE_5GBT);
 532                }
 533        }
 534
 535        return 0;
 536}
 537EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
 538
 539/**
 540 * genphy_c45_read_status - read PHY status
 541 * @phydev: target phy_device struct
 542 *
 543 * Reads status from PHY and sets phy_device members accordingly.
 544 */
 545int genphy_c45_read_status(struct phy_device *phydev)
 546{
 547        int ret;
 548
 549        ret = genphy_c45_read_link(phydev);
 550        if (ret)
 551                return ret;
 552
 553        phydev->speed = SPEED_UNKNOWN;
 554        phydev->duplex = DUPLEX_UNKNOWN;
 555        phydev->pause = 0;
 556        phydev->asym_pause = 0;
 557
 558        if (phydev->autoneg == AUTONEG_ENABLE) {
 559                ret = genphy_c45_read_lpa(phydev);
 560                if (ret)
 561                        return ret;
 562
 563                phy_resolve_aneg_linkmode(phydev);
 564        } else {
 565                ret = genphy_c45_read_pma(phydev);
 566        }
 567
 568        return ret;
 569}
 570EXPORT_SYMBOL_GPL(genphy_c45_read_status);
 571
 572/**
 573 * genphy_c45_config_aneg - restart auto-negotiation or forced setup
 574 * @phydev: target phy_device struct
 575 *
 576 * Description: If auto-negotiation is enabled, we configure the
 577 *   advertising, and then restart auto-negotiation.  If it is not
 578 *   enabled, then we force a configuration.
 579 */
 580int genphy_c45_config_aneg(struct phy_device *phydev)
 581{
 582        bool changed = false;
 583        int ret;
 584
 585        if (phydev->autoneg == AUTONEG_DISABLE)
 586                return genphy_c45_pma_setup_forced(phydev);
 587
 588        ret = genphy_c45_an_config_aneg(phydev);
 589        if (ret < 0)
 590                return ret;
 591        if (ret > 0)
 592                changed = true;
 593
 594        return genphy_c45_check_and_restart_aneg(phydev, changed);
 595}
 596EXPORT_SYMBOL_GPL(genphy_c45_config_aneg);
 597
 598/* The gen10g_* functions are the old Clause 45 stub */
 599
 600int gen10g_config_aneg(struct phy_device *phydev)
 601{
 602        return 0;
 603}
 604EXPORT_SYMBOL_GPL(gen10g_config_aneg);
 605
 606int genphy_c45_loopback(struct phy_device *phydev, bool enable)
 607{
 608        return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
 609                              MDIO_PCS_CTRL1_LOOPBACK,
 610                              enable ? MDIO_PCS_CTRL1_LOOPBACK : 0);
 611}
 612EXPORT_SYMBOL_GPL(genphy_c45_loopback);
 613
 614struct phy_driver genphy_c45_driver = {
 615        .phy_id         = 0xffffffff,
 616        .phy_id_mask    = 0xffffffff,
 617        .name           = "Generic Clause 45 PHY",
 618        .read_status    = genphy_c45_read_status,
 619};
 620