linux/drivers/net/ethernet/xilinx/xilinx_axienet.h
<<
>>
Prefs
   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Definitions for Xilinx Axi Ethernet device driver.
   4 *
   5 * Copyright (c) 2009 Secret Lab Technologies, Ltd.
   6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
   7 */
   8
   9#ifndef XILINX_AXIENET_H
  10#define XILINX_AXIENET_H
  11
  12#include <linux/netdevice.h>
  13#include <linux/spinlock.h>
  14#include <linux/interrupt.h>
  15#include <linux/if_vlan.h>
  16#include <linux/phylink.h>
  17
  18/* Packet size info */
  19#define XAE_HDR_SIZE                    14 /* Size of Ethernet header */
  20#define XAE_TRL_SIZE                     4 /* Size of Ethernet trailer (FCS) */
  21#define XAE_MTU                       1500 /* Max MTU of an Ethernet frame */
  22#define XAE_JUMBO_MTU                 9000 /* Max MTU of a jumbo Eth. frame */
  23
  24#define XAE_MAX_FRAME_SIZE       (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
  25#define XAE_MAX_VLAN_FRAME_SIZE  (XAE_MTU + VLAN_ETH_HLEN + XAE_TRL_SIZE)
  26#define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
  27
  28/* Configuration options */
  29
  30/* Accept all incoming packets. Default: disabled (cleared) */
  31#define XAE_OPTION_PROMISC                      (1 << 0)
  32
  33/* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
  34#define XAE_OPTION_JUMBO                        (1 << 1)
  35
  36/* VLAN Rx & Tx frame support. Default: disabled (cleared) */
  37#define XAE_OPTION_VLAN                         (1 << 2)
  38
  39/* Enable recognition of flow control frames on Rx. Default: enabled (set) */
  40#define XAE_OPTION_FLOW_CONTROL                 (1 << 4)
  41
  42/* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
  43 * stripped. Default: disabled (set)
  44 */
  45#define XAE_OPTION_FCS_STRIP                    (1 << 5)
  46
  47/* Generate FCS field and add PAD automatically for outgoing frames.
  48 * Default: enabled (set)
  49 */
  50#define XAE_OPTION_FCS_INSERT                   (1 << 6)
  51
  52/* Enable Length/Type error checking for incoming frames. When this option is
  53 * set, the MAC will filter frames that have a mismatched type/length field
  54 * and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these
  55 * types of frames are encountered. When this option is cleared, the MAC will
  56 * allow these types of frames to be received. Default: enabled (set)
  57 */
  58#define XAE_OPTION_LENTYPE_ERR                  (1 << 7)
  59
  60/* Enable the transmitter. Default: enabled (set) */
  61#define XAE_OPTION_TXEN                         (1 << 11)
  62
  63/*  Enable the receiver. Default: enabled (set) */
  64#define XAE_OPTION_RXEN                         (1 << 12)
  65
  66/*  Default options set when device is initialized or reset */
  67#define XAE_OPTION_DEFAULTS                                \
  68                                (XAE_OPTION_TXEN |         \
  69                                 XAE_OPTION_FLOW_CONTROL | \
  70                                 XAE_OPTION_RXEN)
  71
  72/* Axi DMA Register definitions */
  73
  74#define XAXIDMA_TX_CR_OFFSET    0x00000000 /* Channel control */
  75#define XAXIDMA_TX_SR_OFFSET    0x00000004 /* Status */
  76#define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
  77#define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
  78
  79#define XAXIDMA_RX_CR_OFFSET    0x00000030 /* Channel control */
  80#define XAXIDMA_RX_SR_OFFSET    0x00000034 /* Status */
  81#define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
  82#define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
  83
  84#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
  85#define XAXIDMA_CR_RESET_MASK   0x00000004 /* Reset DMA engine */
  86
  87#define XAXIDMA_SR_HALT_MASK    0x00000001 /* Indicates DMA channel halted */
  88
  89#define XAXIDMA_BD_NDESC_OFFSET         0x00 /* Next descriptor pointer */
  90#define XAXIDMA_BD_BUFA_OFFSET          0x08 /* Buffer address */
  91#define XAXIDMA_BD_CTRL_LEN_OFFSET      0x18 /* Control/buffer length */
  92#define XAXIDMA_BD_STS_OFFSET           0x1C /* Status */
  93#define XAXIDMA_BD_USR0_OFFSET          0x20 /* User IP specific word0 */
  94#define XAXIDMA_BD_USR1_OFFSET          0x24 /* User IP specific word1 */
  95#define XAXIDMA_BD_USR2_OFFSET          0x28 /* User IP specific word2 */
  96#define XAXIDMA_BD_USR3_OFFSET          0x2C /* User IP specific word3 */
  97#define XAXIDMA_BD_USR4_OFFSET          0x30 /* User IP specific word4 */
  98#define XAXIDMA_BD_ID_OFFSET            0x34 /* Sw ID */
  99#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET  0x38 /* Whether has stscntrl strm */
 100#define XAXIDMA_BD_HAS_DRE_OFFSET       0x3C /* Whether has DRE */
 101
 102#define XAXIDMA_BD_HAS_DRE_SHIFT        8 /* Whether has DRE shift */
 103#define XAXIDMA_BD_HAS_DRE_MASK         0xF00 /* Whether has DRE mask */
 104#define XAXIDMA_BD_WORDLEN_MASK         0xFF /* Whether has DRE mask */
 105
 106#define XAXIDMA_BD_CTRL_LENGTH_MASK     0x007FFFFF /* Requested len */
 107#define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
 108#define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
 109#define XAXIDMA_BD_CTRL_ALL_MASK        0x0C000000 /* All control bits */
 110
 111#define XAXIDMA_DELAY_MASK              0xFF000000 /* Delay timeout counter */
 112#define XAXIDMA_COALESCE_MASK           0x00FF0000 /* Coalesce counter */
 113
 114#define XAXIDMA_DELAY_SHIFT             24
 115#define XAXIDMA_COALESCE_SHIFT          16
 116
 117#define XAXIDMA_IRQ_IOC_MASK            0x00001000 /* Completion intr */
 118#define XAXIDMA_IRQ_DELAY_MASK          0x00002000 /* Delay interrupt */
 119#define XAXIDMA_IRQ_ERROR_MASK          0x00004000 /* Error interrupt */
 120#define XAXIDMA_IRQ_ALL_MASK            0x00007000 /* All interrupts */
 121
 122/* Default TX/RX Threshold and waitbound values for SGDMA mode */
 123#define XAXIDMA_DFT_TX_THRESHOLD        24
 124#define XAXIDMA_DFT_TX_WAITBOUND        254
 125#define XAXIDMA_DFT_RX_THRESHOLD        24
 126#define XAXIDMA_DFT_RX_WAITBOUND        254
 127
 128#define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
 129#define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
 130#define XAXIDMA_BD_CTRL_ALL_MASK        0x0C000000 /* All control bits */
 131
 132#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK  0x007FFFFF /* Actual len */
 133#define XAXIDMA_BD_STS_COMPLETE_MASK    0x80000000 /* Completed */
 134#define XAXIDMA_BD_STS_DEC_ERR_MASK     0x40000000 /* Decode error */
 135#define XAXIDMA_BD_STS_SLV_ERR_MASK     0x20000000 /* Slave error */
 136#define XAXIDMA_BD_STS_INT_ERR_MASK     0x10000000 /* Internal err */
 137#define XAXIDMA_BD_STS_ALL_ERR_MASK     0x70000000 /* All errors */
 138#define XAXIDMA_BD_STS_RXSOF_MASK       0x08000000 /* First rx pkt */
 139#define XAXIDMA_BD_STS_RXEOF_MASK       0x04000000 /* Last rx pkt */
 140#define XAXIDMA_BD_STS_ALL_MASK         0xFC000000 /* All status bits */
 141
 142#define XAXIDMA_BD_MINIMUM_ALIGNMENT    0x40
 143
 144/* Axi Ethernet registers definition */
 145#define XAE_RAF_OFFSET          0x00000000 /* Reset and Address filter */
 146#define XAE_TPF_OFFSET          0x00000004 /* Tx Pause Frame */
 147#define XAE_IFGP_OFFSET         0x00000008 /* Tx Inter-frame gap adjustment*/
 148#define XAE_IS_OFFSET           0x0000000C /* Interrupt status */
 149#define XAE_IP_OFFSET           0x00000010 /* Interrupt pending */
 150#define XAE_IE_OFFSET           0x00000014 /* Interrupt enable */
 151#define XAE_TTAG_OFFSET         0x00000018 /* Tx VLAN TAG */
 152#define XAE_RTAG_OFFSET         0x0000001C /* Rx VLAN TAG */
 153#define XAE_UAWL_OFFSET         0x00000020 /* Unicast address word lower */
 154#define XAE_UAWU_OFFSET         0x00000024 /* Unicast address word upper */
 155#define XAE_TPID0_OFFSET        0x00000028 /* VLAN TPID0 register */
 156#define XAE_TPID1_OFFSET        0x0000002C /* VLAN TPID1 register */
 157#define XAE_PPST_OFFSET         0x00000030 /* PCS PMA Soft Temac Status Reg */
 158#define XAE_RCW0_OFFSET         0x00000400 /* Rx Configuration Word 0 */
 159#define XAE_RCW1_OFFSET         0x00000404 /* Rx Configuration Word 1 */
 160#define XAE_TC_OFFSET           0x00000408 /* Tx Configuration */
 161#define XAE_FCC_OFFSET          0x0000040C /* Flow Control Configuration */
 162#define XAE_EMMC_OFFSET         0x00000410 /* EMAC mode configuration */
 163#define XAE_PHYC_OFFSET         0x00000414 /* RGMII/SGMII configuration */
 164#define XAE_ID_OFFSET           0x000004F8 /* Identification register */
 165#define XAE_MDIO_MC_OFFSET      0x00000500 /* MII Management Config */
 166#define XAE_MDIO_MCR_OFFSET     0x00000504 /* MII Management Control */
 167#define XAE_MDIO_MWD_OFFSET     0x00000508 /* MII Management Write Data */
 168#define XAE_MDIO_MRD_OFFSET     0x0000050C /* MII Management Read Data */
 169#define XAE_UAW0_OFFSET         0x00000700 /* Unicast address word 0 */
 170#define XAE_UAW1_OFFSET         0x00000704 /* Unicast address word 1 */
 171#define XAE_FMI_OFFSET          0x00000708 /* Filter Mask Index */
 172#define XAE_AF0_OFFSET          0x00000710 /* Address Filter 0 */
 173#define XAE_AF1_OFFSET          0x00000714 /* Address Filter 1 */
 174
 175#define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
 176#define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
 177#define XAE_MCAST_TABLE_OFFSET  0x00020000 /* Multicast table address */
 178
 179/* Bit Masks for Axi Ethernet RAF register */
 180/* Reject receive multicast destination address */
 181#define XAE_RAF_MCSTREJ_MASK            0x00000002
 182/* Reject receive broadcast destination address */
 183#define XAE_RAF_BCSTREJ_MASK            0x00000004
 184#define XAE_RAF_TXVTAGMODE_MASK         0x00000018 /* Tx VLAN TAG mode */
 185#define XAE_RAF_RXVTAGMODE_MASK         0x00000060 /* Rx VLAN TAG mode */
 186#define XAE_RAF_TXVSTRPMODE_MASK        0x00000180 /* Tx VLAN STRIP mode */
 187#define XAE_RAF_RXVSTRPMODE_MASK        0x00000600 /* Rx VLAN STRIP mode */
 188#define XAE_RAF_NEWFNCENBL_MASK         0x00000800 /* New function mode */
 189/* Extended Multicast Filtering mode */
 190#define XAE_RAF_EMULTIFLTRENBL_MASK     0x00001000
 191#define XAE_RAF_STATSRST_MASK           0x00002000 /* Stats. Counter Reset */
 192#define XAE_RAF_RXBADFRMEN_MASK         0x00004000 /* Recv Bad Frame Enable */
 193#define XAE_RAF_TXVTAGMODE_SHIFT        3 /* Tx Tag mode shift bits */
 194#define XAE_RAF_RXVTAGMODE_SHIFT        5 /* Rx Tag mode shift bits */
 195#define XAE_RAF_TXVSTRPMODE_SHIFT       7 /* Tx strip mode shift bits*/
 196#define XAE_RAF_RXVSTRPMODE_SHIFT       9 /* Rx Strip mode shift bits*/
 197
 198/* Bit Masks for Axi Ethernet TPF and IFGP registers */
 199#define XAE_TPF_TPFV_MASK               0x0000FFFF /* Tx pause frame value */
 200/* Transmit inter-frame gap adjustment value */
 201#define XAE_IFGP0_IFGP_MASK             0x0000007F
 202
 203/* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
 204 * for all 3 registers.
 205 */
 206/* Hard register access complete */
 207#define XAE_INT_HARDACSCMPLT_MASK       0x00000001
 208/* Auto negotiation complete */
 209#define XAE_INT_AUTONEG_MASK            0x00000002
 210#define XAE_INT_RXCMPIT_MASK            0x00000004 /* Rx complete */
 211#define XAE_INT_RXRJECT_MASK            0x00000008 /* Rx frame rejected */
 212#define XAE_INT_RXFIFOOVR_MASK          0x00000010 /* Rx fifo overrun */
 213#define XAE_INT_TXCMPIT_MASK            0x00000020 /* Tx complete */
 214#define XAE_INT_RXDCMLOCK_MASK          0x00000040 /* Rx Dcm Lock */
 215#define XAE_INT_MGTRDY_MASK             0x00000080 /* MGT clock Lock */
 216#define XAE_INT_PHYRSTCMPLT_MASK        0x00000100 /* Phy Reset complete */
 217#define XAE_INT_ALL_MASK                0x0000003F /* All the ints */
 218
 219/* INT bits that indicate receive errors */
 220#define XAE_INT_RECV_ERROR_MASK                         \
 221        (XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK)
 222
 223/* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
 224#define XAE_TPID_0_MASK         0x0000FFFF /* TPID 0 */
 225#define XAE_TPID_1_MASK         0xFFFF0000 /* TPID 1 */
 226
 227/* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
 228#define XAE_TPID_2_MASK         0x0000FFFF /* TPID 0 */
 229#define XAE_TPID_3_MASK         0xFFFF0000 /* TPID 1 */
 230
 231/* Bit masks for Axi Ethernet RCW1 register */
 232#define XAE_RCW1_RST_MASK       0x80000000 /* Reset */
 233#define XAE_RCW1_JUM_MASK       0x40000000 /* Jumbo frame enable */
 234/* In-Band FCS enable (FCS not stripped) */
 235#define XAE_RCW1_FCS_MASK       0x20000000
 236#define XAE_RCW1_RX_MASK        0x10000000 /* Receiver enable */
 237#define XAE_RCW1_VLAN_MASK      0x08000000 /* VLAN frame enable */
 238/* Length/type field valid check disable */
 239#define XAE_RCW1_LT_DIS_MASK    0x02000000
 240/* Control frame Length check disable */
 241#define XAE_RCW1_CL_DIS_MASK    0x01000000
 242/* Pause frame source address bits [47:32]. Bits [31:0] are
 243 * stored in register RCW0
 244 */
 245#define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF
 246
 247/* Bit masks for Axi Ethernet TC register */
 248#define XAE_TC_RST_MASK         0x80000000 /* Reset */
 249#define XAE_TC_JUM_MASK         0x40000000 /* Jumbo frame enable */
 250/* In-Band FCS enable (FCS not generated) */
 251#define XAE_TC_FCS_MASK         0x20000000
 252#define XAE_TC_TX_MASK          0x10000000 /* Transmitter enable */
 253#define XAE_TC_VLAN_MASK        0x08000000 /* VLAN frame enable */
 254/* Inter-frame gap adjustment enable */
 255#define XAE_TC_IFG_MASK         0x02000000
 256
 257/* Bit masks for Axi Ethernet FCC register */
 258#define XAE_FCC_FCRX_MASK       0x20000000 /* Rx flow control enable */
 259#define XAE_FCC_FCTX_MASK       0x40000000 /* Tx flow control enable */
 260
 261/* Bit masks for Axi Ethernet EMMC register */
 262#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
 263#define XAE_EMMC_RGMII_MASK     0x20000000 /* RGMII mode enable */
 264#define XAE_EMMC_SGMII_MASK     0x10000000 /* SGMII mode enable */
 265#define XAE_EMMC_GPCS_MASK      0x08000000 /* 1000BaseX mode enable */
 266#define XAE_EMMC_HOST_MASK      0x04000000 /* Host interface enable */
 267#define XAE_EMMC_TX16BIT        0x02000000 /* 16 bit Tx client enable */
 268#define XAE_EMMC_RX16BIT        0x01000000 /* 16 bit Rx client enable */
 269#define XAE_EMMC_LINKSPD_10     0x00000000 /* Link Speed mask for 10 Mbit */
 270#define XAE_EMMC_LINKSPD_100    0x40000000 /* Link Speed mask for 100 Mbit */
 271#define XAE_EMMC_LINKSPD_1000   0x80000000 /* Link Speed mask for 1000 Mbit */
 272
 273/* Bit masks for Axi Ethernet PHYC register */
 274#define XAE_PHYC_SGMIILINKSPEED_MASK    0xC0000000 /* SGMII link speed mask*/
 275#define XAE_PHYC_RGMIILINKSPEED_MASK    0x0000000C /* RGMII link speed */
 276#define XAE_PHYC_RGMIIHD_MASK           0x00000002 /* RGMII Half-duplex */
 277#define XAE_PHYC_RGMIILINK_MASK         0x00000001 /* RGMII link status */
 278#define XAE_PHYC_RGLINKSPD_10           0x00000000 /* RGMII link 10 Mbit */
 279#define XAE_PHYC_RGLINKSPD_100          0x00000004 /* RGMII link 100 Mbit */
 280#define XAE_PHYC_RGLINKSPD_1000         0x00000008 /* RGMII link 1000 Mbit */
 281#define XAE_PHYC_SGLINKSPD_10           0x00000000 /* SGMII link 10 Mbit */
 282#define XAE_PHYC_SGLINKSPD_100          0x40000000 /* SGMII link 100 Mbit */
 283#define XAE_PHYC_SGLINKSPD_1000         0x80000000 /* SGMII link 1000 Mbit */
 284
 285/* Bit masks for Axi Ethernet MDIO interface MC register */
 286#define XAE_MDIO_MC_MDIOEN_MASK         0x00000040 /* MII management enable */
 287#define XAE_MDIO_MC_CLOCK_DIVIDE_MAX    0x3F       /* Maximum MDIO divisor */
 288
 289/* Bit masks for Axi Ethernet MDIO interface MCR register */
 290#define XAE_MDIO_MCR_PHYAD_MASK         0x1F000000 /* Phy Address Mask */
 291#define XAE_MDIO_MCR_PHYAD_SHIFT        24         /* Phy Address Shift */
 292#define XAE_MDIO_MCR_REGAD_MASK         0x001F0000 /* Reg Address Mask */
 293#define XAE_MDIO_MCR_REGAD_SHIFT        16         /* Reg Address Shift */
 294#define XAE_MDIO_MCR_OP_MASK            0x0000C000 /* Operation Code Mask */
 295#define XAE_MDIO_MCR_OP_SHIFT           13         /* Operation Code Shift */
 296#define XAE_MDIO_MCR_OP_READ_MASK       0x00008000 /* Op Code Read Mask */
 297#define XAE_MDIO_MCR_OP_WRITE_MASK      0x00004000 /* Op Code Write Mask */
 298#define XAE_MDIO_MCR_INITIATE_MASK      0x00000800 /* Ready Mask */
 299#define XAE_MDIO_MCR_READY_MASK         0x00000080 /* Ready Mask */
 300
 301/* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
 302#define XAE_MDIO_INT_MIIM_RDY_MASK      0x00000001 /* MIIM Interrupt */
 303
 304/* Bit masks for Axi Ethernet UAW1 register */
 305/* Station address bits [47:32]; Station address
 306 * bits [31:0] are stored in register UAW0
 307 */
 308#define XAE_UAW1_UNICASTADDR_MASK       0x0000FFFF
 309
 310/* Bit masks for Axi Ethernet FMI register */
 311#define XAE_FMI_PM_MASK                 0x80000000 /* Promis. mode enable */
 312#define XAE_FMI_IND_MASK                0x00000003 /* Index Mask */
 313
 314#define XAE_MDIO_DIV_DFT                29 /* Default MDIO clock divisor */
 315
 316/* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
 317#define XAE_PHY_TYPE_MII                0
 318#define XAE_PHY_TYPE_GMII               1
 319#define XAE_PHY_TYPE_RGMII_1_3          2
 320#define XAE_PHY_TYPE_RGMII_2_0          3
 321#define XAE_PHY_TYPE_SGMII              4
 322#define XAE_PHY_TYPE_1000BASE_X         5
 323
 324 /* Total number of entries in the hardware multicast table. */
 325#define XAE_MULTICAST_CAM_TABLE_NUM     4
 326
 327/* Axi Ethernet Synthesis features */
 328#define XAE_FEATURE_PARTIAL_RX_CSUM     (1 << 0)
 329#define XAE_FEATURE_PARTIAL_TX_CSUM     (1 << 1)
 330#define XAE_FEATURE_FULL_RX_CSUM        (1 << 2)
 331#define XAE_FEATURE_FULL_TX_CSUM        (1 << 3)
 332#define XAE_FEATURE_DMA_64BIT           (1 << 4)
 333
 334#define XAE_NO_CSUM_OFFLOAD             0
 335
 336#define XAE_FULL_CSUM_STATUS_MASK       0x00000038
 337#define XAE_IP_UDP_CSUM_VALIDATED       0x00000003
 338#define XAE_IP_TCP_CSUM_VALIDATED       0x00000002
 339
 340#define DELAY_OF_ONE_MILLISEC           1000
 341
 342/* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */
 343#define XLNX_MII_STD_SELECT_REG         0x11
 344#define XLNX_MII_STD_SELECT_SGMII       BIT(0)
 345
 346/**
 347 * struct axidma_bd - Axi Dma buffer descriptor layout
 348 * @next:         MM2S/S2MM Next Descriptor Pointer
 349 * @next_msb:     MM2S/S2MM Next Descriptor Pointer (high 32 bits)
 350 * @phys:         MM2S/S2MM Buffer Address
 351 * @phys_msb:     MM2S/S2MM Buffer Address (high 32 bits)
 352 * @reserved3:    Reserved and not used
 353 * @reserved4:    Reserved and not used
 354 * @cntrl:        MM2S/S2MM Control value
 355 * @status:       MM2S/S2MM Status value
 356 * @app0:         MM2S/S2MM User Application Field 0.
 357 * @app1:         MM2S/S2MM User Application Field 1.
 358 * @app2:         MM2S/S2MM User Application Field 2.
 359 * @app3:         MM2S/S2MM User Application Field 3.
 360 * @app4:         MM2S/S2MM User Application Field 4.
 361 */
 362struct axidma_bd {
 363        u32 next;       /* Physical address of next buffer descriptor */
 364        u32 next_msb;   /* high 32 bits for IP >= v7.1, reserved on older IP */
 365        u32 phys;
 366        u32 phys_msb;   /* for IP >= v7.1, reserved for older IP */
 367        u32 reserved3;
 368        u32 reserved4;
 369        u32 cntrl;
 370        u32 status;
 371        u32 app0;
 372        u32 app1;       /* TX start << 16 | insert */
 373        u32 app2;       /* TX csum seed */
 374        u32 app3;
 375        u32 app4;   /* Last field used by HW */
 376        struct sk_buff *skb;
 377} __aligned(XAXIDMA_BD_MINIMUM_ALIGNMENT);
 378
 379#define XAE_NUM_MISC_CLOCKS 3
 380
 381/**
 382 * struct axienet_local - axienet private per device data
 383 * @ndev:       Pointer for net_device to which it will be attached.
 384 * @dev:        Pointer to device structure
 385 * @phy_node:   Pointer to device node structure
 386 * @phylink:    Pointer to phylink instance
 387 * @phylink_config: phylink configuration settings
 388 * @pcs_phy:    Reference to PCS/PMA PHY if used
 389 * @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core
 390 * @axi_clk:    AXI4-Lite bus clock
 391 * @misc_clks:  Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
 392 * @mii_bus:    Pointer to MII bus structure
 393 * @mii_clk_div: MII bus clock divider value
 394 * @regs_start: Resource start for axienet device addresses
 395 * @regs:       Base address for the axienet_local device address space
 396 * @dma_regs:   Base address for the axidma device address space
 397 * @dma_err_task: Work structure to process Axi DMA errors
 398 * @tx_irq:     Axidma TX IRQ number
 399 * @rx_irq:     Axidma RX IRQ number
 400 * @eth_irq:    Ethernet core IRQ number
 401 * @phy_mode:   Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
 402 * @options:    AxiEthernet option word
 403 * @features:   Stores the extended features supported by the axienet hw
 404 * @tx_bd_v:    Virtual address of the TX buffer descriptor ring
 405 * @tx_bd_p:    Physical address(start address) of the TX buffer descr. ring
 406 * @tx_bd_num:  Size of TX buffer descriptor ring
 407 * @rx_bd_v:    Virtual address of the RX buffer descriptor ring
 408 * @rx_bd_p:    Physical address(start address) of the RX buffer descr. ring
 409 * @rx_bd_num:  Size of RX buffer descriptor ring
 410 * @tx_bd_ci:   Stores the index of the Tx buffer descriptor in the ring being
 411 *              accessed currently. Used while alloc. BDs before a TX starts
 412 * @tx_bd_tail: Stores the index of the Tx buffer descriptor in the ring being
 413 *              accessed currently. Used while processing BDs after the TX
 414 *              completed.
 415 * @rx_bd_ci:   Stores the index of the Rx buffer descriptor in the ring being
 416 *              accessed currently.
 417 * @max_frm_size: Stores the maximum size of the frame that can be that
 418 *                Txed/Rxed in the existing hardware. If jumbo option is
 419 *                supported, the maximum frame size would be 9k. Else it is
 420 *                1522 bytes (assuming support for basic VLAN)
 421 * @rxmem:      Stores rx memory size for jumbo frame handling.
 422 * @csum_offload_on_tx_path:    Stores the checksum selection on TX side.
 423 * @csum_offload_on_rx_path:    Stores the checksum selection on RX side.
 424 * @coalesce_count_rx:  Store the irq coalesce on RX side.
 425 * @coalesce_count_tx:  Store the irq coalesce on TX side.
 426 */
 427struct axienet_local {
 428        struct net_device *ndev;
 429        struct device *dev;
 430
 431        struct device_node *phy_node;
 432
 433        struct phylink *phylink;
 434        struct phylink_config phylink_config;
 435
 436        struct mdio_device *pcs_phy;
 437
 438        bool switch_x_sgmii;
 439
 440        struct clk *axi_clk;
 441        struct clk_bulk_data misc_clks[XAE_NUM_MISC_CLOCKS];
 442
 443        struct mii_bus *mii_bus;
 444        u8 mii_clk_div;
 445
 446        resource_size_t regs_start;
 447        void __iomem *regs;
 448        void __iomem *dma_regs;
 449
 450        struct work_struct dma_err_task;
 451
 452        int tx_irq;
 453        int rx_irq;
 454        int eth_irq;
 455        phy_interface_t phy_mode;
 456
 457        u32 options;
 458        u32 features;
 459
 460        struct axidma_bd *tx_bd_v;
 461        dma_addr_t tx_bd_p;
 462        u32 tx_bd_num;
 463        struct axidma_bd *rx_bd_v;
 464        dma_addr_t rx_bd_p;
 465        u32 rx_bd_num;
 466        u32 tx_bd_ci;
 467        u32 tx_bd_tail;
 468        u32 rx_bd_ci;
 469
 470        u32 max_frm_size;
 471        u32 rxmem;
 472
 473        int csum_offload_on_tx_path;
 474        int csum_offload_on_rx_path;
 475
 476        u32 coalesce_count_rx;
 477        u32 coalesce_count_tx;
 478};
 479
 480/**
 481 * struct axiethernet_option - Used to set axi ethernet hardware options
 482 * @opt:        Option to be set.
 483 * @reg:        Register offset to be written for setting the option
 484 * @m_or:       Mask to be ORed for setting the option in the register
 485 */
 486struct axienet_option {
 487        u32 opt;
 488        u32 reg;
 489        u32 m_or;
 490};
 491
 492/**
 493 * axienet_ior - Memory mapped Axi Ethernet register read
 494 * @lp:         Pointer to axienet local structure
 495 * @offset:     Address offset from the base address of Axi Ethernet core
 496 *
 497 * Return: The contents of the Axi Ethernet register
 498 *
 499 * This function returns the contents of the corresponding register.
 500 */
 501static inline u32 axienet_ior(struct axienet_local *lp, off_t offset)
 502{
 503        return ioread32(lp->regs + offset);
 504}
 505
 506static inline u32 axinet_ior_read_mcr(struct axienet_local *lp)
 507{
 508        return axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
 509}
 510
 511static inline void axienet_lock_mii(struct axienet_local *lp)
 512{
 513        if (lp->mii_bus)
 514                mutex_lock(&lp->mii_bus->mdio_lock);
 515}
 516
 517static inline void axienet_unlock_mii(struct axienet_local *lp)
 518{
 519        if (lp->mii_bus)
 520                mutex_unlock(&lp->mii_bus->mdio_lock);
 521}
 522
 523/**
 524 * axienet_iow - Memory mapped Axi Ethernet register write
 525 * @lp:         Pointer to axienet local structure
 526 * @offset:     Address offset from the base address of Axi Ethernet core
 527 * @value:      Value to be written into the Axi Ethernet register
 528 *
 529 * This function writes the desired value into the corresponding Axi Ethernet
 530 * register.
 531 */
 532static inline void axienet_iow(struct axienet_local *lp, off_t offset,
 533                               u32 value)
 534{
 535        iowrite32(value, lp->regs + offset);
 536}
 537
 538/* Function prototypes visible in xilinx_axienet_mdio.c for other files */
 539int axienet_mdio_enable(struct axienet_local *lp);
 540void axienet_mdio_disable(struct axienet_local *lp);
 541int axienet_mdio_setup(struct axienet_local *lp);
 542void axienet_mdio_teardown(struct axienet_local *lp);
 543
 544#endif /* XILINX_AXI_ENET_H */
 545
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.