linux/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (c) 2014-2015 Hisilicon Limited.
   4 */
   5
   6#include <linux/acpi.h>
   7#include <linux/device.h>
   8#include <linux/init.h>
   9#include <linux/interrupt.h>
  10#include <linux/kernel.h>
  11#include <linux/module.h>
  12#include <linux/netdevice.h>
  13#include <linux/mfd/syscon.h>
  14#include <linux/of.h>
  15#include <linux/of_address.h>
  16#include <linux/of_irq.h>
  17#include <linux/of_platform.h>
  18#include <linux/platform_device.h>
  19#include <linux/vmalloc.h>
  20
  21#include "hns_dsaf_mac.h"
  22#include "hns_dsaf_main.h"
  23#include "hns_dsaf_ppe.h"
  24#include "hns_dsaf_rcb.h"
  25#include "hns_dsaf_misc.h"
  26
  27static const char *g_dsaf_mode_match[DSAF_MODE_MAX] = {
  28        [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf",
  29        [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss",
  30        [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf",
  31        [DSAF_MODE_DISABLE_SP] = "single-port",
  32};
  33
  34static const struct acpi_device_id hns_dsaf_acpi_match[] = {
  35        { "HISI00B1", 0 },
  36        { "HISI00B2", 0 },
  37        { },
  38};
  39MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match);
  40
  41static int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev)
  42{
  43        int ret, i;
  44        u32 desc_num;
  45        u32 buf_size;
  46        u32 reset_offset = 0;
  47        u32 res_idx = 0;
  48        const char *mode_str;
  49        struct regmap *syscon;
  50        struct resource *res;
  51        struct device_node *np = dsaf_dev->dev->of_node, *np_temp;
  52        struct platform_device *pdev = to_platform_device(dsaf_dev->dev);
  53
  54        if (dev_of_node(dsaf_dev->dev)) {
  55                if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1"))
  56                        dsaf_dev->dsaf_ver = AE_VERSION_1;
  57                else
  58                        dsaf_dev->dsaf_ver = AE_VERSION_2;
  59        } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
  60                if (acpi_dev_found(hns_dsaf_acpi_match[0].id))
  61                        dsaf_dev->dsaf_ver = AE_VERSION_1;
  62                else if (acpi_dev_found(hns_dsaf_acpi_match[1].id))
  63                        dsaf_dev->dsaf_ver = AE_VERSION_2;
  64                else
  65                        return -ENXIO;
  66        } else {
  67                dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n");
  68                return -ENXIO;
  69        }
  70
  71        ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str);
  72        if (ret) {
  73                dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret);
  74                return ret;
  75        }
  76        for (i = 0; i < DSAF_MODE_MAX; i++) {
  77                if (g_dsaf_mode_match[i] &&
  78                    !strcmp(mode_str, g_dsaf_mode_match[i]))
  79                        break;
  80        }
  81        if (i >= DSAF_MODE_MAX ||
  82            i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) {
  83                dev_err(dsaf_dev->dev,
  84                        "%s prs mode str fail!\n", dsaf_dev->ae_dev.name);
  85                return -EINVAL;
  86        }
  87        dsaf_dev->dsaf_mode = (enum dsaf_mode)i;
  88
  89        if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE)
  90                dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE;
  91        else
  92                dsaf_dev->dsaf_en = HRD_DSAF_MODE;
  93
  94        if ((i == DSAF_MODE_ENABLE_16VM) ||
  95            (i == DSAF_MODE_DISABLE_2PORT_8VM) ||
  96            (i == DSAF_MODE_DISABLE_6PORT_2VM))
  97                dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE;
  98        else
  99                dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE;
 100
 101        if (dev_of_node(dsaf_dev->dev)) {
 102                np_temp = of_parse_phandle(np, "subctrl-syscon", 0);
 103                syscon = syscon_node_to_regmap(np_temp);
 104                of_node_put(np_temp);
 105                if (IS_ERR_OR_NULL(syscon)) {
 106                        res = platform_get_resource(pdev, IORESOURCE_MEM,
 107                                                    res_idx++);
 108                        if (!res) {
 109                                dev_err(dsaf_dev->dev, "subctrl info is needed!\n");
 110                                return -ENOMEM;
 111                        }
 112
 113                        dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev,
 114                                                                  res);
 115                        if (IS_ERR(dsaf_dev->sc_base))
 116                                return PTR_ERR(dsaf_dev->sc_base);
 117
 118                        res = platform_get_resource(pdev, IORESOURCE_MEM,
 119                                                    res_idx++);
 120                        if (!res) {
 121                                dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n");
 122                                return -ENOMEM;
 123                        }
 124
 125                        dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev,
 126                                                                   res);
 127                        if (IS_ERR(dsaf_dev->sds_base))
 128                                return PTR_ERR(dsaf_dev->sds_base);
 129                } else {
 130                        dsaf_dev->sub_ctrl = syscon;
 131                }
 132        }
 133
 134        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base");
 135        if (!res) {
 136                res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++);
 137                if (!res) {
 138                        dev_err(dsaf_dev->dev, "ppe-base info is needed!\n");
 139                        return -ENOMEM;
 140                }
 141        }
 142        dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res);
 143        if (IS_ERR(dsaf_dev->ppe_base))
 144                return PTR_ERR(dsaf_dev->ppe_base);
 145        dsaf_dev->ppe_paddr = res->start;
 146
 147        if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
 148                res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 149                                                   "dsaf-base");
 150                if (!res) {
 151                        res = platform_get_resource(pdev, IORESOURCE_MEM,
 152                                                    res_idx);
 153                        if (!res) {
 154                                dev_err(dsaf_dev->dev,
 155                                        "dsaf-base info is needed!\n");
 156                                return -ENOMEM;
 157                        }
 158                }
 159                dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res);
 160                if (IS_ERR(dsaf_dev->io_base))
 161                        return PTR_ERR(dsaf_dev->io_base);
 162        }
 163
 164        ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num);
 165        if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT ||
 166            desc_num > HNS_DSAF_MAX_DESC_CNT) {
 167                dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n",
 168                        desc_num, ret);
 169                return -EINVAL;
 170        }
 171        dsaf_dev->desc_num = desc_num;
 172
 173        ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset",
 174                                       &reset_offset);
 175        if (ret < 0) {
 176                dev_dbg(dsaf_dev->dev,
 177                        "get reset-field-offset fail, ret=%d!\r\n", ret);
 178        }
 179        dsaf_dev->reset_offset = reset_offset;
 180
 181        ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size);
 182        if (ret < 0) {
 183                dev_err(dsaf_dev->dev,
 184                        "get buf-size fail, ret=%d!\r\n", ret);
 185                return ret;
 186        }
 187        dsaf_dev->buf_size = buf_size;
 188
 189        dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size);
 190        if (dsaf_dev->buf_size_type < 0) {
 191                dev_err(dsaf_dev->dev,
 192                        "buf_size(%d) is wrong!\n", buf_size);
 193                return -EINVAL;
 194        }
 195
 196        dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev);
 197        if (!dsaf_dev->misc_op)
 198                return -ENOMEM;
 199
 200        if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL)))
 201                dev_dbg(dsaf_dev->dev, "set mask to 64bit\n");
 202        else
 203                dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n");
 204
 205        return 0;
 206}
 207
 208/**
 209 * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en
 210 * @dsaf_dev: dsa fabric id
 211 */
 212static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev)
 213{
 214        dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
 215}
 216
 217/**
 218 * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce
 219 * @dsaf_dev: dsa fabric id
 220 * @reg_cnt_clr_ce: config value
 221 */
 222static void
 223hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce)
 224{
 225        dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
 226                         DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce);
 227}
 228
 229/**
 230 * hns_dsaf_ppe_qid_cfg - config ppe qid
 231 * @dsaf_dev: dsa fabric id
 232 * @qid_cfg: value array
 233 */
 234static void
 235hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg)
 236{
 237        u32 i;
 238
 239        for (i = 0; i < DSAF_COMM_CHN; i++) {
 240                dsaf_set_dev_field(dsaf_dev,
 241                                   DSAF_PPE_QID_CFG_0_REG + 0x0004 * i,
 242                                   DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S,
 243                                   qid_cfg);
 244        }
 245}
 246
 247static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev)
 248{
 249        u16 max_q_per_vf, max_vfn;
 250        u32 q_id, q_num_per_port;
 251        u32 i;
 252
 253        hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 254        q_num_per_port = max_vfn * max_q_per_vf;
 255
 256        for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) {
 257                dsaf_set_dev_field(dsaf_dev,
 258                                   DSAF_MIX_DEF_QID_0_REG + 0x0004 * i,
 259                                   0xff, 0, q_id);
 260                q_id += q_num_per_port;
 261        }
 262}
 263
 264static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev)
 265{
 266        u16 max_q_per_vf, max_vfn;
 267        u32 q_id, q_num_per_port;
 268        u32 mac_id;
 269
 270        if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 271                return;
 272
 273        hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 274        q_num_per_port = max_vfn * max_q_per_vf;
 275
 276        for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) {
 277                dsaf_set_dev_field(dsaf_dev,
 278                                   DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
 279                                   DSAFV2_SERDES_LBK_QID_M,
 280                                   DSAFV2_SERDES_LBK_QID_S,
 281                                   q_id);
 282                q_id += q_num_per_port;
 283        }
 284}
 285
 286/**
 287 * hns_dsaf_sw_port_type_cfg - cfg sw type
 288 * @dsaf_dev: dsa fabric id
 289 * @port_type: array
 290 */
 291static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev,
 292                                      enum dsaf_sw_port_type port_type)
 293{
 294        u32 i;
 295
 296        for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
 297                dsaf_set_dev_field(dsaf_dev,
 298                                   DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i,
 299                                   DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S,
 300                                   port_type);
 301        }
 302}
 303
 304/**
 305 * hns_dsaf_stp_port_type_cfg - cfg stp type
 306 * @dsaf_dev: dsa fabric id
 307 * @port_type: array
 308 */
 309static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev,
 310                                       enum dsaf_stp_port_type port_type)
 311{
 312        u32 i;
 313
 314        for (i = 0; i < DSAF_COMM_CHN; i++) {
 315                dsaf_set_dev_field(dsaf_dev,
 316                                   DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i,
 317                                   DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S,
 318                                   port_type);
 319        }
 320}
 321
 322#define HNS_DSAF_SBM_NUM(dev) \
 323        (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM)
 324/**
 325 * hns_dsaf_sbm_cfg - config sbm
 326 * @dsaf_dev: dsa fabric id
 327 */
 328static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev)
 329{
 330        u32 o_sbm_cfg;
 331        u32 i;
 332
 333        for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 334                o_sbm_cfg = dsaf_read_dev(dsaf_dev,
 335                                          DSAF_SBM_CFG_REG_0_REG + 0x80 * i);
 336                dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1);
 337                dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0);
 338                dsaf_write_dev(dsaf_dev,
 339                               DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg);
 340        }
 341}
 342
 343/**
 344 * hns_dsaf_sbm_cfg_mib_en - config sbm
 345 * @dsaf_dev: dsa fabric id
 346 */
 347static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev)
 348{
 349        u32 sbm_cfg_mib_en;
 350        u32 i;
 351        u32 reg;
 352        u32 read_cnt;
 353
 354        /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */
 355        for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 356                reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 357                dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
 358        }
 359
 360        for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 361                reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 362                dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
 363        }
 364
 365        /* waitint for all sbm enable finished */
 366        for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 367                read_cnt = 0;
 368                reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 369                do {
 370                        udelay(1);
 371                        sbm_cfg_mib_en = dsaf_get_dev_bit(
 372                                        dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S);
 373                        read_cnt++;
 374                } while (sbm_cfg_mib_en == 0 &&
 375                        read_cnt < DSAF_CFG_READ_CNT);
 376
 377                if (sbm_cfg_mib_en == 0) {
 378                        dev_err(dsaf_dev->dev,
 379                                "sbm_cfg_mib_en fail,%s,sbm_num=%d\n",
 380                                dsaf_dev->ae_dev.name, i);
 381                        return -ENODEV;
 382                }
 383        }
 384
 385        return 0;
 386}
 387
 388/**
 389 * hns_dsaf_sbm_bp_wl_cfg - config sbm
 390 * @dsaf_dev: dsa fabric id
 391 */
 392static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 393{
 394        u32 o_sbm_bp_cfg;
 395        u32 reg;
 396        u32 i;
 397
 398        /* XGE */
 399        for (i = 0; i < DSAF_XGE_NUM; i++) {
 400                reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 401                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 402                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
 403                               DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512);
 404                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 405                               DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 406                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 407                               DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 408                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 409
 410                reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 411                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 412                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 413                               DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 414                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 415                               DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 416                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 417
 418                reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 419                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 420                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 421                               DSAF_SBM_CFG2_SET_BUF_NUM_S, 104);
 422                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 423                               DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128);
 424                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 425
 426                reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 427                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 428                dsaf_set_field(o_sbm_bp_cfg,
 429                               DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 430                               DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
 431                dsaf_set_field(o_sbm_bp_cfg,
 432                               DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 433                               DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
 434                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 435
 436                /* for no enable pfc mode */
 437                reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 438                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 439                dsaf_set_field(o_sbm_bp_cfg,
 440                               DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 441                               DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128);
 442                dsaf_set_field(o_sbm_bp_cfg,
 443                               DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 444                               DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192);
 445                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 446        }
 447
 448        /* PPE */
 449        for (i = 0; i < DSAF_COMM_CHN; i++) {
 450                reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 451                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 452                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 453                               DSAF_SBM_CFG2_SET_BUF_NUM_S, 10);
 454                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 455                               DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12);
 456                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 457        }
 458
 459        /* RoCEE */
 460        for (i = 0; i < DSAF_COMM_CHN; i++) {
 461                reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 462                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 463                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 464                               DSAF_SBM_CFG2_SET_BUF_NUM_S, 2);
 465                dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 466                               DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4);
 467                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 468        }
 469}
 470
 471static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 472{
 473        u32 o_sbm_bp_cfg;
 474        u32 reg;
 475        u32 i;
 476
 477        /* XGE */
 478        for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) {
 479                reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 480                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 481                dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
 482                               DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256);
 483                dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 484                               DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 485                dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 486                               DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 487                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 488
 489                reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 490                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 491                dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 492                               DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 493                dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 494                               DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 495                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 496
 497                reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 498                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 499                dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
 500                               DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104);
 501                dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
 502                               DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128);
 503                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 504
 505                reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 506                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 507                dsaf_set_field(o_sbm_bp_cfg,
 508                               DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 509                               DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 55);
 510                dsaf_set_field(o_sbm_bp_cfg,
 511                               DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 512                               DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 110);
 513                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 514
 515                /* for no enable pfc mode */
 516                reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 517                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 518                dsaf_set_field(o_sbm_bp_cfg,
 519                               DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M,
 520                               DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 128);
 521                dsaf_set_field(o_sbm_bp_cfg,
 522                               DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M,
 523                               DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 192);
 524                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 525        }
 526
 527        /* PPE */
 528        for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) {
 529                reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 530                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 531                dsaf_set_field(o_sbm_bp_cfg,
 532                               DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M,
 533                               DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2);
 534                dsaf_set_field(o_sbm_bp_cfg,
 535                               DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M,
 536                               DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3);
 537                dsaf_set_field(o_sbm_bp_cfg,
 538                               DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M,
 539                               DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52);
 540                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 541        }
 542
 543        /* RoCEE */
 544        for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) {
 545                reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 546                o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 547                dsaf_set_field(o_sbm_bp_cfg,
 548                               DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M,
 549                               DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2);
 550                dsaf_set_field(o_sbm_bp_cfg,
 551                               DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M,
 552                               DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4);
 553                dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 554        }
 555}
 556
 557/**
 558 * hns_dsaf_voq_bp_all_thrd_cfg -  voq
 559 * @dsaf_dev: dsa fabric id
 560 */
 561static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev)
 562{
 563        u32 voq_bp_all_thrd;
 564        u32 i;
 565
 566        for (i = 0; i < DSAF_VOQ_NUM; i++) {
 567                voq_bp_all_thrd = dsaf_read_dev(
 568                        dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i);
 569                if (i < DSAF_XGE_NUM) {
 570                        dsaf_set_field(voq_bp_all_thrd,
 571                                       DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 572                                       DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930);
 573                        dsaf_set_field(voq_bp_all_thrd,
 574                                       DSAF_VOQ_BP_ALL_UPTHRD_M,
 575                                       DSAF_VOQ_BP_ALL_UPTHRD_S, 950);
 576                } else {
 577                        dsaf_set_field(voq_bp_all_thrd,
 578                                       DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 579                                       DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220);
 580                        dsaf_set_field(voq_bp_all_thrd,
 581                                       DSAF_VOQ_BP_ALL_UPTHRD_M,
 582                                       DSAF_VOQ_BP_ALL_UPTHRD_S, 230);
 583                }
 584                dsaf_write_dev(
 585                        dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i,
 586                        voq_bp_all_thrd);
 587        }
 588}
 589
 590static void hns_dsaf_tbl_tcam_match_cfg(
 591        struct dsaf_device *dsaf_dev,
 592        struct dsaf_tbl_tcam_data *ptbl_tcam_data)
 593{
 594        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_L_REG,
 595                       ptbl_tcam_data->tbl_tcam_data_low);
 596        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_H_REG,
 597                       ptbl_tcam_data->tbl_tcam_data_high);
 598}
 599
 600/**
 601 * hns_dsaf_tbl_tcam_data_cfg - tbl
 602 * @dsaf_dev: dsa fabric id
 603 * @ptbl_tcam_data: addr
 604 */
 605static void hns_dsaf_tbl_tcam_data_cfg(
 606        struct dsaf_device *dsaf_dev,
 607        struct dsaf_tbl_tcam_data *ptbl_tcam_data)
 608{
 609        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
 610                       ptbl_tcam_data->tbl_tcam_data_low);
 611        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
 612                       ptbl_tcam_data->tbl_tcam_data_high);
 613}
 614
 615/**
 616 * hns_dsaf_tbl_tcam_mcast_cfg - tbl
 617 * @dsaf_dev: dsa fabric id
 618 * @mcast: addr
 619 */
 620static void hns_dsaf_tbl_tcam_mcast_cfg(
 621        struct dsaf_device *dsaf_dev,
 622        struct dsaf_tbl_tcam_mcast_cfg *mcast)
 623{
 624        u32 mcast_cfg4;
 625
 626        mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
 627        dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S,
 628                     mcast->tbl_mcast_item_vld);
 629        dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S,
 630                     mcast->tbl_mcast_old_en);
 631        dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
 632                       DSAF_TBL_MCAST_CFG4_VM128_112_S,
 633                       mcast->tbl_mcast_port_msk[4]);
 634        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
 635
 636        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
 637                       mcast->tbl_mcast_port_msk[3]);
 638
 639        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
 640                       mcast->tbl_mcast_port_msk[2]);
 641
 642        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
 643                       mcast->tbl_mcast_port_msk[1]);
 644
 645        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
 646                       mcast->tbl_mcast_port_msk[0]);
 647}
 648
 649/**
 650 * hns_dsaf_tbl_tcam_ucast_cfg - tbl
 651 * @dsaf_dev: dsa fabric id
 652 * @tbl_tcam_ucast: addr
 653 */
 654static void hns_dsaf_tbl_tcam_ucast_cfg(
 655        struct dsaf_device *dsaf_dev,
 656        struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast)
 657{
 658        u32 ucast_cfg1;
 659
 660        ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
 661        dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S,
 662                     tbl_tcam_ucast->tbl_ucast_mac_discard);
 663        dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S,
 664                     tbl_tcam_ucast->tbl_ucast_item_vld);
 665        dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S,
 666                     tbl_tcam_ucast->tbl_ucast_old_en);
 667        dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S,
 668                     tbl_tcam_ucast->tbl_ucast_dvc);
 669        dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
 670                       DSAF_TBL_UCAST_CFG1_OUT_PORT_S,
 671                       tbl_tcam_ucast->tbl_ucast_out_port);
 672        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
 673}
 674
 675/**
 676 * hns_dsaf_tbl_line_cfg - tbl
 677 * @dsaf_dev: dsa fabric id
 678 * @tbl_lin: addr
 679 */
 680static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev,
 681                                  struct dsaf_tbl_line_cfg *tbl_lin)
 682{
 683        u32 tbl_line;
 684
 685        tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG);
 686        dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S,
 687                     tbl_lin->tbl_line_mac_discard);
 688        dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S,
 689                     tbl_lin->tbl_line_dvc);
 690        dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
 691                       DSAF_TBL_LINE_CFG_OUT_PORT_S,
 692                       tbl_lin->tbl_line_out_port);
 693        dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
 694}
 695
 696/**
 697 * hns_dsaf_tbl_tcam_mcast_pul - tbl
 698 * @dsaf_dev: dsa fabric id
 699 */
 700static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev)
 701{
 702        u32 o_tbl_pul;
 703
 704        o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 705        dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 706        dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 707        dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 708        dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 709}
 710
 711/**
 712 * hns_dsaf_tbl_line_pul - tbl
 713 * @dsaf_dev: dsa fabric id
 714 */
 715static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev)
 716{
 717        u32 tbl_pul;
 718
 719        tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 720        dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1);
 721        dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 722        dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0);
 723        dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 724}
 725
 726/**
 727 * hns_dsaf_tbl_tcam_data_mcast_pul - tbl
 728 * @dsaf_dev: dsa fabric id
 729 */
 730static void hns_dsaf_tbl_tcam_data_mcast_pul(
 731        struct dsaf_device *dsaf_dev)
 732{
 733        u32 o_tbl_pul;
 734
 735        o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 736        dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 737        dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 738        dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 739        dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 740        dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 741        dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 742}
 743
 744/**
 745 * hns_dsaf_tbl_tcam_data_ucast_pul - tbl
 746 * @dsaf_dev: dsa fabric id
 747 */
 748static void hns_dsaf_tbl_tcam_data_ucast_pul(
 749        struct dsaf_device *dsaf_dev)
 750{
 751        u32 o_tbl_pul;
 752
 753        o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 754        dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 755        dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1);
 756        dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 757        dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 758        dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0);
 759        dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 760}
 761
 762void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en)
 763{
 764        if (AE_IS_VER1(dsaf_dev->dsaf_ver) && !HNS_DSAF_IS_DEBUG(dsaf_dev))
 765                dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG,
 766                                 DSAF_CFG_MIX_MODE_S, !!en);
 767}
 768
 769/**
 770 * hns_dsaf_tbl_stat_en - tbl
 771 * @dsaf_dev: dsa fabric id
 772 */
 773static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev)
 774{
 775        u32 o_tbl_ctrl;
 776
 777        o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG);
 778        dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1);
 779        dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1);
 780        dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1);
 781        dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1);
 782        dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
 783}
 784
 785/**
 786 * hns_dsaf_rocee_bp_en - rocee back press enable
 787 * @dsaf_dev: dsa fabric id
 788 */
 789static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
 790{
 791        if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 792                dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
 793                                 DSAF_FC_XGE_TX_PAUSE_S, 1);
 794}
 795
 796/* set msk for dsaf exception irq*/
 797static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev,
 798                                     u32 chnn_num, u32 mask_set)
 799{
 800        dsaf_write_dev(dsaf_dev,
 801                       DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set);
 802}
 803
 804static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev,
 805                                     u32 chnn_num, u32 msk_set)
 806{
 807        dsaf_write_dev(dsaf_dev,
 808                       DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set);
 809}
 810
 811static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev,
 812                                       u32 chnn, u32 msk_set)
 813{
 814        dsaf_write_dev(dsaf_dev,
 815                       DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set);
 816}
 817
 818static void
 819hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set)
 820{
 821        dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
 822}
 823
 824/* clr dsaf exception irq*/
 825static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev,
 826                                     u32 chnn_num, u32 int_src)
 827{
 828        dsaf_write_dev(dsaf_dev,
 829                       DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src);
 830}
 831
 832static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev,
 833                                     u32 chnn, u32 int_src)
 834{
 835        dsaf_write_dev(dsaf_dev,
 836                       DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 837}
 838
 839static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev,
 840                                       u32 chnn, u32 int_src)
 841{
 842        dsaf_write_dev(dsaf_dev,
 843                       DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 844}
 845
 846static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev,
 847                                     u32 int_src)
 848{
 849        dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
 850}
 851
 852/**
 853 * hns_dsaf_single_line_tbl_cfg - INT
 854 * @dsaf_dev: dsa fabric id
 855 * @address: the address
 856 * @ptbl_line: the line
 857 */
 858static void hns_dsaf_single_line_tbl_cfg(
 859        struct dsaf_device *dsaf_dev,
 860        u32 address, struct dsaf_tbl_line_cfg *ptbl_line)
 861{
 862        spin_lock_bh(&dsaf_dev->tcam_lock);
 863
 864        /*Write Addr*/
 865        hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address);
 866
 867        /*Write Line*/
 868        hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line);
 869
 870        /*Write Plus*/
 871        hns_dsaf_tbl_line_pul(dsaf_dev);
 872
 873        spin_unlock_bh(&dsaf_dev->tcam_lock);
 874}
 875
 876/**
 877 * hns_dsaf_tcam_uc_cfg - INT
 878 * @dsaf_dev: dsa fabric id
 879 * @address: the address
 880 * @ptbl_tcam_data: the data
 881 * @ptbl_tcam_ucast: unicast
 882 */
 883static void hns_dsaf_tcam_uc_cfg(
 884        struct dsaf_device *dsaf_dev, u32 address,
 885        struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 886        struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
 887{
 888        spin_lock_bh(&dsaf_dev->tcam_lock);
 889
 890        /*Write Addr*/
 891        hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 892        /*Write Tcam Data*/
 893        hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 894        /*Write Tcam Ucast*/
 895        hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast);
 896        /*Write Plus*/
 897        hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
 898
 899        spin_unlock_bh(&dsaf_dev->tcam_lock);
 900}
 901
 902/**
 903 * hns_dsaf_tcam_mc_cfg - cfg the tcam for mc
 904 * @dsaf_dev: dsa fabric device struct pointer
 905 * @address: tcam index
 906 * @ptbl_tcam_data: tcam data struct pointer
 907 * @ptbl_tcam_mask: tcam mask struct pointer, it must be null for HNSv1
 908 * @ptbl_tcam_mcast: tcam data struct pointer
 909 */
 910static void hns_dsaf_tcam_mc_cfg(
 911        struct dsaf_device *dsaf_dev, u32 address,
 912        struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 913        struct dsaf_tbl_tcam_data *ptbl_tcam_mask,
 914        struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
 915{
 916        spin_lock_bh(&dsaf_dev->tcam_lock);
 917
 918        /*Write Addr*/
 919        hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 920        /*Write Tcam Data*/
 921        hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 922        /*Write Tcam Mcast*/
 923        hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast);
 924        /* Write Match Data */
 925        if (ptbl_tcam_mask)
 926                hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, ptbl_tcam_mask);
 927
 928        /* Write Puls */
 929        hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
 930
 931        spin_unlock_bh(&dsaf_dev->tcam_lock);
 932}
 933
 934/**
 935 * hns_dsaf_tcam_uc_cfg_vague - INT
 936 * @dsaf_dev: dsa fabric device struct pointer
 937 * @address: the address
 938 * @tcam_data: the data
 939 * @tcam_mask: the mask
 940 * @tcam_uc: the unicast data
 941 */
 942static void hns_dsaf_tcam_uc_cfg_vague(struct dsaf_device *dsaf_dev,
 943                                       u32 address,
 944                                       struct dsaf_tbl_tcam_data *tcam_data,
 945                                       struct dsaf_tbl_tcam_data *tcam_mask,
 946                                       struct dsaf_tbl_tcam_ucast_cfg *tcam_uc)
 947{
 948        spin_lock_bh(&dsaf_dev->tcam_lock);
 949        hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 950        hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, tcam_data);
 951        hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, tcam_uc);
 952        hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 953        hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
 954
 955        /*Restore Match Data*/
 956        tcam_mask->tbl_tcam_data_high = 0xffffffff;
 957        tcam_mask->tbl_tcam_data_low = 0xffffffff;
 958        hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 959
 960        spin_unlock_bh(&dsaf_dev->tcam_lock);
 961}
 962
 963/**
 964 * hns_dsaf_tcam_mc_cfg_vague - INT
 965 * @dsaf_dev: dsa fabric device struct pointer
 966 * @address: the address
 967 * @tcam_data: the data
 968 * @tcam_mask: the mask
 969 * @tcam_mc: the multicast data
 970 */
 971static void hns_dsaf_tcam_mc_cfg_vague(struct dsaf_device *dsaf_dev,
 972                                       u32 address,
 973                                       struct dsaf_tbl_tcam_data *tcam_data,
 974                                       struct dsaf_tbl_tcam_data *tcam_mask,
 975                                       struct dsaf_tbl_tcam_mcast_cfg *tcam_mc)
 976{
 977        spin_lock_bh(&dsaf_dev->tcam_lock);
 978        hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 979        hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, tcam_data);
 980        hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, tcam_mc);
 981        hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 982        hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
 983
 984        /*Restore Match Data*/
 985        tcam_mask->tbl_tcam_data_high = 0xffffffff;
 986        tcam_mask->tbl_tcam_data_low = 0xffffffff;
 987        hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 988
 989        spin_unlock_bh(&dsaf_dev->tcam_lock);
 990}
 991
 992/**
 993 * hns_dsaf_tcam_mc_invld - INT
 994 * @dsaf_dev: dsa fabric id
 995 * @address: the address
 996 */
 997static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address)
 998{
 999        spin_lock_bh(&dsaf_dev->tcam_lock);
1000
1001        /*Write Addr*/
1002        hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1003
1004        /*write tcam mcast*/
1005        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
1006        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
1007        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
1008        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
1009        dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
1010
1011        /*Write Plus*/
1012        hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev);
1013
1014        spin_unlock_bh(&dsaf_dev->tcam_lock);
1015}
1016
1017static void
1018hns_dsaf_tcam_addr_get(struct dsaf_drv_tbl_tcam_key *mac_key, u8 *addr)
1019{
1020        addr[0] = mac_key->high.bits.mac_0;
1021        addr[1] = mac_key->high.bits.mac_1;
1022        addr[2] = mac_key->high.bits.mac_2;
1023        addr[3] = mac_key->high.bits.mac_3;
1024        addr[4] = mac_key->low.bits.mac_4;
1025        addr[5] = mac_key->low.bits.mac_5;
1026}
1027
1028/**
1029 * hns_dsaf_tcam_uc_get - INT
1030 * @dsaf_dev: dsa fabric id
1031 * @address: the address
1032 * @ptbl_tcam_data: the data
1033 * @ptbl_tcam_ucast: unicast
1034 */
1035static void hns_dsaf_tcam_uc_get(
1036        struct dsaf_device *dsaf_dev, u32 address,
1037        struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1038        struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
1039{
1040        u32 tcam_read_data0;
1041        u32 tcam_read_data4;
1042
1043        spin_lock_bh(&dsaf_dev->tcam_lock);
1044
1045        /*Write Addr*/
1046        hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1047
1048        /*read tcam item puls*/
1049        hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1050
1051        /*read tcam data*/
1052        ptbl_tcam_data->tbl_tcam_data_high
1053                = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1054        ptbl_tcam_data->tbl_tcam_data_low
1055                = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1056
1057        /*read tcam mcast*/
1058        tcam_read_data0 = dsaf_read_dev(dsaf_dev,
1059                                        DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1060        tcam_read_data4 = dsaf_read_dev(dsaf_dev,
1061                                        DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1062
1063        ptbl_tcam_ucast->tbl_ucast_item_vld
1064                = dsaf_get_bit(tcam_read_data4,
1065                               DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1066        ptbl_tcam_ucast->tbl_ucast_old_en
1067                = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1068        ptbl_tcam_ucast->tbl_ucast_mac_discard
1069                = dsaf_get_bit(tcam_read_data0,
1070                               DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S);
1071        ptbl_tcam_ucast->tbl_ucast_out_port
1072                = dsaf_get_field(tcam_read_data0,
1073                                 DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
1074                                 DSAF_TBL_UCAST_CFG1_OUT_PORT_S);
1075        ptbl_tcam_ucast->tbl_ucast_dvc
1076                = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S);
1077
1078        spin_unlock_bh(&dsaf_dev->tcam_lock);
1079}
1080
1081/**
1082 * hns_dsaf_tcam_mc_get - INT
1083 * @dsaf_dev: dsa fabric id
1084 * @address: the address
1085 * @ptbl_tcam_data: the data
1086 * @ptbl_tcam_mcast: tcam multicast data
1087 */
1088static void hns_dsaf_tcam_mc_get(
1089        struct dsaf_device *dsaf_dev, u32 address,
1090        struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1091        struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
1092{
1093        u32 data_tmp;
1094
1095        spin_lock_bh(&dsaf_dev->tcam_lock);
1096
1097        /*Write Addr*/
1098        hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1099
1100        /*read tcam item puls*/
1101        hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1102
1103        /*read tcam data*/
1104        ptbl_tcam_data->tbl_tcam_data_high =
1105                dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1106        ptbl_tcam_data->tbl_tcam_data_low =
1107                dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1108
1109        /*read tcam mcast*/
1110        ptbl_tcam_mcast->tbl_mcast_port_msk[0] =
1111                dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1112        ptbl_tcam_mcast->tbl_mcast_port_msk[1] =
1113                dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
1114        ptbl_tcam_mcast->tbl_mcast_port_msk[2] =
1115                dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
1116        ptbl_tcam_mcast->tbl_mcast_port_msk[3] =
1117                dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
1118
1119        data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1120        ptbl_tcam_mcast->tbl_mcast_item_vld =
1121                dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1122        ptbl_tcam_mcast->tbl_mcast_old_en =
1123                dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1124        ptbl_tcam_mcast->tbl_mcast_port_msk[4] =
1125                dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M,
1126                               DSAF_TBL_MCAST_CFG4_VM128_112_S);
1127
1128        spin_unlock_bh(&dsaf_dev->tcam_lock);
1129}
1130
1131/**
1132 * hns_dsaf_tbl_line_init - INT
1133 * @dsaf_dev: dsa fabric id
1134 */
1135static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev)
1136{
1137        u32 i;
1138        /* defaultly set all lineal mac table entry resulting discard */
1139        struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} };
1140
1141        for (i = 0; i < DSAF_LINE_SUM; i++)
1142                hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line);
1143}
1144
1145/**
1146 * hns_dsaf_tbl_tcam_init - INT
1147 * @dsaf_dev: dsa fabric id
1148 */
1149static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
1150{
1151        u32 i;
1152        struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} };
1153        struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} };
1154
1155        /*tcam tbl*/
1156        for (i = 0; i < DSAF_TCAM_SUM; i++)
1157                hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast);
1158}
1159
1160/**
1161 * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg
1162 * @dsaf_dev: dsa fabric id
1163 * @mac_id: mac contrl block
1164 * @tc_en: traffic class
1165 */
1166static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
1167                                int mac_id, int tc_en)
1168{
1169        dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
1170}
1171
1172static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev,
1173                                   int mac_id, int tx_en, int rx_en)
1174{
1175        if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1176                if (!tx_en || !rx_en)
1177                        dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n");
1178
1179                return;
1180        }
1181
1182        dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1183                         DSAF_PFC_PAUSE_RX_EN_B, !!rx_en);
1184        dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1185                         DSAF_PFC_PAUSE_TX_EN_B, !!tx_en);
1186}
1187
1188int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1189                                 u32 en)
1190{
1191        if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1192                if (!en) {
1193                        dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n");
1194                        return -EINVAL;
1195                }
1196        }
1197
1198        dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1199                         DSAF_MAC_PAUSE_RX_EN_B, !!en);
1200
1201        return 0;
1202}
1203
1204void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1205                                  u32 *en)
1206{
1207        if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1208                *en = 1;
1209        else
1210                *en = dsaf_get_dev_bit(dsaf_dev,
1211                                       DSAF_PAUSE_CFG_REG + mac_id * 4,
1212                                       DSAF_MAC_PAUSE_RX_EN_B);
1213}
1214
1215/**
1216 * hns_dsaf_comm_init - INT
1217 * @dsaf_dev: dsa fabric id
1218 */
1219static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
1220{
1221        u32 i;
1222        u32 o_dsaf_cfg;
1223        bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
1224
1225        o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
1226        dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
1227        dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode);
1228        dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0);
1229        dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0);
1230        dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0);
1231        dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
1232
1233        hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1);
1234        hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD);
1235
1236        /* set 22 queue per tx ppe engine, only used in switch mode */
1237        hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE);
1238
1239        /* set promisc def queue id */
1240        hns_dsaf_mix_def_qid_cfg(dsaf_dev);
1241
1242        /* set inner loopback queue id */
1243        hns_dsaf_inner_qid_cfg(dsaf_dev);
1244
1245        /* in non switch mode, set all port to access mode */
1246        hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
1247
1248        /*set dsaf pfc  to 0 for parseing rx pause*/
1249        for (i = 0; i < DSAF_COMM_CHN; i++) {
1250                hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
1251                hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1);
1252        }
1253
1254        /*msk and  clr exception irqs */
1255        for (i = 0; i < DSAF_COMM_CHN; i++) {
1256                hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful);
1257                hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful);
1258                hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful);
1259
1260                hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful);
1261                hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful);
1262                hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful);
1263        }
1264        hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful);
1265        hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful);
1266}
1267
1268/**
1269 * hns_dsaf_inode_init - INT
1270 * @dsaf_dev: dsa fabric id
1271 */
1272static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev)
1273{
1274        u32 reg;
1275        u32 tc_cfg;
1276        u32 i;
1277
1278        if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE)
1279                tc_cfg = HNS_DSAF_I4TC_CFG;
1280        else
1281                tc_cfg = HNS_DSAF_I8TC_CFG;
1282
1283        if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1284                for (i = 0; i < DSAF_INODE_NUM; i++) {
1285                        reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1286                        dsaf_set_dev_field(dsaf_dev, reg,
1287                                           DSAF_INODE_IN_PORT_NUM_M,
1288                                           DSAF_INODE_IN_PORT_NUM_S,
1289                                           i % DSAF_XGE_NUM);
1290                }
1291        } else {
1292                for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) {
1293                        reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1294                        dsaf_set_dev_field(dsaf_dev, reg,
1295                                           DSAF_INODE_IN_PORT_NUM_M,
1296                                           DSAF_INODE_IN_PORT_NUM_S, 0);
1297                        dsaf_set_dev_field(dsaf_dev, reg,
1298                                           DSAFV2_INODE_IN_PORT1_NUM_M,
1299                                           DSAFV2_INODE_IN_PORT1_NUM_S, 1);
1300                        dsaf_set_dev_field(dsaf_dev, reg,
1301                                           DSAFV2_INODE_IN_PORT2_NUM_M,
1302                                           DSAFV2_INODE_IN_PORT2_NUM_S, 2);
1303                        dsaf_set_dev_field(dsaf_dev, reg,
1304                                           DSAFV2_INODE_IN_PORT3_NUM_M,
1305                                           DSAFV2_INODE_IN_PORT3_NUM_S, 3);
1306                        dsaf_set_dev_field(dsaf_dev, reg,
1307                                           DSAFV2_INODE_IN_PORT4_NUM_M,
1308                                           DSAFV2_INODE_IN_PORT4_NUM_S, 4);
1309                        dsaf_set_dev_field(dsaf_dev, reg,
1310                                           DSAFV2_INODE_IN_PORT5_NUM_M,
1311                                           DSAFV2_INODE_IN_PORT5_NUM_S, 5);
1312                }
1313        }
1314        for (i = 0; i < DSAF_INODE_NUM; i++) {
1315                reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i;
1316                dsaf_write_dev(dsaf_dev, reg, tc_cfg);
1317        }
1318}
1319
1320/**
1321 * hns_dsaf_sbm_init - INT
1322 * @dsaf_dev: dsa fabric id
1323 */
1324static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev)
1325{
1326        u32 flag;
1327        u32 finish_msk;
1328        u32 cnt = 0;
1329        int ret;
1330
1331        if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1332                hns_dsaf_sbm_bp_wl_cfg(dsaf_dev);
1333                finish_msk = DSAF_SRAM_INIT_OVER_M;
1334        } else {
1335                hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev);
1336                finish_msk = DSAFV2_SRAM_INIT_OVER_M;
1337        }
1338
1339        /* enable sbm chanel, disable sbm chanel shcut function*/
1340        hns_dsaf_sbm_cfg(dsaf_dev);
1341
1342        /* enable sbm mib */
1343        ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev);
1344        if (ret) {
1345                dev_err(dsaf_dev->dev,
1346                        "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n",
1347                        dsaf_dev->ae_dev.name, ret);
1348                return ret;
1349        }
1350
1351        /* enable sbm initial link sram */
1352        hns_dsaf_sbm_link_sram_init_en(dsaf_dev);
1353
1354        do {
1355                usleep_range(200, 210);/*udelay(200);*/
1356                flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG,
1357                                          finish_msk, DSAF_SRAM_INIT_OVER_S);
1358                cnt++;
1359        } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) &&
1360                 cnt < DSAF_CFG_READ_CNT);
1361
1362        if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) {
1363                dev_err(dsaf_dev->dev,
1364                        "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n",
1365                        dsaf_dev->ae_dev.name, flag, cnt);
1366                return -ENODEV;
1367        }
1368
1369        hns_dsaf_rocee_bp_en(dsaf_dev);
1370
1371        return 0;
1372}
1373
1374/**
1375 * hns_dsaf_tbl_init - INT
1376 * @dsaf_dev: dsa fabric id
1377 */
1378static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev)
1379{
1380        hns_dsaf_tbl_stat_en(dsaf_dev);
1381
1382        hns_dsaf_tbl_tcam_init(dsaf_dev);
1383        hns_dsaf_tbl_line_init(dsaf_dev);
1384}
1385
1386/**
1387 * hns_dsaf_voq_init - INT
1388 * @dsaf_dev: dsa fabric id
1389 */
1390static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev)
1391{
1392        hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev);
1393}
1394
1395/**
1396 * hns_dsaf_init_hw - init dsa fabric hardware
1397 * @dsaf_dev: dsa fabric device struct pointer
1398 */
1399static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev)
1400{
1401        int ret;
1402
1403        dev_dbg(dsaf_dev->dev,
1404                "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name);
1405
1406        dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1407        mdelay(10);
1408        dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1);
1409
1410        hns_dsaf_comm_init(dsaf_dev);
1411
1412        /*init XBAR_INODE*/
1413        hns_dsaf_inode_init(dsaf_dev);
1414
1415        /*init SBM*/
1416        ret = hns_dsaf_sbm_init(dsaf_dev);
1417        if (ret)
1418                return ret;
1419
1420        /*init TBL*/
1421        hns_dsaf_tbl_init(dsaf_dev);
1422
1423        /*init VOQ*/
1424        hns_dsaf_voq_init(dsaf_dev);
1425
1426        return 0;
1427}
1428
1429/**
1430 * hns_dsaf_remove_hw - uninit dsa fabric hardware
1431 * @dsaf_dev: dsa fabric device struct pointer
1432 */
1433static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev)
1434{
1435        /*reset*/
1436        dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1437}
1438
1439/**
1440 * hns_dsaf_init - init dsa fabric
1441 * @dsaf_dev: dsa fabric device struct pointer
1442 * return 0 - success , negative --fail
1443 */
1444static int hns_dsaf_init(struct dsaf_device *dsaf_dev)
1445{
1446        struct dsaf_drv_priv *priv =
1447            (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1448        u32 i;
1449        int ret;
1450
1451        if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1452                return 0;
1453
1454        if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1455                dsaf_dev->tcam_max_num = DSAF_TCAM_SUM;
1456        else
1457                dsaf_dev->tcam_max_num =
1458                        DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM;
1459
1460        spin_lock_init(&dsaf_dev->tcam_lock);
1461        ret = hns_dsaf_init_hw(dsaf_dev);
1462        if (ret)
1463                return ret;
1464
1465        /* malloc mem for tcam mac key(vlan+mac) */
1466        priv->soft_mac_tbl = vzalloc(array_size(DSAF_TCAM_SUM,
1467                                                sizeof(*priv->soft_mac_tbl)));
1468        if (!priv->soft_mac_tbl) {
1469                ret = -ENOMEM;
1470                goto remove_hw;
1471        }
1472
1473        /*all entry invall */
1474        for (i = 0; i < DSAF_TCAM_SUM; i++)
1475                (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX;
1476
1477        return 0;
1478
1479remove_hw:
1480        hns_dsaf_remove_hw(dsaf_dev);
1481        return ret;
1482}
1483
1484/**
1485 * hns_dsaf_free - free dsa fabric
1486 * @dsaf_dev: dsa fabric device struct pointer
1487 */
1488static void hns_dsaf_free(struct dsaf_device *dsaf_dev)
1489{
1490        struct dsaf_drv_priv *priv =
1491            (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1492
1493        hns_dsaf_remove_hw(dsaf_dev);
1494
1495        /* free all mac mem */
1496        vfree(priv->soft_mac_tbl);
1497        priv->soft_mac_tbl = NULL;
1498}
1499
1500/**
1501 * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry
1502 * @dsaf_dev: dsa fabric device struct pointer
1503 * @mac_key: mac entry struct pointer
1504 */
1505static u16 hns_dsaf_find_soft_mac_entry(
1506        struct dsaf_device *dsaf_dev,
1507        struct dsaf_drv_tbl_tcam_key *mac_key)
1508{
1509        struct dsaf_drv_priv *priv =
1510            (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1511        struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1512        u32 i;
1513
1514        soft_mac_entry = priv->soft_mac_tbl;
1515        for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1516                /* invall tab entry */
1517                if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) &&
1518                    (soft_mac_entry->tcam_key.high.val == mac_key->high.val) &&
1519                    (soft_mac_entry->tcam_key.low.val == mac_key->low.val))
1520                        /* return find result --soft index */
1521                        return soft_mac_entry->index;
1522
1523                soft_mac_entry++;
1524        }
1525        return DSAF_INVALID_ENTRY_IDX;
1526}
1527
1528/**
1529 * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry
1530 * @dsaf_dev: dsa fabric device struct pointer
1531 */
1532static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev)
1533{
1534        struct dsaf_drv_priv *priv =
1535            (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1536        struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1537        u32 i;
1538
1539        soft_mac_entry = priv->soft_mac_tbl;
1540        for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1541                /* inv all entry */
1542                if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1543                        /* return find result --soft index */
1544                        return i;
1545
1546                soft_mac_entry++;
1547        }
1548        return DSAF_INVALID_ENTRY_IDX;
1549}
1550
1551/**
1552 * hns_dsaf_find_empty_mac_entry_reverse
1553 * search dsa fabric soft empty-entry from the end
1554 * @dsaf_dev: dsa fabric device struct pointer
1555 */
1556static u16 hns_dsaf_find_empty_mac_entry_reverse(struct dsaf_device *dsaf_dev)
1557{
1558        struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1559        struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1560        int i;
1561
1562        soft_mac_entry = priv->soft_mac_tbl + (DSAF_TCAM_SUM - 1);
1563        for (i = (DSAF_TCAM_SUM - 1); i > 0; i--) {
1564                /* search all entry from end to start.*/
1565                if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1566                        return i;
1567                soft_mac_entry--;
1568        }
1569        return DSAF_INVALID_ENTRY_IDX;
1570}
1571
1572/**
1573 * hns_dsaf_set_mac_key - set mac key
1574 * @dsaf_dev: dsa fabric device struct pointer
1575 * @mac_key: tcam key pointer
1576 * @vlan_id: vlan id
1577 * @in_port_num: input port num
1578 * @addr: mac addr
1579 */
1580static void hns_dsaf_set_mac_key(
1581        struct dsaf_device *dsaf_dev,
1582        struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num,
1583        u8 *addr)
1584{
1585        u8 port;
1586
1587        if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE)
1588                /*DSAF mode : in port id fixed 0*/
1589                port = 0;
1590        else
1591                /*non-dsaf mode*/
1592                port = in_port_num;
1593
1594        mac_key->high.bits.mac_0 = addr[0];
1595        mac_key->high.bits.mac_1 = addr[1];
1596        mac_key->high.bits.mac_2 = addr[2];
1597        mac_key->high.bits.mac_3 = addr[3];
1598        mac_key->low.bits.mac_4 = addr[4];
1599        mac_key->low.bits.mac_5 = addr[5];
1600        mac_key->low.bits.port_vlan = 0;
1601        dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_VLAN_M,
1602                       DSAF_TBL_TCAM_KEY_VLAN_S, vlan_id);
1603        dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_PORT_M,
1604                       DSAF_TBL_TCAM_KEY_PORT_S, port);
1605}
1606
1607/**
1608 * hns_dsaf_set_mac_uc_entry - set mac uc-entry
1609 * @dsaf_dev: dsa fabric device struct pointer
1610 * @mac_entry: uc-mac entry
1611 */
1612int hns_dsaf_set_mac_uc_entry(
1613        struct dsaf_device *dsaf_dev,
1614        struct dsaf_drv_mac_single_dest_entry *mac_entry)
1615{
1616        u16 entry_index;
1617        struct dsaf_drv_tbl_tcam_key mac_key;
1618        struct dsaf_tbl_tcam_ucast_cfg mac_data;
1619        struct dsaf_drv_priv *priv =
1620            (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1621        struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1622        struct dsaf_tbl_tcam_data tcam_data;
1623
1624        /* mac addr check */
1625        if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1626            MAC_IS_BROADCAST(mac_entry->addr) ||
1627            MAC_IS_MULTICAST(mac_entry->addr)) {
1628                dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n",
1629                        dsaf_dev->ae_dev.name, mac_entry->addr);
1630                return -EINVAL;
1631        }
1632
1633        /* config key */
1634        hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1635                             mac_entry->in_port_num, mac_entry->addr);
1636
1637        /* entry ie exist? */
1638        entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1639        if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1640                /*if has not inv entry,find a empty entry */
1641                entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1642                if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1643                        /* has not empty,return error */
1644                        dev_err(dsaf_dev->dev,
1645                                "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1646                                dsaf_dev->ae_dev.name,
1647                                mac_key.high.val, mac_key.low.val);
1648                        return -EINVAL;
1649                }
1650        }
1651
1652        dev_dbg(dsaf_dev->dev,
1653                "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1654                dsaf_dev->ae_dev.name, mac_key.high.val,
1655                mac_key.low.val, entry_index);
1656
1657        /* config hardware entry */
1658        mac_data.tbl_ucast_item_vld = 1;
1659        mac_data.tbl_ucast_mac_discard = 0;
1660        mac_data.tbl_ucast_old_en = 0;
1661        /* default config dvc to 0 */
1662        mac_data.tbl_ucast_dvc = 0;
1663        mac_data.tbl_ucast_out_port = mac_entry->port_num;
1664        tcam_data.tbl_tcam_data_high = mac_key.high.val;
1665        tcam_data.tbl_tcam_data_low = mac_key.low.val;
1666
1667        hns_dsaf_tcam_uc_cfg(dsaf_dev, entry_index, &tcam_data, &mac_data);
1668
1669        /* config software entry */
1670        soft_mac_entry += entry_index;
1671        soft_mac_entry->index = entry_index;
1672        soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1673        soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1674
1675        return 0;
1676}
1677
1678int hns_dsaf_rm_mac_addr(
1679        struct dsaf_device *dsaf_dev,
1680        struct dsaf_drv_mac_single_dest_entry *mac_entry)
1681{
1682        u16 entry_index;
1683        struct dsaf_tbl_tcam_ucast_cfg mac_data;
1684        struct dsaf_drv_tbl_tcam_key mac_key;
1685
1686        /* mac addr check */
1687        if (!is_valid_ether_addr(mac_entry->addr)) {
1688                dev_err(dsaf_dev->dev, "rm_uc_addr %s Mac %pM err!\n",
1689                        dsaf_dev->ae_dev.name, mac_entry->addr);
1690                return -EINVAL;
1691        }
1692
1693        /* config key */
1694        hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1695                             mac_entry->in_port_num, mac_entry->addr);
1696
1697        entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1698        if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1699                /* can not find the tcam entry, return 0 */
1700                dev_info(dsaf_dev->dev,
1701                         "rm_uc_addr no tcam, %s Mac key(%#x:%#x)\n",
1702                         dsaf_dev->ae_dev.name,
1703                         mac_key.high.val, mac_key.low.val);
1704                return 0;
1705        }
1706
1707        dev_dbg(dsaf_dev->dev,
1708                "rm_uc_addr, %s Mac key(%#x:%#x) entry_index%d\n",
1709                dsaf_dev->ae_dev.name, mac_key.high.val,
1710                mac_key.low.val, entry_index);
1711
1712        hns_dsaf_tcam_uc_get(
1713                        dsaf_dev, entry_index,
1714                        (struct dsaf_tbl_tcam_data *)&mac_key,
1715                        &mac_data);
1716
1717        /* unicast entry not used locally should not clear */
1718        if (mac_entry->port_num != mac_data.tbl_ucast_out_port)
1719                return -EFAULT;
1720
1721        return hns_dsaf_del_mac_entry(dsaf_dev,
1722                                      mac_entry->in_vlan_id,
1723                                      mac_entry->in_port_num,
1724                                      mac_entry->addr);
1725}
1726
1727static void hns_dsaf_setup_mc_mask(struct dsaf_device *dsaf_dev,
1728                                   u8 port_num, u8 *mask, u8 *addr)
1729{
1730        if (MAC_IS_BROADCAST(addr))
1731                eth_broadcast_addr(mask);
1732        else
1733                memcpy(mask, dsaf_dev->mac_cb[port_num]->mc_mask, ETH_ALEN);
1734}
1735
1736static void hns_dsaf_mc_mask_bit_clear(char *dst, const char *src)
1737{
1738        u16 *a = (u16 *)dst;
1739        const u16 *b = (const u16 *)src;
1740
1741        a[0] &= b[0];
1742        a[1] &= b[1];
1743        a[2] &= b[2];
1744}
1745
1746/**
1747 * hns_dsaf_add_mac_mc_port - add mac mc-port
1748 * @dsaf_dev: dsa fabric device struct pointer
1749 * @mac_entry: mc-mac entry
1750 */
1751int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
1752                             struct dsaf_drv_mac_single_dest_entry *mac_entry)
1753{
1754        u16 entry_index;
1755        struct dsaf_drv_tbl_tcam_key mac_key;
1756        struct dsaf_drv_tbl_tcam_key mask_key;
1757        struct dsaf_tbl_tcam_data *pmask_key = NULL;
1758        struct dsaf_tbl_tcam_mcast_cfg mac_data;
1759        struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1760        struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1761        struct dsaf_tbl_tcam_data tcam_data;
1762        u8 mc_addr[ETH_ALEN];
1763        int mskid;
1764
1765        /*chechk mac addr */
1766        if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1767                dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n",
1768                        mac_entry->addr);
1769                return -EINVAL;
1770        }
1771
1772        ether_addr_copy(mc_addr, mac_entry->addr);
1773        if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1774                u8 mc_mask[ETH_ALEN];
1775
1776                /* prepare for key data setting */
1777                hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num,
1778                                       mc_mask, mac_entry->addr);
1779                hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1780
1781                /* config key mask */
1782                hns_dsaf_set_mac_key(dsaf_dev, &mask_key,
1783                                     0x0,
1784                                     0xff,
1785                                     mc_mask);
1786
1787                pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1788        }
1789
1790        /*config key */
1791        hns_dsaf_set_mac_key(
1792                dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1793                mac_entry->in_port_num, mc_addr);
1794
1795        memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg));
1796
1797        /* check if the tcam is exist */
1798        entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1799        if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1800                /*if hasnot , find a empty*/
1801                entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1802                if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1803                        /*if hasnot empty, error*/
1804                        dev_err(dsaf_dev->dev,
1805                                "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1806                                dsaf_dev->ae_dev.name, mac_key.high.val,
1807                                mac_key.low.val);
1808                        return -EINVAL;
1809                }
1810        } else {
1811                /* if exist, add in */
1812                hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data,
1813                                     &mac_data);
1814        }
1815
1816        /* config hardware entry */
1817        if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1818                mskid = mac_entry->port_num;
1819        } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1820                mskid = mac_entry->port_num -
1821                        DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1822        } else {
1823                dev_err(dsaf_dev->dev,
1824                        "%s,pnum(%d)error,key(%#x:%#x)\n",
1825                        dsaf_dev->ae_dev.name, mac_entry->port_num,
1826                        mac_key.high.val, mac_key.low.val);
1827                return -EINVAL;
1828        }
1829        dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1);
1830        mac_data.tbl_mcast_old_en = 0;
1831        mac_data.tbl_mcast_item_vld = 1;
1832
1833        dev_dbg(dsaf_dev->dev,
1834                "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1835                dsaf_dev->ae_dev.name, mac_key.high.val,
1836                mac_key.low.val, entry_index);
1837
1838        tcam_data.tbl_tcam_data_high = mac_key.high.val;
1839        tcam_data.tbl_tcam_data_low = mac_key.low.val;
1840
1841        /* config mc entry with mask */
1842        hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, &tcam_data,
1843                             pmask_key, &mac_data);
1844
1845        /*config software entry */
1846        soft_mac_entry += entry_index;
1847        soft_mac_entry->index = entry_index;
1848        soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1849        soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1850
1851        return 0;
1852}
1853
1854/**
1855 * hns_dsaf_del_mac_entry - del mac mc-port
1856 * @dsaf_dev: dsa fabric device struct pointer
1857 * @vlan_id: vlian id
1858 * @in_port_num: input port num
1859 * @addr : mac addr
1860 */
1861int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
1862                           u8 in_port_num, u8 *addr)
1863{
1864        u16 entry_index;
1865        struct dsaf_drv_tbl_tcam_key mac_key;
1866        struct dsaf_drv_priv *priv =
1867            (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1868        struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1869
1870        /*check mac addr */
1871        if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) {
1872                dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n",
1873                        addr);
1874                return -EINVAL;
1875        }
1876
1877        /*config key */
1878        hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr);
1879
1880        /*exist ?*/
1881        entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1882        if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1883                /*not exist, error */
1884                dev_err(dsaf_dev->dev,
1885                        "del_mac_entry failed, %s Mac key(%#x:%#x)\n",
1886                        dsaf_dev->ae_dev.name,
1887                        mac_key.high.val, mac_key.low.val);
1888                return -EINVAL;
1889        }
1890        dev_dbg(dsaf_dev->dev,
1891                "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1892                dsaf_dev->ae_dev.name, mac_key.high.val,
1893                mac_key.low.val, entry_index);
1894
1895        /*do del opt*/
1896        hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1897
1898        /*del soft emtry */
1899        soft_mac_entry += entry_index;
1900        soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1901
1902        return 0;
1903}
1904
1905/**
1906 * hns_dsaf_del_mac_mc_port - del mac mc- port
1907 * @dsaf_dev: dsa fabric device struct pointer
1908 * @mac_entry: mac entry
1909 */
1910int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
1911                             struct dsaf_drv_mac_single_dest_entry *mac_entry)
1912{
1913        u16 entry_index;
1914        struct dsaf_drv_tbl_tcam_key mac_key;
1915        struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1916        struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1917        u16 vlan_id;
1918        u8 in_port_num;
1919        struct dsaf_tbl_tcam_mcast_cfg mac_data;
1920        struct dsaf_tbl_tcam_data tcam_data;
1921        int mskid;
1922        const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0};
1923        struct dsaf_drv_tbl_tcam_key mask_key;
1924        struct dsaf_tbl_tcam_data *pmask_key = NULL;
1925        u8 mc_addr[ETH_ALEN];
1926
1927        if (!(void *)mac_entry) {
1928                dev_err(dsaf_dev->dev,
1929                        "hns_dsaf_del_mac_mc_port mac_entry is NULL\n");
1930                return -EINVAL;
1931        }
1932
1933        /*check mac addr */
1934        if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1935                dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n",
1936                        mac_entry->addr);
1937                return -EINVAL;
1938        }
1939
1940        /* always mask vlan_id field */
1941        ether_addr_copy(mc_addr, mac_entry->addr);
1942
1943        if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1944                u8 mc_mask[ETH_ALEN];
1945
1946                /* prepare for key data setting */
1947                hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num,
1948                                       mc_mask, mac_entry->addr);
1949                hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1950
1951                /* config key mask */
1952                hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 0x00, 0xff, mc_mask);
1953
1954                pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1955        }
1956
1957        /* get key info */
1958        vlan_id = mac_entry->in_vlan_id;
1959        in_port_num = mac_entry->in_port_num;
1960
1961        /* config key */
1962        hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, mc_addr);
1963
1964        /* check if the tcam entry is exist */
1965        entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1966        if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1967                /*find none */
1968                dev_err(dsaf_dev->dev,
1969                        "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n",
1970                        dsaf_dev->ae_dev.name,
1971                        mac_key.high.val, mac_key.low.val);
1972                return -EINVAL;
1973        }
1974
1975        dev_dbg(dsaf_dev->dev,
1976                "del_mac_mc_port, %s key(%#x:%#x) index%d\n",
1977                dsaf_dev->ae_dev.name, mac_key.high.val,
1978                mac_key.low.val, entry_index);
1979
1980        /* read entry */
1981        hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, &mac_data);
1982
1983        /*del the port*/
1984        if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1985                mskid = mac_entry->port_num;
1986        } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1987                mskid = mac_entry->port_num -
1988                        DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1989        } else {
1990                dev_err(dsaf_dev->dev,
1991                        "%s,pnum(%d)error,key(%#x:%#x)\n",
1992                        dsaf_dev->ae_dev.name, mac_entry->port_num,
1993                        mac_key.high.val, mac_key.low.val);
1994                return -EINVAL;
1995        }
1996        dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0);
1997
1998        /*check non port, do del entry */
1999        if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
2000                    sizeof(mac_data.tbl_mcast_port_msk))) {
2001                hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
2002
2003                /* del soft entry */
2004                soft_mac_entry += entry_index;
2005                soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2006        } else { /* not zero, just del port, update */
2007                tcam_data.tbl_tcam_data_high = mac_key.high.val;
2008                tcam_data.tbl_tcam_data_low = mac_key.low.val;
2009
2010                hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index,
2011                                     &tcam_data,
2012                                     pmask_key, &mac_data);
2013        }
2014
2015        return 0;
2016}
2017
2018int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, u8 mac_id,
2019                             u8 port_num)
2020{
2021        struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2022        struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2023        struct dsaf_tbl_tcam_mcast_cfg mac_data;
2024        int ret = 0, i;
2025
2026        if (HNS_DSAF_IS_DEBUG(dsaf_dev))
2027                return 0;
2028
2029        for (i = 0; i < DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; i++) {
2030                u8 addr[ETH_ALEN];
2031                u8 port;
2032
2033                soft_mac_entry = priv->soft_mac_tbl + i;
2034
2035                hns_dsaf_tcam_addr_get(&soft_mac_entry->tcam_key, addr);
2036                port = dsaf_get_field(
2037                                soft_mac_entry->tcam_key.low.bits.port_vlan,
2038                                DSAF_TBL_TCAM_KEY_PORT_M,
2039                                DSAF_TBL_TCAM_KEY_PORT_S);
2040                /* check valid tcam mc entry */
2041                if (soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX &&
2042                    port == mac_id &&
2043                    is_multicast_ether_addr(addr) &&
2044                    !is_broadcast_ether_addr(addr)) {
2045                        const u32 empty_msk[DSAF_PORT_MSK_NUM] = {0};
2046                        struct dsaf_drv_mac_single_dest_entry mac_entry;
2047
2048                        /* disable receiving of this multicast address for
2049                         * the VF.
2050                         */
2051                        ether_addr_copy(mac_entry.addr, addr);
2052                        mac_entry.in_vlan_id = dsaf_get_field(
2053                                soft_mac_entry->tcam_key.low.bits.port_vlan,
2054                                DSAF_TBL_TCAM_KEY_VLAN_M,
2055                                DSAF_TBL_TCAM_KEY_VLAN_S);
2056                        mac_entry.in_port_num = mac_id;
2057                        mac_entry.port_num = port_num;
2058                        if (hns_dsaf_del_mac_mc_port(dsaf_dev, &mac_entry)) {
2059                                ret = -EINVAL;
2060                                continue;
2061                        }
2062
2063                        /* disable receiving of this multicast address for
2064                         * the mac port if all VF are disable
2065                         */
2066                        hns_dsaf_tcam_mc_get(dsaf_dev, i,
2067                                             (struct dsaf_tbl_tcam_data *)
2068                                             (&soft_mac_entry->tcam_key),
2069                                             &mac_data);
2070                        dsaf_set_bit(mac_data.tbl_mcast_port_msk[mac_id / 32],
2071                                     mac_id % 32, 0);
2072                        if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
2073                                    sizeof(u32) * DSAF_PORT_MSK_NUM)) {
2074                                mac_entry.port_num = mac_id;
2075                                if (hns_dsaf_del_mac_mc_port(dsaf_dev,
2076                                                             &mac_entry)) {
2077                                        ret = -EINVAL;
2078                                        continue;
2079                                }
2080                        }
2081                }
2082        }
2083
2084        return ret;
2085}
2086
2087static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev,
2088                                              size_t sizeof_priv)
2089{
2090        struct dsaf_device *dsaf_dev;
2091
2092        dsaf_dev = devm_kzalloc(dev,
2093                                sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL);
2094        if (unlikely(!dsaf_dev)) {
2095                dsaf_dev = ERR_PTR(-ENOMEM);
2096        } else {
2097                dsaf_dev->dev = dev;
2098                dev_set_drvdata(dev, dsaf_dev);
2099        }
2100
2101        return dsaf_dev;
2102}
2103
2104/**
2105 * hns_dsaf_free_dev - free dev mem
2106 * @dsaf_dev: struct device pointer
2107 */
2108static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev)
2109{
2110        (void)dev_set_drvdata(dsaf_dev->dev, NULL);
2111}
2112
2113/**
2114 * hns_dsaf_pfc_unit_cnt - set pfc unit count
2115 * @dsaf_dev: dsa fabric id
2116 * @mac_id: id in use
2117 * @rate:  value array
2118 */
2119static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int  mac_id,
2120                                  enum dsaf_port_rate_mode rate)
2121{
2122        u32 unit_cnt;
2123
2124        switch (rate) {
2125        case DSAF_PORT_RATE_10000:
2126                unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2127                break;
2128        case DSAF_PORT_RATE_1000:
2129                unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2130                break;
2131        case DSAF_PORT_RATE_2500:
2132                unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2133                break;
2134        default:
2135                unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2136        }
2137
2138        dsaf_set_dev_field(dsaf_dev,
2139                           (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id),
2140                           DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S,
2141                           unit_cnt);
2142}
2143
2144/**
2145 * hns_dsaf_port_work_rate_cfg - fifo
2146 * @dsaf_dev: dsa fabric id
2147 * @mac_id: mac contrl block
2148 * @rate_mode: value array
2149 */
2150static void
2151hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id,
2152                            enum dsaf_port_rate_mode rate_mode)
2153{
2154        u32 port_work_mode;
2155
2156        port_work_mode = dsaf_read_dev(
2157                dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id);
2158
2159        if (rate_mode == DSAF_PORT_RATE_10000)
2160                dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1);
2161        else
2162                dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0);
2163
2164        dsaf_write_dev(dsaf_dev,
2165                       DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id,
2166                       port_work_mode);
2167
2168        hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode);
2169}
2170
2171/**
2172 * hns_dsaf_fix_mac_mode - dsaf modify mac mode
2173 * @mac_cb: mac contrl block
2174 */
2175void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb)
2176{
2177        enum dsaf_port_rate_mode mode;
2178        struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
2179        int mac_id = mac_cb->mac_id;
2180
2181        if (mac_cb->mac_type != HNAE_PORT_SERVICE)
2182                return;
2183        if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII)
2184                mode = DSAF_PORT_RATE_10000;
2185        else
2186                mode = DSAF_PORT_RATE_1000;
2187
2188        hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode);
2189}
2190
2191static u32 hns_dsaf_get_inode_prio_reg(int index)
2192{
2193        int base_index, offset;
2194        u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG;
2195
2196        base_index = (index + 1) / DSAF_REG_PER_ZONE;
2197        offset = (index + 1) % DSAF_REG_PER_ZONE;
2198
2199        return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index +
2200                DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset;
2201}
2202
2203void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
2204{
2205        struct dsaf_hw_stats *hw_stats
2206                = &dsaf_dev->hw_stats[node_num];
2207        bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2208        int i;
2209        u32 reg_tmp;
2210
2211        hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
2212                DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2213        hw_stats->man_pkts += dsaf_read_dev(dsaf_dev,
2214                DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num);
2215        hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev,
2216                DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
2217        hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
2218                DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
2219
2220        reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2221                            DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2222        hw_stats->rx_pause_frame +=
2223                dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num);
2224
2225        hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
2226                DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
2227        hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
2228                DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num);
2229        hw_stats->crc_false += dsaf_read_dev(dsaf_dev,
2230                DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2231        hw_stats->bp_drop += dsaf_read_dev(dsaf_dev,
2232                DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2233        hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev,
2234                DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2235        hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev,
2236                DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2237
2238        hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
2239                DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 4 * (u64)node_num);
2240        hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
2241                DSAF_INODE_IN_DATA_STP_DISC_0_REG + 4 * (u64)node_num);
2242
2243        /* pfc pause frame statistics stored in dsaf inode*/
2244        if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) {
2245                for (i = 0; i < DSAF_PRIO_NR; i++) {
2246                        reg_tmp = hns_dsaf_get_inode_prio_reg(i);
2247                        hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev,
2248                                reg_tmp + 0x4 * (u64)node_num);
2249                        hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev,
2250                                DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG +
2251                                DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i +
2252                                0xF0 * (u64)node_num);
2253                }
2254        }
2255        hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev,
2256                DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num);
2257}
2258
2259/**
2260 *hns_dsaf_get_regs - dump dsaf regs
2261 *@ddev: dsaf device
2262 *@port: port
2263 *@data:data for value of regs
2264 */
2265void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
2266{
2267        u32 i;
2268        u32 j;
2269        u32 *p = data;
2270        u32 reg_tmp;
2271        bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2272
2273        /* dsaf common registers */
2274        p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
2275        p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG);
2276        p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG);
2277        p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG);
2278        p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG);
2279        p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG);
2280        p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG);
2281        p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG);
2282        p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG);
2283
2284        p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4);
2285        p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4);
2286        p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2287        p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2288        p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2289        p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2290        p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4);
2291        p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4);
2292        p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2293        p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4);
2294        p[19] =  dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4);
2295        p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2296        p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4);
2297        p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4);
2298        p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4);
2299
2300        for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2301                p[24 + i] = dsaf_read_dev(ddev,
2302                                DSAF_SW_PORT_TYPE_0_REG + i * 4);
2303
2304        p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4);
2305
2306        for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2307                p[33 + i] = dsaf_read_dev(ddev,
2308                                DSAF_PORT_DEF_VLAN_0_REG + i * 4);
2309
2310        for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++)
2311                p[41 + i] = dsaf_read_dev(ddev,
2312                                DSAF_VM_DEF_VLAN_0_REG + i * 4);
2313
2314        /* dsaf inode registers */
2315        p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG);
2316
2317        p[171] = dsaf_read_dev(ddev,
2318                        DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80);
2319
2320        for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2321                j = i * DSAF_COMM_CHN + port;
2322                p[172 + i] = dsaf_read_dev(ddev,
2323                                DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80);
2324                p[175 + i] = dsaf_read_dev(ddev,
2325                                DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80);
2326                p[178 + i] = dsaf_read_dev(ddev,
2327                                DSAF_INODE_BP_STATUS_0_REG + j * 0x80);
2328                p[181 + i] = dsaf_read_dev(ddev,
2329                                DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80);
2330                p[184 + i] = dsaf_read_dev(ddev,
2331                                DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80);
2332                p[187 + i] = dsaf_read_dev(ddev,
2333                                DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
2334                p[190 + i] = dsaf_read_dev(ddev,
2335                                DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
2336                reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2337                                    DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2338                p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80);
2339                p[196 + i] = dsaf_read_dev(ddev,
2340                                DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
2341                p[199 + i] = dsaf_read_dev(ddev,
2342                                DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80);
2343                p[202 + i] = dsaf_read_dev(ddev,
2344                                DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80);
2345                p[205 + i] = dsaf_read_dev(ddev,
2346                                DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80);
2347                p[208 + i] = dsaf_read_dev(ddev,
2348                                DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80);
2349                p[211 + i] = dsaf_read_dev(ddev,
2350                        DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80);
2351                p[214 + i] = dsaf_read_dev(ddev,
2352                                DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80);
2353                p[217 + i] = dsaf_read_dev(ddev,
2354                                DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4);
2355                p[220 + i] = dsaf_read_dev(ddev,
2356                                DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
2357                p[223 + i] = dsaf_read_dev(ddev,
2358                                DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
2359                p[226 + i] = dsaf_read_dev(ddev,
2360                                DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
2361        }
2362
2363        p[229] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
2364
2365        for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2366                j = i * DSAF_COMM_CHN + port;
2367                p[230 + i] = dsaf_read_dev(ddev,
2368                                DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
2369        }
2370
2371        p[233] = dsaf_read_dev(ddev,
2372                DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 0x80);
2373
2374        /* dsaf inode registers */
2375        for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
2376                j = i * DSAF_COMM_CHN + port;
2377                p[234 + i] = dsaf_read_dev(ddev,
2378                                DSAF_SBM_CFG_REG_0_REG + j * 0x80);
2379                p[237 + i] = dsaf_read_dev(ddev,
2380                                DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
2381                p[240 + i] = dsaf_read_dev(ddev,
2382                                DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
2383                p[243 + i] = dsaf_read_dev(ddev,
2384                                DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
2385                p[246 + i] = dsaf_read_dev(ddev,
2386                                DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
2387                p[249 + i] = dsaf_read_dev(ddev,
2388                                DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
2389                p[252 + i] = dsaf_read_dev(ddev,
2390                                DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
2391                p[255 + i] = dsaf_read_dev(ddev,
2392                                DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
2393                p[258 + i] = dsaf_read_dev(ddev,
2394                                DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
2395                p[261 + i] = dsaf_read_dev(ddev,
2396                                DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
2397                p[264 + i] = dsaf_read_dev(ddev,
2398                                DSAF_SBM_INER_ST_0_REG + j * 0x80);
2399                p[267 + i] = dsaf_read_dev(ddev,
2400                                DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
2401                p[270 + i] = dsaf_read_dev(ddev,
2402                                DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
2403                p[273 + i] = dsaf_read_dev(ddev,
2404                                DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
2405                p[276 + i] = dsaf_read_dev(ddev,
2406                                DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
2407                p[279 + i] = dsaf_read_dev(ddev,
2408                                DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
2409                p[282 + i] = dsaf_read_dev(ddev,
2410                                DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
2411                p[285 + i] = dsaf_read_dev(ddev,
2412                                DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
2413                p[288 + i] = dsaf_read_dev(ddev,
2414                                DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
2415                p[291 + i] = dsaf_read_dev(ddev,
2416                                DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
2417                p[294 + i] = dsaf_read_dev(ddev,
2418                                DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
2419                p[297 + i] = dsaf_read_dev(ddev,
2420                                DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
2421                p[300 + i] = dsaf_read_dev(ddev,
2422                                DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
2423                p[303 + i] = dsaf_read_dev(ddev,
2424                                DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
2425                p[306 + i] = dsaf_read_dev(ddev,
2426                                DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
2427                p[309 + i] = dsaf_read_dev(ddev,
2428                                DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
2429                p[312 + i] = dsaf_read_dev(ddev,
2430                                DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
2431        }
2432
2433        /* dsaf onode registers */
2434        for (i = 0; i < DSAF_XOD_NUM; i++) {
2435                p[315 + i] = dsaf_read_dev(ddev,
2436                                DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
2437                p[323 + i] = dsaf_read_dev(ddev,
2438                                DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
2439                p[331 + i] = dsaf_read_dev(ddev,
2440                                DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
2441                p[339 + i] = dsaf_read_dev(ddev,
2442                                DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
2443                p[347 + i] = dsaf_read_dev(ddev,
2444                                DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
2445                p[355 + i] = dsaf_read_dev(ddev,
2446                                DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
2447        }
2448
2449        p[363] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
2450        p[364] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
2451        p[365] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
2452
2453        for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
2454                j = i * DSAF_COMM_CHN + port;
2455                p[366 + i] = dsaf_read_dev(ddev,
2456                                DSAF_XOD_GNT_L_0_REG + j * 0x90);
2457                p[369 + i] = dsaf_read_dev(ddev,
2458                                DSAF_XOD_GNT_H_0_REG + j * 0x90);
2459                p[372 + i] = dsaf_read_dev(ddev,
2460                                DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
2461                p[375 + i] = dsaf_read_dev(ddev,
2462                                DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
2463                p[378 + i] = dsaf_read_dev(ddev,
2464                                DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
2465                p[381 + i] = dsaf_read_dev(ddev,
2466                                DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
2467                p[384 + i] = dsaf_read_dev(ddev,
2468                                DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
2469                p[387 + i] = dsaf_read_dev(ddev,
2470                                DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
2471                p[390 + i] = dsaf_read_dev(ddev,
2472                                DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
2473                p[393 + i] = dsaf_read_dev(ddev,
2474                                DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
2475        }
2476
2477        p[396] = dsaf_read_dev(ddev,
2478                DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
2479        p[397] = dsaf_read_dev(ddev,
2480                DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
2481        p[398] = dsaf_read_dev(ddev,
2482                DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
2483        p[399] = dsaf_read_dev(ddev,
2484                DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
2485        p[400] = dsaf_read_dev(ddev,
2486                DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
2487        p[401] = dsaf_read_dev(ddev,
2488                DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
2489        p[402] = dsaf_read_dev(ddev,
2490                DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
2491        p[403] = dsaf_read_dev(ddev,
2492                DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
2493        p[404] = dsaf_read_dev(ddev,
2494                DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
2495        p[405] = dsaf_read_dev(ddev,
2496                DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
2497        p[406] = dsaf_read_dev(ddev,
2498                DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
2499        p[407] = dsaf_read_dev(ddev,
2500                DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
2501        p[408] = dsaf_read_dev(ddev,
2502                DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
2503
2504        /* dsaf voq registers */
2505        for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
2506                j = (i * DSAF_COMM_CHN + port) * 0x90;
2507                p[409 + i] = dsaf_read_dev(ddev,
2508                        DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
2509                p[412 + i] = dsaf_read_dev(ddev,
2510                        DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
2511                p[415 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
2512                p[418 + i] = dsaf_read_dev(ddev,
2513                        DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
2514                p[421 + i] = dsaf_read_dev(ddev,
2515                        DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
2516                p[424 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
2517                p[427 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
2518                p[430 + i] = dsaf_read_dev(ddev,
2519                        DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
2520                p[433 + i] = dsaf_read_dev(ddev,
2521                        DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
2522                p[436 + i] = dsaf_read_dev(ddev,
2523                        DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
2524                p[439 + i] = dsaf_read_dev(ddev,
2525                        DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
2526                p[442 + i] = dsaf_read_dev(ddev,
2527                        DSAF_VOQ_BP_ALL_THRD_0_REG + j);
2528        }
2529
2530        /* dsaf tbl registers */
2531        p[445] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
2532        p[446] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
2533        p[447] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
2534        p[448] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
2535        p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
2536        p[450] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
2537        p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
2538        p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
2539        p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
2540        p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
2541        p[455] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
2542        p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
2543        p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
2544        p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
2545        p[459] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
2546        p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
2547        p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
2548        p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
2549        p[463] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
2550        p[464] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
2551        p[465] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
2552        p[466] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
2553        p[467] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
2554
2555        for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
2556                j = i * 0x8;
2557                p[468 + 2 * i] = dsaf_read_dev(ddev,
2558                        DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
2559                p[469 + 2 * i] = dsaf_read_dev(ddev,
2560                        DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
2561        }
2562
2563        p[484] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
2564        p[485] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
2565        p[486] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
2566        p[487] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
2567        p[488] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
2568        p[489] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
2569        p[490] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
2570        p[491] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
2571        p[492] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
2572        p[493] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
2573        p[494] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
2574        p[495] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
2575
2576        /* dsaf other registers */
2577        p[496] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
2578        p[497] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
2579        p[498] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
2580        p[499] = dsaf_read_dev(ddev,
2581                DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
2582        p[500] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
2583        p[501] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
2584
2585        if (!is_ver1)
2586                p[502] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
2587
2588        /* mark end of dsaf regs */
2589        for (i = 503; i < 504; i++)
2590                p[i] = 0xdddddddd;
2591}
2592
2593static char *hns_dsaf_get_node_stats_strings(char *data, int node,
2594                                             struct dsaf_device *dsaf_dev)
2595{
2596        char *buff = data;
2597        int i;
2598        bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2599
2600        snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node);
2601        buff += ETH_GSTRING_LEN;
2602        snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node);
2603        buff += ETH_GSTRING_LEN;
2604        snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node);
2605        buff += ETH_GSTRING_LEN;
2606        snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node);
2607        buff += ETH_GSTRING_LEN;
2608        snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node);
2609        buff += ETH_GSTRING_LEN;
2610        snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node);
2611        buff += ETH_GSTRING_LEN;
2612        snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node);
2613        buff += ETH_GSTRING_LEN;
2614        snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node);
2615        buff += ETH_GSTRING_LEN;
2616        snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node);
2617        buff += ETH_GSTRING_LEN;
2618        snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node);
2619        buff += ETH_GSTRING_LEN;
2620        snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node);
2621        buff += ETH_GSTRING_LEN;
2622        snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node);
2623        buff += ETH_GSTRING_LEN;
2624        snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node);
2625        buff += ETH_GSTRING_LEN;
2626        if (node < DSAF_SERVICE_NW_NUM && !is_ver1) {
2627                for (i = 0; i < DSAF_PRIO_NR; i++) {
2628                        snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2629                                 ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts",
2630                                 node, i);
2631                        snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2632                                 ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts",
2633                                 node, i);
2634                        buff += ETH_GSTRING_LEN;
2635                }
2636                buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN;
2637        }
2638        snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node);
2639        buff += ETH_GSTRING_LEN;
2640
2641        return buff;
2642}
2643
2644static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data,
2645                                    int node_num)
2646{
2647        u64 *p = data;
2648        int i;
2649        struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num];
2650        bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2651
2652        p[0] = hw_stats->pad_drop;
2653        p[1] = hw_stats->man_pkts;
2654        p[2] = hw_stats->rx_pkts;
2655        p[3] = hw_stats->rx_pkt_id;
2656        p[4] = hw_stats->rx_pause_frame;
2657        p[5] = hw_stats->release_buf_num;
2658        p[6] = hw_stats->sbm_drop;
2659        p[7] = hw_stats->crc_false;
2660        p[8] = hw_stats->bp_drop;
2661        p[9] = hw_stats->rslt_drop;
2662        p[10] = hw_stats->local_addr_false;
2663        p[11] = hw_stats->vlan_drop;
2664        p[12] = hw_stats->stp_drop;
2665        if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) {
2666                for (i = 0; i < DSAF_PRIO_NR; i++) {
2667                        p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i];
2668                        p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i];
2669                }
2670                p[29] = hw_stats->tx_pkts;
2671                return &p[30];
2672        }
2673
2674        p[13] = hw_stats->tx_pkts;
2675        return &p[14];
2676}
2677
2678/**
2679 *hns_dsaf_get_stats - get dsaf statistic
2680 *@ddev: dsaf device
2681 *@data:statistic value
2682 *@port: port num
2683 */
2684void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port)
2685{
2686        u64 *p = data;
2687        int node_num = port;
2688
2689        /* for ge/xge node info */
2690        p = hns_dsaf_get_node_stats(ddev, p, node_num);
2691
2692        /* for ppe node info */
2693        node_num = port + DSAF_PPE_INODE_BASE;
2694        (void)hns_dsaf_get_node_stats(ddev, p, node_num);
2695}
2696
2697/**
2698 *hns_dsaf_get_sset_count - get dsaf string set count
2699 *@dsaf_dev: dsaf device
2700 *@stringset: type of values in data
2701 *return dsaf string name count
2702 */
2703int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset)
2704{
2705        bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2706
2707        if (stringset == ETH_SS_STATS) {
2708                if (is_ver1)
2709                        return DSAF_STATIC_NUM;
2710                else
2711                        return DSAF_V2_STATIC_NUM;
2712        }
2713        return 0;
2714}
2715
2716/**
2717 *hns_dsaf_get_strings - get dsaf string set
2718 *@stringset:srting set index
2719 *@data:strings name value
2720 *@port:port index
2721 *@dsaf_dev: dsaf device
2722 */
2723void hns_dsaf_get_strings(int stringset, u8 *data, int port,
2724                          struct dsaf_device *dsaf_dev)
2725{
2726        char *buff = (char *)data;
2727        int node = port;
2728
2729        if (stringset != ETH_SS_STATS)
2730                return;
2731
2732        /* for ge/xge node info */
2733        buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2734
2735        /* for ppe node info */
2736        node = port + DSAF_PPE_INODE_BASE;
2737        (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2738}
2739
2740/**
2741 *hns_dsaf_get_regs_count - get dsaf regs count
2742 *return dsaf regs count
2743 */
2744int hns_dsaf_get_regs_count(void)
2745{
2746        return DSAF_DUMP_REGS_NUM;
2747}
2748
2749static int hns_dsaf_get_port_id(u8 port)
2750{
2751        if (port < DSAF_SERVICE_NW_NUM)
2752                return port;
2753
2754        if (port >= DSAF_BASE_INNER_PORT_NUM)
2755                return port - DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
2756
2757        return -EINVAL;
2758}
2759
2760static void set_promisc_tcam_enable(struct dsaf_device *dsaf_dev, u32 port)
2761{
2762        struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 1, 0, 0, 0x80};
2763        struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port};
2764        struct dsaf_tbl_tcam_data tbl_tcam_mask_uc = {0x01000000, 0xf};
2765        struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} };
2766        struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2767        struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, port};
2768        struct dsaf_drv_mac_single_dest_entry mask_entry;
2769        struct dsaf_drv_tbl_tcam_key temp_key, mask_key;
2770        struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2771        u16 entry_index;
2772        struct dsaf_drv_tbl_tcam_key mac_key;
2773        struct hns_mac_cb *mac_cb;
2774        u8 addr[ETH_ALEN] = {0};
2775        u8 port_num;
2776        int mskid;
2777
2778        /* promisc use vague table match with vlanid = 0 & macaddr = 0 */
2779        hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2780        entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2781        if (entry_index != DSAF_INVALID_ENTRY_IDX)
2782                return;
2783
2784        /* put promisc tcam entry in the end. */
2785        /* 1. set promisc unicast vague tcam entry. */
2786        entry_index = hns_dsaf_find_empty_mac_entry_reverse(dsaf_dev);
2787        if (entry_index == DSAF_INVALID_ENTRY_IDX) {
2788                dev_err(dsaf_dev->dev,
2789                        "enable uc promisc failed (port:%#x)\n",
2790                        port);
2791                return;
2792        }
2793
2794        mac_cb = dsaf_dev->mac_cb[port];
2795        (void)hns_mac_get_inner_port_num(mac_cb, 0, &port_num);
2796        tbl_tcam_ucast.tbl_ucast_out_port = port_num;
2797
2798        /* config uc vague table */
2799        hns_dsaf_tcam_uc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_uc,
2800                                   &tbl_tcam_mask_uc, &tbl_tcam_ucast);
2801
2802        /* update software entry */
2803        soft_mac_entry = priv->soft_mac_tbl;
2804        soft_mac_entry += entry_index;
2805        soft_mac_entry->index = entry_index;
2806        soft_mac_entry->tcam_key.high.val = mac_key.high.val;
2807        soft_mac_entry->tcam_key.low.val = mac_key.low.val;
2808        /* step back to the START for mc. */
2809        soft_mac_entry = priv->soft_mac_tbl;
2810
2811        /* 2. set promisc multicast vague tcam entry. */
2812        entry_index = hns_dsaf_find_empty_mac_entry_reverse(dsaf_dev);
2813        if (entry_index == DSAF_INVALID_ENTRY_IDX) {
2814                dev_err(dsaf_dev->dev,
2815                        "enable mc promisc failed (port:%#x)\n",
2816                        port);
2817                return;
2818        }
2819
2820        memset(&mask_entry, 0x0, sizeof(mask_entry));
2821        memset(&mask_key, 0x0, sizeof(mask_key));
2822        memset(&temp_key, 0x0, sizeof(temp_key));
2823        mask_entry.addr[0] = 0x01;
2824        hns_dsaf_set_mac_key(dsaf_dev, &mask_key, mask_entry.in_vlan_id,
2825                             0xf, mask_entry.addr);
2826        tbl_tcam_mcast.tbl_mcast_item_vld = 1;
2827        tbl_tcam_mcast.tbl_mcast_old_en = 0;
2828
2829        /* set MAC port to handle multicast */
2830        mskid = hns_dsaf_get_port_id(port);
2831        if (mskid == -EINVAL) {
2832                dev_err(dsaf_dev->dev, "%s,pnum(%d)error,key(%#x:%#x)\n",
2833                        dsaf_dev->ae_dev.name, port,
2834                        mask_key.high.val, mask_key.low.val);
2835                return;
2836        }
2837        dsaf_set_bit(tbl_tcam_mcast.tbl_mcast_port_msk[mskid / 32],
2838                     mskid % 32, 1);
2839
2840        /* set pool bit map to handle multicast */
2841        mskid = hns_dsaf_get_port_id(port_num);
2842        if (mskid == -EINVAL) {
2843                dev_err(dsaf_dev->dev,
2844                        "%s, pool bit map pnum(%d)error,key(%#x:%#x)\n",
2845                        dsaf_dev->ae_dev.name, port_num,
2846                        mask_key.high.val, mask_key.low.val);
2847                return;
2848        }
2849        dsaf_set_bit(tbl_tcam_mcast.tbl_mcast_port_msk[mskid / 32],
2850                     mskid % 32, 1);
2851
2852        memcpy(&temp_key, &mask_key, sizeof(mask_key));
2853        hns_dsaf_tcam_mc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_mc,
2854                                   (struct dsaf_tbl_tcam_data *)(&mask_key),
2855                                   &tbl_tcam_mcast);
2856
2857        /* update software entry */
2858        soft_mac_entry += entry_index;
2859        soft_mac_entry->index = entry_index;
2860        soft_mac_entry->tcam_key.high.val = temp_key.high.val;
2861        soft_mac_entry->tcam_key.low.val = temp_key.low.val;
2862}
2863
2864static void set_promisc_tcam_disable(struct dsaf_device *dsaf_dev, u32 port)
2865{
2866        struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port};
2867        struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 0, 0, 0, 0};
2868        struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} };
2869        struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2870        struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, 0};
2871        struct dsaf_tbl_tcam_data tbl_tcam_mask = {0, 0};
2872        struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2873        u16 entry_index;
2874        struct dsaf_drv_tbl_tcam_key mac_key;
2875        u8 addr[ETH_ALEN] = {0};
2876
2877        /* 1. delete uc vague tcam entry. */
2878        /* promisc use vague table match with vlanid = 0 & macaddr = 0 */
2879        hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2880        entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2881
2882        if (entry_index == DSAF_INVALID_ENTRY_IDX)
2883                return;
2884
2885        /* config uc vague table */
2886        hns_dsaf_tcam_uc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_uc,
2887                                   &tbl_tcam_mask, &tbl_tcam_ucast);
2888        /* update soft management table. */
2889        soft_mac_entry = priv->soft_mac_tbl;
2890        soft_mac_entry += entry_index;
2891        soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2892        /* step back to the START for mc. */
2893        soft_mac_entry = priv->soft_mac_tbl;
2894
2895        /* 2. delete mc vague tcam entry. */
2896        addr[0] = 0x01;
2897        memset(&mac_key, 0x0, sizeof(mac_key));
2898        hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2899        entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2900
2901        if (entry_index == DSAF_INVALID_ENTRY_IDX)
2902                return;
2903
2904        /* config mc vague table */
2905        hns_dsaf_tcam_mc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_mc,
2906                                   &tbl_tcam_mask, &tbl_tcam_mcast);
2907        /* update soft management table. */
2908        soft_mac_entry += entry_index;
2909        soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2910}
2911
2912/* Reserve the last TCAM entry for promisc support */
2913void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
2914                               u32 port, bool enable)
2915{
2916        if (enable)
2917                set_promisc_tcam_enable(dsaf_dev, port);
2918        else
2919                set_promisc_tcam_disable(dsaf_dev, port);
2920}
2921
2922int hns_dsaf_wait_pkt_clean(struct dsaf_device *dsaf_dev, int port)
2923{
2924        u32 val, val_tmp;
2925        int wait_cnt;
2926
2927        if (port >= DSAF_SERVICE_NW_NUM)
2928                return 0;
2929
2930        wait_cnt = 0;
2931        while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
2932                val = dsaf_read_dev(dsaf_dev, DSAF_VOQ_IN_PKT_NUM_0_REG +
2933                        (port + DSAF_XGE_NUM) * 0x40);
2934                val_tmp = dsaf_read_dev(dsaf_dev, DSAF_VOQ_OUT_PKT_NUM_0_REG +
2935                        (port + DSAF_XGE_NUM) * 0x40);
2936                if (val == val_tmp)
2937                        break;
2938
2939                usleep_range(100, 200);
2940        }
2941
2942        if (wait_cnt >= HNS_MAX_WAIT_CNT) {
2943                dev_err(dsaf_dev->dev, "hns dsaf clean wait timeout(%u - %u).\n",
2944                        val, val_tmp);
2945                return -EBUSY;
2946        }
2947
2948        return 0;
2949}
2950
2951/**
2952 * hns_dsaf_probe - probo dsaf dev
2953 * @pdev: dasf platform device
2954 * return 0 - success , negative --fail
2955 */
2956static int hns_dsaf_probe(struct platform_device *pdev)
2957{
2958        struct dsaf_device *dsaf_dev;
2959        int ret;
2960
2961        dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv));
2962        if (IS_ERR(dsaf_dev)) {
2963                ret = PTR_ERR(dsaf_dev);
2964                dev_err(&pdev->dev,
2965                        "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret);
2966                return ret;
2967        }
2968
2969        ret = hns_dsaf_get_cfg(dsaf_dev);
2970        if (ret)
2971                goto free_dev;
2972
2973        ret = hns_dsaf_init(dsaf_dev);
2974        if (ret)
2975                goto free_dev;
2976
2977        ret = hns_mac_init(dsaf_dev);
2978        if (ret)
2979                goto uninit_dsaf;
2980
2981        ret = hns_ppe_init(dsaf_dev);
2982        if (ret)
2983                goto uninit_mac;
2984
2985        ret = hns_dsaf_ae_init(dsaf_dev);
2986        if (ret)
2987                goto uninit_ppe;
2988
2989        return 0;
2990
2991uninit_ppe:
2992        hns_ppe_uninit(dsaf_dev);
2993
2994uninit_mac:
2995        hns_mac_uninit(dsaf_dev);
2996
2997uninit_dsaf:
2998        hns_dsaf_free(dsaf_dev);
2999
3000free_dev:
3001        hns_dsaf_free_dev(dsaf_dev);
3002
3003        return ret;
3004}
3005
3006/**
3007 * hns_dsaf_remove - remove dsaf dev
3008 * @pdev: dasf platform device
3009 */
3010static int hns_dsaf_remove(struct platform_device *pdev)
3011{
3012        struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev);
3013
3014        hns_dsaf_ae_uninit(dsaf_dev);
3015
3016        hns_ppe_uninit(dsaf_dev);
3017
3018        hns_mac_uninit(dsaf_dev);
3019
3020        hns_dsaf_free(dsaf_dev);
3021
3022        hns_dsaf_free_dev(dsaf_dev);
3023
3024        return 0;
3025}
3026
3027static const struct of_device_id g_dsaf_match[] = {
3028        {.compatible = "hisilicon,hns-dsaf-v1"},
3029        {.compatible = "hisilicon,hns-dsaf-v2"},
3030        {}
3031};
3032MODULE_DEVICE_TABLE(of, g_dsaf_match);
3033
3034static struct platform_driver g_dsaf_driver = {
3035        .probe = hns_dsaf_probe,
3036        .remove = hns_dsaf_remove,
3037        .driver = {
3038                .name = DSAF_DRV_NAME,
3039                .of_match_table = g_dsaf_match,
3040                .acpi_match_table = hns_dsaf_acpi_match,
3041        },
3042};
3043
3044module_platform_driver(g_dsaf_driver);
3045
3046/**
3047 * hns_dsaf_roce_reset - reset dsaf and roce
3048 * @dsaf_fwnode: Pointer to framework node for the dasf
3049 * @dereset: false - request reset , true - drop reset
3050 * return 0 - success , negative -fail
3051 */
3052int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)
3053{
3054        struct dsaf_device *dsaf_dev;
3055        struct platform_device *pdev;
3056        u32 mp;
3057        u32 sl;
3058        u32 credit;
3059        int i;
3060        static const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
3061                {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
3062                {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
3063                {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
3064                {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
3065                {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
3066                {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
3067                {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
3068                {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
3069        };
3070        static const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
3071                {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
3072                {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
3073                {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
3074                {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
3075                {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
3076                {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
3077                {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
3078                {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
3079        };
3080
3081        /* find the platform device corresponding to fwnode */
3082        if (is_of_node(dsaf_fwnode)) {
3083                pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
3084        } else if (is_acpi_device_node(dsaf_fwnode)) {
3085                pdev = hns_dsaf_find_platform_device(dsaf_fwnode);
3086        } else {
3087                pr_err("fwnode is neither OF or ACPI type\n");
3088                return -EINVAL;
3089        }
3090
3091        /* check if we were a success in fetching pdev */
3092        if (!pdev) {
3093                pr_err("couldn't find platform device for node\n");
3094                return -ENODEV;
3095        }
3096
3097        /* retrieve the dsaf_device from the driver data */
3098        dsaf_dev = dev_get_drvdata(&pdev->dev);
3099        if (!dsaf_dev) {
3100                dev_err(&pdev->dev, "dsaf_dev is NULL\n");
3101                put_device(&pdev->dev);
3102                return -ENODEV;
3103        }
3104
3105        /* now, make sure we are running on compatible SoC */
3106        if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
3107                dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
3108                        dsaf_dev->ae_dev.name);
3109                put_device(&pdev->dev);
3110                return -ENODEV;
3111        }
3112
3113        /* do reset or de-reset according to the flag */
3114        if (!dereset) {
3115                /* reset rocee-channels in dsaf and rocee */
3116                dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
3117                                                      false);
3118                dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);
3119        } else {
3120                /* configure dsaf tx roce correspond to port map and sl map */
3121                mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
3122                for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
3123                        dsaf_set_field(mp, 7 << i * 3, i * 3,
3124                                       port_map[i][DSAF_ROCE_6PORT_MODE]);
3125                dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
3126                dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
3127
3128                sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
3129                for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
3130                        dsaf_set_field(sl, 3 << i * 2, i * 2,
3131                                       sl_map[i][DSAF_ROCE_6PORT_MODE]);
3132                dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
3133
3134                /* de-reset rocee-channels in dsaf and rocee */
3135                dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
3136                                                      true);
3137                msleep(SRST_TIME_INTERVAL);
3138                dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);
3139
3140                /* enable dsaf channel rocee credit */
3141                credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
3142                dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
3143                dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
3144
3145                dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
3146                dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
3147        }
3148
3149        put_device(&pdev->dev);
3150
3151        return 0;
3152}
3153EXPORT_SYMBOL(hns_dsaf_roce_reset);
3154
3155MODULE_LICENSE("GPL");
3156MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3157MODULE_DESCRIPTION("HNS DSAF driver");
3158MODULE_VERSION(DSAF_MOD_VERSION);
3159
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.