linux/drivers/net/ethernet/freescale/gianfar.h
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   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * drivers/net/ethernet/freescale/gianfar.h
   4 *
   5 * Gianfar Ethernet Driver
   6 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
   7 * Based on 8260_io/fcc_enet.c
   8 *
   9 * Author: Andy Fleming
  10 * Maintainer: Kumar Gala
  11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12 *
  13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  14 *
  15 *  Still left to do:
  16 *      -Add support for module parameters
  17 *      -Add patch for ethtool phys id
  18 */
  19#ifndef __GIANFAR_H
  20#define __GIANFAR_H
  21
  22#include <linux/kernel.h>
  23#include <linux/sched.h>
  24#include <linux/string.h>
  25#include <linux/errno.h>
  26#include <linux/slab.h>
  27#include <linux/interrupt.h>
  28#include <linux/delay.h>
  29#include <linux/netdevice.h>
  30#include <linux/etherdevice.h>
  31#include <linux/skbuff.h>
  32#include <linux/spinlock.h>
  33#include <linux/mm.h>
  34#include <linux/mii.h>
  35#include <linux/phy.h>
  36
  37#include <asm/io.h>
  38#include <asm/irq.h>
  39#include <linux/uaccess.h>
  40#include <linux/module.h>
  41#include <linux/crc32.h>
  42#include <linux/workqueue.h>
  43#include <linux/ethtool.h>
  44
  45struct ethtool_flow_spec_container {
  46        struct ethtool_rx_flow_spec fs;
  47        struct list_head list;
  48};
  49
  50struct ethtool_rx_list {
  51        struct list_head list;
  52        unsigned int count;
  53};
  54
  55/* The maximum number of packets to be handled in one call of gfar_poll */
  56#define GFAR_DEV_WEIGHT 64
  57
  58/* Length for FCB */
  59#define GMAC_FCB_LEN 8
  60
  61/* Length for TxPAL */
  62#define GMAC_TXPAL_LEN 16
  63
  64/* Default padding amount */
  65#define DEFAULT_PADDING 2
  66
  67/* Number of bytes to align the rx bufs to */
  68#define RXBUF_ALIGNMENT 64
  69
  70#define DRV_NAME "gfar-enet"
  71
  72/* MAXIMUM NUMBER OF QUEUES SUPPORTED */
  73#define MAX_TX_QS       0x8
  74#define MAX_RX_QS       0x8
  75
  76/* MAXIMUM NUMBER OF GROUPS SUPPORTED */
  77#define MAXGROUPS 0x2
  78
  79/* These need to be powers of 2 for this driver */
  80#define DEFAULT_TX_RING_SIZE    256
  81#define DEFAULT_RX_RING_SIZE    256
  82
  83#define GFAR_RX_BUFF_ALLOC      16
  84
  85#define GFAR_RX_MAX_RING_SIZE   256
  86#define GFAR_TX_MAX_RING_SIZE   256
  87
  88#define FBTHR_SHIFT        24
  89#define DEFAULT_RX_LFC_THR  16
  90#define DEFAULT_LFC_PTVVAL  4
  91
  92#define GFAR_RXB_TRUESIZE 2048
  93#define GFAR_SKBFRAG_OVR (RXBUF_ALIGNMENT \
  94                          + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
  95#define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
  96#define GFAR_SKBFRAG_SIZE (GFAR_RXB_SIZE + GFAR_SKBFRAG_OVR)
  97
  98#define TX_RING_MOD_MASK(size) (size-1)
  99#define RX_RING_MOD_MASK(size) (size-1)
 100#define GFAR_JUMBO_FRAME_SIZE 9600
 101
 102#define DEFAULT_FIFO_TX_THR 0x100
 103#define DEFAULT_FIFO_TX_STARVE 0x40
 104#define DEFAULT_FIFO_TX_STARVE_OFF 0x80
 105
 106/* The number of Exact Match registers */
 107#define GFAR_EM_NUM     15
 108
 109/* Latency of interface clock in nanoseconds */
 110/* Interface clock latency , in this case, means the
 111 * time described by a value of 1 in the interrupt
 112 * coalescing registers' time fields.  Since those fields
 113 * refer to the time it takes for 64 clocks to pass, the
 114 * latencies are as such:
 115 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
 116 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
 117 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
 118 */
 119#define GFAR_GBIT_TIME  512
 120#define GFAR_100_TIME   2560
 121#define GFAR_10_TIME    25600
 122
 123#define DEFAULT_TX_COALESCE 1
 124#define DEFAULT_TXCOUNT 16
 125#define DEFAULT_TXTIME  21
 126
 127#define DEFAULT_RXTIME  21
 128
 129#define DEFAULT_RX_COALESCE 0
 130#define DEFAULT_RXCOUNT 0
 131
 132/* TBI register addresses */
 133#define MII_TBICON              0x11
 134
 135/* TBICON register bit fields */
 136#define TBICON_CLK_SELECT       0x0020
 137
 138/* MAC register bits */
 139#define MACCFG1_SOFT_RESET      0x80000000
 140#define MACCFG1_RESET_RX_MC     0x00080000
 141#define MACCFG1_RESET_TX_MC     0x00040000
 142#define MACCFG1_RESET_RX_FUN    0x00020000
 143#define MACCFG1_RESET_TX_FUN    0x00010000
 144#define MACCFG1_LOOPBACK        0x00000100
 145#define MACCFG1_RX_FLOW         0x00000020
 146#define MACCFG1_TX_FLOW         0x00000010
 147#define MACCFG1_SYNCD_RX_EN     0x00000008
 148#define MACCFG1_RX_EN           0x00000004
 149#define MACCFG1_SYNCD_TX_EN     0x00000002
 150#define MACCFG1_TX_EN           0x00000001
 151
 152#define MACCFG2_INIT_SETTINGS   0x00007205
 153#define MACCFG2_FULL_DUPLEX     0x00000001
 154#define MACCFG2_IF              0x00000300
 155#define MACCFG2_MII             0x00000100
 156#define MACCFG2_GMII            0x00000200
 157#define MACCFG2_HUGEFRAME       0x00000020
 158#define MACCFG2_LENGTHCHECK     0x00000010
 159#define MACCFG2_MPEN            0x00000008
 160
 161#define ECNTRL_FIFM             0x00008000
 162#define ECNTRL_INIT_SETTINGS    0x00001000
 163#define ECNTRL_TBI_MODE         0x00000020
 164#define ECNTRL_REDUCED_MODE     0x00000010
 165#define ECNTRL_R100             0x00000008
 166#define ECNTRL_REDUCED_MII_MODE 0x00000004
 167#define ECNTRL_SGMII_MODE       0x00000002
 168
 169#define MINFLR_INIT_SETTINGS    0x00000040
 170
 171/* Tqueue control */
 172#define TQUEUE_EN0              0x00008000
 173#define TQUEUE_EN1              0x00004000
 174#define TQUEUE_EN2              0x00002000
 175#define TQUEUE_EN3              0x00001000
 176#define TQUEUE_EN4              0x00000800
 177#define TQUEUE_EN5              0x00000400
 178#define TQUEUE_EN6              0x00000200
 179#define TQUEUE_EN7              0x00000100
 180#define TQUEUE_EN_ALL           0x0000FF00
 181
 182#define TR03WT_WT0_MASK         0xFF000000
 183#define TR03WT_WT1_MASK         0x00FF0000
 184#define TR03WT_WT2_MASK         0x0000FF00
 185#define TR03WT_WT3_MASK         0x000000FF
 186
 187#define TR47WT_WT4_MASK         0xFF000000
 188#define TR47WT_WT5_MASK         0x00FF0000
 189#define TR47WT_WT6_MASK         0x0000FF00
 190#define TR47WT_WT7_MASK         0x000000FF
 191
 192/* Rqueue control */
 193#define RQUEUE_EX0              0x00800000
 194#define RQUEUE_EX1              0x00400000
 195#define RQUEUE_EX2              0x00200000
 196#define RQUEUE_EX3              0x00100000
 197#define RQUEUE_EX4              0x00080000
 198#define RQUEUE_EX5              0x00040000
 199#define RQUEUE_EX6              0x00020000
 200#define RQUEUE_EX7              0x00010000
 201#define RQUEUE_EX_ALL           0x00FF0000
 202
 203#define RQUEUE_EN0              0x00000080
 204#define RQUEUE_EN1              0x00000040
 205#define RQUEUE_EN2              0x00000020
 206#define RQUEUE_EN3              0x00000010
 207#define RQUEUE_EN4              0x00000008
 208#define RQUEUE_EN5              0x00000004
 209#define RQUEUE_EN6              0x00000002
 210#define RQUEUE_EN7              0x00000001
 211#define RQUEUE_EN_ALL           0x000000FF
 212
 213/* Init to do tx snooping for buffers and descriptors */
 214#define DMACTRL_INIT_SETTINGS   0x000000c3
 215#define DMACTRL_GRS             0x00000010
 216#define DMACTRL_GTS             0x00000008
 217
 218#define TSTAT_CLEAR_THALT_ALL   0xFF000000
 219#define TSTAT_CLEAR_THALT       0x80000000
 220#define TSTAT_CLEAR_THALT0      0x80000000
 221#define TSTAT_CLEAR_THALT1      0x40000000
 222#define TSTAT_CLEAR_THALT2      0x20000000
 223#define TSTAT_CLEAR_THALT3      0x10000000
 224#define TSTAT_CLEAR_THALT4      0x08000000
 225#define TSTAT_CLEAR_THALT5      0x04000000
 226#define TSTAT_CLEAR_THALT6      0x02000000
 227#define TSTAT_CLEAR_THALT7      0x01000000
 228
 229/* Interrupt coalescing macros */
 230#define IC_ICEN                 0x80000000
 231#define IC_ICFT_MASK            0x1fe00000
 232#define IC_ICFT_SHIFT           21
 233#define mk_ic_icft(x)           \
 234        (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
 235#define IC_ICTT_MASK            0x0000ffff
 236#define mk_ic_ictt(x)           (x&IC_ICTT_MASK)
 237
 238#define mk_ic_value(count, time) (IC_ICEN | \
 239                                mk_ic_icft(count) | \
 240                                mk_ic_ictt(time))
 241#define get_icft_value(ic)      (((unsigned long)ic & IC_ICFT_MASK) >> \
 242                                 IC_ICFT_SHIFT)
 243#define get_ictt_value(ic)      ((unsigned long)ic & IC_ICTT_MASK)
 244
 245#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
 246#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
 247
 248#define RCTRL_TS_ENABLE         0x01000000
 249#define RCTRL_PAL_MASK          0x001f0000
 250#define RCTRL_LFC               0x00004000
 251#define RCTRL_VLEX              0x00002000
 252#define RCTRL_FILREN            0x00001000
 253#define RCTRL_GHTX              0x00000400
 254#define RCTRL_IPCSEN            0x00000200
 255#define RCTRL_TUCSEN            0x00000100
 256#define RCTRL_PRSDEP_MASK       0x000000c0
 257#define RCTRL_PRSDEP_INIT       0x000000c0
 258#define RCTRL_PRSFM             0x00000020
 259#define RCTRL_PROM              0x00000008
 260#define RCTRL_EMEN              0x00000002
 261#define RCTRL_REQ_PARSER        (RCTRL_VLEX | RCTRL_IPCSEN | \
 262                                 RCTRL_TUCSEN | RCTRL_FILREN)
 263#define RCTRL_CHECKSUMMING      (RCTRL_IPCSEN | RCTRL_TUCSEN | \
 264                                RCTRL_PRSDEP_INIT)
 265#define RCTRL_EXTHASH           (RCTRL_GHTX)
 266#define RCTRL_VLAN              (RCTRL_PRSDEP_INIT)
 267#define RCTRL_PADDING(x)        ((x << 16) & RCTRL_PAL_MASK)
 268
 269
 270#define RSTAT_CLEAR_RHALT       0x00800000
 271#define RSTAT_CLEAR_RXF0        0x00000080
 272#define RSTAT_RXF_MASK          0x000000ff
 273
 274#define TCTRL_IPCSEN            0x00004000
 275#define TCTRL_TUCSEN            0x00002000
 276#define TCTRL_VLINS             0x00001000
 277#define TCTRL_THDF              0x00000800
 278#define TCTRL_RFCPAUSE          0x00000010
 279#define TCTRL_TFCPAUSE          0x00000008
 280#define TCTRL_TXSCHED_MASK      0x00000006
 281#define TCTRL_TXSCHED_INIT      0x00000000
 282/* priority scheduling */
 283#define TCTRL_TXSCHED_PRIO      0x00000002
 284/* weighted round-robin scheduling (WRRS) */
 285#define TCTRL_TXSCHED_WRRS      0x00000004
 286/* default WRRS weight and policy setting,
 287 * tailored to the tr03wt and tr47wt registers:
 288 * equal weight for all Tx Qs, measured in 64byte units
 289 */
 290#define DEFAULT_WRRS_WEIGHT     0x18181818
 291
 292#define TCTRL_INIT_CSUM         (TCTRL_TUCSEN | TCTRL_IPCSEN)
 293
 294#define IEVENT_INIT_CLEAR       0xffffffff
 295#define IEVENT_BABR             0x80000000
 296#define IEVENT_RXC              0x40000000
 297#define IEVENT_BSY              0x20000000
 298#define IEVENT_EBERR            0x10000000
 299#define IEVENT_MSRO             0x04000000
 300#define IEVENT_GTSC             0x02000000
 301#define IEVENT_BABT             0x01000000
 302#define IEVENT_TXC              0x00800000
 303#define IEVENT_TXE              0x00400000
 304#define IEVENT_TXB              0x00200000
 305#define IEVENT_TXF              0x00100000
 306#define IEVENT_LC               0x00040000
 307#define IEVENT_CRL              0x00020000
 308#define IEVENT_XFUN             0x00010000
 309#define IEVENT_RXB0             0x00008000
 310#define IEVENT_MAG              0x00000800
 311#define IEVENT_GRSC             0x00000100
 312#define IEVENT_RXF0             0x00000080
 313#define IEVENT_FGPI             0x00000010
 314#define IEVENT_FIR              0x00000008
 315#define IEVENT_FIQ              0x00000004
 316#define IEVENT_DPE              0x00000002
 317#define IEVENT_PERR             0x00000001
 318#define IEVENT_RX_MASK          (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
 319#define IEVENT_TX_MASK          (IEVENT_TXB | IEVENT_TXF)
 320#define IEVENT_RTX_MASK         (IEVENT_RX_MASK | IEVENT_TX_MASK)
 321#define IEVENT_ERR_MASK         \
 322(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
 323 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
 324 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
 325 | IEVENT_MAG | IEVENT_BABR)
 326
 327#define IMASK_INIT_CLEAR        0x00000000
 328#define IMASK_BABR              0x80000000
 329#define IMASK_RXC               0x40000000
 330#define IMASK_BSY               0x20000000
 331#define IMASK_EBERR             0x10000000
 332#define IMASK_MSRO              0x04000000
 333#define IMASK_GTSC              0x02000000
 334#define IMASK_BABT              0x01000000
 335#define IMASK_TXC               0x00800000
 336#define IMASK_TXEEN             0x00400000
 337#define IMASK_TXBEN             0x00200000
 338#define IMASK_TXFEN             0x00100000
 339#define IMASK_LC                0x00040000
 340#define IMASK_CRL               0x00020000
 341#define IMASK_XFUN              0x00010000
 342#define IMASK_RXB0              0x00008000
 343#define IMASK_MAG               0x00000800
 344#define IMASK_GRSC              0x00000100
 345#define IMASK_RXFEN0            0x00000080
 346#define IMASK_FGPI              0x00000010
 347#define IMASK_FIR               0x00000008
 348#define IMASK_FIQ               0x00000004
 349#define IMASK_DPE               0x00000002
 350#define IMASK_PERR              0x00000001
 351#define IMASK_DEFAULT  (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
 352                IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
 353                IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
 354                | IMASK_PERR)
 355#define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY)
 356#define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN)
 357
 358#define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT)
 359#define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT)
 360
 361/* Attribute fields */
 362
 363/* This enables rx snooping for buffers and descriptors */
 364#define ATTR_BDSTASH            0x00000800
 365
 366#define ATTR_BUFSTASH           0x00004000
 367
 368#define ATTR_SNOOPING           0x000000c0
 369#define ATTR_INIT_SETTINGS      ATTR_SNOOPING
 370
 371#define ATTRELI_INIT_SETTINGS   0x0
 372#define ATTRELI_EL_MASK         0x3fff0000
 373#define ATTRELI_EL(x) (x << 16)
 374#define ATTRELI_EI_MASK         0x00003fff
 375#define ATTRELI_EI(x) (x)
 376
 377#define BD_LFLAG(flags) ((flags) << 16)
 378#define BD_LENGTH_MASK          0x0000ffff
 379
 380#define FPR_FILER_MASK  0xFFFFFFFF
 381#define MAX_FILER_IDX   0xFF
 382
 383/* This default RIR value directly corresponds
 384 * to the 3-bit hash value generated */
 385#define DEFAULT_8RXQ_RIR0       0x05397700
 386/* Map even hash values to Q0, and odd ones to Q1 */
 387#define DEFAULT_2RXQ_RIR0       0x04104100
 388
 389/* RQFCR register bits */
 390#define RQFCR_GPI               0x80000000
 391#define RQFCR_HASHTBL_Q         0x00000000
 392#define RQFCR_HASHTBL_0         0x00020000
 393#define RQFCR_HASHTBL_1         0x00040000
 394#define RQFCR_HASHTBL_2         0x00060000
 395#define RQFCR_HASHTBL_3         0x00080000
 396#define RQFCR_HASH              0x00010000
 397#define RQFCR_QUEUE             0x0000FC00
 398#define RQFCR_CLE               0x00000200
 399#define RQFCR_RJE               0x00000100
 400#define RQFCR_AND               0x00000080
 401#define RQFCR_CMP_EXACT         0x00000000
 402#define RQFCR_CMP_MATCH         0x00000020
 403#define RQFCR_CMP_NOEXACT       0x00000040
 404#define RQFCR_CMP_NOMATCH       0x00000060
 405
 406/* RQFCR PID values */
 407#define RQFCR_PID_MASK          0x00000000
 408#define RQFCR_PID_PARSE         0x00000001
 409#define RQFCR_PID_ARB           0x00000002
 410#define RQFCR_PID_DAH           0x00000003
 411#define RQFCR_PID_DAL           0x00000004
 412#define RQFCR_PID_SAH           0x00000005
 413#define RQFCR_PID_SAL           0x00000006
 414#define RQFCR_PID_ETY           0x00000007
 415#define RQFCR_PID_VID           0x00000008
 416#define RQFCR_PID_PRI           0x00000009
 417#define RQFCR_PID_TOS           0x0000000A
 418#define RQFCR_PID_L4P           0x0000000B
 419#define RQFCR_PID_DIA           0x0000000C
 420#define RQFCR_PID_SIA           0x0000000D
 421#define RQFCR_PID_DPT           0x0000000E
 422#define RQFCR_PID_SPT           0x0000000F
 423
 424/* RQFPR when PID is 0x0001 */
 425#define RQFPR_HDR_GE_512        0x00200000
 426#define RQFPR_LERR              0x00100000
 427#define RQFPR_RAR               0x00080000
 428#define RQFPR_RARQ              0x00040000
 429#define RQFPR_AR                0x00020000
 430#define RQFPR_ARQ               0x00010000
 431#define RQFPR_EBC               0x00008000
 432#define RQFPR_VLN               0x00004000
 433#define RQFPR_CFI               0x00002000
 434#define RQFPR_JUM               0x00001000
 435#define RQFPR_IPF               0x00000800
 436#define RQFPR_FIF               0x00000400
 437#define RQFPR_IPV4              0x00000200
 438#define RQFPR_IPV6              0x00000100
 439#define RQFPR_ICC               0x00000080
 440#define RQFPR_ICV               0x00000040
 441#define RQFPR_TCP               0x00000020
 442#define RQFPR_UDP               0x00000010
 443#define RQFPR_TUC               0x00000008
 444#define RQFPR_TUV               0x00000004
 445#define RQFPR_PER               0x00000002
 446#define RQFPR_EER               0x00000001
 447
 448/* CAR1 bits */
 449#define CAR1_C164               0x80000000
 450#define CAR1_C1127              0x40000000
 451#define CAR1_C1255              0x20000000
 452#define CAR1_C1511              0x10000000
 453#define CAR1_C11K               0x08000000
 454#define CAR1_C1MAX              0x04000000
 455#define CAR1_C1MGV              0x02000000
 456#define CAR1_C1REJ              0x00020000
 457#define CAR1_C1RBY              0x00010000
 458#define CAR1_C1RPK              0x00008000
 459#define CAR1_C1RFC              0x00004000
 460#define CAR1_C1RMC              0x00002000
 461#define CAR1_C1RBC              0x00001000
 462#define CAR1_C1RXC              0x00000800
 463#define CAR1_C1RXP              0x00000400
 464#define CAR1_C1RXU              0x00000200
 465#define CAR1_C1RAL              0x00000100
 466#define CAR1_C1RFL              0x00000080
 467#define CAR1_C1RCD              0x00000040
 468#define CAR1_C1RCS              0x00000020
 469#define CAR1_C1RUN              0x00000010
 470#define CAR1_C1ROV              0x00000008
 471#define CAR1_C1RFR              0x00000004
 472#define CAR1_C1RJB              0x00000002
 473#define CAR1_C1RDR              0x00000001
 474
 475/* CAM1 bits */
 476#define CAM1_M164               0x80000000
 477#define CAM1_M1127              0x40000000
 478#define CAM1_M1255              0x20000000
 479#define CAM1_M1511              0x10000000
 480#define CAM1_M11K               0x08000000
 481#define CAM1_M1MAX              0x04000000
 482#define CAM1_M1MGV              0x02000000
 483#define CAM1_M1REJ              0x00020000
 484#define CAM1_M1RBY              0x00010000
 485#define CAM1_M1RPK              0x00008000
 486#define CAM1_M1RFC              0x00004000
 487#define CAM1_M1RMC              0x00002000
 488#define CAM1_M1RBC              0x00001000
 489#define CAM1_M1RXC              0x00000800
 490#define CAM1_M1RXP              0x00000400
 491#define CAM1_M1RXU              0x00000200
 492#define CAM1_M1RAL              0x00000100
 493#define CAM1_M1RFL              0x00000080
 494#define CAM1_M1RCD              0x00000040
 495#define CAM1_M1RCS              0x00000020
 496#define CAM1_M1RUN              0x00000010
 497#define CAM1_M1ROV              0x00000008
 498#define CAM1_M1RFR              0x00000004
 499#define CAM1_M1RJB              0x00000002
 500#define CAM1_M1RDR              0x00000001
 501
 502/* TxBD status field bits */
 503#define TXBD_READY              0x8000
 504#define TXBD_PADCRC             0x4000
 505#define TXBD_WRAP               0x2000
 506#define TXBD_INTERRUPT          0x1000
 507#define TXBD_LAST               0x0800
 508#define TXBD_CRC                0x0400
 509#define TXBD_DEF                0x0200
 510#define TXBD_HUGEFRAME          0x0080
 511#define TXBD_LATECOLLISION      0x0080
 512#define TXBD_RETRYLIMIT         0x0040
 513#define TXBD_RETRYCOUNTMASK     0x003c
 514#define TXBD_UNDERRUN           0x0002
 515#define TXBD_TOE                0x0002
 516
 517/* Tx FCB param bits */
 518#define TXFCB_VLN               0x80
 519#define TXFCB_IP                0x40
 520#define TXFCB_IP6               0x20
 521#define TXFCB_TUP               0x10
 522#define TXFCB_UDP               0x08
 523#define TXFCB_CIP               0x04
 524#define TXFCB_CTU               0x02
 525#define TXFCB_NPH               0x01
 526#define TXFCB_DEFAULT           (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
 527
 528/* RxBD status field bits */
 529#define RXBD_EMPTY              0x8000
 530#define RXBD_RO1                0x4000
 531#define RXBD_WRAP               0x2000
 532#define RXBD_INTERRUPT          0x1000
 533#define RXBD_LAST               0x0800
 534#define RXBD_FIRST              0x0400
 535#define RXBD_MISS               0x0100
 536#define RXBD_BROADCAST          0x0080
 537#define RXBD_MULTICAST          0x0040
 538#define RXBD_LARGE              0x0020
 539#define RXBD_NONOCTET           0x0010
 540#define RXBD_SHORT              0x0008
 541#define RXBD_CRCERR             0x0004
 542#define RXBD_OVERRUN            0x0002
 543#define RXBD_TRUNCATED          0x0001
 544#define RXBD_STATS              0x01ff
 545#define RXBD_ERR                (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET        \
 546                                | RXBD_CRCERR | RXBD_OVERRUN                    \
 547                                | RXBD_TRUNCATED)
 548
 549/* Rx FCB status field bits */
 550#define RXFCB_VLN               0x8000
 551#define RXFCB_IP                0x4000
 552#define RXFCB_IP6               0x2000
 553#define RXFCB_TUP               0x1000
 554#define RXFCB_CIP               0x0800
 555#define RXFCB_CTU               0x0400
 556#define RXFCB_EIP               0x0200
 557#define RXFCB_ETU               0x0100
 558#define RXFCB_CSUM_MASK         0x0f00
 559#define RXFCB_PERR_MASK         0x000c
 560#define RXFCB_PERR_BADL3        0x0008
 561
 562#define GFAR_INT_NAME_MAX       (IFNAMSIZ + 6)  /* '_g#_xx' */
 563
 564#define GFAR_WOL_MAGIC          0x00000001
 565#define GFAR_WOL_FILER_UCAST    0x00000002
 566
 567struct txbd8
 568{
 569        union {
 570                struct {
 571                        __be16  status; /* Status Fields */
 572                        __be16  length; /* Buffer length */
 573                };
 574                __be32 lstatus;
 575        };
 576        __be32  bufPtr; /* Buffer Pointer */
 577};
 578
 579struct txfcb {
 580        u8      flags;
 581        u8      ptp;    /* Flag to enable tx timestamping */
 582        u8      l4os;   /* Level 4 Header Offset */
 583        u8      l3os;   /* Level 3 Header Offset */
 584        __be16  phcs;   /* Pseudo-header Checksum */
 585        __be16  vlctl;  /* VLAN control word */
 586};
 587
 588struct rxbd8
 589{
 590        union {
 591                struct {
 592                        __be16  status; /* Status Fields */
 593                        __be16  length; /* Buffer Length */
 594                };
 595                __be32 lstatus;
 596        };
 597        __be32  bufPtr; /* Buffer Pointer */
 598};
 599
 600struct rxfcb {
 601        __be16  flags;
 602        u8      rq;     /* Receive Queue index */
 603        u8      pro;    /* Layer 4 Protocol */
 604        u16     reserved;
 605        __be16  vlctl;  /* VLAN control word */
 606};
 607
 608struct gianfar_skb_cb {
 609        unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */
 610};
 611
 612#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
 613
 614struct rmon_mib
 615{
 616        u32     tr64;   /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
 617        u32     tr127;  /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
 618        u32     tr255;  /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
 619        u32     tr511;  /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
 620        u32     tr1k;   /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
 621        u32     trmax;  /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
 622        u32     trmgv;  /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
 623        u32     rbyt;   /* 0x.69c - Receive Byte Counter */
 624        u32     rpkt;   /* 0x.6a0 - Receive Packet Counter */
 625        u32     rfcs;   /* 0x.6a4 - Receive FCS Error Counter */
 626        u32     rmca;   /* 0x.6a8 - Receive Multicast Packet Counter */
 627        u32     rbca;   /* 0x.6ac - Receive Broadcast Packet Counter */
 628        u32     rxcf;   /* 0x.6b0 - Receive Control Frame Packet Counter */
 629        u32     rxpf;   /* 0x.6b4 - Receive Pause Frame Packet Counter */
 630        u32     rxuo;   /* 0x.6b8 - Receive Unknown OP Code Counter */
 631        u32     raln;   /* 0x.6bc - Receive Alignment Error Counter */
 632        u32     rflr;   /* 0x.6c0 - Receive Frame Length Error Counter */
 633        u32     rcde;   /* 0x.6c4 - Receive Code Error Counter */
 634        u32     rcse;   /* 0x.6c8 - Receive Carrier Sense Error Counter */
 635        u32     rund;   /* 0x.6cc - Receive Undersize Packet Counter */
 636        u32     rovr;   /* 0x.6d0 - Receive Oversize Packet Counter */
 637        u32     rfrg;   /* 0x.6d4 - Receive Fragments Counter */
 638        u32     rjbr;   /* 0x.6d8 - Receive Jabber Counter */
 639        u32     rdrp;   /* 0x.6dc - Receive Drop Counter */
 640        u32     tbyt;   /* 0x.6e0 - Transmit Byte Counter Counter */
 641        u32     tpkt;   /* 0x.6e4 - Transmit Packet Counter */
 642        u32     tmca;   /* 0x.6e8 - Transmit Multicast Packet Counter */
 643        u32     tbca;   /* 0x.6ec - Transmit Broadcast Packet Counter */
 644        u32     txpf;   /* 0x.6f0 - Transmit Pause Control Frame Counter */
 645        u32     tdfr;   /* 0x.6f4 - Transmit Deferral Packet Counter */
 646        u32     tedf;   /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
 647        u32     tscl;   /* 0x.6fc - Transmit Single Collision Packet Counter */
 648        u32     tmcl;   /* 0x.700 - Transmit Multiple Collision Packet Counter */
 649        u32     tlcl;   /* 0x.704 - Transmit Late Collision Packet Counter */
 650        u32     txcl;   /* 0x.708 - Transmit Excessive Collision Packet Counter */
 651        u32     tncl;   /* 0x.70c - Transmit Total Collision Counter */
 652        u8      res1[4];
 653        u32     tdrp;   /* 0x.714 - Transmit Drop Frame Counter */
 654        u32     tjbr;   /* 0x.718 - Transmit Jabber Frame Counter */
 655        u32     tfcs;   /* 0x.71c - Transmit FCS Error Counter */
 656        u32     txcf;   /* 0x.720 - Transmit Control Frame Counter */
 657        u32     tovr;   /* 0x.724 - Transmit Oversize Frame Counter */
 658        u32     tund;   /* 0x.728 - Transmit Undersize Frame Counter */
 659        u32     tfrg;   /* 0x.72c - Transmit Fragments Frame Counter */
 660        u32     car1;   /* 0x.730 - Carry Register One */
 661        u32     car2;   /* 0x.734 - Carry Register Two */
 662        u32     cam1;   /* 0x.738 - Carry Mask Register One */
 663        u32     cam2;   /* 0x.73c - Carry Mask Register Two */
 664};
 665
 666struct rmon_overflow {
 667        /* lock for synchronization of the rdrp field of this struct, and
 668         * CAR1/CAR2 registers
 669         */
 670        spinlock_t lock;
 671        u32     imask;
 672        u64     rdrp;
 673};
 674
 675struct gfar_extra_stats {
 676        atomic64_t rx_alloc_err;
 677        atomic64_t rx_large;
 678        atomic64_t rx_short;
 679        atomic64_t rx_nonoctet;
 680        atomic64_t rx_crcerr;
 681        atomic64_t rx_overrun;
 682        atomic64_t rx_bsy;
 683        atomic64_t rx_babr;
 684        atomic64_t rx_trunc;
 685        atomic64_t eberr;
 686        atomic64_t tx_babt;
 687        atomic64_t tx_underrun;
 688        atomic64_t tx_timeout;
 689};
 690
 691#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
 692#define GFAR_EXTRA_STATS_LEN \
 693        (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t))
 694
 695/* Number of stats exported via ethtool */
 696#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
 697
 698struct gfar {
 699        u32     tsec_id;        /* 0x.000 - Controller ID register */
 700        u32     tsec_id2;       /* 0x.004 - Controller ID2 register */
 701        u8      res1[8];
 702        u32     ievent;         /* 0x.010 - Interrupt Event Register */
 703        u32     imask;          /* 0x.014 - Interrupt Mask Register */
 704        u32     edis;           /* 0x.018 - Error Disabled Register */
 705        u32     emapg;          /* 0x.01c - Group Error mapping register */
 706        u32     ecntrl;         /* 0x.020 - Ethernet Control Register */
 707        u32     minflr;         /* 0x.024 - Minimum Frame Length Register */
 708        u32     ptv;            /* 0x.028 - Pause Time Value Register */
 709        u32     dmactrl;        /* 0x.02c - DMA Control Register */
 710        u32     tbipa;          /* 0x.030 - TBI PHY Address Register */
 711        u8      res2[28];
 712        u32     fifo_rx_pause;  /* 0x.050 - FIFO receive pause start threshold
 713                                        register */
 714        u32     fifo_rx_pause_shutoff;  /* x.054 - FIFO receive starve shutoff
 715                                                register */
 716        u32     fifo_rx_alarm;  /* 0x.058 - FIFO receive alarm start threshold
 717                                                register */
 718        u32     fifo_rx_alarm_shutoff;  /*0x.05c - FIFO receive alarm  starve
 719                                                shutoff register */
 720        u8      res3[44];
 721        u32     fifo_tx_thr;    /* 0x.08c - FIFO transmit threshold register */
 722        u8      res4[8];
 723        u32     fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
 724        u32     fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
 725        u8      res5[96];
 726        u32     tctrl;          /* 0x.100 - Transmit Control Register */
 727        u32     tstat;          /* 0x.104 - Transmit Status Register */
 728        u32     dfvlan;         /* 0x.108 - Default VLAN Control word */
 729        u32     tbdlen;         /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
 730        u32     txic;           /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
 731        u32     tqueue;         /* 0x.114 - Transmit queue control register */
 732        u8      res7[40];
 733        u32     tr03wt;         /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
 734        u32     tr47wt;         /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
 735        u8      res8[52];
 736        u32     tbdbph;         /* 0x.17c - Tx data buffer pointer high */
 737        u8      res9a[4];
 738        u32     tbptr0;         /* 0x.184 - TxBD Pointer for ring 0 */
 739        u8      res9b[4];
 740        u32     tbptr1;         /* 0x.18c - TxBD Pointer for ring 1 */
 741        u8      res9c[4];
 742        u32     tbptr2;         /* 0x.194 - TxBD Pointer for ring 2 */
 743        u8      res9d[4];
 744        u32     tbptr3;         /* 0x.19c - TxBD Pointer for ring 3 */
 745        u8      res9e[4];
 746        u32     tbptr4;         /* 0x.1a4 - TxBD Pointer for ring 4 */
 747        u8      res9f[4];
 748        u32     tbptr5;         /* 0x.1ac - TxBD Pointer for ring 5 */
 749        u8      res9g[4];
 750        u32     tbptr6;         /* 0x.1b4 - TxBD Pointer for ring 6 */
 751        u8      res9h[4];
 752        u32     tbptr7;         /* 0x.1bc - TxBD Pointer for ring 7 */
 753        u8      res9[64];
 754        u32     tbaseh;         /* 0x.200 - TxBD base address high */
 755        u32     tbase0;         /* 0x.204 - TxBD Base Address of ring 0 */
 756        u8      res10a[4];
 757        u32     tbase1;         /* 0x.20c - TxBD Base Address of ring 1 */
 758        u8      res10b[4];
 759        u32     tbase2;         /* 0x.214 - TxBD Base Address of ring 2 */
 760        u8      res10c[4];
 761        u32     tbase3;         /* 0x.21c - TxBD Base Address of ring 3 */
 762        u8      res10d[4];
 763        u32     tbase4;         /* 0x.224 - TxBD Base Address of ring 4 */
 764        u8      res10e[4];
 765        u32     tbase5;         /* 0x.22c - TxBD Base Address of ring 5 */
 766        u8      res10f[4];
 767        u32     tbase6;         /* 0x.234 - TxBD Base Address of ring 6 */
 768        u8      res10g[4];
 769        u32     tbase7;         /* 0x.23c - TxBD Base Address of ring 7 */
 770        u8      res10[192];
 771        u32     rctrl;          /* 0x.300 - Receive Control Register */
 772        u32     rstat;          /* 0x.304 - Receive Status Register */
 773        u8      res12[8];
 774        u32     rxic;           /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
 775        u32     rqueue;         /* 0x.314 - Receive queue control register */
 776        u32     rir0;           /* 0x.318 - Ring mapping register 0 */
 777        u32     rir1;           /* 0x.31c - Ring mapping register 1 */
 778        u32     rir2;           /* 0x.320 - Ring mapping register 2 */
 779        u32     rir3;           /* 0x.324 - Ring mapping register 3 */
 780        u8      res13[8];
 781        u32     rbifx;          /* 0x.330 - Receive bit field extract control register */
 782        u32     rqfar;          /* 0x.334 - Receive queue filing table address register */
 783        u32     rqfcr;          /* 0x.338 - Receive queue filing table control register */
 784        u32     rqfpr;          /* 0x.33c - Receive queue filing table property register */
 785        u32     mrblr;          /* 0x.340 - Maximum Receive Buffer Length Register */
 786        u8      res14[56];
 787        u32     rbdbph;         /* 0x.37c - Rx data buffer pointer high */
 788        u8      res15a[4];
 789        u32     rbptr0;         /* 0x.384 - RxBD pointer for ring 0 */
 790        u8      res15b[4];
 791        u32     rbptr1;         /* 0x.38c - RxBD pointer for ring 1 */
 792        u8      res15c[4];
 793        u32     rbptr2;         /* 0x.394 - RxBD pointer for ring 2 */
 794        u8      res15d[4];
 795        u32     rbptr3;         /* 0x.39c - RxBD pointer for ring 3 */
 796        u8      res15e[4];
 797        u32     rbptr4;         /* 0x.3a4 - RxBD pointer for ring 4 */
 798        u8      res15f[4];
 799        u32     rbptr5;         /* 0x.3ac - RxBD pointer for ring 5 */
 800        u8      res15g[4];
 801        u32     rbptr6;         /* 0x.3b4 - RxBD pointer for ring 6 */
 802        u8      res15h[4];
 803        u32     rbptr7;         /* 0x.3bc - RxBD pointer for ring 7 */
 804        u8      res16[64];
 805        u32     rbaseh;         /* 0x.400 - RxBD base address high */
 806        u32     rbase0;         /* 0x.404 - RxBD base address of ring 0 */
 807        u8      res17a[4];
 808        u32     rbase1;         /* 0x.40c - RxBD base address of ring 1 */
 809        u8      res17b[4];
 810        u32     rbase2;         /* 0x.414 - RxBD base address of ring 2 */
 811        u8      res17c[4];
 812        u32     rbase3;         /* 0x.41c - RxBD base address of ring 3 */
 813        u8      res17d[4];
 814        u32     rbase4;         /* 0x.424 - RxBD base address of ring 4 */
 815        u8      res17e[4];
 816        u32     rbase5;         /* 0x.42c - RxBD base address of ring 5 */
 817        u8      res17f[4];
 818        u32     rbase6;         /* 0x.434 - RxBD base address of ring 6 */
 819        u8      res17g[4];
 820        u32     rbase7;         /* 0x.43c - RxBD base address of ring 7 */
 821        u8      res17[192];
 822        u32     maccfg1;        /* 0x.500 - MAC Configuration 1 Register */
 823        u32     maccfg2;        /* 0x.504 - MAC Configuration 2 Register */
 824        u32     ipgifg;         /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
 825        u32     hafdup;         /* 0x.50c - Half Duplex Register */
 826        u32     maxfrm;         /* 0x.510 - Maximum Frame Length Register */
 827        u8      res18[12];
 828        u8      gfar_mii_regs[24];      /* See gianfar_phy.h */
 829        u32     ifctrl;         /* 0x.538 - Interface control register */
 830        u32     ifstat;         /* 0x.53c - Interface Status Register */
 831        u32     macstnaddr1;    /* 0x.540 - Station Address Part 1 Register */
 832        u32     macstnaddr2;    /* 0x.544 - Station Address Part 2 Register */
 833        u32     mac01addr1;     /* 0x.548 - MAC exact match address 1, part 1 */
 834        u32     mac01addr2;     /* 0x.54c - MAC exact match address 1, part 2 */
 835        u32     mac02addr1;     /* 0x.550 - MAC exact match address 2, part 1 */
 836        u32     mac02addr2;     /* 0x.554 - MAC exact match address 2, part 2 */
 837        u32     mac03addr1;     /* 0x.558 - MAC exact match address 3, part 1 */
 838        u32     mac03addr2;     /* 0x.55c - MAC exact match address 3, part 2 */
 839        u32     mac04addr1;     /* 0x.560 - MAC exact match address 4, part 1 */
 840        u32     mac04addr2;     /* 0x.564 - MAC exact match address 4, part 2 */
 841        u32     mac05addr1;     /* 0x.568 - MAC exact match address 5, part 1 */
 842        u32     mac05addr2;     /* 0x.56c - MAC exact match address 5, part 2 */
 843        u32     mac06addr1;     /* 0x.570 - MAC exact match address 6, part 1 */
 844        u32     mac06addr2;     /* 0x.574 - MAC exact match address 6, part 2 */
 845        u32     mac07addr1;     /* 0x.578 - MAC exact match address 7, part 1 */
 846        u32     mac07addr2;     /* 0x.57c - MAC exact match address 7, part 2 */
 847        u32     mac08addr1;     /* 0x.580 - MAC exact match address 8, part 1 */
 848        u32     mac08addr2;     /* 0x.584 - MAC exact match address 8, part 2 */
 849        u32     mac09addr1;     /* 0x.588 - MAC exact match address 9, part 1 */
 850        u32     mac09addr2;     /* 0x.58c - MAC exact match address 9, part 2 */
 851        u32     mac10addr1;     /* 0x.590 - MAC exact match address 10, part 1*/
 852        u32     mac10addr2;     /* 0x.594 - MAC exact match address 10, part 2*/
 853        u32     mac11addr1;     /* 0x.598 - MAC exact match address 11, part 1*/
 854        u32     mac11addr2;     /* 0x.59c - MAC exact match address 11, part 2*/
 855        u32     mac12addr1;     /* 0x.5a0 - MAC exact match address 12, part 1*/
 856        u32     mac12addr2;     /* 0x.5a4 - MAC exact match address 12, part 2*/
 857        u32     mac13addr1;     /* 0x.5a8 - MAC exact match address 13, part 1*/
 858        u32     mac13addr2;     /* 0x.5ac - MAC exact match address 13, part 2*/
 859        u32     mac14addr1;     /* 0x.5b0 - MAC exact match address 14, part 1*/
 860        u32     mac14addr2;     /* 0x.5b4 - MAC exact match address 14, part 2*/
 861        u32     mac15addr1;     /* 0x.5b8 - MAC exact match address 15, part 1*/
 862        u32     mac15addr2;     /* 0x.5bc - MAC exact match address 15, part 2*/
 863        u8      res20[192];
 864        struct rmon_mib rmon;   /* 0x.680-0x.73c */
 865        u32     rrej;           /* 0x.740 - Receive filer rejected packet counter */
 866        u8      res21[188];
 867        u32     igaddr0;        /* 0x.800 - Indivdual/Group address register 0*/
 868        u32     igaddr1;        /* 0x.804 - Indivdual/Group address register 1*/
 869        u32     igaddr2;        /* 0x.808 - Indivdual/Group address register 2*/
 870        u32     igaddr3;        /* 0x.80c - Indivdual/Group address register 3*/
 871        u32     igaddr4;        /* 0x.810 - Indivdual/Group address register 4*/
 872        u32     igaddr5;        /* 0x.814 - Indivdual/Group address register 5*/
 873        u32     igaddr6;        /* 0x.818 - Indivdual/Group address register 6*/
 874        u32     igaddr7;        /* 0x.81c - Indivdual/Group address register 7*/
 875        u8      res22[96];
 876        u32     gaddr0;         /* 0x.880 - Group address register 0 */
 877        u32     gaddr1;         /* 0x.884 - Group address register 1 */
 878        u32     gaddr2;         /* 0x.888 - Group address register 2 */
 879        u32     gaddr3;         /* 0x.88c - Group address register 3 */
 880        u32     gaddr4;         /* 0x.890 - Group address register 4 */
 881        u32     gaddr5;         /* 0x.894 - Group address register 5 */
 882        u32     gaddr6;         /* 0x.898 - Group address register 6 */
 883        u32     gaddr7;         /* 0x.89c - Group address register 7 */
 884        u8      res23a[352];
 885        u32     fifocfg;        /* 0x.a00 - FIFO interface config register */
 886        u8      res23b[252];
 887        u8      res23c[248];
 888        u32     attr;           /* 0x.bf8 - Attributes Register */
 889        u32     attreli;        /* 0x.bfc - Attributes Extract Length and Extract Index Register */
 890        u32     rqprm0; /* 0x.c00 - Receive queue parameters register 0 */
 891        u32     rqprm1; /* 0x.c04 - Receive queue parameters register 1 */
 892        u32     rqprm2; /* 0x.c08 - Receive queue parameters register 2 */
 893        u32     rqprm3; /* 0x.c0c - Receive queue parameters register 3 */
 894        u32     rqprm4; /* 0x.c10 - Receive queue parameters register 4 */
 895        u32     rqprm5; /* 0x.c14 - Receive queue parameters register 5 */
 896        u32     rqprm6; /* 0x.c18 - Receive queue parameters register 6 */
 897        u32     rqprm7; /* 0x.c1c - Receive queue parameters register 7 */
 898        u8      res24[36];
 899        u32     rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */
 900        u8      res24a[4];
 901        u32     rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */
 902        u8      res24b[4];
 903        u32     rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */
 904        u8      res24c[4];
 905        u32     rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */
 906        u8      res24d[4];
 907        u32     rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */
 908        u8      res24e[4];
 909        u32     rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */
 910        u8      res24f[4];
 911        u32     rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */
 912        u8      res24g[4];
 913        u32     rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */
 914        u8      res24h[4];
 915        u8      res24x[556];
 916        u32     isrg0;          /* 0x.eb0 - Interrupt steering group 0 register */
 917        u32     isrg1;          /* 0x.eb4 - Interrupt steering group 1 register */
 918        u32     isrg2;          /* 0x.eb8 - Interrupt steering group 2 register */
 919        u32     isrg3;          /* 0x.ebc - Interrupt steering group 3 register */
 920        u8      res25[16];
 921        u32     rxic0;          /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
 922        u32     rxic1;          /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
 923        u32     rxic2;          /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
 924        u32     rxic3;          /* 0x.edc - Ring 3 Rx interrupt coalescing */
 925        u32     rxic4;          /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
 926        u32     rxic5;          /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
 927        u32     rxic6;          /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
 928        u32     rxic7;          /* 0x.eec - Ring 7 Rx interrupt coalescing */
 929        u8      res26[32];
 930        u32     txic0;          /* 0x.f10 - Ring 0 Tx interrupt coalescing */
 931        u32     txic1;          /* 0x.f14 - Ring 1 Tx interrupt coalescing */
 932        u32     txic2;          /* 0x.f18 - Ring 2 Tx interrupt coalescing */
 933        u32     txic3;          /* 0x.f1c - Ring 3 Tx interrupt coalescing */
 934        u32     txic4;          /* 0x.f20 - Ring 4 Tx interrupt coalescing */
 935        u32     txic5;          /* 0x.f24 - Ring 5 Tx interrupt coalescing */
 936        u32     txic6;          /* 0x.f28 - Ring 6 Tx interrupt coalescing */
 937        u32     txic7;          /* 0x.f2c - Ring 7 Tx interrupt coalescing */
 938        u8      res27[208];
 939};
 940
 941/* Flags related to gianfar device features */
 942#define FSL_GIANFAR_DEV_HAS_GIGABIT             0x00000001
 943#define FSL_GIANFAR_DEV_HAS_COALESCE            0x00000002
 944#define FSL_GIANFAR_DEV_HAS_RMON                0x00000004
 945#define FSL_GIANFAR_DEV_HAS_MULTI_INTR          0x00000008
 946#define FSL_GIANFAR_DEV_HAS_CSUM                0x00000010
 947#define FSL_GIANFAR_DEV_HAS_VLAN                0x00000020
 948#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH       0x00000040
 949#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET        0x00000100
 950#define FSL_GIANFAR_DEV_HAS_BD_STASHING         0x00000200
 951#define FSL_GIANFAR_DEV_HAS_BUF_STASHING        0x00000400
 952#define FSL_GIANFAR_DEV_HAS_TIMER               0x00000800
 953#define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER       0x00001000
 954#define FSL_GIANFAR_DEV_HAS_RX_FILER            0x00002000
 955
 956#if (MAXGROUPS == 2)
 957#define DEFAULT_MAPPING         0xAA
 958#else
 959#define DEFAULT_MAPPING         0xFF
 960#endif
 961
 962#define ISRG_RR0        0x80000000
 963#define ISRG_TR0        0x00800000
 964
 965/* The same driver can operate in two modes */
 966/* SQ_SG_MODE: Single Queue Single Group Mode
 967 *              (Backward compatible mode)
 968 * MQ_MG_MODE: Multi Queue Multi Group mode
 969 */
 970enum {
 971        SQ_SG_MODE = 0,
 972        MQ_MG_MODE
 973};
 974
 975/*
 976 * Per TX queue stats
 977 */
 978struct tx_q_stats {
 979        u64 tx_packets;
 980        u64 tx_bytes;
 981};
 982
 983/**
 984 *      struct gfar_priv_tx_q - per tx queue structure
 985 *      @txlock: per queue tx spin lock
 986 *      @tx_skbuff:skb pointers
 987 *      @skb_curtx: to be used skb pointer
 988 *      @skb_dirtytx:the last used skb pointer
 989 *      @stats: bytes/packets stats
 990 *      @qindex: index of this queue
 991 *      @dev: back pointer to the dev structure
 992 *      @grp: back pointer to the group to which this queue belongs
 993 *      @tx_bd_base: First tx buffer descriptor
 994 *      @cur_tx: Next free ring entry
 995 *      @dirty_tx: First buffer in line to be transmitted
 996 *      @tx_ring_size: Tx ring size
 997 *      @num_txbdfree: number of free TxBds
 998 *      @txcoalescing: enable/disable tx coalescing
 999 *      @txic: transmit interrupt coalescing value
1000 *      @txcount: coalescing value if based on tx frame count
1001 *      @txtime: coalescing value if based on time
1002 */
1003struct gfar_priv_tx_q {
1004        /* cacheline 1 */
1005        spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
1006        struct  txbd8 *tx_bd_base;
1007        struct  txbd8 *cur_tx;
1008        unsigned int num_txbdfree;
1009        unsigned short skb_curtx;
1010        unsigned short tx_ring_size;
1011        struct tx_q_stats stats;
1012        struct gfar_priv_grp *grp;
1013        /* cacheline 2 */
1014        struct net_device *dev;
1015        struct sk_buff **tx_skbuff;
1016        struct  txbd8 *dirty_tx;
1017        unsigned short skb_dirtytx;
1018        unsigned short qindex;
1019        /* Configuration info for the coalescing features */
1020        unsigned int txcoalescing;
1021        unsigned long txic;
1022        dma_addr_t tx_bd_dma_base;
1023};
1024
1025/*
1026 * Per RX queue stats
1027 */
1028struct rx_q_stats {
1029        u64 rx_packets;
1030        u64 rx_bytes;
1031        u64 rx_dropped;
1032};
1033
1034struct gfar_rx_buff {
1035        dma_addr_t dma;
1036        struct page *page;
1037        unsigned int page_offset;
1038};
1039
1040/**
1041 *      struct gfar_priv_rx_q - per rx queue structure
1042 *      @rx_buff: Array of buffer info metadata structs
1043 *      @rx_bd_base: First rx buffer descriptor
1044 *      @next_to_use: index of the next buffer to be alloc'd
1045 *      @next_to_clean: index of the next buffer to be cleaned
1046 *      @qindex: index of this queue
1047 *      @ndev: back pointer to net_device
1048 *      @rx_ring_size: Rx ring size
1049 *      @rxcoalescing: enable/disable rx-coalescing
1050 *      @rxic: receive interrupt coalescing vlaue
1051 */
1052
1053struct gfar_priv_rx_q {
1054        struct  gfar_rx_buff *rx_buff __aligned(SMP_CACHE_BYTES);
1055        struct  rxbd8 *rx_bd_base;
1056        struct  net_device *ndev;
1057        struct  device *dev;
1058        u16 rx_ring_size;
1059        u16 qindex;
1060        struct  gfar_priv_grp *grp;
1061        u16 next_to_clean;
1062        u16 next_to_use;
1063        u16 next_to_alloc;
1064        struct  sk_buff *skb;
1065        struct rx_q_stats stats;
1066        u32 __iomem *rfbptr;
1067        unsigned char rxcoalescing;
1068        unsigned long rxic;
1069        dma_addr_t rx_bd_dma_base;
1070};
1071
1072enum gfar_irqinfo_id {
1073        GFAR_TX = 0,
1074        GFAR_RX = 1,
1075        GFAR_ER = 2,
1076        GFAR_NUM_IRQS = 3
1077};
1078
1079struct gfar_irqinfo {
1080        unsigned int irq;
1081        char name[GFAR_INT_NAME_MAX];
1082};
1083
1084/**
1085 *      struct gfar_priv_grp - per group structure
1086 *      @napi: the napi poll function
1087 *      @priv: back pointer to the priv structure
1088 *      @regs: the ioremapped register space for this group
1089 *      @irqinfo: TX/RX/ER irq data for this group
1090 */
1091
1092struct gfar_priv_grp {
1093        spinlock_t grplock __aligned(SMP_CACHE_BYTES);
1094        struct  napi_struct napi_rx;
1095        struct  napi_struct napi_tx;
1096        struct gfar __iomem *regs;
1097        struct gfar_priv_tx_q *tx_queue;
1098        struct gfar_priv_rx_q *rx_queue;
1099        unsigned int tstat;
1100        unsigned int rstat;
1101
1102        struct gfar_private *priv;
1103        unsigned long num_tx_queues;
1104        unsigned long tx_bit_map;
1105        unsigned long num_rx_queues;
1106        unsigned long rx_bit_map;
1107
1108        struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
1109};
1110
1111#define gfar_irq(grp, ID) \
1112        ((grp)->irqinfo[GFAR_##ID])
1113
1114enum gfar_errata {
1115        GFAR_ERRATA_74          = 0x01,
1116        GFAR_ERRATA_76          = 0x02,
1117        GFAR_ERRATA_A002        = 0x04,
1118        GFAR_ERRATA_12          = 0x08, /* a.k.a errata eTSEC49 */
1119};
1120
1121enum gfar_dev_state {
1122        GFAR_DOWN = 1,
1123        GFAR_RESETTING
1124};
1125
1126/* Struct stolen almost completely (and shamelessly) from the FCC enet source
1127 * (Ok, that's not so true anymore, but there is a family resemblance)
1128 * The GFAR buffer descriptors track the ring buffers.  The rx_bd_base
1129 * and tx_bd_base always point to the currently available buffer.
1130 * The dirty_tx tracks the current buffer that is being sent by the
1131 * controller.  The cur_tx and dirty_tx are equal under both completely
1132 * empty and completely full conditions.  The empty/ready indicator in
1133 * the buffer descriptor determines the actual condition.
1134 */
1135struct gfar_private {
1136        struct device *dev;
1137        struct net_device *ndev;
1138        enum gfar_errata errata;
1139
1140        u16 uses_rxfcb;
1141        u16 padding;
1142        u32 device_flags;
1143
1144        /* HW time stamping enabled flag */
1145        int hwts_rx_en;
1146        int hwts_tx_en;
1147
1148        struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1149        struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1150        struct gfar_priv_grp gfargrp[MAXGROUPS];
1151
1152        unsigned long state;
1153
1154        unsigned short mode;
1155        unsigned int num_tx_queues;
1156        unsigned int num_rx_queues;
1157        unsigned int num_grps;
1158        int tx_actual_en;
1159
1160        /* Network Statistics */
1161        struct gfar_extra_stats extra_stats;
1162        struct rmon_overflow rmon_overflow;
1163
1164        /* PHY stuff */
1165        phy_interface_t interface;
1166        struct device_node *phy_node;
1167        struct device_node *tbi_node;
1168        struct mii_bus *mii_bus;
1169        int oldspeed;
1170        int oldduplex;
1171        int oldlink;
1172
1173        uint32_t msg_enable;
1174
1175        struct work_struct reset_task;
1176
1177        struct platform_device *ofdev;
1178        unsigned char
1179                extended_hash:1,
1180                bd_stash_en:1,
1181                rx_filer_enable:1,
1182                /* Enable priorty based Tx scheduling in Hw */
1183                prio_sched_en:1,
1184                /* Flow control flags */
1185                pause_aneg_en:1,
1186                tx_pause_en:1,
1187                rx_pause_en:1;
1188
1189        /* The total tx and rx ring size for the enabled queues */
1190        unsigned int total_tx_ring_size;
1191        unsigned int total_rx_ring_size;
1192
1193        u32 rqueue;
1194        u32 tqueue;
1195
1196        /* RX per device parameters */
1197        unsigned int rx_stash_size;
1198        unsigned int rx_stash_index;
1199
1200        u32 cur_filer_idx;
1201
1202        /* RX queue filer rule set*/
1203        struct ethtool_rx_list rx_list;
1204        struct mutex rx_queue_access;
1205
1206        /* Hash registers and their width */
1207        u32 __iomem *hash_regs[16];
1208        int hash_width;
1209
1210        /* wake-on-lan settings */
1211        u16 wol_opts;
1212        u16 wol_supported;
1213
1214        /*Filer table*/
1215        unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1216        unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1217};
1218
1219
1220static inline int gfar_has_errata(struct gfar_private *priv,
1221                                  enum gfar_errata err)
1222{
1223        return priv->errata & err;
1224}
1225
1226static inline u32 gfar_read(unsigned __iomem *addr)
1227{
1228        u32 val;
1229        val = ioread32be(addr);
1230        return val;
1231}
1232
1233static inline void gfar_write(unsigned __iomem *addr, u32 val)
1234{
1235        iowrite32be(val, addr);
1236}
1237
1238static inline void gfar_write_filer(struct gfar_private *priv,
1239                unsigned int far, unsigned int fcr, unsigned int fpr)
1240{
1241        struct gfar __iomem *regs = priv->gfargrp[0].regs;
1242
1243        gfar_write(&regs->rqfar, far);
1244        gfar_write(&regs->rqfcr, fcr);
1245        gfar_write(&regs->rqfpr, fpr);
1246}
1247
1248static inline void gfar_read_filer(struct gfar_private *priv,
1249                unsigned int far, unsigned int *fcr, unsigned int *fpr)
1250{
1251        struct gfar __iomem *regs = priv->gfargrp[0].regs;
1252
1253        gfar_write(&regs->rqfar, far);
1254        *fcr = gfar_read(&regs->rqfcr);
1255        *fpr = gfar_read(&regs->rqfpr);
1256}
1257
1258static inline void gfar_write_isrg(struct gfar_private *priv)
1259{
1260        struct gfar __iomem *regs = priv->gfargrp[0].regs;
1261        u32 __iomem *baddr = &regs->isrg0;
1262        u32 isrg = 0;
1263        int grp_idx, i;
1264
1265        for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1266                struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx];
1267
1268                for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
1269                        isrg |= (ISRG_RR0 >> i);
1270                }
1271
1272                for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
1273                        isrg |= (ISRG_TR0 >> i);
1274                }
1275
1276                gfar_write(baddr, isrg);
1277
1278                baddr++;
1279                isrg = 0;
1280        }
1281}
1282
1283static inline int gfar_is_dma_stopped(struct gfar_private *priv)
1284{
1285        struct gfar __iomem *regs = priv->gfargrp[0].regs;
1286
1287        return ((gfar_read(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) ==
1288               (IEVENT_GRSC | IEVENT_GTSC));
1289}
1290
1291static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv)
1292{
1293        struct gfar __iomem *regs = priv->gfargrp[0].regs;
1294
1295        return gfar_read(&regs->ievent) & IEVENT_GRSC;
1296}
1297
1298static inline void gfar_wmb(void)
1299{
1300#if defined(CONFIG_PPC)
1301        /* The powerpc-specific eieio() is used, as wmb() has too strong
1302         * semantics (it requires synchronization between cacheable and
1303         * uncacheable mappings, which eieio() doesn't provide and which we
1304         * don't need), thus requiring a more expensive sync instruction.  At
1305         * some point, the set of architecture-independent barrier functions
1306         * should be expanded to include weaker barriers.
1307         */
1308        eieio();
1309#else
1310        wmb(); /* order write acesses for BD (or FCB) fields */
1311#endif
1312}
1313
1314static inline void gfar_clear_txbd_status(struct txbd8 *bdp)
1315{
1316        u32 lstatus = be32_to_cpu(bdp->lstatus);
1317
1318        lstatus &= BD_LFLAG(TXBD_WRAP);
1319        bdp->lstatus = cpu_to_be32(lstatus);
1320}
1321
1322static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq)
1323{
1324        if (rxq->next_to_clean > rxq->next_to_use)
1325                return rxq->next_to_clean - rxq->next_to_use - 1;
1326
1327        return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1;
1328}
1329
1330static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq)
1331{
1332        struct rxbd8 *bdp;
1333        u32 bdp_dma;
1334        int i;
1335
1336        i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1;
1337        bdp = &rxq->rx_bd_base[i];
1338        bdp_dma = lower_32_bits(rxq->rx_bd_dma_base);
1339        bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base;
1340
1341        return bdp_dma;
1342}
1343
1344int startup_gfar(struct net_device *dev);
1345void stop_gfar(struct net_device *dev);
1346void gfar_mac_reset(struct gfar_private *priv);
1347int gfar_set_features(struct net_device *dev, netdev_features_t features);
1348
1349extern const struct ethtool_ops gfar_ethtool_ops;
1350
1351#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
1352
1353#define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1354#define RQFCR_PID_L4P_MASK 0xFFFFFF00
1355#define RQFCR_PID_VID_MASK 0xFFFFF000
1356#define RQFCR_PID_PORT_MASK 0xFFFF0000
1357#define RQFCR_PID_MAC_MASK 0xFF000000
1358
1359/* Represents a receive filer table entry */
1360struct gfar_filer_entry {
1361        u32 ctrl;
1362        u32 prop;
1363};
1364
1365
1366/* The 20 additional entries are a shadow for one extra element */
1367struct filer_table {
1368        u32 index;
1369        struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
1370};
1371
1372#endif /* __GIANFAR_H */
1373
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