linux/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
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   1/* bnx2x_ethtool.c: QLogic Everest network driver.
   2 *
   3 * Copyright (c) 2007-2013 Broadcom Corporation
   4 * Copyright (c) 2014 QLogic Corporation
   5 * All rights reserved
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation.
  10 *
  11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  12 * Written by: Eliezer Tamir
  13 * Based on code from Michael Chan's bnx2 driver
  14 * UDP CSUM errata workaround by Arik Gendelman
  15 * Slowpath and fastpath rework by Vladislav Zolotarov
  16 * Statistics and Link management by Yitchak Gertner
  17 *
  18 */
  19
  20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22#include <linux/ethtool.h>
  23#include <linux/netdevice.h>
  24#include <linux/types.h>
  25#include <linux/sched.h>
  26#include <linux/crc32.h>
  27#include "bnx2x.h"
  28#include "bnx2x_cmn.h"
  29#include "bnx2x_dump.h"
  30#include "bnx2x_init.h"
  31
  32/* Note: in the format strings below %s is replaced by the queue-name which is
  33 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  34 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  35 */
  36#define MAX_QUEUE_NAME_LEN      4
  37static const struct {
  38        long offset;
  39        int size;
  40        char string[ETH_GSTRING_LEN];
  41} bnx2x_q_stats_arr[] = {
  42/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  43        { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  44                                                8, "[%s]: rx_ucast_packets" },
  45        { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  46                                                8, "[%s]: rx_mcast_packets" },
  47        { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  48                                                8, "[%s]: rx_bcast_packets" },
  49        { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  50        { Q_STATS_OFFSET32(rx_err_discard_pkt),
  51                                         4, "[%s]: rx_phy_ip_err_discards"},
  52        { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  53                                         4, "[%s]: rx_skb_alloc_discard" },
  54        { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  55        { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
  56        { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  57/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  58                                                8, "[%s]: tx_ucast_packets" },
  59        { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  60                                                8, "[%s]: tx_mcast_packets" },
  61        { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  62                                                8, "[%s]: tx_bcast_packets" },
  63        { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  64                                                8, "[%s]: tpa_aggregations" },
  65        { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  66                                        8, "[%s]: tpa_aggregated_frames"},
  67        { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
  68        { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
  69                                        4, "[%s]: driver_filtered_tx_pkt" }
  70};
  71
  72#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  73
  74static const struct {
  75        long offset;
  76        int size;
  77        bool is_port_stat;
  78        char string[ETH_GSTRING_LEN];
  79} bnx2x_stats_arr[] = {
  80/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  81                                8, false, "rx_bytes" },
  82        { STATS_OFFSET32(error_bytes_received_hi),
  83                                8, false, "rx_error_bytes" },
  84        { STATS_OFFSET32(total_unicast_packets_received_hi),
  85                                8, false, "rx_ucast_packets" },
  86        { STATS_OFFSET32(total_multicast_packets_received_hi),
  87                                8, false, "rx_mcast_packets" },
  88        { STATS_OFFSET32(total_broadcast_packets_received_hi),
  89                                8, false, "rx_bcast_packets" },
  90        { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  91                                8, true, "rx_crc_errors" },
  92        { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  93                                8, true, "rx_align_errors" },
  94        { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  95                                8, true, "rx_undersize_packets" },
  96        { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  97                                8, true, "rx_oversize_packets" },
  98/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  99                                8, true, "rx_fragments" },
 100        { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 101                                8, true, "rx_jabbers" },
 102        { STATS_OFFSET32(no_buff_discard_hi),
 103                                8, false, "rx_discards" },
 104        { STATS_OFFSET32(mac_filter_discard),
 105                                4, true, "rx_filtered_packets" },
 106        { STATS_OFFSET32(mf_tag_discard),
 107                                4, true, "rx_mf_tag_discard" },
 108        { STATS_OFFSET32(pfc_frames_received_hi),
 109                                8, true, "pfc_frames_received" },
 110        { STATS_OFFSET32(pfc_frames_sent_hi),
 111                                8, true, "pfc_frames_sent" },
 112        { STATS_OFFSET32(brb_drop_hi),
 113                                8, true, "rx_brb_discard" },
 114        { STATS_OFFSET32(brb_truncate_hi),
 115                                8, true, "rx_brb_truncate" },
 116        { STATS_OFFSET32(pause_frames_received_hi),
 117                                8, true, "rx_pause_frames" },
 118        { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 119                                8, true, "rx_mac_ctrl_frames" },
 120        { STATS_OFFSET32(nig_timer_max),
 121                                4, true, "rx_constant_pause_events" },
 122/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 123                                4, false, "rx_phy_ip_err_discards"},
 124        { STATS_OFFSET32(rx_skb_alloc_failed),
 125                                4, false, "rx_skb_alloc_discard" },
 126        { STATS_OFFSET32(hw_csum_err),
 127                                4, false, "rx_csum_offload_errors" },
 128        { STATS_OFFSET32(driver_xoff),
 129                                4, false, "tx_exhaustion_events" },
 130        { STATS_OFFSET32(total_bytes_transmitted_hi),
 131                                8, false, "tx_bytes" },
 132        { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 133                                8, true, "tx_error_bytes" },
 134        { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 135                                8, false, "tx_ucast_packets" },
 136        { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 137                                8, false, "tx_mcast_packets" },
 138        { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 139                                8, false, "tx_bcast_packets" },
 140        { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 141                                8, true, "tx_mac_errors" },
 142        { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 143                                8, true, "tx_carrier_errors" },
 144/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 145                                8, true, "tx_single_collisions" },
 146        { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 147                                8, true, "tx_multi_collisions" },
 148        { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 149                                8, true, "tx_deferred" },
 150        { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 151                                8, true, "tx_excess_collisions" },
 152        { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 153                                8, true, "tx_late_collisions" },
 154        { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 155                                8, true, "tx_total_collisions" },
 156        { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 157                                8, true, "tx_64_byte_packets" },
 158        { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 159                                8, true, "tx_65_to_127_byte_packets" },
 160        { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 161                                8, true, "tx_128_to_255_byte_packets" },
 162        { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 163                                8, true, "tx_256_to_511_byte_packets" },
 164/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 165                                8, true, "tx_512_to_1023_byte_packets" },
 166        { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 167                                8, true, "tx_1024_to_1522_byte_packets" },
 168        { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 169                                8, true, "tx_1523_to_9022_byte_packets" },
 170        { STATS_OFFSET32(pause_frames_sent_hi),
 171                                8, true, "tx_pause_frames" },
 172        { STATS_OFFSET32(total_tpa_aggregations_hi),
 173                                8, false, "tpa_aggregations" },
 174        { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 175                                8, false, "tpa_aggregated_frames"},
 176        { STATS_OFFSET32(total_tpa_bytes_hi),
 177                                8, false, "tpa_bytes"},
 178        { STATS_OFFSET32(recoverable_error),
 179                                4, false, "recoverable_errors" },
 180        { STATS_OFFSET32(unrecoverable_error),
 181                                4, false, "unrecoverable_errors" },
 182        { STATS_OFFSET32(driver_filtered_tx_pkt),
 183                                4, false, "driver_filtered_tx_pkt" },
 184        { STATS_OFFSET32(eee_tx_lpi),
 185                                4, true, "Tx LPI entry count"},
 186        { STATS_OFFSET32(ptp_skip_tx_ts),
 187                                4, false, "ptp_skipped_tx_tstamp" },
 188};
 189
 190#define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 191
 192static int bnx2x_get_port_type(struct bnx2x *bp)
 193{
 194        int port_type;
 195        u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 196        switch (bp->link_params.phy[phy_idx].media_type) {
 197        case ETH_PHY_SFPP_10G_FIBER:
 198        case ETH_PHY_SFP_1G_FIBER:
 199        case ETH_PHY_XFP_FIBER:
 200        case ETH_PHY_KR:
 201        case ETH_PHY_CX4:
 202                port_type = PORT_FIBRE;
 203                break;
 204        case ETH_PHY_DA_TWINAX:
 205                port_type = PORT_DA;
 206                break;
 207        case ETH_PHY_BASE_T:
 208                port_type = PORT_TP;
 209                break;
 210        case ETH_PHY_NOT_PRESENT:
 211                port_type = PORT_NONE;
 212                break;
 213        case ETH_PHY_UNSPECIFIED:
 214        default:
 215                port_type = PORT_OTHER;
 216                break;
 217        }
 218        return port_type;
 219}
 220
 221static int bnx2x_get_vf_link_ksettings(struct net_device *dev,
 222                                       struct ethtool_link_ksettings *cmd)
 223{
 224        struct bnx2x *bp = netdev_priv(dev);
 225        u32 supported, advertising;
 226
 227        ethtool_convert_link_mode_to_legacy_u32(&supported,
 228                                                cmd->link_modes.supported);
 229        ethtool_convert_link_mode_to_legacy_u32(&advertising,
 230                                                cmd->link_modes.advertising);
 231
 232        if (bp->state == BNX2X_STATE_OPEN) {
 233                if (test_bit(BNX2X_LINK_REPORT_FD,
 234                             &bp->vf_link_vars.link_report_flags))
 235                        cmd->base.duplex = DUPLEX_FULL;
 236                else
 237                        cmd->base.duplex = DUPLEX_HALF;
 238
 239                cmd->base.speed = bp->vf_link_vars.line_speed;
 240        } else {
 241                cmd->base.duplex = DUPLEX_UNKNOWN;
 242                cmd->base.speed = SPEED_UNKNOWN;
 243        }
 244
 245        cmd->base.port          = PORT_OTHER;
 246        cmd->base.phy_address   = 0;
 247        cmd->base.autoneg       = AUTONEG_DISABLE;
 248
 249        DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 250           "  supported 0x%x  advertising 0x%x  speed %u\n"
 251           "  duplex %d  port %d  phy_address %d\n"
 252           "  autoneg %d\n",
 253           cmd->base.cmd, supported, advertising,
 254           cmd->base.speed,
 255           cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
 256           cmd->base.autoneg);
 257
 258        return 0;
 259}
 260
 261static int bnx2x_get_link_ksettings(struct net_device *dev,
 262                                    struct ethtool_link_ksettings *cmd)
 263{
 264        struct bnx2x *bp = netdev_priv(dev);
 265        int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 266        u32 media_type;
 267        u32 supported, advertising, lp_advertising;
 268
 269        ethtool_convert_link_mode_to_legacy_u32(&lp_advertising,
 270                                                cmd->link_modes.lp_advertising);
 271
 272        /* Dual Media boards present all available port types */
 273        supported = bp->port.supported[cfg_idx] |
 274                (bp->port.supported[cfg_idx ^ 1] &
 275                 (SUPPORTED_TP | SUPPORTED_FIBRE));
 276        advertising = bp->port.advertising[cfg_idx];
 277        media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
 278        if (media_type == ETH_PHY_SFP_1G_FIBER) {
 279                supported &= ~(SUPPORTED_10000baseT_Full);
 280                advertising &= ~(ADVERTISED_10000baseT_Full);
 281        }
 282
 283        if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
 284            !(bp->flags & MF_FUNC_DIS)) {
 285                cmd->base.duplex = bp->link_vars.duplex;
 286
 287                if (IS_MF(bp) && !BP_NOMCP(bp))
 288                        cmd->base.speed = bnx2x_get_mf_speed(bp);
 289                else
 290                        cmd->base.speed = bp->link_vars.line_speed;
 291        } else {
 292                cmd->base.duplex = DUPLEX_UNKNOWN;
 293                cmd->base.speed = SPEED_UNKNOWN;
 294        }
 295
 296        cmd->base.port = bnx2x_get_port_type(bp);
 297
 298        cmd->base.phy_address = bp->mdio.prtad;
 299
 300        if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 301                cmd->base.autoneg = AUTONEG_ENABLE;
 302        else
 303                cmd->base.autoneg = AUTONEG_DISABLE;
 304
 305        /* Publish LP advertised speeds and FC */
 306        if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 307                u32 status = bp->link_vars.link_status;
 308
 309                lp_advertising |= ADVERTISED_Autoneg;
 310                if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 311                        lp_advertising |= ADVERTISED_Pause;
 312                if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 313                        lp_advertising |= ADVERTISED_Asym_Pause;
 314
 315                if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 316                        lp_advertising |= ADVERTISED_10baseT_Half;
 317                if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 318                        lp_advertising |= ADVERTISED_10baseT_Full;
 319                if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 320                        lp_advertising |= ADVERTISED_100baseT_Half;
 321                if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 322                        lp_advertising |= ADVERTISED_100baseT_Full;
 323                if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 324                        lp_advertising |= ADVERTISED_1000baseT_Half;
 325                if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
 326                        if (media_type == ETH_PHY_KR) {
 327                                lp_advertising |=
 328                                        ADVERTISED_1000baseKX_Full;
 329                        } else {
 330                                lp_advertising |=
 331                                        ADVERTISED_1000baseT_Full;
 332                        }
 333                }
 334                if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 335                        lp_advertising |= ADVERTISED_2500baseX_Full;
 336                if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
 337                        if (media_type == ETH_PHY_KR) {
 338                                lp_advertising |=
 339                                        ADVERTISED_10000baseKR_Full;
 340                        } else {
 341                                lp_advertising |=
 342                                        ADVERTISED_10000baseT_Full;
 343                        }
 344                }
 345                if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
 346                        lp_advertising |= ADVERTISED_20000baseKR2_Full;
 347        }
 348
 349        ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
 350                                                supported);
 351        ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
 352                                                advertising);
 353        ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
 354                                                lp_advertising);
 355
 356        DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 357           "  supported 0x%x  advertising 0x%x  speed %u\n"
 358           "  duplex %d  port %d  phy_address %d\n"
 359           "  autoneg %d\n",
 360           cmd->base.cmd, supported, advertising,
 361           cmd->base.speed,
 362           cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
 363           cmd->base.autoneg);
 364
 365        return 0;
 366}
 367
 368static int bnx2x_set_link_ksettings(struct net_device *dev,
 369                                    const struct ethtool_link_ksettings *cmd)
 370{
 371        struct bnx2x *bp = netdev_priv(dev);
 372        u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 373        u32 speed, phy_idx;
 374        u32 supported;
 375        u8 duplex = cmd->base.duplex;
 376
 377        ethtool_convert_link_mode_to_legacy_u32(&supported,
 378                                                cmd->link_modes.supported);
 379        ethtool_convert_link_mode_to_legacy_u32(&advertising,
 380                                                cmd->link_modes.advertising);
 381
 382        if (IS_MF_SD(bp))
 383                return 0;
 384
 385        DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 386           "  supported 0x%x  advertising 0x%x  speed %u\n"
 387           "  duplex %d  port %d  phy_address %d\n"
 388           "  autoneg %d\n",
 389           cmd->base.cmd, supported, advertising,
 390           cmd->base.speed,
 391           cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
 392           cmd->base.autoneg);
 393
 394        speed = cmd->base.speed;
 395
 396        /* If received a request for an unknown duplex, assume full*/
 397        if (duplex == DUPLEX_UNKNOWN)
 398                duplex = DUPLEX_FULL;
 399
 400        if (IS_MF_SI(bp)) {
 401                u32 part;
 402                u32 line_speed = bp->link_vars.line_speed;
 403
 404                /* use 10G if no link detected */
 405                if (!line_speed)
 406                        line_speed = 10000;
 407
 408                if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 409                        DP(BNX2X_MSG_ETHTOOL,
 410                           "To set speed BC %X or higher is required, please upgrade BC\n",
 411                           REQ_BC_VER_4_SET_MF_BW);
 412                        return -EINVAL;
 413                }
 414
 415                part = (speed * 100) / line_speed;
 416
 417                if (line_speed < speed || !part) {
 418                        DP(BNX2X_MSG_ETHTOOL,
 419                           "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 420                        return -EINVAL;
 421                }
 422
 423                if (bp->state != BNX2X_STATE_OPEN)
 424                        /* store value for following "load" */
 425                        bp->pending_max = part;
 426                else
 427                        bnx2x_update_max_mf_config(bp, part);
 428
 429                return 0;
 430        }
 431
 432        cfg_idx = bnx2x_get_link_cfg_idx(bp);
 433        old_multi_phy_config = bp->link_params.multi_phy_config;
 434        if (cmd->base.port != bnx2x_get_port_type(bp)) {
 435                switch (cmd->base.port) {
 436                case PORT_TP:
 437                        if (!(bp->port.supported[0] & SUPPORTED_TP ||
 438                              bp->port.supported[1] & SUPPORTED_TP)) {
 439                                DP(BNX2X_MSG_ETHTOOL,
 440                                   "Unsupported port type\n");
 441                                return -EINVAL;
 442                        }
 443                        bp->link_params.multi_phy_config &=
 444                                ~PORT_HW_CFG_PHY_SELECTION_MASK;
 445                        if (bp->link_params.multi_phy_config &
 446                            PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 447                                bp->link_params.multi_phy_config |=
 448                                PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 449                        else
 450                                bp->link_params.multi_phy_config |=
 451                                PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 452                        break;
 453                case PORT_FIBRE:
 454                case PORT_DA:
 455                case PORT_NONE:
 456                        if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 457                              bp->port.supported[1] & SUPPORTED_FIBRE)) {
 458                                DP(BNX2X_MSG_ETHTOOL,
 459                                   "Unsupported port type\n");
 460                                return -EINVAL;
 461                        }
 462                        bp->link_params.multi_phy_config &=
 463                                ~PORT_HW_CFG_PHY_SELECTION_MASK;
 464                        if (bp->link_params.multi_phy_config &
 465                            PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 466                                bp->link_params.multi_phy_config |=
 467                                PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 468                        else
 469                                bp->link_params.multi_phy_config |=
 470                                PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 471                        break;
 472                default:
 473                        DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 474                        return -EINVAL;
 475                }
 476        }
 477        /* Save new config in case command complete successfully */
 478        new_multi_phy_config = bp->link_params.multi_phy_config;
 479        /* Get the new cfg_idx */
 480        cfg_idx = bnx2x_get_link_cfg_idx(bp);
 481        /* Restore old config in case command failed */
 482        bp->link_params.multi_phy_config = old_multi_phy_config;
 483        DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 484
 485        if (cmd->base.autoneg == AUTONEG_ENABLE) {
 486                u32 an_supported_speed = bp->port.supported[cfg_idx];
 487                if (bp->link_params.phy[EXT_PHY1].type ==
 488                    PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 489                        an_supported_speed |= (SUPPORTED_100baseT_Half |
 490                                               SUPPORTED_100baseT_Full);
 491                if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 492                        DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 493                        return -EINVAL;
 494                }
 495
 496                /* advertise the requested speed and duplex if supported */
 497                if (advertising & ~an_supported_speed) {
 498                        DP(BNX2X_MSG_ETHTOOL,
 499                           "Advertisement parameters are not supported\n");
 500                        return -EINVAL;
 501                }
 502
 503                bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 504                bp->link_params.req_duplex[cfg_idx] = duplex;
 505                bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 506                                         advertising);
 507                if (advertising) {
 508
 509                        bp->link_params.speed_cap_mask[cfg_idx] = 0;
 510                        if (advertising & ADVERTISED_10baseT_Half) {
 511                                bp->link_params.speed_cap_mask[cfg_idx] |=
 512                                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 513                        }
 514                        if (advertising & ADVERTISED_10baseT_Full)
 515                                bp->link_params.speed_cap_mask[cfg_idx] |=
 516                                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 517
 518                        if (advertising & ADVERTISED_100baseT_Full)
 519                                bp->link_params.speed_cap_mask[cfg_idx] |=
 520                                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 521
 522                        if (advertising & ADVERTISED_100baseT_Half) {
 523                                bp->link_params.speed_cap_mask[cfg_idx] |=
 524                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 525                        }
 526                        if (advertising & ADVERTISED_1000baseT_Half) {
 527                                bp->link_params.speed_cap_mask[cfg_idx] |=
 528                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 529                        }
 530                        if (advertising & (ADVERTISED_1000baseT_Full |
 531                                                ADVERTISED_1000baseKX_Full))
 532                                bp->link_params.speed_cap_mask[cfg_idx] |=
 533                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 534
 535                        if (advertising & (ADVERTISED_10000baseT_Full |
 536                                                ADVERTISED_10000baseKX4_Full |
 537                                                ADVERTISED_10000baseKR_Full))
 538                                bp->link_params.speed_cap_mask[cfg_idx] |=
 539                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 540
 541                        if (advertising & ADVERTISED_20000baseKR2_Full)
 542                                bp->link_params.speed_cap_mask[cfg_idx] |=
 543                                        PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
 544                }
 545        } else { /* forced speed */
 546                /* advertise the requested speed and duplex if supported */
 547                switch (speed) {
 548                case SPEED_10:
 549                        if (duplex == DUPLEX_FULL) {
 550                                if (!(bp->port.supported[cfg_idx] &
 551                                      SUPPORTED_10baseT_Full)) {
 552                                        DP(BNX2X_MSG_ETHTOOL,
 553                                           "10M full not supported\n");
 554                                        return -EINVAL;
 555                                }
 556
 557                                advertising = (ADVERTISED_10baseT_Full |
 558                                               ADVERTISED_TP);
 559                        } else {
 560                                if (!(bp->port.supported[cfg_idx] &
 561                                      SUPPORTED_10baseT_Half)) {
 562                                        DP(BNX2X_MSG_ETHTOOL,
 563                                           "10M half not supported\n");
 564                                        return -EINVAL;
 565                                }
 566
 567                                advertising = (ADVERTISED_10baseT_Half |
 568                                               ADVERTISED_TP);
 569                        }
 570                        break;
 571
 572                case SPEED_100:
 573                        if (duplex == DUPLEX_FULL) {
 574                                if (!(bp->port.supported[cfg_idx] &
 575                                                SUPPORTED_100baseT_Full)) {
 576                                        DP(BNX2X_MSG_ETHTOOL,
 577                                           "100M full not supported\n");
 578                                        return -EINVAL;
 579                                }
 580
 581                                advertising = (ADVERTISED_100baseT_Full |
 582                                               ADVERTISED_TP);
 583                        } else {
 584                                if (!(bp->port.supported[cfg_idx] &
 585                                                SUPPORTED_100baseT_Half)) {
 586                                        DP(BNX2X_MSG_ETHTOOL,
 587                                           "100M half not supported\n");
 588                                        return -EINVAL;
 589                                }
 590
 591                                advertising = (ADVERTISED_100baseT_Half |
 592                                               ADVERTISED_TP);
 593                        }
 594                        break;
 595
 596                case SPEED_1000:
 597                        if (duplex != DUPLEX_FULL) {
 598                                DP(BNX2X_MSG_ETHTOOL,
 599                                   "1G half not supported\n");
 600                                return -EINVAL;
 601                        }
 602
 603                        if (bp->port.supported[cfg_idx] &
 604                             SUPPORTED_1000baseT_Full) {
 605                                advertising = (ADVERTISED_1000baseT_Full |
 606                                               ADVERTISED_TP);
 607
 608                        } else if (bp->port.supported[cfg_idx] &
 609                                   SUPPORTED_1000baseKX_Full) {
 610                                advertising = ADVERTISED_1000baseKX_Full;
 611                        } else {
 612                                DP(BNX2X_MSG_ETHTOOL,
 613                                   "1G full not supported\n");
 614                                return -EINVAL;
 615                        }
 616
 617                        break;
 618
 619                case SPEED_2500:
 620                        if (duplex != DUPLEX_FULL) {
 621                                DP(BNX2X_MSG_ETHTOOL,
 622                                   "2.5G half not supported\n");
 623                                return -EINVAL;
 624                        }
 625
 626                        if (!(bp->port.supported[cfg_idx]
 627                              & SUPPORTED_2500baseX_Full)) {
 628                                DP(BNX2X_MSG_ETHTOOL,
 629                                   "2.5G full not supported\n");
 630                                return -EINVAL;
 631                        }
 632
 633                        advertising = (ADVERTISED_2500baseX_Full |
 634                                       ADVERTISED_TP);
 635                        break;
 636
 637                case SPEED_10000:
 638                        if (duplex != DUPLEX_FULL) {
 639                                DP(BNX2X_MSG_ETHTOOL,
 640                                   "10G half not supported\n");
 641                                return -EINVAL;
 642                        }
 643                        phy_idx = bnx2x_get_cur_phy_idx(bp);
 644                        if ((bp->port.supported[cfg_idx] &
 645                             SUPPORTED_10000baseT_Full) &&
 646                            (bp->link_params.phy[phy_idx].media_type !=
 647                             ETH_PHY_SFP_1G_FIBER)) {
 648                                advertising = (ADVERTISED_10000baseT_Full |
 649                                               ADVERTISED_FIBRE);
 650                        } else if (bp->port.supported[cfg_idx] &
 651                               SUPPORTED_10000baseKR_Full) {
 652                                advertising = (ADVERTISED_10000baseKR_Full |
 653                                               ADVERTISED_FIBRE);
 654                        } else {
 655                                DP(BNX2X_MSG_ETHTOOL,
 656                                   "10G full not supported\n");
 657                                return -EINVAL;
 658                        }
 659
 660                        break;
 661
 662                default:
 663                        DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 664                        return -EINVAL;
 665                }
 666
 667                bp->link_params.req_line_speed[cfg_idx] = speed;
 668                bp->link_params.req_duplex[cfg_idx] = duplex;
 669                bp->port.advertising[cfg_idx] = advertising;
 670        }
 671
 672        DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 673           "  req_duplex %d  advertising 0x%x\n",
 674           bp->link_params.req_line_speed[cfg_idx],
 675           bp->link_params.req_duplex[cfg_idx],
 676           bp->port.advertising[cfg_idx]);
 677
 678        /* Set new config */
 679        bp->link_params.multi_phy_config = new_multi_phy_config;
 680        if (netif_running(dev)) {
 681                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 682                bnx2x_force_link_reset(bp);
 683                bnx2x_link_set(bp);
 684        }
 685
 686        return 0;
 687}
 688
 689#define DUMP_ALL_PRESETS                0x1FFF
 690#define DUMP_MAX_PRESETS                13
 691
 692static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
 693{
 694        if (CHIP_IS_E1(bp))
 695                return dump_num_registers[0][preset-1];
 696        else if (CHIP_IS_E1H(bp))
 697                return dump_num_registers[1][preset-1];
 698        else if (CHIP_IS_E2(bp))
 699                return dump_num_registers[2][preset-1];
 700        else if (CHIP_IS_E3A0(bp))
 701                return dump_num_registers[3][preset-1];
 702        else if (CHIP_IS_E3B0(bp))
 703                return dump_num_registers[4][preset-1];
 704        else
 705                return 0;
 706}
 707
 708static int __bnx2x_get_regs_len(struct bnx2x *bp)
 709{
 710        u32 preset_idx;
 711        int regdump_len = 0;
 712
 713        /* Calculate the total preset regs length */
 714        for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
 715                regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
 716
 717        return regdump_len;
 718}
 719
 720static int bnx2x_get_regs_len(struct net_device *dev)
 721{
 722        struct bnx2x *bp = netdev_priv(dev);
 723        int regdump_len = 0;
 724
 725        if (IS_VF(bp))
 726                return 0;
 727
 728        regdump_len = __bnx2x_get_regs_len(bp);
 729        regdump_len *= 4;
 730        regdump_len += sizeof(struct dump_header);
 731
 732        return regdump_len;
 733}
 734
 735#define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
 736#define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
 737#define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
 738#define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
 739#define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
 740
 741#define IS_REG_IN_PRESET(presets, idx)  \
 742                ((presets & (1 << (idx-1))) == (1 << (idx-1)))
 743
 744/******* Paged registers info selectors ********/
 745static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 746{
 747        if (CHIP_IS_E2(bp))
 748                return page_vals_e2;
 749        else if (CHIP_IS_E3(bp))
 750                return page_vals_e3;
 751        else
 752                return NULL;
 753}
 754
 755static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 756{
 757        if (CHIP_IS_E2(bp))
 758                return PAGE_MODE_VALUES_E2;
 759        else if (CHIP_IS_E3(bp))
 760                return PAGE_MODE_VALUES_E3;
 761        else
 762                return 0;
 763}
 764
 765static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 766{
 767        if (CHIP_IS_E2(bp))
 768                return page_write_regs_e2;
 769        else if (CHIP_IS_E3(bp))
 770                return page_write_regs_e3;
 771        else
 772                return NULL;
 773}
 774
 775static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 776{
 777        if (CHIP_IS_E2(bp))
 778                return PAGE_WRITE_REGS_E2;
 779        else if (CHIP_IS_E3(bp))
 780                return PAGE_WRITE_REGS_E3;
 781        else
 782                return 0;
 783}
 784
 785static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 786{
 787        if (CHIP_IS_E2(bp))
 788                return page_read_regs_e2;
 789        else if (CHIP_IS_E3(bp))
 790                return page_read_regs_e3;
 791        else
 792                return NULL;
 793}
 794
 795static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 796{
 797        if (CHIP_IS_E2(bp))
 798                return PAGE_READ_REGS_E2;
 799        else if (CHIP_IS_E3(bp))
 800                return PAGE_READ_REGS_E3;
 801        else
 802                return 0;
 803}
 804
 805static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
 806                                       const struct reg_addr *reg_info)
 807{
 808        if (CHIP_IS_E1(bp))
 809                return IS_E1_REG(reg_info->chips);
 810        else if (CHIP_IS_E1H(bp))
 811                return IS_E1H_REG(reg_info->chips);
 812        else if (CHIP_IS_E2(bp))
 813                return IS_E2_REG(reg_info->chips);
 814        else if (CHIP_IS_E3A0(bp))
 815                return IS_E3A0_REG(reg_info->chips);
 816        else if (CHIP_IS_E3B0(bp))
 817                return IS_E3B0_REG(reg_info->chips);
 818        else
 819                return false;
 820}
 821
 822static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
 823        const struct wreg_addr *wreg_info)
 824{
 825        if (CHIP_IS_E1(bp))
 826                return IS_E1_REG(wreg_info->chips);
 827        else if (CHIP_IS_E1H(bp))
 828                return IS_E1H_REG(wreg_info->chips);
 829        else if (CHIP_IS_E2(bp))
 830                return IS_E2_REG(wreg_info->chips);
 831        else if (CHIP_IS_E3A0(bp))
 832                return IS_E3A0_REG(wreg_info->chips);
 833        else if (CHIP_IS_E3B0(bp))
 834                return IS_E3B0_REG(wreg_info->chips);
 835        else
 836                return false;
 837}
 838
 839/**
 840 * bnx2x_read_pages_regs - read "paged" registers
 841 *
 842 * @bp:         device handle
 843 * @p:          output buffer
 844 * @preset:     the preset value
 845 *
 846 * Reads "paged" memories: memories that may only be read by first writing to a
 847 * specific address ("write address") and then reading from a specific address
 848 * ("read address"). There may be more than one write address per "page" and
 849 * more than one read address per write address.
 850 */
 851static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
 852{
 853        u32 i, j, k, n;
 854
 855        /* addresses of the paged registers */
 856        const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 857        /* number of paged registers */
 858        int num_pages = __bnx2x_get_page_reg_num(bp);
 859        /* write addresses */
 860        const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 861        /* number of write addresses */
 862        int write_num = __bnx2x_get_page_write_num(bp);
 863        /* read addresses info */
 864        const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 865        /* number of read addresses */
 866        int read_num = __bnx2x_get_page_read_num(bp);
 867        u32 addr, size;
 868
 869        for (i = 0; i < num_pages; i++) {
 870                for (j = 0; j < write_num; j++) {
 871                        REG_WR(bp, write_addr[j], page_addr[i]);
 872
 873                        for (k = 0; k < read_num; k++) {
 874                                if (IS_REG_IN_PRESET(read_addr[k].presets,
 875                                                     preset)) {
 876                                        size = read_addr[k].size;
 877                                        for (n = 0; n < size; n++) {
 878                                                addr = read_addr[k].addr + n*4;
 879                                                *p++ = REG_RD(bp, addr);
 880                                        }
 881                                }
 882                        }
 883                }
 884        }
 885}
 886
 887static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
 888{
 889        u32 i, j, addr;
 890        const struct wreg_addr *wreg_addr_p = NULL;
 891
 892        if (CHIP_IS_E1(bp))
 893                wreg_addr_p = &wreg_addr_e1;
 894        else if (CHIP_IS_E1H(bp))
 895                wreg_addr_p = &wreg_addr_e1h;
 896        else if (CHIP_IS_E2(bp))
 897                wreg_addr_p = &wreg_addr_e2;
 898        else if (CHIP_IS_E3A0(bp))
 899                wreg_addr_p = &wreg_addr_e3;
 900        else if (CHIP_IS_E3B0(bp))
 901                wreg_addr_p = &wreg_addr_e3b0;
 902
 903        /* Read the idle_chk registers */
 904        for (i = 0; i < IDLE_REGS_COUNT; i++) {
 905                if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
 906                    IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
 907                        for (j = 0; j < idle_reg_addrs[i].size; j++)
 908                                *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
 909                }
 910        }
 911
 912        /* Read the regular registers */
 913        for (i = 0; i < REGS_COUNT; i++) {
 914                if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
 915                    IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
 916                        for (j = 0; j < reg_addrs[i].size; j++)
 917                                *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 918                }
 919        }
 920
 921        /* Read the CAM registers */
 922        if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
 923            IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
 924                for (i = 0; i < wreg_addr_p->size; i++) {
 925                        *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
 926
 927                        /* In case of wreg_addr register, read additional
 928                           registers from read_regs array
 929                        */
 930                        for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
 931                                addr = *(wreg_addr_p->read_regs);
 932                                *p++ = REG_RD(bp, addr + j*4);
 933                        }
 934                }
 935        }
 936
 937        /* Paged registers are supported in E2 & E3 only */
 938        if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
 939                /* Read "paged" registers */
 940                bnx2x_read_pages_regs(bp, p, preset);
 941        }
 942
 943        return 0;
 944}
 945
 946static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 947{
 948        u32 preset_idx;
 949
 950        /* Read all registers, by reading all preset registers */
 951        for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
 952                /* Skip presets with IOR */
 953                if ((preset_idx == 2) ||
 954                    (preset_idx == 5) ||
 955                    (preset_idx == 8) ||
 956                    (preset_idx == 11))
 957                        continue;
 958                __bnx2x_get_preset_regs(bp, p, preset_idx);
 959                p += __bnx2x_get_preset_regs_len(bp, preset_idx);
 960        }
 961}
 962
 963static void bnx2x_get_regs(struct net_device *dev,
 964                           struct ethtool_regs *regs, void *_p)
 965{
 966        u32 *p = _p;
 967        struct bnx2x *bp = netdev_priv(dev);
 968        struct dump_header dump_hdr = {0};
 969
 970        regs->version = 2;
 971        memset(p, 0, regs->len);
 972
 973        if (!netif_running(bp->dev))
 974                return;
 975
 976        /* Disable parity attentions as long as following dump may
 977         * cause false alarms by reading never written registers. We
 978         * will re-enable parity attentions right after the dump.
 979         */
 980
 981        bnx2x_disable_blocks_parity(bp);
 982
 983        dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 984        dump_hdr.preset = DUMP_ALL_PRESETS;
 985        dump_hdr.version = BNX2X_DUMP_VERSION;
 986
 987        /* dump_meta_data presents OR of CHIP and PATH. */
 988        if (CHIP_IS_E1(bp)) {
 989                dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 990        } else if (CHIP_IS_E1H(bp)) {
 991                dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 992        } else if (CHIP_IS_E2(bp)) {
 993                dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 994                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 995        } else if (CHIP_IS_E3A0(bp)) {
 996                dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 997                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 998        } else if (CHIP_IS_E3B0(bp)) {
 999                dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1000                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1001        }
1002
1003        memcpy(p, &dump_hdr, sizeof(struct dump_header));
1004        p += dump_hdr.header_size + 1;
1005
1006        /* This isn't really an error, but since attention handling is going
1007         * to print the GRC timeouts using this macro, we use the same.
1008         */
1009        BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n");
1010
1011        /* Actually read the registers */
1012        __bnx2x_get_regs(bp, p);
1013
1014        /* Re-enable parity attentions */
1015        bnx2x_clear_blocks_parity(bp);
1016        bnx2x_enable_blocks_parity(bp);
1017}
1018
1019static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
1020{
1021        struct bnx2x *bp = netdev_priv(dev);
1022        int regdump_len = 0;
1023
1024        regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1025        regdump_len *= 4;
1026        regdump_len += sizeof(struct dump_header);
1027
1028        return regdump_len;
1029}
1030
1031static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1032{
1033        struct bnx2x *bp = netdev_priv(dev);
1034
1035        /* Use the ethtool_dump "flag" field as the dump preset index */
1036        if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1037                return -EINVAL;
1038
1039        bp->dump_preset_idx = val->flag;
1040        return 0;
1041}
1042
1043static int bnx2x_get_dump_flag(struct net_device *dev,
1044                               struct ethtool_dump *dump)
1045{
1046        struct bnx2x *bp = netdev_priv(dev);
1047
1048        dump->version = BNX2X_DUMP_VERSION;
1049        dump->flag = bp->dump_preset_idx;
1050        /* Calculate the requested preset idx length */
1051        dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1052        DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1053           bp->dump_preset_idx, dump->len);
1054        return 0;
1055}
1056
1057static int bnx2x_get_dump_data(struct net_device *dev,
1058                               struct ethtool_dump *dump,
1059                               void *buffer)
1060{
1061        u32 *p = buffer;
1062        struct bnx2x *bp = netdev_priv(dev);
1063        struct dump_header dump_hdr = {0};
1064
1065        /* Disable parity attentions as long as following dump may
1066         * cause false alarms by reading never written registers. We
1067         * will re-enable parity attentions right after the dump.
1068         */
1069
1070        bnx2x_disable_blocks_parity(bp);
1071
1072        dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1073        dump_hdr.preset = bp->dump_preset_idx;
1074        dump_hdr.version = BNX2X_DUMP_VERSION;
1075
1076        DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1077
1078        /* dump_meta_data presents OR of CHIP and PATH. */
1079        if (CHIP_IS_E1(bp)) {
1080                dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1081        } else if (CHIP_IS_E1H(bp)) {
1082                dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1083        } else if (CHIP_IS_E2(bp)) {
1084                dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1085                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1086        } else if (CHIP_IS_E3A0(bp)) {
1087                dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1088                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1089        } else if (CHIP_IS_E3B0(bp)) {
1090                dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1091                (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1092        }
1093
1094        memcpy(p, &dump_hdr, sizeof(struct dump_header));
1095        p += dump_hdr.header_size + 1;
1096
1097        /* Actually read the registers */
1098        __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1099
1100        /* Re-enable parity attentions */
1101        bnx2x_clear_blocks_parity(bp);
1102        bnx2x_enable_blocks_parity(bp);
1103
1104        return 0;
1105}
1106
1107static void bnx2x_get_drvinfo(struct net_device *dev,
1108                              struct ethtool_drvinfo *info)
1109{
1110        struct bnx2x *bp = netdev_priv(dev);
1111        char version[ETHTOOL_FWVERS_LEN];
1112        int ext_dev_info_offset;
1113        u32 mbi;
1114
1115        strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1116
1117        if (SHMEM2_HAS(bp, extended_dev_info_shared_addr)) {
1118                ext_dev_info_offset = SHMEM2_RD(bp,
1119                                                extended_dev_info_shared_addr);
1120                mbi = REG_RD(bp, ext_dev_info_offset +
1121                             offsetof(struct extended_dev_info_shared_cfg,
1122                                      mbi_version));
1123                if (mbi) {
1124                        memset(version, 0, sizeof(version));
1125                        snprintf(version, ETHTOOL_FWVERS_LEN, "mbi %d.%d.%d ",
1126                                 (mbi & 0xff000000) >> 24,
1127                                 (mbi & 0x00ff0000) >> 16,
1128                                 (mbi & 0x0000ff00) >> 8);
1129                        strlcpy(info->fw_version, version,
1130                                sizeof(info->fw_version));
1131                }
1132        }
1133
1134        memset(version, 0, sizeof(version));
1135        bnx2x_fill_fw_str(bp, version, ETHTOOL_FWVERS_LEN);
1136        strlcat(info->fw_version, version, sizeof(info->fw_version));
1137
1138        strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1139}
1140
1141static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1142{
1143        struct bnx2x *bp = netdev_priv(dev);
1144
1145        if (bp->flags & NO_WOL_FLAG) {
1146                wol->supported = 0;
1147                wol->wolopts = 0;
1148        } else {
1149                wol->supported = WAKE_MAGIC;
1150                if (bp->wol)
1151                        wol->wolopts = WAKE_MAGIC;
1152                else
1153                        wol->wolopts = 0;
1154        }
1155        memset(&wol->sopass, 0, sizeof(wol->sopass));
1156}
1157
1158static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1159{
1160        struct bnx2x *bp = netdev_priv(dev);
1161
1162        if (wol->wolopts & ~WAKE_MAGIC) {
1163                DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1164                return -EINVAL;
1165        }
1166
1167        if (wol->wolopts & WAKE_MAGIC) {
1168                if (bp->flags & NO_WOL_FLAG) {
1169                        DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1170                        return -EINVAL;
1171                }
1172                bp->wol = 1;
1173        } else
1174                bp->wol = 0;
1175
1176        if (SHMEM2_HAS(bp, curr_cfg))
1177                SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1178
1179        return 0;
1180}
1181
1182static u32 bnx2x_get_msglevel(struct net_device *dev)
1183{
1184        struct bnx2x *bp = netdev_priv(dev);
1185
1186        return bp->msg_enable;
1187}
1188
1189static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1190{
1191        struct bnx2x *bp = netdev_priv(dev);
1192
1193        if (capable(CAP_NET_ADMIN)) {
1194                /* dump MCP trace */
1195                if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1196                        bnx2x_fw_dump_lvl(bp, KERN_INFO);
1197                bp->msg_enable = level;
1198        }
1199}
1200
1201static int bnx2x_nway_reset(struct net_device *dev)
1202{
1203        struct bnx2x *bp = netdev_priv(dev);
1204
1205        if (!bp->port.pmf)
1206                return 0;
1207
1208        if (netif_running(dev)) {
1209                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1210                bnx2x_force_link_reset(bp);
1211                bnx2x_link_set(bp);
1212        }
1213
1214        return 0;
1215}
1216
1217static u32 bnx2x_get_link(struct net_device *dev)
1218{
1219        struct bnx2x *bp = netdev_priv(dev);
1220
1221        if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1222                return 0;
1223
1224        if (IS_VF(bp))
1225                return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1226                                 &bp->vf_link_vars.link_report_flags);
1227
1228        return bp->link_vars.link_up;
1229}
1230
1231static int bnx2x_get_eeprom_len(struct net_device *dev)
1232{
1233        struct bnx2x *bp = netdev_priv(dev);
1234
1235        return bp->common.flash_size;
1236}
1237
1238/* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1239 * had we done things the other way around, if two pfs from the same port would
1240 * attempt to access nvram at the same time, we could run into a scenario such
1241 * as:
1242 * pf A takes the port lock.
1243 * pf B succeeds in taking the same lock since they are from the same port.
1244 * pf A takes the per pf misc lock. Performs eeprom access.
1245 * pf A finishes. Unlocks the per pf misc lock.
1246 * Pf B takes the lock and proceeds to perform it's own access.
1247 * pf A unlocks the per port lock, while pf B is still working (!).
1248 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1249 * access corrupted by pf B)
1250 */
1251static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1252{
1253        int port = BP_PORT(bp);
1254        int count, i;
1255        u32 val;
1256
1257        /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1258        bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1259
1260        /* adjust timeout for emulation/FPGA */
1261        count = BNX2X_NVRAM_TIMEOUT_COUNT;
1262        if (CHIP_REV_IS_SLOW(bp))
1263                count *= 100;
1264
1265        /* request access to nvram interface */
1266        REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1267               (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1268
1269        for (i = 0; i < count*10; i++) {
1270                val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1271                if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1272                        break;
1273
1274                udelay(5);
1275        }
1276
1277        if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1278                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1279                   "cannot get access to nvram interface\n");
1280                bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1281                return -EBUSY;
1282        }
1283
1284        return 0;
1285}
1286
1287static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1288{
1289        int port = BP_PORT(bp);
1290        int count, i;
1291        u32 val;
1292
1293        /* adjust timeout for emulation/FPGA */
1294        count = BNX2X_NVRAM_TIMEOUT_COUNT;
1295        if (CHIP_REV_IS_SLOW(bp))
1296                count *= 100;
1297
1298        /* relinquish nvram interface */
1299        REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1300               (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1301
1302        for (i = 0; i < count*10; i++) {
1303                val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1304                if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1305                        break;
1306
1307                udelay(5);
1308        }
1309
1310        if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1311                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1312                   "cannot free access to nvram interface\n");
1313                return -EBUSY;
1314        }
1315
1316        /* release HW lock: protect against other PFs in PF Direct Assignment */
1317        bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1318        return 0;
1319}
1320
1321static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1322{
1323        u32 val;
1324
1325        val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1326
1327        /* enable both bits, even on read */
1328        REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1329               (val | MCPR_NVM_ACCESS_ENABLE_EN |
1330                      MCPR_NVM_ACCESS_ENABLE_WR_EN));
1331}
1332
1333static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1334{
1335        u32 val;
1336
1337        val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1338
1339        /* disable both bits, even after read */
1340        REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1341               (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1342                        MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1343}
1344
1345static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1346                                  u32 cmd_flags)
1347{
1348        int count, i, rc;
1349        u32 val;
1350
1351        /* build the command word */
1352        cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1353
1354        /* need to clear DONE bit separately */
1355        REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1356
1357        /* address of the NVRAM to read from */
1358        REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1359               (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1360
1361        /* issue a read command */
1362        REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1363
1364        /* adjust timeout for emulation/FPGA */
1365        count = BNX2X_NVRAM_TIMEOUT_COUNT;
1366        if (CHIP_REV_IS_SLOW(bp))
1367                count *= 100;
1368
1369        /* wait for completion */
1370        *ret_val = 0;
1371        rc = -EBUSY;
1372        for (i = 0; i < count; i++) {
1373                udelay(5);
1374                val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1375
1376                if (val & MCPR_NVM_COMMAND_DONE) {
1377                        val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1378                        /* we read nvram data in cpu order
1379                         * but ethtool sees it as an array of bytes
1380                         * converting to big-endian will do the work
1381                         */
1382                        *ret_val = cpu_to_be32(val);
1383                        rc = 0;
1384                        break;
1385                }
1386        }
1387        if (rc == -EBUSY)
1388                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1389                   "nvram read timeout expired\n");
1390        return rc;
1391}
1392
1393int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1394                     int buf_size)
1395{
1396        int rc;
1397        u32 cmd_flags;
1398        __be32 val;
1399
1400        if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1401                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1402                   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1403                   offset, buf_size);
1404                return -EINVAL;
1405        }
1406
1407        if (offset + buf_size > bp->common.flash_size) {
1408                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1409                   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1410                   offset, buf_size, bp->common.flash_size);
1411                return -EINVAL;
1412        }
1413
1414        /* request access to nvram interface */
1415        rc = bnx2x_acquire_nvram_lock(bp);
1416        if (rc)
1417                return rc;
1418
1419        /* enable access to nvram interface */
1420        bnx2x_enable_nvram_access(bp);
1421
1422        /* read the first word(s) */
1423        cmd_flags = MCPR_NVM_COMMAND_FIRST;
1424        while ((buf_size > sizeof(u32)) && (rc == 0)) {
1425                rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1426                memcpy(ret_buf, &val, 4);
1427
1428                /* advance to the next dword */
1429                offset += sizeof(u32);
1430                ret_buf += sizeof(u32);
1431                buf_size -= sizeof(u32);
1432                cmd_flags = 0;
1433        }
1434
1435        if (rc == 0) {
1436                cmd_flags |= MCPR_NVM_COMMAND_LAST;
1437                rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1438                memcpy(ret_buf, &val, 4);
1439        }
1440
1441        /* disable access to nvram interface */
1442        bnx2x_disable_nvram_access(bp);
1443        bnx2x_release_nvram_lock(bp);
1444
1445        return rc;
1446}
1447
1448static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1449                              int buf_size)
1450{
1451        int rc;
1452
1453        rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1454
1455        if (!rc) {
1456                __be32 *be = (__be32 *)buf;
1457
1458                while ((buf_size -= 4) >= 0)
1459                        *buf++ = be32_to_cpu(*be++);
1460        }
1461
1462        return rc;
1463}
1464
1465static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1466{
1467        int rc = 1;
1468        u16 pm = 0;
1469        struct net_device *dev = pci_get_drvdata(bp->pdev);
1470
1471        if (bp->pdev->pm_cap)
1472                rc = pci_read_config_word(bp->pdev,
1473                                          bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1474
1475        if ((rc && !netif_running(dev)) ||
1476            (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1477                return false;
1478
1479        return true;
1480}
1481
1482static int bnx2x_get_eeprom(struct net_device *dev,
1483                            struct ethtool_eeprom *eeprom, u8 *eebuf)
1484{
1485        struct bnx2x *bp = netdev_priv(dev);
1486
1487        if (!bnx2x_is_nvm_accessible(bp)) {
1488                DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1489                   "cannot access eeprom when the interface is down\n");
1490                return -EAGAIN;
1491        }
1492
1493        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1494           "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1495           eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1496           eeprom->len, eeprom->len);
1497
1498        /* parameters already validated in ethtool_get_eeprom */
1499
1500        return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1501}
1502
1503static int bnx2x_get_module_eeprom(struct net_device *dev,
1504                                   struct ethtool_eeprom *ee,
1505                                   u8 *data)
1506{
1507        struct bnx2x *bp = netdev_priv(dev);
1508        int rc = -EINVAL, phy_idx;
1509        u8 *user_data = data;
1510        unsigned int start_addr = ee->offset, xfer_size = 0;
1511
1512        if (!bnx2x_is_nvm_accessible(bp)) {
1513                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1514                   "cannot access eeprom when the interface is down\n");
1515                return -EAGAIN;
1516        }
1517
1518        phy_idx = bnx2x_get_cur_phy_idx(bp);
1519
1520        /* Read A0 section */
1521        if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1522                /* Limit transfer size to the A0 section boundary */
1523                if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1524                        xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1525                else
1526                        xfer_size = ee->len;
1527                bnx2x_acquire_phy_lock(bp);
1528                rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1529                                                  &bp->link_params,
1530                                                  I2C_DEV_ADDR_A0,
1531                                                  start_addr,
1532                                                  xfer_size,
1533                                                  user_data);
1534                bnx2x_release_phy_lock(bp);
1535                if (rc) {
1536                        DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1537
1538                        return -EINVAL;
1539                }
1540                user_data += xfer_size;
1541                start_addr += xfer_size;
1542        }
1543
1544        /* Read A2 section */
1545        if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1546            (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1547                xfer_size = ee->len - xfer_size;
1548                /* Limit transfer size to the A2 section boundary */
1549                if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1550                        xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1551                start_addr -= ETH_MODULE_SFF_8079_LEN;
1552                bnx2x_acquire_phy_lock(bp);
1553                rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1554                                                  &bp->link_params,
1555                                                  I2C_DEV_ADDR_A2,
1556                                                  start_addr,
1557                                                  xfer_size,
1558                                                  user_data);
1559                bnx2x_release_phy_lock(bp);
1560                if (rc) {
1561                        DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1562                        return -EINVAL;
1563                }
1564        }
1565        return rc;
1566}
1567
1568static int bnx2x_get_module_info(struct net_device *dev,
1569                                 struct ethtool_modinfo *modinfo)
1570{
1571        struct bnx2x *bp = netdev_priv(dev);
1572        int phy_idx, rc;
1573        u8 sff8472_comp, diag_type;
1574
1575        if (!bnx2x_is_nvm_accessible(bp)) {
1576                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1577                   "cannot access eeprom when the interface is down\n");
1578                return -EAGAIN;
1579        }
1580        phy_idx = bnx2x_get_cur_phy_idx(bp);
1581        bnx2x_acquire_phy_lock(bp);
1582        rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1583                                          &bp->link_params,
1584                                          I2C_DEV_ADDR_A0,
1585                                          SFP_EEPROM_SFF_8472_COMP_ADDR,
1586                                          SFP_EEPROM_SFF_8472_COMP_SIZE,
1587                                          &sff8472_comp);
1588        bnx2x_release_phy_lock(bp);
1589        if (rc) {
1590                DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1591                return -EINVAL;
1592        }
1593
1594        bnx2x_acquire_phy_lock(bp);
1595        rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1596                                          &bp->link_params,
1597                                          I2C_DEV_ADDR_A0,
1598                                          SFP_EEPROM_DIAG_TYPE_ADDR,
1599                                          SFP_EEPROM_DIAG_TYPE_SIZE,
1600                                          &diag_type);
1601        bnx2x_release_phy_lock(bp);
1602        if (rc) {
1603                DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1604                return -EINVAL;
1605        }
1606
1607        if (!sff8472_comp ||
1608            (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ) ||
1609            !(diag_type & SFP_EEPROM_DDM_IMPLEMENTED)) {
1610                modinfo->type = ETH_MODULE_SFF_8079;
1611                modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1612        } else {
1613                modinfo->type = ETH_MODULE_SFF_8472;
1614                modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1615        }
1616        return 0;
1617}
1618
1619static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1620                                   u32 cmd_flags)
1621{
1622        int count, i, rc;
1623
1624        /* build the command word */
1625        cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1626
1627        /* need to clear DONE bit separately */
1628        REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1629
1630        /* write the data */
1631        REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1632
1633        /* address of the NVRAM to write to */
1634        REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1635               (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1636
1637        /* issue the write command */
1638        REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1639
1640        /* adjust timeout for emulation/FPGA */
1641        count = BNX2X_NVRAM_TIMEOUT_COUNT;
1642        if (CHIP_REV_IS_SLOW(bp))
1643                count *= 100;
1644
1645        /* wait for completion */
1646        rc = -EBUSY;
1647        for (i = 0; i < count; i++) {
1648                udelay(5);
1649                val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1650                if (val & MCPR_NVM_COMMAND_DONE) {
1651                        rc = 0;
1652                        break;
1653                }
1654        }
1655
1656        if (rc == -EBUSY)
1657                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1658                   "nvram write timeout expired\n");
1659        return rc;
1660}
1661
1662#define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1663
1664static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1665                              int buf_size)
1666{
1667        int rc;
1668        u32 cmd_flags, align_offset, val;
1669        __be32 val_be;
1670
1671        if (offset + buf_size > bp->common.flash_size) {
1672                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1673                   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1674                   offset, buf_size, bp->common.flash_size);
1675                return -EINVAL;
1676        }
1677
1678        /* request access to nvram interface */
1679        rc = bnx2x_acquire_nvram_lock(bp);
1680        if (rc)
1681                return rc;
1682
1683        /* enable access to nvram interface */
1684        bnx2x_enable_nvram_access(bp);
1685
1686        cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1687        align_offset = (offset & ~0x03);
1688        rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1689
1690        if (rc == 0) {
1691                /* nvram data is returned as an array of bytes
1692                 * convert it back to cpu order
1693                 */
1694                val = be32_to_cpu(val_be);
1695
1696                val &= ~le32_to_cpu((__force __le32)
1697                                    (0xff << BYTE_OFFSET(offset)));
1698                val |= le32_to_cpu((__force __le32)
1699                                   (*data_buf << BYTE_OFFSET(offset)));
1700
1701                rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1702                                             cmd_flags);
1703        }
1704
1705        /* disable access to nvram interface */
1706        bnx2x_disable_nvram_access(bp);
1707        bnx2x_release_nvram_lock(bp);
1708
1709        return rc;
1710}
1711
1712static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1713                             int buf_size)
1714{
1715        int rc;
1716        u32 cmd_flags;
1717        u32 val;
1718        u32 written_so_far;
1719
1720        if (buf_size == 1)      /* ethtool */
1721                return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1722
1723        if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1724                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1725                   "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1726                   offset, buf_size);
1727                return -EINVAL;
1728        }
1729
1730        if (offset + buf_size > bp->common.flash_size) {
1731                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1732                   "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1733                   offset, buf_size, bp->common.flash_size);
1734                return -EINVAL;
1735        }
1736
1737        /* request access to nvram interface */
1738        rc = bnx2x_acquire_nvram_lock(bp);
1739        if (rc)
1740                return rc;
1741
1742        /* enable access to nvram interface */
1743        bnx2x_enable_nvram_access(bp);
1744
1745        written_so_far = 0;
1746        cmd_flags = MCPR_NVM_COMMAND_FIRST;
1747        while ((written_so_far < buf_size) && (rc == 0)) {
1748                if (written_so_far == (buf_size - sizeof(u32)))
1749                        cmd_flags |= MCPR_NVM_COMMAND_LAST;
1750                else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1751                        cmd_flags |= MCPR_NVM_COMMAND_LAST;
1752                else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1753                        cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1754
1755                memcpy(&val, data_buf, 4);
1756
1757                /* Notice unlike bnx2x_nvram_read_dword() this will not
1758                 * change val using be32_to_cpu(), which causes data to flip
1759                 * if the eeprom is read and then written back. This is due
1760                 * to tools utilizing this functionality that would break
1761                 * if this would be resolved.
1762                 */
1763                rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1764
1765                /* advance to the next dword */
1766                offset += sizeof(u32);
1767                data_buf += sizeof(u32);
1768                written_so_far += sizeof(u32);
1769
1770                /* At end of each 4Kb page, release nvram lock to allow MFW
1771                 * chance to take it for its own use.
1772                 */
1773                if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1774                    (written_so_far < buf_size)) {
1775                        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1776                           "Releasing NVM lock after offset 0x%x\n",
1777                           (u32)(offset - sizeof(u32)));
1778                        bnx2x_release_nvram_lock(bp);
1779                        usleep_range(1000, 2000);
1780                        rc = bnx2x_acquire_nvram_lock(bp);
1781                        if (rc)
1782                                return rc;
1783                }
1784
1785                cmd_flags = 0;
1786        }
1787
1788        /* disable access to nvram interface */
1789        bnx2x_disable_nvram_access(bp);
1790        bnx2x_release_nvram_lock(bp);
1791
1792        return rc;
1793}
1794
1795static int bnx2x_set_eeprom(struct net_device *dev,
1796                            struct ethtool_eeprom *eeprom, u8 *eebuf)
1797{
1798        struct bnx2x *bp = netdev_priv(dev);
1799        int port = BP_PORT(bp);
1800        int rc = 0;
1801        u32 ext_phy_config;
1802
1803        if (!bnx2x_is_nvm_accessible(bp)) {
1804                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1805                   "cannot access eeprom when the interface is down\n");
1806                return -EAGAIN;
1807        }
1808
1809        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1810           "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1811           eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1812           eeprom->len, eeprom->len);
1813
1814        /* parameters already validated in ethtool_set_eeprom */
1815
1816        /* PHY eeprom can be accessed only by the PMF */
1817        if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1818            !bp->port.pmf) {
1819                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1820                   "wrong magic or interface is not pmf\n");
1821                return -EINVAL;
1822        }
1823
1824        ext_phy_config =
1825                SHMEM_RD(bp,
1826                         dev_info.port_hw_config[port].external_phy_config);
1827
1828        if (eeprom->magic == 0x50485950) {
1829                /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1830                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1831
1832                bnx2x_acquire_phy_lock(bp);
1833                rc |= bnx2x_link_reset(&bp->link_params,
1834                                       &bp->link_vars, 0);
1835                if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1836                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1837                        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1838                                       MISC_REGISTERS_GPIO_HIGH, port);
1839                bnx2x_release_phy_lock(bp);
1840                bnx2x_link_report(bp);
1841
1842        } else if (eeprom->magic == 0x50485952) {
1843                /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1844                if (bp->state == BNX2X_STATE_OPEN) {
1845                        bnx2x_acquire_phy_lock(bp);
1846                        rc |= bnx2x_link_reset(&bp->link_params,
1847                                               &bp->link_vars, 1);
1848
1849                        rc |= bnx2x_phy_init(&bp->link_params,
1850                                             &bp->link_vars);
1851                        bnx2x_release_phy_lock(bp);
1852                        bnx2x_calc_fc_adv(bp);
1853                }
1854        } else if (eeprom->magic == 0x53985943) {
1855                /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1856                if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1857                                       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1858
1859                        /* DSP Remove Download Mode */
1860                        bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1861                                       MISC_REGISTERS_GPIO_LOW, port);
1862
1863                        bnx2x_acquire_phy_lock(bp);
1864
1865                        bnx2x_sfx7101_sp_sw_reset(bp,
1866                                                &bp->link_params.phy[EXT_PHY1]);
1867
1868                        /* wait 0.5 sec to allow it to run */
1869                        msleep(500);
1870                        bnx2x_ext_phy_hw_reset(bp, port);
1871                        msleep(500);
1872                        bnx2x_release_phy_lock(bp);
1873                }
1874        } else
1875                rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1876
1877        return rc;
1878}
1879
1880static int bnx2x_get_coalesce(struct net_device *dev,
1881                              struct ethtool_coalesce *coal)
1882{
1883        struct bnx2x *bp = netdev_priv(dev);
1884
1885        memset(coal, 0, sizeof(struct ethtool_coalesce));
1886
1887        coal->rx_coalesce_usecs = bp->rx_ticks;
1888        coal->tx_coalesce_usecs = bp->tx_ticks;
1889
1890        return 0;
1891}
1892
1893static int bnx2x_set_coalesce(struct net_device *dev,
1894                              struct ethtool_coalesce *coal)
1895{
1896        struct bnx2x *bp = netdev_priv(dev);
1897
1898        bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1899        if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1900                bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1901
1902        bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1903        if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1904                bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1905
1906        if (netif_running(dev))
1907                bnx2x_update_coalesce(bp);
1908
1909        return 0;
1910}
1911
1912static void bnx2x_get_ringparam(struct net_device *dev,
1913                                struct ethtool_ringparam *ering)
1914{
1915        struct bnx2x *bp = netdev_priv(dev);
1916
1917        ering->rx_max_pending = MAX_RX_AVAIL;
1918
1919        /* If size isn't already set, we give an estimation of the number
1920         * of buffers we'll have. We're neglecting some possible conditions
1921         * [we couldn't know for certain at this point if number of queues
1922         * might shrink] but the number would be correct for the likely
1923         * scenario.
1924         */
1925        if (bp->rx_ring_size)
1926                ering->rx_pending = bp->rx_ring_size;
1927        else if (BNX2X_NUM_RX_QUEUES(bp))
1928                ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp);
1929        else
1930                ering->rx_pending = MAX_RX_AVAIL;
1931
1932        ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1933        ering->tx_pending = bp->tx_ring_size;
1934}
1935
1936static int bnx2x_set_ringparam(struct net_device *dev,
1937                               struct ethtool_ringparam *ering)
1938{
1939        struct bnx2x *bp = netdev_priv(dev);
1940
1941        DP(BNX2X_MSG_ETHTOOL,
1942           "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1943           ering->rx_pending, ering->tx_pending);
1944
1945        if (pci_num_vf(bp->pdev)) {
1946                DP(BNX2X_MSG_IOV,
1947                   "VFs are enabled, can not change ring parameters\n");
1948                return -EPERM;
1949        }
1950
1951        if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1952                DP(BNX2X_MSG_ETHTOOL,
1953                   "Handling parity error recovery. Try again later\n");
1954                return -EAGAIN;
1955        }
1956
1957        if ((ering->rx_pending > MAX_RX_AVAIL) ||
1958            (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1959                                                    MIN_RX_SIZE_TPA)) ||
1960            (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1961            (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1962                DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1963                return -EINVAL;
1964        }
1965
1966        bp->rx_ring_size = ering->rx_pending;
1967        bp->tx_ring_size = ering->tx_pending;
1968
1969        return bnx2x_reload_if_running(dev);
1970}
1971
1972static void bnx2x_get_pauseparam(struct net_device *dev,
1973                                 struct ethtool_pauseparam *epause)
1974{
1975        struct bnx2x *bp = netdev_priv(dev);
1976        int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1977        int cfg_reg;
1978
1979        epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1980                           BNX2X_FLOW_CTRL_AUTO);
1981
1982        if (!epause->autoneg)
1983                cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1984        else
1985                cfg_reg = bp->link_params.req_fc_auto_adv;
1986
1987        epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1988                            BNX2X_FLOW_CTRL_RX);
1989        epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1990                            BNX2X_FLOW_CTRL_TX);
1991
1992        DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1993           "  autoneg %d  rx_pause %d  tx_pause %d\n",
1994           epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1995}
1996
1997static int bnx2x_set_pauseparam(struct net_device *dev,
1998                                struct ethtool_pauseparam *epause)
1999{
2000        struct bnx2x *bp = netdev_priv(dev);
2001        u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2002        if (IS_MF(bp))
2003                return 0;
2004
2005        DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
2006           "  autoneg %d  rx_pause %d  tx_pause %d\n",
2007           epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
2008
2009        bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
2010
2011        if (epause->rx_pause)
2012                bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
2013
2014        if (epause->tx_pause)
2015                bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
2016
2017        if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
2018                bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
2019
2020        if (epause->autoneg) {
2021                if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
2022                        DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
2023                        return -EINVAL;
2024                }
2025
2026                if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
2027                        bp->link_params.req_flow_ctrl[cfg_idx] =
2028                                BNX2X_FLOW_CTRL_AUTO;
2029                }
2030                bp->link_params.req_fc_auto_adv = 0;
2031                if (epause->rx_pause)
2032                        bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
2033
2034                if (epause->tx_pause)
2035                        bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
2036
2037                if (!bp->link_params.req_fc_auto_adv)
2038                        bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
2039        }
2040
2041        DP(BNX2X_MSG_ETHTOOL,
2042           "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
2043
2044        if (netif_running(dev)) {
2045                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2046                bnx2x_force_link_reset(bp);
2047                bnx2x_link_set(bp);
2048        }
2049
2050        return 0;
2051}
2052
2053static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
2054        "register_test (offline)    ",
2055        "memory_test (offline)      ",
2056        "int_loopback_test (offline)",
2057        "ext_loopback_test (offline)",
2058        "nvram_test (online)        ",
2059        "interrupt_test (online)    ",
2060        "link_test (online)         "
2061};
2062
2063enum {
2064        BNX2X_PRI_FLAG_ISCSI,
2065        BNX2X_PRI_FLAG_FCOE,
2066        BNX2X_PRI_FLAG_STORAGE,
2067        BNX2X_PRI_FLAG_LEN,
2068};
2069
2070static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2071        "iSCSI offload support",
2072        "FCoE offload support",
2073        "Storage only interface"
2074};
2075
2076static u32 bnx2x_eee_to_adv(u32 eee_adv)
2077{
2078        u32 modes = 0;
2079
2080        if (eee_adv & SHMEM_EEE_100M_ADV)
2081                modes |= ADVERTISED_100baseT_Full;
2082        if (eee_adv & SHMEM_EEE_1G_ADV)
2083                modes |= ADVERTISED_1000baseT_Full;
2084        if (eee_adv & SHMEM_EEE_10G_ADV)
2085                modes |= ADVERTISED_10000baseT_Full;
2086
2087        return modes;
2088}
2089
2090static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2091{
2092        u32 eee_adv = 0;
2093        if (modes & ADVERTISED_100baseT_Full)
2094                eee_adv |= SHMEM_EEE_100M_ADV;
2095        if (modes & ADVERTISED_1000baseT_Full)
2096                eee_adv |= SHMEM_EEE_1G_ADV;
2097        if (modes & ADVERTISED_10000baseT_Full)
2098                eee_adv |= SHMEM_EEE_10G_ADV;
2099
2100        return eee_adv << shift;
2101}
2102
2103static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2104{
2105        struct bnx2x *bp = netdev_priv(dev);
2106        u32 eee_cfg;
2107
2108        if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2109                DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2110                return -EOPNOTSUPP;
2111        }
2112
2113        eee_cfg = bp->link_vars.eee_status;
2114
2115        edata->supported =
2116                bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2117                                 SHMEM_EEE_SUPPORTED_SHIFT);
2118
2119        edata->advertised =
2120                bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2121                                 SHMEM_EEE_ADV_STATUS_SHIFT);
2122        edata->lp_advertised =
2123                bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2124                                 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2125
2126        /* SHMEM value is in 16u units --> Convert to 1u units. */
2127        edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2128
2129        edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
2130        edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
2131        edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2132
2133        return 0;
2134}
2135
2136static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2137{
2138        struct bnx2x *bp = netdev_priv(dev);
2139        u32 eee_cfg;
2140        u32 advertised;
2141
2142        if (IS_MF(bp))
2143                return 0;
2144
2145        if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2146                DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2147                return -EOPNOTSUPP;
2148        }
2149
2150        eee_cfg = bp->link_vars.eee_status;
2151
2152        if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2153                DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2154                return -EOPNOTSUPP;
2155        }
2156
2157        advertised = bnx2x_adv_to_eee(edata->advertised,
2158                                      SHMEM_EEE_ADV_STATUS_SHIFT);
2159        if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2160                DP(BNX2X_MSG_ETHTOOL,
2161                   "Direct manipulation of EEE advertisement is not supported\n");
2162                return -EINVAL;
2163        }
2164
2165        if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2166                DP(BNX2X_MSG_ETHTOOL,
2167                   "Maximal Tx Lpi timer supported is %x(u)\n",
2168                   EEE_MODE_TIMER_MASK);
2169                return -EINVAL;
2170        }
2171        if (edata->tx_lpi_enabled &&
2172            (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2173                DP(BNX2X_MSG_ETHTOOL,
2174                   "Minimal Tx Lpi timer supported is %d(u)\n",
2175                   EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2176                return -EINVAL;
2177        }
2178
2179        /* All is well; Apply changes*/
2180        if (edata->eee_enabled)
2181                bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2182        else
2183                bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2184
2185        if (edata->tx_lpi_enabled)
2186                bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2187        else
2188                bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2189
2190        bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2191        bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2192                                    EEE_MODE_TIMER_MASK) |
2193                                    EEE_MODE_OVERRIDE_NVRAM |
2194                                    EEE_MODE_OUTPUT_TIME;
2195
2196        /* Restart link to propagate changes */
2197        if (netif_running(dev)) {
2198                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2199                bnx2x_force_link_reset(bp);
2200                bnx2x_link_set(bp);
2201        }
2202
2203        return 0;
2204}
2205
2206enum {
2207        BNX2X_CHIP_E1_OFST = 0,
2208        BNX2X_CHIP_E1H_OFST,
2209        BNX2X_CHIP_E2_OFST,
2210        BNX2X_CHIP_E3_OFST,
2211        BNX2X_CHIP_E3B0_OFST,
2212        BNX2X_CHIP_MAX_OFST
2213};
2214
2215#define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
2216#define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
2217#define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
2218#define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
2219#define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
2220
2221#define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2222#define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2223
2224static int bnx2x_test_registers(struct bnx2x *bp)
2225{
2226        int idx, i, rc = -ENODEV;
2227        u32 wr_val = 0, hw;
2228        int port = BP_PORT(bp);
2229        static const struct {
2230                u32 hw;
2231                u32 offset0;
2232                u32 offset1;
2233                u32 mask;
2234        } reg_tbl[] = {
2235/* 0 */         { BNX2X_CHIP_MASK_ALL,
2236                        BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2237                { BNX2X_CHIP_MASK_ALL,
2238                        DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2239                { BNX2X_CHIP_MASK_E1X,
2240                        HC_REG_AGG_INT_0,               4, 0x000003ff },
2241                { BNX2X_CHIP_MASK_ALL,
2242                        PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2243                { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2244                        PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2245                { BNX2X_CHIP_MASK_E3B0,
2246                        PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2247                { BNX2X_CHIP_MASK_ALL,
2248                        PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2249                { BNX2X_CHIP_MASK_ALL,
2250                        PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2251                { BNX2X_CHIP_MASK_ALL,
2252                        PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2253                { BNX2X_CHIP_MASK_ALL,
2254                        PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2255/* 10 */        { BNX2X_CHIP_MASK_ALL,
2256                        PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2257                { BNX2X_CHIP_MASK_ALL,
2258                        PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2259                { BNX2X_CHIP_MASK_ALL,
2260                        QM_REG_CONNNUM_0,               4, 0x000fffff },
2261                { BNX2X_CHIP_MASK_ALL,
2262                        TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2263                { BNX2X_CHIP_MASK_ALL,
2264                        SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2265                { BNX2X_CHIP_MASK_ALL,
2266                        SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2267                { BNX2X_CHIP_MASK_ALL,
2268                        XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2269                { BNX2X_CHIP_MASK_ALL,
2270                        XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2271                { BNX2X_CHIP_MASK_ALL,
2272                        XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2273                { BNX2X_CHIP_MASK_ALL,
2274                        NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2275/* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2276                        NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2277                { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2278                        NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2279                { BNX2X_CHIP_MASK_ALL,
2280                        NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2281                { BNX2X_CHIP_MASK_ALL,
2282                        NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2283                { BNX2X_CHIP_MASK_ALL,
2284                        NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2285                { BNX2X_CHIP_MASK_ALL,
2286                        NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2287                { BNX2X_CHIP_MASK_ALL,
2288                        NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2289                { BNX2X_CHIP_MASK_ALL,
2290                        NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2291                { BNX2X_CHIP_MASK_ALL,
2292                        NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2293                { BNX2X_CHIP_MASK_ALL,
2294                        NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2295/* 30 */        { BNX2X_CHIP_MASK_ALL,
2296                        NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2297                { BNX2X_CHIP_MASK_ALL,
2298                        NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2299                { BNX2X_CHIP_MASK_ALL,
2300                        NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2301                { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2302                        NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2303                { BNX2X_CHIP_MASK_ALL,
2304                        NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2305                { BNX2X_CHIP_MASK_ALL,
2306                        NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2307                { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2308                        NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2309                { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2310                        NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2311
2312                { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2313        };
2314
2315        if (!bnx2x_is_nvm_accessible(bp)) {
2316                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2317                   "cannot access eeprom when the interface is down\n");
2318                return rc;
2319        }
2320
2321        if (CHIP_IS_E1(bp))
2322                hw = BNX2X_CHIP_MASK_E1;
2323        else if (CHIP_IS_E1H(bp))
2324                hw = BNX2X_CHIP_MASK_E1H;
2325        else if (CHIP_IS_E2(bp))
2326                hw = BNX2X_CHIP_MASK_E2;
2327        else if (CHIP_IS_E3B0(bp))
2328                hw = BNX2X_CHIP_MASK_E3B0;
2329        else /* e3 A0 */
2330                hw = BNX2X_CHIP_MASK_E3;
2331
2332        /* Repeat the test twice:
2333         * First by writing 0x00000000, second by writing 0xffffffff
2334         */
2335        for (idx = 0; idx < 2; idx++) {
2336
2337                switch (idx) {
2338                case 0:
2339                        wr_val = 0;
2340                        break;
2341                case 1:
2342                        wr_val = 0xffffffff;
2343                        break;
2344                }
2345
2346                for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2347                        u32 offset, mask, save_val, val;
2348                        if (!(hw & reg_tbl[i].hw))
2349                                continue;
2350
2351                        offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2352                        mask = reg_tbl[i].mask;
2353
2354                        save_val = REG_RD(bp, offset);
2355
2356                        REG_WR(bp, offset, wr_val & mask);
2357
2358                        val = REG_RD(bp, offset);
2359
2360                        /* Restore the original register's value */
2361                        REG_WR(bp, offset, save_val);
2362
2363                        /* verify value is as expected */
2364                        if ((val & mask) != (wr_val & mask)) {
2365                                DP(BNX2X_MSG_ETHTOOL,
2366                                   "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2367                                   offset, val, wr_val, mask);
2368                                goto test_reg_exit;
2369                        }
2370                }
2371        }
2372
2373        rc = 0;
2374
2375test_reg_exit:
2376        return rc;
2377}
2378
2379static int bnx2x_test_memory(struct bnx2x *bp)
2380{
2381        int i, j, rc = -ENODEV;
2382        u32 val, index;
2383        static const struct {
2384                u32 offset;
2385                int size;
2386        } mem_tbl[] = {
2387                { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2388                { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2389                { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2390                { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2391                { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2392                { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2393                { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2394
2395                { 0xffffffff, 0 }
2396        };
2397
2398        static const struct {
2399                char *name;
2400                u32 offset;
2401                u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2402        } prty_tbl[] = {
2403                { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2404                        {0x3ffc0, 0,   0, 0} },
2405                { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2406                        {0x2,     0x2, 0, 0} },
2407                { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2408                        {0,       0,   0, 0} },
2409                { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2410                        {0x3ffc0, 0,   0, 0} },
2411                { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2412                        {0x3ffc0, 0,   0, 0} },
2413                { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2414                        {0x3ffc1, 0,   0, 0} },
2415
2416                { NULL, 0xffffffff, {0, 0, 0, 0} }
2417        };
2418
2419        if (!bnx2x_is_nvm_accessible(bp)) {
2420                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2421                   "cannot access eeprom when the interface is down\n");
2422                return rc;
2423        }
2424
2425        if (CHIP_IS_E1(bp))
2426                index = BNX2X_CHIP_E1_OFST;
2427        else if (CHIP_IS_E1H(bp))
2428                index = BNX2X_CHIP_E1H_OFST;
2429        else if (CHIP_IS_E2(bp))
2430                index = BNX2X_CHIP_E2_OFST;
2431        else /* e3 */
2432                index = BNX2X_CHIP_E3_OFST;
2433
2434        /* pre-Check the parity status */
2435        for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2436                val = REG_RD(bp, prty_tbl[i].offset);
2437                if (val & ~(prty_tbl[i].hw_mask[index])) {
2438                        DP(BNX2X_MSG_ETHTOOL,
2439                           "%s is 0x%x\n", prty_tbl[i].name, val);
2440                        goto test_mem_exit;
2441                }
2442        }
2443
2444        /* Go through all the memories */
2445        for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2446                for (j = 0; j < mem_tbl[i].size; j++)
2447                        REG_RD(bp, mem_tbl[i].offset + j*4);
2448
2449        /* Check the parity status */
2450        for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2451                val = REG_RD(bp, prty_tbl[i].offset);
2452                if (val & ~(prty_tbl[i].hw_mask[index])) {
2453                        DP(BNX2X_MSG_ETHTOOL,
2454                           "%s is 0x%x\n", prty_tbl[i].name, val);
2455                        goto test_mem_exit;
2456                }
2457        }
2458
2459        rc = 0;
2460
2461test_mem_exit:
2462        return rc;
2463}
2464
2465static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2466{
2467        int cnt = 1400;
2468
2469        if (link_up) {
2470                while (bnx2x_link_test(bp, is_serdes) && cnt--)
2471                        msleep(20);
2472
2473                if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2474                        DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2475
2476                cnt = 1400;
2477                while (!bp->link_vars.link_up && cnt--)
2478                        msleep(20);
2479
2480                if (cnt <= 0 && !bp->link_vars.link_up)
2481                        DP(BNX2X_MSG_ETHTOOL,
2482                           "Timeout waiting for link init\n");
2483        }
2484}
2485
2486static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2487{
2488        unsigned int pkt_size, num_pkts, i;
2489        struct sk_buff *skb;
2490        unsigned char *packet;
2491        struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2492        struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2493        struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2494        u16 tx_start_idx, tx_idx;
2495        u16 rx_start_idx, rx_idx;
2496        u16 pkt_prod, bd_prod;
2497        struct sw_tx_bd *tx_buf;
2498        struct eth_tx_start_bd *tx_start_bd;
2499        dma_addr_t mapping;
2500        union eth_rx_cqe *cqe;
2501        u8 cqe_fp_flags, cqe_fp_type;
2502        struct sw_rx_bd *rx_buf;
2503        u16 len;
2504        int rc = -ENODEV;
2505        u8 *data;
2506        struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2507                                                       txdata->txq_index);
2508
2509        /* check the loopback mode */
2510        switch (loopback_mode) {
2511        case BNX2X_PHY_LOOPBACK:
2512                if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2513                        DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2514                        return -EINVAL;
2515                }
2516                break;
2517        case BNX2X_MAC_LOOPBACK:
2518                if (CHIP_IS_E3(bp)) {
2519                        int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2520                        if (bp->port.supported[cfg_idx] &
2521                            (SUPPORTED_10000baseT_Full |
2522                             SUPPORTED_20000baseMLD2_Full |
2523                             SUPPORTED_20000baseKR2_Full))
2524                                bp->link_params.loopback_mode = LOOPBACK_XMAC;
2525                        else
2526                                bp->link_params.loopback_mode = LOOPBACK_UMAC;
2527                } else
2528                        bp->link_params.loopback_mode = LOOPBACK_BMAC;
2529
2530                bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2531                break;
2532        case BNX2X_EXT_LOOPBACK:
2533                if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2534                        DP(BNX2X_MSG_ETHTOOL,
2535                           "Can't configure external loopback\n");
2536                        return -EINVAL;
2537                }
2538                break;
2539        default:
2540                DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2541                return -EINVAL;
2542        }
2543
2544        /* prepare the loopback packet */
2545        pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2546                     bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2547        skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2548        if (!skb) {
2549                DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2550                rc = -ENOMEM;
2551                goto test_loopback_exit;
2552        }
2553        packet = skb_put(skb, pkt_size);
2554        memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2555        eth_zero_addr(packet + ETH_ALEN);
2556        memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2557        for (i = ETH_HLEN; i < pkt_size; i++)
2558                packet[i] = (unsigned char) (i & 0xff);
2559        mapping = dma_map_single(&bp->pdev->dev, skb->data,
2560                                 skb_headlen(skb), DMA_TO_DEVICE);
2561        if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2562                rc = -ENOMEM;
2563                dev_kfree_skb(skb);
2564                DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2565                goto test_loopback_exit;
2566        }
2567
2568        /* send the loopback packet */
2569        num_pkts = 0;
2570        tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2571        rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2572
2573        netdev_tx_sent_queue(txq, skb->len);
2574
2575        pkt_prod = txdata->tx_pkt_prod++;
2576        tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2577        tx_buf->first_bd = txdata->tx_bd_prod;
2578        tx_buf->skb = skb;
2579        tx_buf->flags = 0;
2580
2581        bd_prod = TX_BD(txdata->tx_bd_prod);
2582        tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2583        tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2584        tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2585        tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2586        tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2587        tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2588        tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2589        SET_FLAG(tx_start_bd->general_data,
2590                 ETH_TX_START_BD_HDR_NBDS,
2591                 1);
2592        SET_FLAG(tx_start_bd->general_data,
2593                 ETH_TX_START_BD_PARSE_NBDS,
2594                 0);
2595
2596        /* turn on parsing and get a BD */
2597        bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2598
2599        if (CHIP_IS_E1x(bp)) {
2600                u16 global_data = 0;
2601                struct eth_tx_parse_bd_e1x  *pbd_e1x =
2602                        &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2603                memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2604                SET_FLAG(global_data,
2605                         ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2606                pbd_e1x->global_data = cpu_to_le16(global_data);
2607        } else {
2608                u32 parsing_data = 0;
2609                struct eth_tx_parse_bd_e2  *pbd_e2 =
2610                        &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2611                memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2612                SET_FLAG(parsing_data,
2613                         ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2614                pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2615        }
2616        wmb();
2617
2618        txdata->tx_db.data.prod += 2;
2619        /* make sure descriptor update is observed by the HW */
2620        wmb();
2621        DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw);
2622
2623        barrier();
2624
2625        num_pkts++;
2626        txdata->tx_bd_prod += 2; /* start + pbd */
2627
2628        udelay(100);
2629
2630        tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2631        if (tx_idx != tx_start_idx + num_pkts)
2632                goto test_loopback_exit;
2633
2634        /* Unlike HC IGU won't generate an interrupt for status block
2635         * updates that have been performed while interrupts were
2636         * disabled.
2637         */
2638        if (bp->common.int_block == INT_BLOCK_IGU) {
2639                /* Disable local BHes to prevent a dead-lock situation between
2640                 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2641                 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2642                 */
2643                local_bh_disable();
2644                bnx2x_tx_int(bp, txdata);
2645                local_bh_enable();
2646        }
2647
2648        rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2649        if (rx_idx != rx_start_idx + num_pkts)
2650                goto test_loopback_exit;
2651
2652        cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2653        cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2654        cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2655        if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2656                goto test_loopback_rx_exit;
2657
2658        len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2659        if (len != pkt_size)
2660                goto test_loopback_rx_exit;
2661
2662        rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2663        dma_sync_single_for_cpu(&bp->pdev->dev,
2664                                   dma_unmap_addr(rx_buf, mapping),
2665                                   fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2666        data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2667        for (i = ETH_HLEN; i < pkt_size; i++)
2668                if (*(data + i) != (unsigned char) (i & 0xff))
2669                        goto test_loopback_rx_exit;
2670
2671        rc = 0;
2672
2673test_loopback_rx_exit:
2674
2675        fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2676        fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2677        fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2678        fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2679
2680        /* Update producers */
2681        bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2682                             fp_rx->rx_sge_prod);
2683
2684test_loopback_exit:
2685        bp->link_params.loopback_mode = LOOPBACK_NONE;
2686
2687        return rc;
2688}
2689
2690static int bnx2x_test_loopback(struct bnx2x *bp)
2691{
2692        int rc = 0, res;
2693
2694        if (BP_NOMCP(bp))
2695                return rc;
2696
2697        if (!netif_running(bp->dev))
2698                return BNX2X_LOOPBACK_FAILED;
2699
2700        bnx2x_netif_stop(bp, 1);
2701        bnx2x_acquire_phy_lock(bp);
2702
2703        res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2704        if (res) {
2705                DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2706                rc |= BNX2X_PHY_LOOPBACK_FAILED;
2707        }
2708
2709        res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2710        if (res) {
2711                DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2712                rc |= BNX2X_MAC_LOOPBACK_FAILED;
2713        }
2714
2715        bnx2x_release_phy_lock(bp);
2716        bnx2x_netif_start(bp);
2717
2718        return rc;
2719}
2720
2721static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2722{
2723        int rc;
2724        u8 is_serdes =
2725                (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2726
2727        if (BP_NOMCP(bp))
2728                return -ENODEV;
2729
2730        if (!netif_running(bp->dev))
2731                return BNX2X_EXT_LOOPBACK_FAILED;
2732
2733        bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2734        rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2735        if (rc) {
2736                DP(BNX2X_MSG_ETHTOOL,
2737                   "Can't perform self-test, nic_load (for external lb) failed\n");
2738                return -ENODEV;
2739        }
2740        bnx2x_wait_for_link(bp, 1, is_serdes);
2741
2742        bnx2x_netif_stop(bp, 1);
2743
2744        rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2745        if (rc)
2746                DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2747
2748        bnx2x_netif_start(bp);
2749
2750        return rc;
2751}
2752
2753struct code_entry {
2754        u32 sram_start_addr;
2755        u32 code_attribute;
2756#define CODE_IMAGE_TYPE_MASK                    0xf0800003
2757#define CODE_IMAGE_VNTAG_PROFILES_DATA          0xd0000003
2758#define CODE_IMAGE_LENGTH_MASK                  0x007ffffc
2759#define CODE_IMAGE_TYPE_EXTENDED_DIR            0xe0000000
2760        u32 nvm_start_addr;
2761};
2762
2763#define CODE_ENTRY_MAX                  16
2764#define CODE_ENTRY_EXTENDED_DIR_IDX     15
2765#define MAX_IMAGES_IN_EXTENDED_DIR      64
2766#define NVRAM_DIR_OFFSET                0x14
2767
2768#define EXTENDED_DIR_EXISTS(code)                                         \
2769        ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2770         (code & CODE_IMAGE_LENGTH_MASK) != 0)
2771
2772#define CRC32_RESIDUAL                  0xdebb20e3
2773#define CRC_BUFF_SIZE                   256
2774
2775static int bnx2x_nvram_crc(struct bnx2x *bp,
2776                           int offset,
2777                           int size,
2778                           u8 *buff)
2779{
2780        u32 crc = ~0;
2781        int rc = 0, done = 0;
2782
2783        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2784           "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2785
2786        while (done < size) {
2787                int count = min_t(int, size - done, CRC_BUFF_SIZE);
2788
2789                rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2790
2791                if (rc)
2792                        return rc;
2793
2794                crc = crc32_le(crc, buff, count);
2795                done += count;
2796        }
2797
2798        if (crc != CRC32_RESIDUAL)
2799                rc = -EINVAL;
2800
2801        return rc;
2802}
2803
2804static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2805                                struct code_entry *entry,
2806                                u8 *buff)
2807{
2808        size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2809        u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2810        int rc;
2811
2812        /* Zero-length images and AFEX profiles do not have CRC */
2813        if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2814                return 0;
2815
2816        rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2817        if (rc)
2818                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2819                   "image %x has failed crc test (rc %d)\n", type, rc);
2820
2821        return rc;
2822}
2823
2824static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2825{
2826        int rc;
2827        struct code_entry entry;
2828
2829        rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2830        if (rc)
2831                return rc;
2832
2833        return bnx2x_test_nvram_dir(bp, &entry, buff);
2834}
2835
2836static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2837{
2838        u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2839        struct code_entry entry;
2840        int i;
2841
2842        rc = bnx2x_nvram_read32(bp,
2843                                dir_offset +
2844                                sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2845                                (u32 *)&entry, sizeof(entry));
2846        if (rc)
2847                return rc;
2848
2849        if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2850                return 0;
2851
2852        rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2853                                &cnt, sizeof(u32));
2854        if (rc)
2855                return rc;
2856
2857        dir_offset = entry.nvm_start_addr + 8;
2858
2859        for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2860                rc = bnx2x_test_dir_entry(bp, dir_offset +
2861                                              sizeof(struct code_entry) * i,
2862                                          buff);
2863                if (rc)
2864                        return rc;
2865        }
2866
2867        return 0;
2868}
2869
2870static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2871{
2872        u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2873        int i;
2874
2875        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2876
2877        for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2878                rc = bnx2x_test_dir_entry(bp, dir_offset +
2879                                              sizeof(struct code_entry) * i,
2880                                          buff);
2881                if (rc)
2882                        return rc;
2883        }
2884
2885        return bnx2x_test_nvram_ext_dirs(bp, buff);
2886}
2887
2888struct crc_pair {
2889        int offset;
2890        int size;
2891};
2892
2893static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2894                                const struct crc_pair *nvram_tbl, u8 *buf)
2895{
2896        int i;
2897
2898        for (i = 0; nvram_tbl[i].size; i++) {
2899                int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2900                                         nvram_tbl[i].size, buf);
2901                if (rc) {
2902                        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2903                           "nvram_tbl[%d] has failed crc test (rc %d)\n",
2904                           i, rc);
2905                        return rc;
2906                }
2907        }
2908
2909        return 0;
2910}
2911
2912static int bnx2x_test_nvram(struct bnx2x *bp)
2913{
2914        static const struct crc_pair nvram_tbl[] = {
2915                {     0,  0x14 }, /* bootstrap */
2916                {  0x14,  0xec }, /* dir */
2917                { 0x100, 0x350 }, /* manuf_info */
2918                { 0x450,  0xf0 }, /* feature_info */
2919                { 0x640,  0x64 }, /* upgrade_key_info */
2920                { 0x708,  0x70 }, /* manuf_key_info */
2921                {     0,     0 }
2922        };
2923        static const struct crc_pair nvram_tbl2[] = {
2924                { 0x7e8, 0x350 }, /* manuf_info2 */
2925                { 0xb38,  0xf0 }, /* feature_info */
2926                {     0,     0 }
2927        };
2928
2929        u8 *buf;
2930        int rc;
2931        u32 magic;
2932
2933        if (BP_NOMCP(bp))
2934                return 0;
2935
2936        buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2937        if (!buf) {
2938                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2939                rc = -ENOMEM;
2940                goto test_nvram_exit;
2941        }
2942
2943        rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2944        if (rc) {
2945                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2946                   "magic value read (rc %d)\n", rc);
2947                goto test_nvram_exit;
2948        }
2949
2950        if (magic != 0x669955aa) {
2951                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2952                   "wrong magic value (0x%08x)\n", magic);
2953                rc = -ENODEV;
2954                goto test_nvram_exit;
2955        }
2956
2957        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2958        rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2959        if (rc)
2960                goto test_nvram_exit;
2961
2962        if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2963                u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2964                           SHARED_HW_CFG_HIDE_PORT1;
2965
2966                if (!hide) {
2967                        DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2968                           "Port 1 CRC test-set\n");
2969                        rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2970                        if (rc)
2971                                goto test_nvram_exit;
2972                }
2973        }
2974
2975        rc = bnx2x_test_nvram_dirs(bp, buf);
2976
2977test_nvram_exit:
2978        kfree(buf);
2979        return rc;
2980}
2981
2982/* Send an EMPTY ramrod on the first queue */
2983static int bnx2x_test_intr(struct bnx2x *bp)
2984{
2985        struct bnx2x_queue_state_params params = {NULL};
2986
2987        if (!netif_running(bp->dev)) {
2988                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2989                   "cannot access eeprom when the interface is down\n");
2990                return -ENODEV;
2991        }
2992
2993        params.q_obj = &bp->sp_objs->q_obj;
2994        params.cmd = BNX2X_Q_CMD_EMPTY;
2995
2996        __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2997
2998        return bnx2x_queue_state_change(bp, &params);
2999}
3000
3001static void bnx2x_self_test(struct net_device *dev,
3002                            struct ethtool_test *etest, u64 *buf)
3003{
3004        struct bnx2x *bp = netdev_priv(dev);
3005        u8 is_serdes, link_up;
3006        int rc, cnt = 0;
3007
3008        if (pci_num_vf(bp->pdev)) {
3009                DP(BNX2X_MSG_IOV,
3010                   "VFs are enabled, can not perform self test\n");
3011                return;
3012        }
3013
3014        if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
3015                netdev_err(bp->dev,
3016                           "Handling parity error recovery. Try again later\n");
3017                etest->flags |= ETH_TEST_FL_FAILED;
3018                return;
3019        }
3020
3021        DP(BNX2X_MSG_ETHTOOL,
3022           "Self-test command parameters: offline = %d, external_lb = %d\n",
3023           (etest->flags & ETH_TEST_FL_OFFLINE),
3024           (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
3025
3026        memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
3027
3028        if (bnx2x_test_nvram(bp) != 0) {
3029                if (!IS_MF(bp))
3030                        buf[4] = 1;
3031                else
3032                        buf[0] = 1;
3033                etest->flags |= ETH_TEST_FL_FAILED;
3034        }
3035
3036        if (!netif_running(dev)) {
3037                DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
3038                return;
3039        }
3040
3041        is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
3042        link_up = bp->link_vars.link_up;
3043        /* offline tests are not supported in MF mode */
3044        if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
3045                int port = BP_PORT(bp);
3046                u32 val;
3047
3048                /* save current value of input enable for TX port IF */
3049                val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
3050                /* disable input for TX port IF */
3051                REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
3052
3053                bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3054                rc = bnx2x_nic_load(bp, LOAD_DIAG);
3055                if (rc) {
3056                        etest->flags |= ETH_TEST_FL_FAILED;
3057                        DP(BNX2X_MSG_ETHTOOL,
3058                           "Can't perform self-test, nic_load (for offline) failed\n");
3059                        return;
3060                }
3061
3062                /* wait until link state is restored */
3063                bnx2x_wait_for_link(bp, 1, is_serdes);
3064
3065                if (bnx2x_test_registers(bp) != 0) {
3066                        buf[0] = 1;
3067                        etest->flags |= ETH_TEST_FL_FAILED;
3068                }
3069                if (bnx2x_test_memory(bp) != 0) {
3070                        buf[1] = 1;
3071                        etest->flags |= ETH_TEST_FL_FAILED;
3072                }
3073
3074                buf[2] = bnx2x_test_loopback(bp); /* internal LB */
3075                if (buf[2] != 0)
3076                        etest->flags |= ETH_TEST_FL_FAILED;
3077
3078                if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3079                        buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3080                        if (buf[3] != 0)
3081                                etest->flags |= ETH_TEST_FL_FAILED;
3082                        etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3083                }
3084
3085                bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3086
3087                /* restore input for TX port IF */
3088                REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3089                rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3090                if (rc) {
3091                        etest->flags |= ETH_TEST_FL_FAILED;
3092                        DP(BNX2X_MSG_ETHTOOL,
3093                           "Can't perform self-test, nic_load (for online) failed\n");
3094                        return;
3095                }
3096                /* wait until link state is restored */
3097                bnx2x_wait_for_link(bp, link_up, is_serdes);
3098        }
3099
3100        if (bnx2x_test_intr(bp) != 0) {
3101                if (!IS_MF(bp))
3102                        buf[5] = 1;
3103                else
3104                        buf[1] = 1;
3105                etest->flags |= ETH_TEST_FL_FAILED;
3106        }
3107
3108        if (link_up) {
3109                cnt = 100;
3110                while (bnx2x_link_test(bp, is_serdes) && --cnt)
3111                        msleep(20);
3112        }
3113
3114        if (!cnt) {
3115                if (!IS_MF(bp))
3116                        buf[6] = 1;
3117                else
3118                        buf[2] = 1;
3119                etest->flags |= ETH_TEST_FL_FAILED;
3120        }
3121}
3122
3123#define IS_PORT_STAT(i)         (bnx2x_stats_arr[i].is_port_stat)
3124#define HIDE_PORT_STAT(bp)      IS_VF(bp)
3125
3126/* ethtool statistics are displayed for all regular ethernet queues and the
3127 * fcoe L2 queue if not disabled
3128 */
3129static int bnx2x_num_stat_queues(struct bnx2x *bp)
3130{
3131        return BNX2X_NUM_ETH_QUEUES(bp);
3132}
3133
3134static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3135{
3136        struct bnx2x *bp = netdev_priv(dev);
3137        int i, num_strings = 0;
3138
3139        switch (stringset) {
3140        case ETH_SS_STATS:
3141                if (is_multi(bp)) {
3142                        num_strings = bnx2x_num_stat_queues(bp) *
3143                                      BNX2X_NUM_Q_STATS;
3144                } else
3145                        num_strings = 0;
3146                if (HIDE_PORT_STAT(bp)) {
3147                        for (i = 0; i < BNX2X_NUM_STATS; i++)
3148                                if (!IS_PORT_STAT(i))
3149                                        num_strings++;
3150                } else
3151                        num_strings += BNX2X_NUM_STATS;
3152
3153                return num_strings;
3154
3155        case ETH_SS_TEST:
3156                return BNX2X_NUM_TESTS(bp);
3157
3158        case ETH_SS_PRIV_FLAGS:
3159                return BNX2X_PRI_FLAG_LEN;
3160
3161        default:
3162                return -EINVAL;
3163        }
3164}
3165
3166static u32 bnx2x_get_private_flags(struct net_device *dev)
3167{
3168        struct bnx2x *bp = netdev_priv(dev);
3169        u32 flags = 0;
3170
3171        flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3172        flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3173        flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3174
3175        return flags;
3176}
3177
3178static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3179{
3180        struct bnx2x *bp = netdev_priv(dev);
3181        int i, j, k, start;
3182        char queue_name[MAX_QUEUE_NAME_LEN+1];
3183
3184        switch (stringset) {
3185        case ETH_SS_STATS:
3186                k = 0;
3187                if (is_multi(bp)) {
3188                        for_each_eth_queue(bp, i) {
3189                                memset(queue_name, 0, sizeof(queue_name));
3190                                snprintf(queue_name, sizeof(queue_name),
3191                                         "%d", i);
3192                                for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3193                                        snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3194                                                ETH_GSTRING_LEN,
3195                                                bnx2x_q_stats_arr[j].string,
3196                                                queue_name);
3197                                k += BNX2X_NUM_Q_STATS;
3198                        }
3199                }
3200
3201                for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3202                        if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3203                                continue;
3204                        strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3205                                   bnx2x_stats_arr[i].string);
3206                        j++;
3207                }
3208
3209                break;
3210
3211        case ETH_SS_TEST:
3212                /* First 4 tests cannot be done in MF mode */
3213                if (!IS_MF(bp))
3214                        start = 0;
3215                else
3216                        start = 4;
3217                memcpy(buf, bnx2x_tests_str_arr + start,
3218                       ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3219                break;
3220
3221        case ETH_SS_PRIV_FLAGS:
3222                memcpy(buf, bnx2x_private_arr,
3223                       ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3224                break;
3225        }
3226}
3227
3228static void bnx2x_get_ethtool_stats(struct net_device *dev,
3229                                    struct ethtool_stats *stats, u64 *buf)
3230{
3231        struct bnx2x *bp = netdev_priv(dev);
3232        u32 *hw_stats, *offset;
3233        int i, j, k = 0;
3234
3235        if (is_multi(bp)) {
3236                for_each_eth_queue(bp, i) {
3237                        hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3238                        for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3239                                if (bnx2x_q_stats_arr[j].size == 0) {
3240                                        /* skip this counter */
3241                                        buf[k + j] = 0;
3242                                        continue;
3243                                }
3244                                offset = (hw_stats +
3245                                          bnx2x_q_stats_arr[j].offset);
3246                                if (bnx2x_q_stats_arr[j].size == 4) {
3247                                        /* 4-byte counter */
3248                                        buf[k + j] = (u64) *offset;
3249                                        continue;
3250                                }
3251                                /* 8-byte counter */
3252                                buf[k + j] = HILO_U64(*offset, *(offset + 1));
3253                        }
3254                        k += BNX2X_NUM_Q_STATS;
3255                }
3256        }
3257
3258        hw_stats = (u32 *)&bp->eth_stats;
3259        for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3260                if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3261                        continue;
3262                if (bnx2x_stats_arr[i].size == 0) {
3263                        /* skip this counter */
3264                        buf[k + j] = 0;
3265                        j++;
3266                        continue;
3267                }
3268                offset = (hw_stats + bnx2x_stats_arr[i].offset);
3269                if (bnx2x_stats_arr[i].size == 4) {
3270                        /* 4-byte counter */
3271                        buf[k + j] = (u64) *offset;
3272                        j++;
3273                        continue;
3274                }
3275                /* 8-byte counter */
3276                buf[k + j] = HILO_U64(*offset, *(offset + 1));
3277                j++;
3278        }
3279}
3280
3281static int bnx2x_set_phys_id(struct net_device *dev,
3282                             enum ethtool_phys_id_state state)
3283{
3284        struct bnx2x *bp = netdev_priv(dev);
3285
3286        if (!bnx2x_is_nvm_accessible(bp)) {
3287                DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3288                   "cannot access eeprom when the interface is down\n");
3289                return -EAGAIN;
3290        }
3291
3292        switch (state) {
3293        case ETHTOOL_ID_ACTIVE:
3294                return 1;       /* cycle on/off once per second */
3295
3296        case ETHTOOL_ID_ON:
3297                bnx2x_acquire_phy_lock(bp);
3298                bnx2x_set_led(&bp->link_params, &bp->link_vars,
3299                              LED_MODE_ON, SPEED_1000);
3300                bnx2x_release_phy_lock(bp);
3301                break;
3302
3303        case ETHTOOL_ID_OFF:
3304                bnx2x_acquire_phy_lock(bp);
3305                bnx2x_set_led(&bp->link_params, &bp->link_vars,
3306                              LED_MODE_FRONT_PANEL_OFF, 0);
3307                bnx2x_release_phy_lock(bp);
3308                break;
3309
3310        case ETHTOOL_ID_INACTIVE:
3311                bnx2x_acquire_phy_lock(bp);
3312                bnx2x_set_led(&bp->link_params, &bp->link_vars,
3313                              LED_MODE_OPER,
3314                              bp->link_vars.line_speed);
3315                bnx2x_release_phy_lock(bp);
3316        }
3317
3318        return 0;
3319}
3320
3321static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3322{
3323        switch (info->flow_type) {
3324        case TCP_V4_FLOW:
3325        case TCP_V6_FLOW:
3326                info->data = RXH_IP_SRC | RXH_IP_DST |
3327                             RXH_L4_B_0_1 | RXH_L4_B_2_3;
3328                break;
3329        case UDP_V4_FLOW:
3330                if (bp->rss_conf_obj.udp_rss_v4)
3331                        info->data = RXH_IP_SRC | RXH_IP_DST |
3332                                     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3333                else
3334                        info->data = RXH_IP_SRC | RXH_IP_DST;
3335                break;
3336        case UDP_V6_FLOW:
3337                if (bp->rss_conf_obj.udp_rss_v6)
3338                        info->data = RXH_IP_SRC | RXH_IP_DST |
3339                                     RXH_L4_B_0_1 | RXH_L4_B_2_3;
3340                else
3341                        info->data = RXH_IP_SRC | RXH_IP_DST;
3342                break;
3343        case IPV4_FLOW:
3344        case IPV6_FLOW:
3345                info->data = RXH_IP_SRC | RXH_IP_DST;
3346                break;
3347        default:
3348                info->data = 0;
3349                break;
3350        }
3351
3352        return 0;
3353}
3354
3355static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3356                           u32 *rules __always_unused)
3357{
3358        struct bnx2x *bp = netdev_priv(dev);
3359
3360        switch (info->cmd) {
3361        case ETHTOOL_GRXRINGS:
3362                info->data = BNX2X_NUM_ETH_QUEUES(bp);
3363                return 0;
3364        case ETHTOOL_GRXFH:
3365                return bnx2x_get_rss_flags(bp, info);
3366        default:
3367                DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3368                return -EOPNOTSUPP;
3369        }
3370}
3371
3372static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3373{
3374        int udp_rss_requested;
3375
3376        DP(BNX2X_MSG_ETHTOOL,
3377           "Set rss flags command parameters: flow type = %d, data = %llu\n",
3378           info->flow_type, info->data);
3379
3380        switch (info->flow_type) {
3381        case TCP_V4_FLOW:
3382        case TCP_V6_FLOW:
3383                /* For TCP only 4-tupple hash is supported */
3384                if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3385                                  RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3386                        DP(BNX2X_MSG_ETHTOOL,
3387                           "Command parameters not supported\n");
3388                        return -EINVAL;
3389                }
3390                return 0;
3391
3392        case UDP_V4_FLOW:
3393        case UDP_V6_FLOW:
3394                /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3395                if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3396                                   RXH_L4_B_0_1 | RXH_L4_B_2_3))
3397                        udp_rss_requested = 1;
3398                else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3399                        udp_rss_requested = 0;
3400                else
3401                        return -EINVAL;
3402
3403                if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3404                        DP(BNX2X_MSG_ETHTOOL,
3405                           "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3406                        return -EINVAL;
3407                }
3408
3409                if ((info->flow_type == UDP_V4_FLOW) &&
3410                    (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3411                        bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3412                        DP(BNX2X_MSG_ETHTOOL,
3413                           "rss re-configured, UDP 4-tupple %s\n",
3414                           udp_rss_requested ? "enabled" : "disabled");
3415                        if (bp->state == BNX2X_STATE_OPEN)
3416                                return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3417                                                 true);
3418                } else if ((info->flow_type == UDP_V6_FLOW) &&
3419                           (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3420                        bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3421                        DP(BNX2X_MSG_ETHTOOL,
3422                           "rss re-configured, UDP 4-tupple %s\n",
3423                           udp_rss_requested ? "enabled" : "disabled");
3424                        if (bp->state == BNX2X_STATE_OPEN)
3425                                return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3426                                                 true);
3427                }
3428                return 0;
3429
3430        case IPV4_FLOW:
3431        case IPV6_FLOW:
3432                /* For IP only 2-tupple hash is supported */
3433                if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3434                        DP(BNX2X_MSG_ETHTOOL,
3435                           "Command parameters not supported\n");
3436                        return -EINVAL;
3437                }
3438                return 0;
3439
3440        case SCTP_V4_FLOW:
3441        case AH_ESP_V4_FLOW:
3442        case AH_V4_FLOW:
3443        case ESP_V4_FLOW:
3444        case SCTP_V6_FLOW:
3445        case AH_ESP_V6_FLOW:
3446        case AH_V6_FLOW:
3447        case ESP_V6_FLOW:
3448        case IP_USER_FLOW:
3449        case ETHER_FLOW:
3450                /* RSS is not supported for these protocols */
3451                if (info->data) {
3452                        DP(BNX2X_MSG_ETHTOOL,
3453                           "Command parameters not supported\n");
3454                        return -EINVAL;
3455                }
3456                return 0;
3457
3458        default:
3459                return -EINVAL;
3460        }
3461}
3462
3463static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3464{
3465        struct bnx2x *bp = netdev_priv(dev);
3466
3467        switch (info->cmd) {
3468        case ETHTOOL_SRXFH:
3469                return bnx2x_set_rss_flags(bp, info);
3470        default:
3471                DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3472                return -EOPNOTSUPP;
3473        }
3474}
3475
3476static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3477{
3478        return T_ETH_INDIRECTION_TABLE_SIZE;
3479}
3480
3481static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3482                          u8 *hfunc)
3483{
3484        struct bnx2x *bp = netdev_priv(dev);
3485        u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3486        size_t i;
3487
3488        if (hfunc)
3489                *hfunc = ETH_RSS_HASH_TOP;
3490        if (!indir)
3491                return 0;
3492
3493        /* Get the current configuration of the RSS indirection table */
3494        bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3495
3496        /*
3497         * We can't use a memcpy() as an internal storage of an
3498         * indirection table is a u8 array while indir->ring_index
3499         * points to an array of u32.
3500         *
3501         * Indirection table contains the FW Client IDs, so we need to
3502         * align the returned table to the Client ID of the leading RSS
3503         * queue.
3504         */
3505        for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3506                indir[i] = ind_table[i] - bp->fp->cl_id;
3507
3508        return 0;
3509}
3510
3511static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3512                          const u8 *key, const u8 hfunc)
3513{
3514        struct bnx2x *bp = netdev_priv(dev);
3515        size_t i;
3516
3517        /* We require at least one supported parameter to be changed and no
3518         * change in any of the unsupported parameters
3519         */
3520        if (key ||
3521            (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3522                return -EOPNOTSUPP;
3523
3524        if (!indir)
3525                return 0;
3526
3527        for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3528                /*
3529                 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3530                 * as an internal storage of an indirection table is a u8 array
3531                 * while indir->ring_index points to an array of u32.
3532                 *
3533                 * Indirection table contains the FW Client IDs, so we need to
3534                 * align the received table to the Client ID of the leading RSS
3535                 * queue
3536                 */
3537                bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3538        }
3539
3540        if (bp->state == BNX2X_STATE_OPEN)
3541                return bnx2x_config_rss_eth(bp, false);
3542
3543        return 0;
3544}
3545
3546/**
3547 * bnx2x_get_channels - gets the number of RSS queues.
3548 *
3549 * @dev:                net device
3550 * @channels:           returns the number of max / current queues
3551 */
3552static void bnx2x_get_channels(struct net_device *dev,
3553                               struct ethtool_channels *channels)
3554{
3555        struct bnx2x *bp = netdev_priv(dev);
3556
3557        channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3558        channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3559}
3560
3561/**
3562 * bnx2x_change_num_queues - change the number of RSS queues.
3563 *
3564 * @bp:                 bnx2x private structure
3565 * @num_rss:            rss count
3566 *
3567 * Re-configure interrupt mode to get the new number of MSI-X
3568 * vectors and re-add NAPI objects.
3569 */
3570static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3571{
3572        bnx2x_disable_msi(bp);
3573        bp->num_ethernet_queues = num_rss;
3574        bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3575        BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3576        bnx2x_set_int_mode(bp);
3577}
3578
3579/**
3580 * bnx2x_set_channels - sets the number of RSS queues.
3581 *
3582 * @dev:                net device
3583 * @channels:           includes the number of queues requested
3584 */
3585static int bnx2x_set_channels(struct net_device *dev,
3586                              struct ethtool_channels *channels)
3587{
3588        struct bnx2x *bp = netdev_priv(dev);
3589
3590        DP(BNX2X_MSG_ETHTOOL,
3591           "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3592           channels->rx_count, channels->tx_count, channels->other_count,
3593           channels->combined_count);
3594
3595        if (pci_num_vf(bp->pdev)) {
3596                DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3597                return -EPERM;
3598        }
3599
3600        /* We don't support separate rx / tx channels.
3601         * We don't allow setting 'other' channels.
3602         */
3603        if (channels->rx_count || channels->tx_count || channels->other_count
3604            || (channels->combined_count == 0) ||
3605            (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3606                DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3607                return -EINVAL;
3608        }
3609
3610        /* Check if there was a change in the active parameters */
3611        if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3612                DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3613                return 0;
3614        }
3615
3616        /* Set the requested number of queues in bp context.
3617         * Note that the actual number of queues created during load may be
3618         * less than requested if memory is low.
3619         */
3620        if (unlikely(!netif_running(dev))) {
3621                bnx2x_change_num_queues(bp, channels->combined_count);
3622                return 0;
3623        }
3624        bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3625        bnx2x_change_num_queues(bp, channels->combined_count);
3626        return bnx2x_nic_load(bp, LOAD_NORMAL);
3627}
3628
3629static int bnx2x_get_ts_info(struct net_device *dev,
3630                             struct ethtool_ts_info *info)
3631{
3632        struct bnx2x *bp = netdev_priv(dev);
3633
3634        if (bp->flags & PTP_SUPPORTED) {
3635                info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3636                                        SOF_TIMESTAMPING_RX_SOFTWARE |
3637                                        SOF_TIMESTAMPING_SOFTWARE |
3638                                        SOF_TIMESTAMPING_TX_HARDWARE |
3639                                        SOF_TIMESTAMPING_RX_HARDWARE |
3640                                        SOF_TIMESTAMPING_RAW_HARDWARE;
3641
3642                if (bp->ptp_clock)
3643                        info->phc_index = ptp_clock_index(bp->ptp_clock);
3644                else
3645                        info->phc_index = -1;
3646
3647                info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3648                                   (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3649                                   (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3650                                   (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3651
3652                info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3653
3654                return 0;
3655        }
3656
3657        return ethtool_op_get_ts_info(dev, info);
3658}
3659
3660static const struct ethtool_ops bnx2x_ethtool_ops = {
3661        .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
3662        .get_drvinfo            = bnx2x_get_drvinfo,
3663        .get_regs_len           = bnx2x_get_regs_len,
3664        .get_regs               = bnx2x_get_regs,
3665        .get_dump_flag          = bnx2x_get_dump_flag,
3666        .get_dump_data          = bnx2x_get_dump_data,
3667        .set_dump               = bnx2x_set_dump,
3668        .get_wol                = bnx2x_get_wol,
3669        .set_wol                = bnx2x_set_wol,
3670        .get_msglevel           = bnx2x_get_msglevel,
3671        .set_msglevel           = bnx2x_set_msglevel,
3672        .nway_reset             = bnx2x_nway_reset,
3673        .get_link               = bnx2x_get_link,
3674        .get_eeprom_len         = bnx2x_get_eeprom_len,
3675        .get_eeprom             = bnx2x_get_eeprom,
3676        .set_eeprom             = bnx2x_set_eeprom,
3677        .get_coalesce           = bnx2x_get_coalesce,
3678        .set_coalesce           = bnx2x_set_coalesce,
3679        .get_ringparam          = bnx2x_get_ringparam,
3680        .set_ringparam          = bnx2x_set_ringparam,
3681        .get_pauseparam         = bnx2x_get_pauseparam,
3682        .set_pauseparam         = bnx2x_set_pauseparam,
3683        .self_test              = bnx2x_self_test,
3684        .get_sset_count         = bnx2x_get_sset_count,
3685        .get_priv_flags         = bnx2x_get_private_flags,
3686        .get_strings            = bnx2x_get_strings,
3687        .set_phys_id            = bnx2x_set_phys_id,
3688        .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3689        .get_rxnfc              = bnx2x_get_rxnfc,
3690        .set_rxnfc              = bnx2x_set_rxnfc,
3691        .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3692        .get_rxfh               = bnx2x_get_rxfh,
3693        .set_rxfh               = bnx2x_set_rxfh,
3694        .get_channels           = bnx2x_get_channels,
3695        .set_channels           = bnx2x_set_channels,
3696        .get_module_info        = bnx2x_get_module_info,
3697        .get_module_eeprom      = bnx2x_get_module_eeprom,
3698        .get_eee                = bnx2x_get_eee,
3699        .set_eee                = bnx2x_set_eee,
3700        .get_ts_info            = bnx2x_get_ts_info,
3701        .get_link_ksettings     = bnx2x_get_link_ksettings,
3702        .set_link_ksettings     = bnx2x_set_link_ksettings,
3703};
3704
3705static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3706        .get_drvinfo            = bnx2x_get_drvinfo,
3707        .get_msglevel           = bnx2x_get_msglevel,
3708        .set_msglevel           = bnx2x_set_msglevel,
3709        .get_link               = bnx2x_get_link,
3710        .get_coalesce           = bnx2x_get_coalesce,
3711        .get_ringparam          = bnx2x_get_ringparam,
3712        .set_ringparam          = bnx2x_set_ringparam,
3713        .get_sset_count         = bnx2x_get_sset_count,
3714        .get_strings            = bnx2x_get_strings,
3715        .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3716        .get_rxnfc              = bnx2x_get_rxnfc,
3717        .set_rxnfc              = bnx2x_set_rxnfc,
3718        .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3719        .get_rxfh               = bnx2x_get_rxfh,
3720        .set_rxfh               = bnx2x_set_rxfh,
3721        .get_channels           = bnx2x_get_channels,
3722        .set_channels           = bnx2x_set_channels,
3723        .get_link_ksettings     = bnx2x_get_vf_link_ksettings,
3724};
3725
3726void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3727{
3728        netdev->ethtool_ops = (IS_PF(bp)) ?
3729                &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3730}
3731
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