linux/drivers/i2c/busses/i2c-s3c2410.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/* linux/drivers/i2c/busses/i2c-s3c2410.c
   3 *
   4 * Copyright (C) 2004,2005,2009 Simtec Electronics
   5 *      Ben Dooks <ben@simtec.co.uk>
   6 *
   7 * S3C2410 I2C Controller
   8*/
   9
  10#include <linux/kernel.h>
  11#include <linux/module.h>
  12
  13#include <linux/i2c.h>
  14#include <linux/init.h>
  15#include <linux/time.h>
  16#include <linux/interrupt.h>
  17#include <linux/delay.h>
  18#include <linux/errno.h>
  19#include <linux/err.h>
  20#include <linux/platform_device.h>
  21#include <linux/pm_runtime.h>
  22#include <linux/clk.h>
  23#include <linux/cpufreq.h>
  24#include <linux/slab.h>
  25#include <linux/io.h>
  26#include <linux/of.h>
  27#include <linux/of_device.h>
  28#include <linux/gpio/consumer.h>
  29#include <linux/pinctrl/consumer.h>
  30#include <linux/mfd/syscon.h>
  31#include <linux/regmap.h>
  32
  33#include <asm/irq.h>
  34
  35#include <linux/platform_data/i2c-s3c2410.h>
  36
  37/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
  38
  39#define S3C2410_IICCON                  0x00
  40#define S3C2410_IICSTAT                 0x04
  41#define S3C2410_IICADD                  0x08
  42#define S3C2410_IICDS                   0x0C
  43#define S3C2440_IICLC                   0x10
  44
  45#define S3C2410_IICCON_ACKEN            (1 << 7)
  46#define S3C2410_IICCON_TXDIV_16         (0 << 6)
  47#define S3C2410_IICCON_TXDIV_512        (1 << 6)
  48#define S3C2410_IICCON_IRQEN            (1 << 5)
  49#define S3C2410_IICCON_IRQPEND          (1 << 4)
  50#define S3C2410_IICCON_SCALE(x)         ((x) & 0xf)
  51#define S3C2410_IICCON_SCALEMASK        (0xf)
  52
  53#define S3C2410_IICSTAT_MASTER_RX       (2 << 6)
  54#define S3C2410_IICSTAT_MASTER_TX       (3 << 6)
  55#define S3C2410_IICSTAT_SLAVE_RX        (0 << 6)
  56#define S3C2410_IICSTAT_SLAVE_TX        (1 << 6)
  57#define S3C2410_IICSTAT_MODEMASK        (3 << 6)
  58
  59#define S3C2410_IICSTAT_START           (1 << 5)
  60#define S3C2410_IICSTAT_BUSBUSY         (1 << 5)
  61#define S3C2410_IICSTAT_TXRXEN          (1 << 4)
  62#define S3C2410_IICSTAT_ARBITR          (1 << 3)
  63#define S3C2410_IICSTAT_ASSLAVE         (1 << 2)
  64#define S3C2410_IICSTAT_ADDR0           (1 << 1)
  65#define S3C2410_IICSTAT_LASTBIT         (1 << 0)
  66
  67#define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
  68#define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
  69#define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
  70#define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
  71#define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
  72
  73#define S3C2410_IICLC_FILTER_ON         (1 << 2)
  74
  75/* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
  76#define QUIRK_S3C2440           (1 << 0)
  77#define QUIRK_HDMIPHY           (1 << 1)
  78#define QUIRK_NO_GPIO           (1 << 2)
  79#define QUIRK_POLL              (1 << 3)
  80
  81/* Max time to wait for bus to become idle after a xfer (in us) */
  82#define S3C2410_IDLE_TIMEOUT    5000
  83
  84/* Exynos5 Sysreg offset */
  85#define EXYNOS5_SYS_I2C_CFG     0x0234
  86
  87/* i2c controller state */
  88enum s3c24xx_i2c_state {
  89        STATE_IDLE,
  90        STATE_START,
  91        STATE_READ,
  92        STATE_WRITE,
  93        STATE_STOP
  94};
  95
  96struct s3c24xx_i2c {
  97        wait_queue_head_t       wait;
  98        kernel_ulong_t          quirks;
  99
 100        struct i2c_msg          *msg;
 101        unsigned int            msg_num;
 102        unsigned int            msg_idx;
 103        unsigned int            msg_ptr;
 104
 105        unsigned int            tx_setup;
 106        unsigned int            irq;
 107
 108        enum s3c24xx_i2c_state  state;
 109        unsigned long           clkrate;
 110
 111        void __iomem            *regs;
 112        struct clk              *clk;
 113        struct device           *dev;
 114        struct i2c_adapter      adap;
 115
 116        struct s3c2410_platform_i2c     *pdata;
 117        struct gpio_desc        *gpios[2];
 118        struct pinctrl          *pctrl;
 119#if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 120        struct notifier_block   freq_transition;
 121#endif
 122        struct regmap           *sysreg;
 123        unsigned int            sys_i2c_cfg;
 124};
 125
 126static const struct platform_device_id s3c24xx_driver_ids[] = {
 127        {
 128                .name           = "s3c2410-i2c",
 129                .driver_data    = 0,
 130        }, {
 131                .name           = "s3c2440-i2c",
 132                .driver_data    = QUIRK_S3C2440,
 133        }, {
 134                .name           = "s3c2440-hdmiphy-i2c",
 135                .driver_data    = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
 136        }, { },
 137};
 138MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 139
 140static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
 141
 142#ifdef CONFIG_OF
 143static const struct of_device_id s3c24xx_i2c_match[] = {
 144        { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
 145        { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
 146        { .compatible = "samsung,s3c2440-hdmiphy-i2c",
 147          .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
 148        { .compatible = "samsung,exynos5-sata-phy-i2c",
 149          .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
 150        {},
 151};
 152MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
 153#endif
 154
 155/*
 156 * Get controller type either from device tree or platform device variant.
 157 */
 158static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
 159{
 160        if (pdev->dev.of_node)
 161                return (kernel_ulong_t)of_device_get_match_data(&pdev->dev);
 162
 163        return platform_get_device_id(pdev)->driver_data;
 164}
 165
 166/*
 167 * Complete the message and wake up the caller, using the given return code,
 168 * or zero to mean ok.
 169 */
 170static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 171{
 172        dev_dbg(i2c->dev, "master_complete %d\n", ret);
 173
 174        i2c->msg_ptr = 0;
 175        i2c->msg = NULL;
 176        i2c->msg_idx++;
 177        i2c->msg_num = 0;
 178        if (ret)
 179                i2c->msg_idx = ret;
 180
 181        if (!(i2c->quirks & QUIRK_POLL))
 182                wake_up(&i2c->wait);
 183}
 184
 185static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 186{
 187        unsigned long tmp;
 188
 189        tmp = readl(i2c->regs + S3C2410_IICCON);
 190        writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 191}
 192
 193static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 194{
 195        unsigned long tmp;
 196
 197        tmp = readl(i2c->regs + S3C2410_IICCON);
 198        writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 199}
 200
 201/* irq enable/disable functions */
 202static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 203{
 204        unsigned long tmp;
 205
 206        tmp = readl(i2c->regs + S3C2410_IICCON);
 207        writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 208}
 209
 210static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 211{
 212        unsigned long tmp;
 213
 214        tmp = readl(i2c->regs + S3C2410_IICCON);
 215        writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 216}
 217
 218static bool is_ack(struct s3c24xx_i2c *i2c)
 219{
 220        int tries;
 221
 222        for (tries = 50; tries; --tries) {
 223                if (readl(i2c->regs + S3C2410_IICCON)
 224                        & S3C2410_IICCON_IRQPEND) {
 225                        if (!(readl(i2c->regs + S3C2410_IICSTAT)
 226                                & S3C2410_IICSTAT_LASTBIT))
 227                                return true;
 228                }
 229                usleep_range(1000, 2000);
 230        }
 231        dev_err(i2c->dev, "ack was not received\n");
 232        return false;
 233}
 234
 235/*
 236 * put the start of a message onto the bus
 237 */
 238static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 239                                      struct i2c_msg *msg)
 240{
 241        unsigned int addr = (msg->addr & 0x7f) << 1;
 242        unsigned long stat;
 243        unsigned long iiccon;
 244
 245        stat = 0;
 246        stat |=  S3C2410_IICSTAT_TXRXEN;
 247
 248        if (msg->flags & I2C_M_RD) {
 249                stat |= S3C2410_IICSTAT_MASTER_RX;
 250                addr |= 1;
 251        } else
 252                stat |= S3C2410_IICSTAT_MASTER_TX;
 253
 254        if (msg->flags & I2C_M_REV_DIR_ADDR)
 255                addr ^= 1;
 256
 257        /* todo - check for whether ack wanted or not */
 258        s3c24xx_i2c_enable_ack(i2c);
 259
 260        iiccon = readl(i2c->regs + S3C2410_IICCON);
 261        writel(stat, i2c->regs + S3C2410_IICSTAT);
 262
 263        dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 264        writeb(addr, i2c->regs + S3C2410_IICDS);
 265
 266        /*
 267         * delay here to ensure the data byte has gotten onto the bus
 268         * before the transaction is started
 269         */
 270        ndelay(i2c->tx_setup);
 271
 272        dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 273        writel(iiccon, i2c->regs + S3C2410_IICCON);
 274
 275        stat |= S3C2410_IICSTAT_START;
 276        writel(stat, i2c->regs + S3C2410_IICSTAT);
 277
 278        if (i2c->quirks & QUIRK_POLL) {
 279                while ((i2c->msg_num != 0) && is_ack(i2c)) {
 280                        i2c_s3c_irq_nextbyte(i2c, stat);
 281                        stat = readl(i2c->regs + S3C2410_IICSTAT);
 282
 283                        if (stat & S3C2410_IICSTAT_ARBITR)
 284                                dev_err(i2c->dev, "deal with arbitration loss\n");
 285                }
 286        }
 287}
 288
 289static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 290{
 291        unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 292
 293        dev_dbg(i2c->dev, "STOP\n");
 294
 295        /*
 296         * The datasheet says that the STOP sequence should be:
 297         *  1) I2CSTAT.5 = 0    - Clear BUSY (or 'generate STOP')
 298         *  2) I2CCON.4 = 0     - Clear IRQPEND
 299         *  3) Wait until the stop condition takes effect.
 300         *  4*) I2CSTAT.4 = 0   - Clear TXRXEN
 301         *
 302         * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
 303         *
 304         * However, after much experimentation, it appears that:
 305         * a) normal buses automatically clear BUSY and transition from
 306         *    Master->Slave when they complete generating a STOP condition.
 307         *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
 308         *    after starting the STOP generation here.
 309         * b) HDMIPHY bus does neither, so there is no way to do step 3.
 310         *    There is no indication when this bus has finished generating
 311         *    STOP.
 312         *
 313         * In fact, we have found that as soon as the IRQPEND bit is cleared in
 314         * step 2, the HDMIPHY bus generates the STOP condition, and then
 315         * immediately starts transferring another data byte, even though the
 316         * bus is supposedly stopped.  This is presumably because the bus is
 317         * still in "Master" mode, and its BUSY bit is still set.
 318         *
 319         * To avoid these extra post-STOP transactions on HDMI phy devices, we
 320         * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
 321         * instead of first generating a proper STOP condition.  This should
 322         * float SDA & SCK terminating the transfer.  Subsequent transfers
 323         *  start with a proper START condition, and proceed normally.
 324         *
 325         * The HDMIPHY bus is an internal bus that always has exactly two
 326         * devices, the host as Master and the HDMIPHY device as the slave.
 327         * Skipping the STOP condition has been tested on this bus and works.
 328         */
 329        if (i2c->quirks & QUIRK_HDMIPHY) {
 330                /* Stop driving the I2C pins */
 331                iicstat &= ~S3C2410_IICSTAT_TXRXEN;
 332        } else {
 333                /* stop the transfer */
 334                iicstat &= ~S3C2410_IICSTAT_START;
 335        }
 336        writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 337
 338        i2c->state = STATE_STOP;
 339
 340        s3c24xx_i2c_master_complete(i2c, ret);
 341        s3c24xx_i2c_disable_irq(i2c);
 342}
 343
 344/*
 345 * helper functions to determine the current state in the set of
 346 * messages we are sending
 347 */
 348
 349/*
 350 * returns TRUE if the current message is the last in the set
 351 */
 352static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 353{
 354        return i2c->msg_idx >= (i2c->msg_num - 1);
 355}
 356
 357/*
 358 * returns TRUE if we this is the last byte in the current message
 359 */
 360static inline int is_msglast(struct s3c24xx_i2c *i2c)
 361{
 362        /*
 363         * msg->len is always 1 for the first byte of smbus block read.
 364         * Actual length will be read from slave. More bytes will be
 365         * read according to the length then.
 366         */
 367        if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 368                return 0;
 369
 370        return i2c->msg_ptr == i2c->msg->len-1;
 371}
 372
 373/*
 374 * returns TRUE if we reached the end of the current message
 375 */
 376static inline int is_msgend(struct s3c24xx_i2c *i2c)
 377{
 378        return i2c->msg_ptr >= i2c->msg->len;
 379}
 380
 381/*
 382 * process an interrupt and work out what to do
 383 */
 384static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 385{
 386        unsigned long tmp;
 387        unsigned char byte;
 388        int ret = 0;
 389
 390        switch (i2c->state) {
 391
 392        case STATE_IDLE:
 393                dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 394                goto out;
 395
 396        case STATE_STOP:
 397                dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 398                s3c24xx_i2c_disable_irq(i2c);
 399                goto out_ack;
 400
 401        case STATE_START:
 402                /*
 403                 * last thing we did was send a start condition on the
 404                 * bus, or started a new i2c message
 405                 */
 406                if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 407                    !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 408                        /* ack was not received... */
 409                        dev_dbg(i2c->dev, "ack was not received\n");
 410                        s3c24xx_i2c_stop(i2c, -ENXIO);
 411                        goto out_ack;
 412                }
 413
 414                if (i2c->msg->flags & I2C_M_RD)
 415                        i2c->state = STATE_READ;
 416                else
 417                        i2c->state = STATE_WRITE;
 418
 419                /*
 420                 * Terminate the transfer if there is nothing to do
 421                 * as this is used by the i2c probe to find devices.
 422                 */
 423                if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 424                        s3c24xx_i2c_stop(i2c, 0);
 425                        goto out_ack;
 426                }
 427
 428                if (i2c->state == STATE_READ)
 429                        goto prepare_read;
 430
 431                /*
 432                 * fall through to the write state, as we will need to
 433                 * send a byte as well
 434                 */
 435                fallthrough;
 436        case STATE_WRITE:
 437                /*
 438                 * we are writing data to the device... check for the
 439                 * end of the message, and if so, work out what to do
 440                 */
 441                if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 442                        if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 443                                dev_dbg(i2c->dev, "WRITE: No Ack\n");
 444
 445                                s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 446                                goto out_ack;
 447                        }
 448                }
 449
 450 retry_write:
 451
 452                if (!is_msgend(i2c)) {
 453                        byte = i2c->msg->buf[i2c->msg_ptr++];
 454                        writeb(byte, i2c->regs + S3C2410_IICDS);
 455
 456                        /*
 457                         * delay after writing the byte to allow the
 458                         * data setup time on the bus, as writing the
 459                         * data to the register causes the first bit
 460                         * to appear on SDA, and SCL will change as
 461                         * soon as the interrupt is acknowledged
 462                         */
 463                        ndelay(i2c->tx_setup);
 464
 465                } else if (!is_lastmsg(i2c)) {
 466                        /* we need to go to the next i2c message */
 467
 468                        dev_dbg(i2c->dev, "WRITE: Next Message\n");
 469
 470                        i2c->msg_ptr = 0;
 471                        i2c->msg_idx++;
 472                        i2c->msg++;
 473
 474                        /* check to see if we need to do another message */
 475                        if (i2c->msg->flags & I2C_M_NOSTART) {
 476
 477                                if (i2c->msg->flags & I2C_M_RD) {
 478                                        /*
 479                                         * cannot do this, the controller
 480                                         * forces us to send a new START
 481                                         * when we change direction
 482                                         */
 483                                        dev_dbg(i2c->dev,
 484                                                "missing START before write->read\n");
 485                                        s3c24xx_i2c_stop(i2c, -EINVAL);
 486                                        break;
 487                                }
 488
 489                                goto retry_write;
 490                        } else {
 491                                /* send the new start */
 492                                s3c24xx_i2c_message_start(i2c, i2c->msg);
 493                                i2c->state = STATE_START;
 494                        }
 495
 496                } else {
 497                        /* send stop */
 498                        s3c24xx_i2c_stop(i2c, 0);
 499                }
 500                break;
 501
 502        case STATE_READ:
 503                /*
 504                 * we have a byte of data in the data register, do
 505                 * something with it, and then work out whether we are
 506                 * going to do any more read/write
 507                 */
 508                byte = readb(i2c->regs + S3C2410_IICDS);
 509                i2c->msg->buf[i2c->msg_ptr++] = byte;
 510
 511                /* Add actual length to read for smbus block read */
 512                if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 513                        i2c->msg->len += byte;
 514 prepare_read:
 515                if (is_msglast(i2c)) {
 516                        /* last byte of buffer */
 517
 518                        if (is_lastmsg(i2c))
 519                                s3c24xx_i2c_disable_ack(i2c);
 520
 521                } else if (is_msgend(i2c)) {
 522                        /*
 523                         * ok, we've read the entire buffer, see if there
 524                         * is anything else we need to do
 525                         */
 526                        if (is_lastmsg(i2c)) {
 527                                /* last message, send stop and complete */
 528                                dev_dbg(i2c->dev, "READ: Send Stop\n");
 529
 530                                s3c24xx_i2c_stop(i2c, 0);
 531                        } else {
 532                                /* go to the next transfer */
 533                                dev_dbg(i2c->dev, "READ: Next Transfer\n");
 534
 535                                i2c->msg_ptr = 0;
 536                                i2c->msg_idx++;
 537                                i2c->msg++;
 538                        }
 539                }
 540
 541                break;
 542        }
 543
 544        /* acknowlegde the IRQ and get back on with the work */
 545
 546 out_ack:
 547        tmp = readl(i2c->regs + S3C2410_IICCON);
 548        tmp &= ~S3C2410_IICCON_IRQPEND;
 549        writel(tmp, i2c->regs + S3C2410_IICCON);
 550 out:
 551        return ret;
 552}
 553
 554/*
 555 * top level IRQ servicing routine
 556 */
 557static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 558{
 559        struct s3c24xx_i2c *i2c = dev_id;
 560        unsigned long status;
 561        unsigned long tmp;
 562
 563        status = readl(i2c->regs + S3C2410_IICSTAT);
 564
 565        if (status & S3C2410_IICSTAT_ARBITR) {
 566                /* deal with arbitration loss */
 567                dev_err(i2c->dev, "deal with arbitration loss\n");
 568        }
 569
 570        if (i2c->state == STATE_IDLE) {
 571                dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 572
 573                tmp = readl(i2c->regs + S3C2410_IICCON);
 574                tmp &= ~S3C2410_IICCON_IRQPEND;
 575                writel(tmp, i2c->regs +  S3C2410_IICCON);
 576                goto out;
 577        }
 578
 579        /*
 580         * pretty much this leaves us with the fact that we've
 581         * transmitted or received whatever byte we last sent
 582         */
 583        i2c_s3c_irq_nextbyte(i2c, status);
 584
 585 out:
 586        return IRQ_HANDLED;
 587}
 588
 589/*
 590 * Disable the bus so that we won't get any interrupts from now on, or try
 591 * to drive any lines. This is the default state when we don't have
 592 * anything to send/receive.
 593 *
 594 * If there is an event on the bus, or we have a pre-existing event at
 595 * kernel boot time, we may not notice the event and the I2C controller
 596 * will lock the bus with the I2C clock line low indefinitely.
 597 */
 598static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
 599{
 600        unsigned long tmp;
 601
 602        /* Stop driving the I2C pins */
 603        tmp = readl(i2c->regs + S3C2410_IICSTAT);
 604        tmp &= ~S3C2410_IICSTAT_TXRXEN;
 605        writel(tmp, i2c->regs + S3C2410_IICSTAT);
 606
 607        /* We don't expect any interrupts now, and don't want send acks */
 608        tmp = readl(i2c->regs + S3C2410_IICCON);
 609        tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
 610                S3C2410_IICCON_ACKEN);
 611        writel(tmp, i2c->regs + S3C2410_IICCON);
 612}
 613
 614
 615/*
 616 * get the i2c bus for a master transaction
 617 */
 618static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 619{
 620        unsigned long iicstat;
 621        int timeout = 400;
 622
 623        while (timeout-- > 0) {
 624                iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 625
 626                if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 627                        return 0;
 628
 629                msleep(1);
 630        }
 631
 632        return -ETIMEDOUT;
 633}
 634
 635/*
 636 * wait for the i2c bus to become idle.
 637 */
 638static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
 639{
 640        unsigned long iicstat;
 641        ktime_t start, now;
 642        unsigned long delay;
 643        int spins;
 644
 645        /* ensure the stop has been through the bus */
 646
 647        dev_dbg(i2c->dev, "waiting for bus idle\n");
 648
 649        start = now = ktime_get();
 650
 651        /*
 652         * Most of the time, the bus is already idle within a few usec of the
 653         * end of a transaction.  However, really slow i2c devices can stretch
 654         * the clock, delaying STOP generation.
 655         *
 656         * On slower SoCs this typically happens within a very small number of
 657         * instructions so busy wait briefly to avoid scheduling overhead.
 658         */
 659        spins = 3;
 660        iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 661        while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
 662                cpu_relax();
 663                iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 664        }
 665
 666        /*
 667         * If we do get an appreciable delay as a compromise between idle
 668         * detection latency for the normal, fast case, and system load in the
 669         * slow device case, use an exponential back off in the polling loop,
 670         * up to 1/10th of the total timeout, then continue to poll at a
 671         * constant rate up to the timeout.
 672         */
 673        delay = 1;
 674        while ((iicstat & S3C2410_IICSTAT_START) &&
 675               ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
 676                usleep_range(delay, 2 * delay);
 677                if (delay < S3C2410_IDLE_TIMEOUT / 10)
 678                        delay <<= 1;
 679                now = ktime_get();
 680                iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 681        }
 682
 683        if (iicstat & S3C2410_IICSTAT_START)
 684                dev_warn(i2c->dev, "timeout waiting for bus idle\n");
 685}
 686
 687/*
 688 * this starts an i2c transfer
 689 */
 690static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 691                              struct i2c_msg *msgs, int num)
 692{
 693        unsigned long timeout;
 694        int ret;
 695
 696        ret = s3c24xx_i2c_set_master(i2c);
 697        if (ret != 0) {
 698                dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 699                ret = -EAGAIN;
 700                goto out;
 701        }
 702
 703        i2c->msg     = msgs;
 704        i2c->msg_num = num;
 705        i2c->msg_ptr = 0;
 706        i2c->msg_idx = 0;
 707        i2c->state   = STATE_START;
 708
 709        s3c24xx_i2c_enable_irq(i2c);
 710        s3c24xx_i2c_message_start(i2c, msgs);
 711
 712        if (i2c->quirks & QUIRK_POLL) {
 713                ret = i2c->msg_idx;
 714
 715                if (ret != num)
 716                        dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 717
 718                goto out;
 719        }
 720
 721        timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 722
 723        ret = i2c->msg_idx;
 724
 725        /*
 726         * Having these next two as dev_err() makes life very
 727         * noisy when doing an i2cdetect
 728         */
 729        if (timeout == 0)
 730                dev_dbg(i2c->dev, "timeout\n");
 731        else if (ret != num)
 732                dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 733
 734        /* For QUIRK_HDMIPHY, bus is already disabled */
 735        if (i2c->quirks & QUIRK_HDMIPHY)
 736                goto out;
 737
 738        s3c24xx_i2c_wait_idle(i2c);
 739
 740        s3c24xx_i2c_disable_bus(i2c);
 741
 742 out:
 743        i2c->state = STATE_IDLE;
 744
 745        return ret;
 746}
 747
 748/*
 749 * first port of call from the i2c bus code when an message needs
 750 * transferring across the i2c bus.
 751 */
 752static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 753                        struct i2c_msg *msgs, int num)
 754{
 755        struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 756        int retry;
 757        int ret;
 758
 759        ret = clk_enable(i2c->clk);
 760        if (ret)
 761                return ret;
 762
 763        for (retry = 0; retry < adap->retries; retry++) {
 764
 765                ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 766
 767                if (ret != -EAGAIN) {
 768                        clk_disable(i2c->clk);
 769                        return ret;
 770                }
 771
 772                dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 773
 774                udelay(100);
 775        }
 776
 777        clk_disable(i2c->clk);
 778        return -EREMOTEIO;
 779}
 780
 781/* declare our i2c functionality */
 782static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 783{
 784        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL_ALL | I2C_FUNC_NOSTART |
 785                I2C_FUNC_PROTOCOL_MANGLING;
 786}
 787
 788/* i2c bus registration info */
 789static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 790        .master_xfer            = s3c24xx_i2c_xfer,
 791        .functionality          = s3c24xx_i2c_func,
 792};
 793
 794/*
 795 * return the divisor settings for a given frequency
 796 */
 797static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 798                                   unsigned int *div1, unsigned int *divs)
 799{
 800        unsigned int calc_divs = clkin / wanted;
 801        unsigned int calc_div1;
 802
 803        if (calc_divs > (16*16))
 804                calc_div1 = 512;
 805        else
 806                calc_div1 = 16;
 807
 808        calc_divs += calc_div1-1;
 809        calc_divs /= calc_div1;
 810
 811        if (calc_divs == 0)
 812                calc_divs = 1;
 813        if (calc_divs > 17)
 814                calc_divs = 17;
 815
 816        *divs = calc_divs;
 817        *div1 = calc_div1;
 818
 819        return clkin / (calc_divs * calc_div1);
 820}
 821
 822/*
 823 * work out a divisor for the user requested frequency setting,
 824 * either by the requested frequency, or scanning the acceptable
 825 * range of frequencies until something is found
 826 */
 827static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 828{
 829        struct s3c2410_platform_i2c *pdata = i2c->pdata;
 830        unsigned long clkin = clk_get_rate(i2c->clk);
 831        unsigned int divs, div1;
 832        unsigned long target_frequency;
 833        u32 iiccon;
 834        int freq;
 835
 836        i2c->clkrate = clkin;
 837        clkin /= 1000;  /* clkin now in KHz */
 838
 839        dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
 840
 841        target_frequency = pdata->frequency ?: I2C_MAX_STANDARD_MODE_FREQ;
 842
 843        target_frequency /= 1000; /* Target frequency now in KHz */
 844
 845        freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
 846
 847        if (freq > target_frequency) {
 848                dev_err(i2c->dev,
 849                        "Unable to achieve desired frequency %luKHz."   \
 850                        " Lowest achievable %dKHz\n", target_frequency, freq);
 851                return -EINVAL;
 852        }
 853
 854        *got = freq;
 855
 856        iiccon = readl(i2c->regs + S3C2410_IICCON);
 857        iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 858        iiccon |= (divs-1);
 859
 860        if (div1 == 512)
 861                iiccon |= S3C2410_IICCON_TXDIV_512;
 862
 863        if (i2c->quirks & QUIRK_POLL)
 864                iiccon |= S3C2410_IICCON_SCALE(2);
 865
 866        writel(iiccon, i2c->regs + S3C2410_IICCON);
 867
 868        if (i2c->quirks & QUIRK_S3C2440) {
 869                unsigned long sda_delay;
 870
 871                if (pdata->sda_delay) {
 872                        sda_delay = clkin * pdata->sda_delay;
 873                        sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
 874                        sda_delay = DIV_ROUND_UP(sda_delay, 5);
 875                        if (sda_delay > 3)
 876                                sda_delay = 3;
 877                        sda_delay |= S3C2410_IICLC_FILTER_ON;
 878                } else
 879                        sda_delay = 0;
 880
 881                dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
 882                writel(sda_delay, i2c->regs + S3C2440_IICLC);
 883        }
 884
 885        return 0;
 886}
 887
 888#if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 889
 890#define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 891
 892static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 893                                          unsigned long val, void *data)
 894{
 895        struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 896        unsigned int got;
 897        int delta_f;
 898        int ret;
 899
 900        delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 901
 902        /* if we're post-change and the input clock has slowed down
 903         * or at pre-change and the clock is about to speed up, then
 904         * adjust our clock rate. <0 is slow, >0 speedup.
 905         */
 906
 907        if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 908            (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 909                i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
 910                ret = s3c24xx_i2c_clockrate(i2c, &got);
 911                i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
 912
 913                if (ret < 0)
 914                        dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
 915                else
 916                        dev_info(i2c->dev, "setting freq %d\n", got);
 917        }
 918
 919        return 0;
 920}
 921
 922static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 923{
 924        i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 925
 926        return cpufreq_register_notifier(&i2c->freq_transition,
 927                                         CPUFREQ_TRANSITION_NOTIFIER);
 928}
 929
 930static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 931{
 932        cpufreq_unregister_notifier(&i2c->freq_transition,
 933                                    CPUFREQ_TRANSITION_NOTIFIER);
 934}
 935
 936#else
 937static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 938{
 939        return 0;
 940}
 941
 942static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 943{
 944}
 945#endif
 946
 947#ifdef CONFIG_OF
 948static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 949{
 950        int i;
 951
 952        if (i2c->quirks & QUIRK_NO_GPIO)
 953                return 0;
 954
 955        for (i = 0; i < 2; i++) {
 956                i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL,
 957                                                     i, GPIOD_ASIS);
 958                if (IS_ERR(i2c->gpios[i])) {
 959                        dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i);
 960                        return -EINVAL;
 961                }
 962        }
 963        return 0;
 964}
 965
 966#else
 967static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 968{
 969        return 0;
 970}
 971#endif
 972
 973/*
 974 * initialise the controller, set the IO lines and frequency
 975 */
 976static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 977{
 978        struct s3c2410_platform_i2c *pdata;
 979        unsigned int freq;
 980
 981        /* get the plafrom data */
 982
 983        pdata = i2c->pdata;
 984
 985        /* write slave address */
 986
 987        writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
 988
 989        dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
 990
 991        writel(0, i2c->regs + S3C2410_IICCON);
 992        writel(0, i2c->regs + S3C2410_IICSTAT);
 993
 994        /* we need to work out the divisors for the clock... */
 995
 996        if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
 997                dev_err(i2c->dev, "cannot meet bus frequency required\n");
 998                return -EINVAL;
 999        }
1000
1001        /* todo - check that the i2c lines aren't being dragged anywhere */
1002
1003        dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1004        dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1005                readl(i2c->regs + S3C2410_IICCON));
1006
1007        return 0;
1008}
1009
1010#ifdef CONFIG_OF
1011/*
1012 * Parse the device tree node and retreive the platform data.
1013 */
1014static void
1015s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1016{
1017        struct s3c2410_platform_i2c *pdata = i2c->pdata;
1018        int id;
1019
1020        if (!np)
1021                return;
1022
1023        pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1024        of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1025        of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1026        of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1027                                (u32 *)&pdata->frequency);
1028        /*
1029         * Exynos5's legacy i2c controller and new high speed i2c
1030         * controller have muxed interrupt sources. By default the
1031         * interrupts for 4-channel HS-I2C controller are enabled.
1032         * If nodes for first four channels of legacy i2c controller
1033         * are available then re-configure the interrupts via the
1034         * system register.
1035         */
1036        id = of_alias_get_id(np, "i2c");
1037        i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1038                        "samsung,sysreg-phandle");
1039        if (IS_ERR(i2c->sysreg))
1040                return;
1041
1042        regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1043}
1044#else
1045static void
1046s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
1047#endif
1048
1049static int s3c24xx_i2c_probe(struct platform_device *pdev)
1050{
1051        struct s3c24xx_i2c *i2c;
1052        struct s3c2410_platform_i2c *pdata = NULL;
1053        struct resource *res;
1054        int ret;
1055
1056        if (!pdev->dev.of_node) {
1057                pdata = dev_get_platdata(&pdev->dev);
1058                if (!pdata) {
1059                        dev_err(&pdev->dev, "no platform data\n");
1060                        return -EINVAL;
1061                }
1062        }
1063
1064        i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1065        if (!i2c)
1066                return -ENOMEM;
1067
1068        i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1069        if (!i2c->pdata)
1070                return -ENOMEM;
1071
1072        i2c->quirks = s3c24xx_get_device_quirks(pdev);
1073        i2c->sysreg = ERR_PTR(-ENOENT);
1074        if (pdata)
1075                memcpy(i2c->pdata, pdata, sizeof(*pdata));
1076        else
1077                s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1078
1079        strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1080        i2c->adap.owner = THIS_MODULE;
1081        i2c->adap.algo = &s3c24xx_i2c_algorithm;
1082        i2c->adap.retries = 2;
1083        i2c->adap.class = I2C_CLASS_DEPRECATED;
1084        i2c->tx_setup = 50;
1085
1086        init_waitqueue_head(&i2c->wait);
1087
1088        /* find the clock and enable it */
1089        i2c->dev = &pdev->dev;
1090        i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1091        if (IS_ERR(i2c->clk)) {
1092                dev_err(&pdev->dev, "cannot get clock\n");
1093                return -ENOENT;
1094        }
1095
1096        dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1097
1098        /* map the registers */
1099        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1100        i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1101
1102        if (IS_ERR(i2c->regs))
1103                return PTR_ERR(i2c->regs);
1104
1105        dev_dbg(&pdev->dev, "registers %p (%p)\n",
1106                i2c->regs, res);
1107
1108        /* setup info block for the i2c core */
1109        i2c->adap.algo_data = i2c;
1110        i2c->adap.dev.parent = &pdev->dev;
1111        i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1112
1113        /* inititalise the i2c gpio lines */
1114        if (i2c->pdata->cfg_gpio)
1115                i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1116        else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1117                return -EINVAL;
1118
1119        /* initialise the i2c controller */
1120        ret = clk_prepare_enable(i2c->clk);
1121        if (ret) {
1122                dev_err(&pdev->dev, "I2C clock enable failed\n");
1123                return ret;
1124        }
1125
1126        ret = s3c24xx_i2c_init(i2c);
1127        clk_disable(i2c->clk);
1128        if (ret != 0) {
1129                dev_err(&pdev->dev, "I2C controller init failed\n");
1130                clk_unprepare(i2c->clk);
1131                return ret;
1132        }
1133
1134        /*
1135         * find the IRQ for this unit (note, this relies on the init call to
1136         * ensure no current IRQs pending
1137         */
1138        if (!(i2c->quirks & QUIRK_POLL)) {
1139                i2c->irq = ret = platform_get_irq(pdev, 0);
1140                if (ret <= 0) {
1141                        dev_err(&pdev->dev, "cannot find IRQ\n");
1142                        clk_unprepare(i2c->clk);
1143                        return ret;
1144                }
1145
1146                ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1147                                       0, dev_name(&pdev->dev), i2c);
1148                if (ret != 0) {
1149                        dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1150                        clk_unprepare(i2c->clk);
1151                        return ret;
1152                }
1153        }
1154
1155        ret = s3c24xx_i2c_register_cpufreq(i2c);
1156        if (ret < 0) {
1157                dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1158                clk_unprepare(i2c->clk);
1159                return ret;
1160        }
1161
1162        /*
1163         * Note, previous versions of the driver used i2c_add_adapter()
1164         * to add the bus at any number. We now pass the bus number via
1165         * the platform data, so if unset it will now default to always
1166         * being bus 0.
1167         */
1168        i2c->adap.nr = i2c->pdata->bus_num;
1169        i2c->adap.dev.of_node = pdev->dev.of_node;
1170
1171        platform_set_drvdata(pdev, i2c);
1172
1173        pm_runtime_enable(&pdev->dev);
1174
1175        ret = i2c_add_numbered_adapter(&i2c->adap);
1176        if (ret < 0) {
1177                pm_runtime_disable(&pdev->dev);
1178                s3c24xx_i2c_deregister_cpufreq(i2c);
1179                clk_unprepare(i2c->clk);
1180                return ret;
1181        }
1182
1183        dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1184        return 0;
1185}
1186
1187static int s3c24xx_i2c_remove(struct platform_device *pdev)
1188{
1189        struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1190
1191        clk_unprepare(i2c->clk);
1192
1193        pm_runtime_disable(&pdev->dev);
1194
1195        s3c24xx_i2c_deregister_cpufreq(i2c);
1196
1197        i2c_del_adapter(&i2c->adap);
1198
1199        return 0;
1200}
1201
1202#ifdef CONFIG_PM_SLEEP
1203static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1204{
1205        struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1206
1207        i2c_mark_adapter_suspended(&i2c->adap);
1208
1209        if (!IS_ERR(i2c->sysreg))
1210                regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1211
1212        return 0;
1213}
1214
1215static int s3c24xx_i2c_resume_noirq(struct device *dev)
1216{
1217        struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1218        int ret;
1219
1220        if (!IS_ERR(i2c->sysreg))
1221                regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1222
1223        ret = clk_enable(i2c->clk);
1224        if (ret)
1225                return ret;
1226        s3c24xx_i2c_init(i2c);
1227        clk_disable(i2c->clk);
1228        i2c_mark_adapter_resumed(&i2c->adap);
1229
1230        return 0;
1231}
1232#endif
1233
1234#ifdef CONFIG_PM
1235static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1236        SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1237                                      s3c24xx_i2c_resume_noirq)
1238};
1239
1240#define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1241#else
1242#define S3C24XX_DEV_PM_OPS NULL
1243#endif
1244
1245static struct platform_driver s3c24xx_i2c_driver = {
1246        .probe          = s3c24xx_i2c_probe,
1247        .remove         = s3c24xx_i2c_remove,
1248        .id_table       = s3c24xx_driver_ids,
1249        .driver         = {
1250                .name   = "s3c-i2c",
1251                .pm     = S3C24XX_DEV_PM_OPS,
1252                .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1253        },
1254};
1255
1256static int __init i2c_adap_s3c_init(void)
1257{
1258        return platform_driver_register(&s3c24xx_i2c_driver);
1259}
1260subsys_initcall(i2c_adap_s3c_init);
1261
1262static void __exit i2c_adap_s3c_exit(void)
1263{
1264        platform_driver_unregister(&s3c24xx_i2c_driver);
1265}
1266module_exit(i2c_adap_s3c_exit);
1267
1268MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1269MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1270MODULE_LICENSE("GPL");
1271
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