linux/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
   4 * Copyright (C) 2013 Red Hat
   5 * Author: Rob Clark <robdclark@gmail.com>
   6 */
   7
   8#define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
   9#include <linux/debugfs.h>
  10#include <linux/kthread.h>
  11#include <linux/seq_file.h>
  12
  13#include <drm/drm_crtc.h>
  14#include <drm/drm_file.h>
  15#include <drm/drm_probe_helper.h>
  16
  17#include "msm_drv.h"
  18#include "dpu_kms.h"
  19#include "dpu_hwio.h"
  20#include "dpu_hw_catalog.h"
  21#include "dpu_hw_intf.h"
  22#include "dpu_hw_ctl.h"
  23#include "dpu_hw_dspp.h"
  24#include "dpu_formats.h"
  25#include "dpu_encoder_phys.h"
  26#include "dpu_crtc.h"
  27#include "dpu_trace.h"
  28#include "dpu_core_irq.h"
  29#include "disp/msm_disp_snapshot.h"
  30
  31#define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
  32                (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  33
  34#define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
  35                (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  36
  37#define DPU_DEBUG_PHYS(p, fmt, ...) DRM_DEBUG_ATOMIC("enc%d intf%d pp%d " fmt,\
  38                (p) ? (p)->parent->base.id : -1, \
  39                (p) ? (p)->intf_idx - INTF_0 : -1, \
  40                (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  41                ##__VA_ARGS__)
  42
  43#define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\
  44                (p) ? (p)->parent->base.id : -1, \
  45                (p) ? (p)->intf_idx - INTF_0 : -1, \
  46                (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  47                ##__VA_ARGS__)
  48
  49/*
  50 * Two to anticipate panels that can do cmd/vid dynamic switching
  51 * plan is to create all possible physical encoder types, and switch between
  52 * them at runtime
  53 */
  54#define NUM_PHYS_ENCODER_TYPES 2
  55
  56#define MAX_PHYS_ENCODERS_PER_VIRTUAL \
  57        (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
  58
  59#define MAX_CHANNELS_PER_ENC 2
  60
  61#define IDLE_SHORT_TIMEOUT      1
  62
  63#define MAX_HDISPLAY_SPLIT 1080
  64
  65/* timeout in frames waiting for frame done */
  66#define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
  67
  68/**
  69 * enum dpu_enc_rc_events - events for resource control state machine
  70 * @DPU_ENC_RC_EVENT_KICKOFF:
  71 *      This event happens at NORMAL priority.
  72 *      Event that signals the start of the transfer. When this event is
  73 *      received, enable MDP/DSI core clocks. Regardless of the previous
  74 *      state, the resource should be in ON state at the end of this event.
  75 * @DPU_ENC_RC_EVENT_FRAME_DONE:
  76 *      This event happens at INTERRUPT level.
  77 *      Event signals the end of the data transfer after the PP FRAME_DONE
  78 *      event. At the end of this event, a delayed work is scheduled to go to
  79 *      IDLE_PC state after IDLE_TIMEOUT time.
  80 * @DPU_ENC_RC_EVENT_PRE_STOP:
  81 *      This event happens at NORMAL priority.
  82 *      This event, when received during the ON state, leave the RC STATE
  83 *      in the PRE_OFF state. It should be followed by the STOP event as
  84 *      part of encoder disable.
  85 *      If received during IDLE or OFF states, it will do nothing.
  86 * @DPU_ENC_RC_EVENT_STOP:
  87 *      This event happens at NORMAL priority.
  88 *      When this event is received, disable all the MDP/DSI core clocks, and
  89 *      disable IRQs. It should be called from the PRE_OFF or IDLE states.
  90 *      IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  91 *      PRE_OFF is expected when PRE_STOP was executed during the ON state.
  92 *      Resource state should be in OFF at the end of the event.
  93 * @DPU_ENC_RC_EVENT_ENTER_IDLE:
  94 *      This event happens at NORMAL priority from a work item.
  95 *      Event signals that there were no frame updates for IDLE_TIMEOUT time.
  96 *      This would disable MDP/DSI core clocks and change the resource state
  97 *      to IDLE.
  98 */
  99enum dpu_enc_rc_events {
 100        DPU_ENC_RC_EVENT_KICKOFF = 1,
 101        DPU_ENC_RC_EVENT_FRAME_DONE,
 102        DPU_ENC_RC_EVENT_PRE_STOP,
 103        DPU_ENC_RC_EVENT_STOP,
 104        DPU_ENC_RC_EVENT_ENTER_IDLE
 105};
 106
 107/*
 108 * enum dpu_enc_rc_states - states that the resource control maintains
 109 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
 110 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
 111 * @DPU_ENC_RC_STATE_ON: Resource is in ON state
 112 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
 113 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
 114 */
 115enum dpu_enc_rc_states {
 116        DPU_ENC_RC_STATE_OFF,
 117        DPU_ENC_RC_STATE_PRE_OFF,
 118        DPU_ENC_RC_STATE_ON,
 119        DPU_ENC_RC_STATE_IDLE
 120};
 121
 122/**
 123 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
 124 *      encoders. Virtual encoder manages one "logical" display. Physical
 125 *      encoders manage one intf block, tied to a specific panel/sub-panel.
 126 *      Virtual encoder defers as much as possible to the physical encoders.
 127 *      Virtual encoder registers itself with the DRM Framework as the encoder.
 128 * @base:               drm_encoder base class for registration with DRM
 129 * @enc_spinlock:       Virtual-Encoder-Wide Spin Lock for IRQ purposes
 130 * @bus_scaling_client: Client handle to the bus scaling interface
 131 * @enabled:            True if the encoder is active, protected by enc_lock
 132 * @num_phys_encs:      Actual number of physical encoders contained.
 133 * @phys_encs:          Container of physical encoders managed.
 134 * @cur_master:         Pointer to the current master in this mode. Optimization
 135 *                      Only valid after enable. Cleared as disable.
 136 * @cur_slave:          As above but for the slave encoder.
 137 * @hw_pp:              Handle to the pingpong blocks used for the display. No.
 138 *                      pingpong blocks can be different than num_phys_encs.
 139 * @intfs_swapped:      Whether or not the phys_enc interfaces have been swapped
 140 *                      for partial update right-only cases, such as pingpong
 141 *                      split where virtual pingpong does not generate IRQs
 142 * @crtc:               Pointer to the currently assigned crtc. Normally you
 143 *                      would use crtc->state->encoder_mask to determine the
 144 *                      link between encoder/crtc. However in this case we need
 145 *                      to track crtc in the disable() hook which is called
 146 *                      _after_ encoder_mask is cleared.
 147 * @crtc_kickoff_cb:            Callback into CRTC that will flush & start
 148 *                              all CTL paths
 149 * @crtc_kickoff_cb_data:       Opaque user data given to crtc_kickoff_cb
 150 * @debugfs_root:               Debug file system root file node
 151 * @enc_lock:                   Lock around physical encoder
 152 *                              create/destroy/enable/disable
 153 * @frame_busy_mask:            Bitmask tracking which phys_enc we are still
 154 *                              busy processing current command.
 155 *                              Bit0 = phys_encs[0] etc.
 156 * @crtc_frame_event_cb:        callback handler for frame event
 157 * @crtc_frame_event_cb_data:   callback handler private data
 158 * @frame_done_timeout_ms:      frame done timeout in ms
 159 * @frame_done_timer:           watchdog timer for frame done event
 160 * @vsync_event_timer:          vsync timer
 161 * @disp_info:                  local copy of msm_display_info struct
 162 * @idle_pc_supported:          indicate if idle power collaps is supported
 163 * @rc_lock:                    resource control mutex lock to protect
 164 *                              virt encoder over various state changes
 165 * @rc_state:                   resource controller state
 166 * @delayed_off_work:           delayed worker to schedule disabling of
 167 *                              clks and resources after IDLE_TIMEOUT time.
 168 * @vsync_event_work:           worker to handle vsync event for autorefresh
 169 * @topology:                   topology of the display
 170 * @idle_timeout:               idle timeout duration in milliseconds
 171 */
 172struct dpu_encoder_virt {
 173        struct drm_encoder base;
 174        spinlock_t enc_spinlock;
 175        uint32_t bus_scaling_client;
 176
 177        bool enabled;
 178
 179        unsigned int num_phys_encs;
 180        struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
 181        struct dpu_encoder_phys *cur_master;
 182        struct dpu_encoder_phys *cur_slave;
 183        struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
 184
 185        bool intfs_swapped;
 186
 187        struct drm_crtc *crtc;
 188
 189        struct dentry *debugfs_root;
 190        struct mutex enc_lock;
 191        DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
 192        void (*crtc_frame_event_cb)(void *, u32 event);
 193        void *crtc_frame_event_cb_data;
 194
 195        atomic_t frame_done_timeout_ms;
 196        struct timer_list frame_done_timer;
 197        struct timer_list vsync_event_timer;
 198
 199        struct msm_display_info disp_info;
 200
 201        bool idle_pc_supported;
 202        struct mutex rc_lock;
 203        enum dpu_enc_rc_states rc_state;
 204        struct delayed_work delayed_off_work;
 205        struct kthread_work vsync_event_work;
 206        struct msm_display_topology topology;
 207
 208        u32 idle_timeout;
 209};
 210
 211#define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 212
 213static u32 dither_matrix[DITHER_MATRIX_SZ] = {
 214        15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
 215};
 216
 217static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
 218{
 219        struct dpu_hw_dither_cfg dither_cfg = { 0 };
 220
 221        if (!hw_pp->ops.setup_dither)
 222                return;
 223
 224        switch (bpc) {
 225        case 6:
 226                dither_cfg.c0_bitdepth = 6;
 227                dither_cfg.c1_bitdepth = 6;
 228                dither_cfg.c2_bitdepth = 6;
 229                dither_cfg.c3_bitdepth = 6;
 230                dither_cfg.temporal_en = 0;
 231                break;
 232        default:
 233                hw_pp->ops.setup_dither(hw_pp, NULL);
 234                return;
 235        }
 236
 237        memcpy(&dither_cfg.matrix, dither_matrix,
 238                        sizeof(u32) * DITHER_MATRIX_SZ);
 239
 240        hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
 241}
 242
 243void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
 244                enum dpu_intr_idx intr_idx)
 245{
 246        DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
 247                  DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
 248                  phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
 249
 250        if (phys_enc->parent_ops->handle_frame_done)
 251                phys_enc->parent_ops->handle_frame_done(
 252                                phys_enc->parent, phys_enc,
 253                                DPU_ENCODER_FRAME_EVENT_ERROR);
 254}
 255
 256static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
 257                u32 irq_idx, struct dpu_encoder_wait_info *info);
 258
 259int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
 260                enum dpu_intr_idx intr_idx,
 261                struct dpu_encoder_wait_info *wait_info)
 262{
 263        struct dpu_encoder_irq *irq;
 264        u32 irq_status;
 265        int ret;
 266
 267        if (!wait_info || intr_idx >= INTR_IDX_MAX) {
 268                DPU_ERROR("invalid params\n");
 269                return -EINVAL;
 270        }
 271        irq = &phys_enc->irq[intr_idx];
 272
 273        /* note: do master / slave checking outside */
 274
 275        /* return EWOULDBLOCK since we know the wait isn't necessary */
 276        if (phys_enc->enable_state == DPU_ENC_DISABLED) {
 277                DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d",
 278                          DRMID(phys_enc->parent), intr_idx,
 279                          irq->irq_idx);
 280                return -EWOULDBLOCK;
 281        }
 282
 283        if (irq->irq_idx < 0) {
 284                DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s",
 285                              DRMID(phys_enc->parent), intr_idx,
 286                              irq->name);
 287                return 0;
 288        }
 289
 290        DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d",
 291                      DRMID(phys_enc->parent), intr_idx,
 292                      irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
 293                      atomic_read(wait_info->atomic_cnt));
 294
 295        ret = dpu_encoder_helper_wait_event_timeout(
 296                        DRMID(phys_enc->parent),
 297                        irq->irq_idx,
 298                        wait_info);
 299
 300        if (ret <= 0) {
 301                irq_status = dpu_core_irq_read(phys_enc->dpu_kms,
 302                                irq->irq_idx, true);
 303                if (irq_status) {
 304                        unsigned long flags;
 305
 306                        DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, "
 307                                      "irq=%d, pp=%d, atomic_cnt=%d",
 308                                      DRMID(phys_enc->parent), intr_idx,
 309                                      irq->irq_idx,
 310                                      phys_enc->hw_pp->idx - PINGPONG_0,
 311                                      atomic_read(wait_info->atomic_cnt));
 312                        local_irq_save(flags);
 313                        irq->cb.func(phys_enc, irq->irq_idx);
 314                        local_irq_restore(flags);
 315                        ret = 0;
 316                } else {
 317                        ret = -ETIMEDOUT;
 318                        DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, "
 319                                      "irq=%d, pp=%d, atomic_cnt=%d",
 320                                      DRMID(phys_enc->parent), intr_idx,
 321                                      irq->irq_idx,
 322                                      phys_enc->hw_pp->idx - PINGPONG_0,
 323                                      atomic_read(wait_info->atomic_cnt));
 324                }
 325        } else {
 326                ret = 0;
 327                trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
 328                        intr_idx, irq->irq_idx,
 329                        phys_enc->hw_pp->idx - PINGPONG_0,
 330                        atomic_read(wait_info->atomic_cnt));
 331        }
 332
 333        return ret;
 334}
 335
 336int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
 337                enum dpu_intr_idx intr_idx)
 338{
 339        struct dpu_encoder_irq *irq;
 340        int ret = 0;
 341
 342        if (intr_idx >= INTR_IDX_MAX) {
 343                DPU_ERROR("invalid params\n");
 344                return -EINVAL;
 345        }
 346        irq = &phys_enc->irq[intr_idx];
 347
 348        if (irq->irq_idx < 0) {
 349                DPU_ERROR_PHYS(phys_enc,
 350                        "invalid IRQ index:%d\n", irq->irq_idx);
 351                return -EINVAL;
 352        }
 353
 354        ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx,
 355                        &irq->cb);
 356        if (ret) {
 357                DPU_ERROR_PHYS(phys_enc,
 358                        "failed to register IRQ callback for %s\n",
 359                        irq->name);
 360                irq->irq_idx = -EINVAL;
 361                return ret;
 362        }
 363
 364        trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx,
 365                                irq->irq_idx);
 366
 367        return ret;
 368}
 369
 370int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
 371                enum dpu_intr_idx intr_idx)
 372{
 373        struct dpu_encoder_irq *irq;
 374        int ret;
 375
 376        irq = &phys_enc->irq[intr_idx];
 377
 378        /* silently skip irqs that weren't registered */
 379        if (irq->irq_idx < 0) {
 380                DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d",
 381                          DRMID(phys_enc->parent), intr_idx,
 382                          irq->irq_idx);
 383                return 0;
 384        }
 385
 386        ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx,
 387                        &irq->cb);
 388        if (ret) {
 389                DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d",
 390                          DRMID(phys_enc->parent), intr_idx,
 391                          irq->irq_idx, ret);
 392        }
 393
 394        trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx,
 395                                             irq->irq_idx);
 396
 397        return 0;
 398}
 399
 400int dpu_encoder_get_frame_count(struct drm_encoder *drm_enc)
 401{
 402        struct dpu_encoder_virt *dpu_enc;
 403        struct dpu_encoder_phys *phys;
 404        int framecount = 0;
 405
 406        dpu_enc = to_dpu_encoder_virt(drm_enc);
 407        phys = dpu_enc ? dpu_enc->cur_master : NULL;
 408
 409        if (phys && phys->ops.get_frame_count)
 410                framecount = phys->ops.get_frame_count(phys);
 411
 412        return framecount;
 413}
 414
 415int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)
 416{
 417        struct dpu_encoder_virt *dpu_enc;
 418        struct dpu_encoder_phys *phys;
 419        int linecount = 0;
 420
 421        dpu_enc = to_dpu_encoder_virt(drm_enc);
 422        phys = dpu_enc ? dpu_enc->cur_master : NULL;
 423
 424        if (phys && phys->ops.get_line_count)
 425                linecount = phys->ops.get_line_count(phys);
 426
 427        return linecount;
 428}
 429
 430void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
 431                                  struct dpu_encoder_hw_resources *hw_res)
 432{
 433        struct dpu_encoder_virt *dpu_enc = NULL;
 434        int i = 0;
 435
 436        dpu_enc = to_dpu_encoder_virt(drm_enc);
 437        DPU_DEBUG_ENC(dpu_enc, "\n");
 438
 439        /* Query resources used by phys encs, expected to be without overlap */
 440        memset(hw_res, 0, sizeof(*hw_res));
 441
 442        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 443                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 444
 445                if (phys->ops.get_hw_resources)
 446                        phys->ops.get_hw_resources(phys, hw_res);
 447        }
 448}
 449
 450static void dpu_encoder_destroy(struct drm_encoder *drm_enc)
 451{
 452        struct dpu_encoder_virt *dpu_enc = NULL;
 453        int i = 0;
 454
 455        if (!drm_enc) {
 456                DPU_ERROR("invalid encoder\n");
 457                return;
 458        }
 459
 460        dpu_enc = to_dpu_encoder_virt(drm_enc);
 461        DPU_DEBUG_ENC(dpu_enc, "\n");
 462
 463        mutex_lock(&dpu_enc->enc_lock);
 464
 465        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 466                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 467
 468                if (phys->ops.destroy) {
 469                        phys->ops.destroy(phys);
 470                        --dpu_enc->num_phys_encs;
 471                        dpu_enc->phys_encs[i] = NULL;
 472                }
 473        }
 474
 475        if (dpu_enc->num_phys_encs)
 476                DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n",
 477                                dpu_enc->num_phys_encs);
 478        dpu_enc->num_phys_encs = 0;
 479        mutex_unlock(&dpu_enc->enc_lock);
 480
 481        drm_encoder_cleanup(drm_enc);
 482        mutex_destroy(&dpu_enc->enc_lock);
 483}
 484
 485void dpu_encoder_helper_split_config(
 486                struct dpu_encoder_phys *phys_enc,
 487                enum dpu_intf interface)
 488{
 489        struct dpu_encoder_virt *dpu_enc;
 490        struct split_pipe_cfg cfg = { 0 };
 491        struct dpu_hw_mdp *hw_mdptop;
 492        struct msm_display_info *disp_info;
 493
 494        if (!phys_enc->hw_mdptop || !phys_enc->parent) {
 495                DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
 496                return;
 497        }
 498
 499        dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
 500        hw_mdptop = phys_enc->hw_mdptop;
 501        disp_info = &dpu_enc->disp_info;
 502
 503        if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
 504                return;
 505
 506        /**
 507         * disable split modes since encoder will be operating in as the only
 508         * encoder, either for the entire use case in the case of, for example,
 509         * single DSI, or for this frame in the case of left/right only partial
 510         * update.
 511         */
 512        if (phys_enc->split_role == ENC_ROLE_SOLO) {
 513                if (hw_mdptop->ops.setup_split_pipe)
 514                        hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 515                return;
 516        }
 517
 518        cfg.en = true;
 519        cfg.mode = phys_enc->intf_mode;
 520        cfg.intf = interface;
 521
 522        if (cfg.en && phys_enc->ops.needs_single_flush &&
 523                        phys_enc->ops.needs_single_flush(phys_enc))
 524                cfg.split_flush_en = true;
 525
 526        if (phys_enc->split_role == ENC_ROLE_MASTER) {
 527                DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
 528
 529                if (hw_mdptop->ops.setup_split_pipe)
 530                        hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
 531        }
 532}
 533
 534static struct msm_display_topology dpu_encoder_get_topology(
 535                        struct dpu_encoder_virt *dpu_enc,
 536                        struct dpu_kms *dpu_kms,
 537                        struct drm_display_mode *mode)
 538{
 539        struct msm_display_topology topology = {0};
 540        int i, intf_count = 0;
 541
 542        for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
 543                if (dpu_enc->phys_encs[i])
 544                        intf_count++;
 545
 546        /* Datapath topology selection
 547         *
 548         * Dual display
 549         * 2 LM, 2 INTF ( Split display using 2 interfaces)
 550         *
 551         * Single display
 552         * 1 LM, 1 INTF
 553         * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
 554         *
 555         * Adding color blocks only to primary interface if available in
 556         * sufficient number
 557         */
 558        if (intf_count == 2)
 559                topology.num_lm = 2;
 560        else if (!dpu_kms->catalog->caps->has_3d_merge)
 561                topology.num_lm = 1;
 562        else
 563                topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
 564
 565        if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
 566                if (dpu_kms->catalog->dspp &&
 567                        (dpu_kms->catalog->dspp_count >= topology.num_lm))
 568                        topology.num_dspp = topology.num_lm;
 569        }
 570
 571        topology.num_enc = 0;
 572        topology.num_intf = intf_count;
 573
 574        return topology;
 575}
 576static int dpu_encoder_virt_atomic_check(
 577                struct drm_encoder *drm_enc,
 578                struct drm_crtc_state *crtc_state,
 579                struct drm_connector_state *conn_state)
 580{
 581        struct dpu_encoder_virt *dpu_enc;
 582        struct msm_drm_private *priv;
 583        struct dpu_kms *dpu_kms;
 584        const struct drm_display_mode *mode;
 585        struct drm_display_mode *adj_mode;
 586        struct msm_display_topology topology;
 587        struct dpu_global_state *global_state;
 588        int i = 0;
 589        int ret = 0;
 590
 591        if (!drm_enc || !crtc_state || !conn_state) {
 592                DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
 593                                drm_enc != NULL, crtc_state != NULL, conn_state != NULL);
 594                return -EINVAL;
 595        }
 596
 597        dpu_enc = to_dpu_encoder_virt(drm_enc);
 598        DPU_DEBUG_ENC(dpu_enc, "\n");
 599
 600        priv = drm_enc->dev->dev_private;
 601        dpu_kms = to_dpu_kms(priv->kms);
 602        mode = &crtc_state->mode;
 603        adj_mode = &crtc_state->adjusted_mode;
 604        global_state = dpu_kms_get_global_state(crtc_state->state);
 605        if (IS_ERR(global_state))
 606                return PTR_ERR(global_state);
 607
 608        trace_dpu_enc_atomic_check(DRMID(drm_enc));
 609
 610        /* perform atomic check on the first physical encoder (master) */
 611        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 612                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 613
 614                if (phys->ops.atomic_check)
 615                        ret = phys->ops.atomic_check(phys, crtc_state,
 616                                        conn_state);
 617                else if (phys->ops.mode_fixup)
 618                        if (!phys->ops.mode_fixup(phys, mode, adj_mode))
 619                                ret = -EINVAL;
 620
 621                if (ret) {
 622                        DPU_ERROR_ENC(dpu_enc,
 623                                        "mode unsupported, phys idx %d\n", i);
 624                        break;
 625                }
 626        }
 627
 628        topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 629
 630        /* Reserve dynamic resources now. */
 631        if (!ret) {
 632                /*
 633                 * Release and Allocate resources on every modeset
 634                 * Dont allocate when active is false.
 635                 */
 636                if (drm_atomic_crtc_needs_modeset(crtc_state)) {
 637                        dpu_rm_release(global_state, drm_enc);
 638
 639                        if (!crtc_state->active_changed || crtc_state->active)
 640                                ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
 641                                                drm_enc, crtc_state, topology);
 642                }
 643        }
 644
 645        trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
 646
 647        return ret;
 648}
 649
 650static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
 651                        struct msm_display_info *disp_info)
 652{
 653        struct dpu_vsync_source_cfg vsync_cfg = { 0 };
 654        struct msm_drm_private *priv;
 655        struct dpu_kms *dpu_kms;
 656        struct dpu_hw_mdp *hw_mdptop;
 657        struct drm_encoder *drm_enc;
 658        int i;
 659
 660        if (!dpu_enc || !disp_info) {
 661                DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
 662                                        dpu_enc != NULL, disp_info != NULL);
 663                return;
 664        } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
 665                DPU_ERROR("invalid num phys enc %d/%d\n",
 666                                dpu_enc->num_phys_encs,
 667                                (int) ARRAY_SIZE(dpu_enc->hw_pp));
 668                return;
 669        }
 670
 671        drm_enc = &dpu_enc->base;
 672        /* this pointers are checked in virt_enable_helper */
 673        priv = drm_enc->dev->dev_private;
 674
 675        dpu_kms = to_dpu_kms(priv->kms);
 676        hw_mdptop = dpu_kms->hw_mdp;
 677        if (!hw_mdptop) {
 678                DPU_ERROR("invalid mdptop\n");
 679                return;
 680        }
 681
 682        if (hw_mdptop->ops.setup_vsync_source &&
 683                        disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
 684                for (i = 0; i < dpu_enc->num_phys_encs; i++)
 685                        vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
 686
 687                vsync_cfg.pp_count = dpu_enc->num_phys_encs;
 688                if (disp_info->is_te_using_watchdog_timer)
 689                        vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
 690                else
 691                        vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
 692
 693                hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
 694        }
 695}
 696
 697static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
 698{
 699        struct dpu_encoder_virt *dpu_enc;
 700        int i;
 701
 702        if (!drm_enc) {
 703                DPU_ERROR("invalid encoder\n");
 704                return;
 705        }
 706
 707        dpu_enc = to_dpu_encoder_virt(drm_enc);
 708
 709        DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable);
 710        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 711                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 712
 713                if (phys->ops.irq_control)
 714                        phys->ops.irq_control(phys, enable);
 715        }
 716
 717}
 718
 719static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc,
 720                bool enable)
 721{
 722        struct msm_drm_private *priv;
 723        struct dpu_kms *dpu_kms;
 724        struct dpu_encoder_virt *dpu_enc;
 725
 726        dpu_enc = to_dpu_encoder_virt(drm_enc);
 727        priv = drm_enc->dev->dev_private;
 728        dpu_kms = to_dpu_kms(priv->kms);
 729
 730        trace_dpu_enc_rc_helper(DRMID(drm_enc), enable);
 731
 732        if (!dpu_enc->cur_master) {
 733                DPU_ERROR("encoder master not set\n");
 734                return;
 735        }
 736
 737        if (enable) {
 738                /* enable DPU core clks */
 739                pm_runtime_get_sync(&dpu_kms->pdev->dev);
 740
 741                /* enable all the irq */
 742                _dpu_encoder_irq_control(drm_enc, true);
 743
 744        } else {
 745                /* disable all the irq */
 746                _dpu_encoder_irq_control(drm_enc, false);
 747
 748                /* disable DPU core clks */
 749                pm_runtime_put_sync(&dpu_kms->pdev->dev);
 750        }
 751
 752}
 753
 754static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
 755                u32 sw_event)
 756{
 757        struct dpu_encoder_virt *dpu_enc;
 758        struct msm_drm_private *priv;
 759        bool is_vid_mode = false;
 760
 761        if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
 762                DPU_ERROR("invalid parameters\n");
 763                return -EINVAL;
 764        }
 765        dpu_enc = to_dpu_encoder_virt(drm_enc);
 766        priv = drm_enc->dev->dev_private;
 767        is_vid_mode = dpu_enc->disp_info.capabilities &
 768                                                MSM_DISPLAY_CAP_VID_MODE;
 769
 770        /*
 771         * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
 772         * events and return early for other events (ie wb display).
 773         */
 774        if (!dpu_enc->idle_pc_supported &&
 775                        (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
 776                        sw_event != DPU_ENC_RC_EVENT_STOP &&
 777                        sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
 778                return 0;
 779
 780        trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
 781                         dpu_enc->rc_state, "begin");
 782
 783        switch (sw_event) {
 784        case DPU_ENC_RC_EVENT_KICKOFF:
 785                /* cancel delayed off work, if any */
 786                if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
 787                        DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 788                                        sw_event);
 789
 790                mutex_lock(&dpu_enc->rc_lock);
 791
 792                /* return if the resource control is already in ON state */
 793                if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 794                        DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
 795                                      DRMID(drm_enc), sw_event);
 796                        mutex_unlock(&dpu_enc->rc_lock);
 797                        return 0;
 798                } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
 799                                dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
 800                        DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
 801                                      DRMID(drm_enc), sw_event,
 802                                      dpu_enc->rc_state);
 803                        mutex_unlock(&dpu_enc->rc_lock);
 804                        return -EINVAL;
 805                }
 806
 807                if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
 808                        _dpu_encoder_irq_control(drm_enc, true);
 809                else
 810                        _dpu_encoder_resource_control_helper(drm_enc, true);
 811
 812                dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
 813
 814                trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 815                                 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 816                                 "kickoff");
 817
 818                mutex_unlock(&dpu_enc->rc_lock);
 819                break;
 820
 821        case DPU_ENC_RC_EVENT_FRAME_DONE:
 822                /*
 823                 * mutex lock is not used as this event happens at interrupt
 824                 * context. And locking is not required as, the other events
 825                 * like KICKOFF and STOP does a wait-for-idle before executing
 826                 * the resource_control
 827                 */
 828                if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 829                        DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
 830                                      DRMID(drm_enc), sw_event,
 831                                      dpu_enc->rc_state);
 832                        return -EINVAL;
 833                }
 834
 835                /*
 836                 * schedule off work item only when there are no
 837                 * frames pending
 838                 */
 839                if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
 840                        DRM_DEBUG_KMS("id:%d skip schedule work\n",
 841                                      DRMID(drm_enc));
 842                        return 0;
 843                }
 844
 845                queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
 846                                   msecs_to_jiffies(dpu_enc->idle_timeout));
 847
 848                trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 849                                 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 850                                 "frame done");
 851                break;
 852
 853        case DPU_ENC_RC_EVENT_PRE_STOP:
 854                /* cancel delayed off work, if any */
 855                if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
 856                        DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
 857                                        sw_event);
 858
 859                mutex_lock(&dpu_enc->rc_lock);
 860
 861                if (is_vid_mode &&
 862                          dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 863                        _dpu_encoder_irq_control(drm_enc, true);
 864                }
 865                /* skip if is already OFF or IDLE, resources are off already */
 866                else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
 867                                dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
 868                        DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
 869                                      DRMID(drm_enc), sw_event,
 870                                      dpu_enc->rc_state);
 871                        mutex_unlock(&dpu_enc->rc_lock);
 872                        return 0;
 873                }
 874
 875                dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
 876
 877                trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 878                                 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 879                                 "pre stop");
 880
 881                mutex_unlock(&dpu_enc->rc_lock);
 882                break;
 883
 884        case DPU_ENC_RC_EVENT_STOP:
 885                mutex_lock(&dpu_enc->rc_lock);
 886
 887                /* return if the resource control is already in OFF state */
 888                if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
 889                        DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
 890                                      DRMID(drm_enc), sw_event);
 891                        mutex_unlock(&dpu_enc->rc_lock);
 892                        return 0;
 893                } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
 894                        DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
 895                                  DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 896                        mutex_unlock(&dpu_enc->rc_lock);
 897                        return -EINVAL;
 898                }
 899
 900                /**
 901                 * expect to arrive here only if in either idle state or pre-off
 902                 * and in IDLE state the resources are already disabled
 903                 */
 904                if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
 905                        _dpu_encoder_resource_control_helper(drm_enc, false);
 906
 907                dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
 908
 909                trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 910                                 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 911                                 "stop");
 912
 913                mutex_unlock(&dpu_enc->rc_lock);
 914                break;
 915
 916        case DPU_ENC_RC_EVENT_ENTER_IDLE:
 917                mutex_lock(&dpu_enc->rc_lock);
 918
 919                if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
 920                        DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
 921                                  DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 922                        mutex_unlock(&dpu_enc->rc_lock);
 923                        return 0;
 924                }
 925
 926                /*
 927                 * if we are in ON but a frame was just kicked off,
 928                 * ignore the IDLE event, it's probably a stale timer event
 929                 */
 930                if (dpu_enc->frame_busy_mask[0]) {
 931                        DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
 932                                  DRMID(drm_enc), sw_event, dpu_enc->rc_state);
 933                        mutex_unlock(&dpu_enc->rc_lock);
 934                        return 0;
 935                }
 936
 937                if (is_vid_mode)
 938                        _dpu_encoder_irq_control(drm_enc, false);
 939                else
 940                        _dpu_encoder_resource_control_helper(drm_enc, false);
 941
 942                dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
 943
 944                trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 945                                 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 946                                 "idle");
 947
 948                mutex_unlock(&dpu_enc->rc_lock);
 949                break;
 950
 951        default:
 952                DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
 953                          sw_event);
 954                trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 955                                 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 956                                 "error");
 957                break;
 958        }
 959
 960        trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
 961                         dpu_enc->idle_pc_supported, dpu_enc->rc_state,
 962                         "end");
 963        return 0;
 964}
 965
 966static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 967                                      struct drm_display_mode *mode,
 968                                      struct drm_display_mode *adj_mode)
 969{
 970        struct dpu_encoder_virt *dpu_enc;
 971        struct msm_drm_private *priv;
 972        struct dpu_kms *dpu_kms;
 973        struct list_head *connector_list;
 974        struct drm_connector *conn = NULL, *conn_iter;
 975        struct drm_crtc *drm_crtc;
 976        struct dpu_crtc_state *cstate;
 977        struct dpu_global_state *global_state;
 978        struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
 979        struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
 980        struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
 981        struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
 982        int num_lm, num_ctl, num_pp;
 983        int i, j;
 984
 985        if (!drm_enc) {
 986                DPU_ERROR("invalid encoder\n");
 987                return;
 988        }
 989
 990        dpu_enc = to_dpu_encoder_virt(drm_enc);
 991        DPU_DEBUG_ENC(dpu_enc, "\n");
 992
 993        priv = drm_enc->dev->dev_private;
 994        dpu_kms = to_dpu_kms(priv->kms);
 995        connector_list = &dpu_kms->dev->mode_config.connector_list;
 996
 997        global_state = dpu_kms_get_existing_global_state(dpu_kms);
 998        if (IS_ERR_OR_NULL(global_state)) {
 999                DPU_ERROR("Failed to get global state");
1000                return;
1001        }
1002
1003        trace_dpu_enc_mode_set(DRMID(drm_enc));
1004
1005        if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp)
1006                msm_dp_display_mode_set(priv->dp, drm_enc, mode, adj_mode);
1007
1008        list_for_each_entry(conn_iter, connector_list, head)
1009                if (conn_iter->encoder == drm_enc)
1010                        conn = conn_iter;
1011
1012        if (!conn) {
1013                DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n");
1014                return;
1015        } else if (!conn->state) {
1016                DPU_ERROR_ENC(dpu_enc, "invalid connector state\n");
1017                return;
1018        }
1019
1020        drm_for_each_crtc(drm_crtc, drm_enc->dev)
1021                if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc))
1022                        break;
1023
1024        /* Query resource that have been reserved in atomic check step. */
1025        num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1026                drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
1027                ARRAY_SIZE(hw_pp));
1028        num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1029                drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1030        num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1031                drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
1032        dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1033                drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
1034                ARRAY_SIZE(hw_dspp));
1035
1036        for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1037                dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1038                                                : NULL;
1039
1040        cstate = to_dpu_crtc_state(drm_crtc->state);
1041
1042        for (i = 0; i < num_lm; i++) {
1043                int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
1044
1045                cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
1046                cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
1047                cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
1048        }
1049
1050        cstate->num_mixers = num_lm;
1051
1052        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1053                int num_blk;
1054                struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC];
1055                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1056
1057                if (!dpu_enc->hw_pp[i]) {
1058                        DPU_ERROR_ENC(dpu_enc,
1059                                "no pp block assigned at idx: %d\n", i);
1060                        return;
1061                }
1062
1063                if (!hw_ctl[i]) {
1064                        DPU_ERROR_ENC(dpu_enc,
1065                                "no ctl block assigned at idx: %d\n", i);
1066                        return;
1067                }
1068
1069                phys->hw_pp = dpu_enc->hw_pp[i];
1070                phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
1071
1072                num_blk = dpu_rm_get_assigned_resources(&dpu_kms->rm,
1073                        global_state, drm_enc->base.id, DPU_HW_BLK_INTF,
1074                        hw_blk, ARRAY_SIZE(hw_blk));
1075                for (j = 0; j < num_blk; j++) {
1076                        struct dpu_hw_intf *hw_intf;
1077
1078                        hw_intf = to_dpu_hw_intf(hw_blk[i]);
1079                        if (hw_intf->idx == phys->intf_idx)
1080                                phys->hw_intf = hw_intf;
1081                }
1082
1083                if (!phys->hw_intf) {
1084                        DPU_ERROR_ENC(dpu_enc,
1085                                      "no intf block assigned at idx: %d\n", i);
1086                        return;
1087                }
1088
1089                phys->connector = conn->state->connector;
1090                if (phys->ops.mode_set)
1091                        phys->ops.mode_set(phys, mode, adj_mode);
1092        }
1093}
1094
1095static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1096{
1097        struct dpu_encoder_virt *dpu_enc = NULL;
1098        int i;
1099
1100        if (!drm_enc || !drm_enc->dev) {
1101                DPU_ERROR("invalid parameters\n");
1102                return;
1103        }
1104
1105        dpu_enc = to_dpu_encoder_virt(drm_enc);
1106        if (!dpu_enc || !dpu_enc->cur_master) {
1107                DPU_ERROR("invalid dpu encoder/master\n");
1108                return;
1109        }
1110
1111
1112        if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
1113                dpu_enc->cur_master->hw_mdptop &&
1114                dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1115                dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1116                        dpu_enc->cur_master->hw_mdptop);
1117
1118        _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1119
1120        if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1121                        !WARN_ON(dpu_enc->num_phys_encs == 0)) {
1122                unsigned bpc = dpu_enc->phys_encs[0]->connector->display_info.bpc;
1123                for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1124                        if (!dpu_enc->hw_pp[i])
1125                                continue;
1126                        _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1127                }
1128        }
1129}
1130
1131void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1132{
1133        struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1134
1135        mutex_lock(&dpu_enc->enc_lock);
1136
1137        if (!dpu_enc->enabled)
1138                goto out;
1139
1140        if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1141                dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1142        if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1143                dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1144
1145        _dpu_encoder_virt_enable_helper(drm_enc);
1146
1147out:
1148        mutex_unlock(&dpu_enc->enc_lock);
1149}
1150
1151static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
1152{
1153        struct dpu_encoder_virt *dpu_enc = NULL;
1154        int ret = 0;
1155        struct msm_drm_private *priv;
1156        struct drm_display_mode *cur_mode = NULL;
1157
1158        if (!drm_enc) {
1159                DPU_ERROR("invalid encoder\n");
1160                return;
1161        }
1162        dpu_enc = to_dpu_encoder_virt(drm_enc);
1163
1164        mutex_lock(&dpu_enc->enc_lock);
1165        cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1166        priv = drm_enc->dev->dev_private;
1167
1168        trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1169                             cur_mode->vdisplay);
1170
1171        /* always enable slave encoder before master */
1172        if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1173                dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1174
1175        if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1176                dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1177
1178        ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1179        if (ret) {
1180                DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1181                                ret);
1182                goto out;
1183        }
1184
1185        _dpu_encoder_virt_enable_helper(drm_enc);
1186
1187        if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
1188                ret = msm_dp_display_enable(priv->dp,
1189                                                drm_enc);
1190                if (ret) {
1191                        DPU_ERROR_ENC(dpu_enc, "dp display enable failed: %d\n",
1192                                ret);
1193                        goto out;
1194                }
1195        }
1196        dpu_enc->enabled = true;
1197
1198out:
1199        mutex_unlock(&dpu_enc->enc_lock);
1200}
1201
1202static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
1203{
1204        struct dpu_encoder_virt *dpu_enc = NULL;
1205        struct msm_drm_private *priv;
1206        int i = 0;
1207
1208        if (!drm_enc) {
1209                DPU_ERROR("invalid encoder\n");
1210                return;
1211        } else if (!drm_enc->dev) {
1212                DPU_ERROR("invalid dev\n");
1213                return;
1214        }
1215
1216        dpu_enc = to_dpu_encoder_virt(drm_enc);
1217        DPU_DEBUG_ENC(dpu_enc, "\n");
1218
1219        mutex_lock(&dpu_enc->enc_lock);
1220        dpu_enc->enabled = false;
1221
1222        priv = drm_enc->dev->dev_private;
1223
1224        trace_dpu_enc_disable(DRMID(drm_enc));
1225
1226        /* wait for idle */
1227        dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
1228
1229        if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
1230                if (msm_dp_display_pre_disable(priv->dp, drm_enc))
1231                        DPU_ERROR_ENC(dpu_enc, "dp display push idle failed\n");
1232        }
1233
1234        dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1235
1236        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1237                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1238
1239                if (phys->ops.disable)
1240                        phys->ops.disable(phys);
1241        }
1242
1243
1244        /* after phys waits for frame-done, should be no more frames pending */
1245        if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1246                DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1247                del_timer_sync(&dpu_enc->frame_done_timer);
1248        }
1249
1250        dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1251
1252        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1253                dpu_enc->phys_encs[i]->connector = NULL;
1254        }
1255
1256        DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1257
1258        if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && priv->dp) {
1259                if (msm_dp_display_disable(priv->dp, drm_enc))
1260                        DPU_ERROR_ENC(dpu_enc, "dp display disable failed\n");
1261        }
1262
1263        mutex_unlock(&dpu_enc->enc_lock);
1264}
1265
1266static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
1267                enum dpu_intf_type type, u32 controller_id)
1268{
1269        int i = 0;
1270
1271        for (i = 0; i < catalog->intf_count; i++) {
1272                if (catalog->intf[i].type == type
1273                    && catalog->intf[i].controller_id == controller_id) {
1274                        return catalog->intf[i].id;
1275                }
1276        }
1277
1278        return INTF_MAX;
1279}
1280
1281static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1282                struct dpu_encoder_phys *phy_enc)
1283{
1284        struct dpu_encoder_virt *dpu_enc = NULL;
1285        unsigned long lock_flags;
1286
1287        if (!drm_enc || !phy_enc)
1288                return;
1289
1290        DPU_ATRACE_BEGIN("encoder_vblank_callback");
1291        dpu_enc = to_dpu_encoder_virt(drm_enc);
1292
1293        spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1294        if (dpu_enc->crtc)
1295                dpu_crtc_vblank_callback(dpu_enc->crtc);
1296        spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1297
1298        atomic_inc(&phy_enc->vsync_cnt);
1299        DPU_ATRACE_END("encoder_vblank_callback");
1300}
1301
1302static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1303                struct dpu_encoder_phys *phy_enc)
1304{
1305        if (!phy_enc)
1306                return;
1307
1308        DPU_ATRACE_BEGIN("encoder_underrun_callback");
1309        atomic_inc(&phy_enc->underrun_cnt);
1310
1311        /* trigger dump only on the first underrun */
1312        if (atomic_read(&phy_enc->underrun_cnt) == 1)
1313                msm_disp_snapshot_state(drm_enc->dev);
1314
1315        trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1316                                  atomic_read(&phy_enc->underrun_cnt));
1317        DPU_ATRACE_END("encoder_underrun_callback");
1318}
1319
1320void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1321{
1322        struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1323        unsigned long lock_flags;
1324
1325        spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1326        /* crtc should always be cleared before re-assigning */
1327        WARN_ON(crtc && dpu_enc->crtc);
1328        dpu_enc->crtc = crtc;
1329        spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1330}
1331
1332void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1333                                        struct drm_crtc *crtc, bool enable)
1334{
1335        struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1336        unsigned long lock_flags;
1337        int i;
1338
1339        trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1340
1341        spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1342        if (dpu_enc->crtc != crtc) {
1343                spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1344                return;
1345        }
1346        spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1347
1348        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1349                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1350
1351                if (phys->ops.control_vblank_irq)
1352                        phys->ops.control_vblank_irq(phys, enable);
1353        }
1354}
1355
1356void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
1357                void (*frame_event_cb)(void *, u32 event),
1358                void *frame_event_cb_data)
1359{
1360        struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1361        unsigned long lock_flags;
1362        bool enable;
1363
1364        enable = frame_event_cb ? true : false;
1365
1366        if (!drm_enc) {
1367                DPU_ERROR("invalid encoder\n");
1368                return;
1369        }
1370        trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable);
1371
1372        spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1373        dpu_enc->crtc_frame_event_cb = frame_event_cb;
1374        dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data;
1375        spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1376}
1377
1378static void dpu_encoder_frame_done_callback(
1379                struct drm_encoder *drm_enc,
1380                struct dpu_encoder_phys *ready_phys, u32 event)
1381{
1382        struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1383        unsigned int i;
1384
1385        if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1386                        | DPU_ENCODER_FRAME_EVENT_ERROR
1387                        | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1388
1389                if (!dpu_enc->frame_busy_mask[0]) {
1390                        /**
1391                         * suppress frame_done without waiter,
1392                         * likely autorefresh
1393                         */
1394                        trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
1395                                        event, ready_phys->intf_idx);
1396                        return;
1397                }
1398
1399                /* One of the physical encoders has become idle */
1400                for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1401                        if (dpu_enc->phys_encs[i] == ready_phys) {
1402                                trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1403                                                dpu_enc->frame_busy_mask[0]);
1404                                clear_bit(i, dpu_enc->frame_busy_mask);
1405                        }
1406                }
1407
1408                if (!dpu_enc->frame_busy_mask[0]) {
1409                        atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1410                        del_timer(&dpu_enc->frame_done_timer);
1411
1412                        dpu_encoder_resource_control(drm_enc,
1413                                        DPU_ENC_RC_EVENT_FRAME_DONE);
1414
1415                        if (dpu_enc->crtc_frame_event_cb)
1416                                dpu_enc->crtc_frame_event_cb(
1417                                        dpu_enc->crtc_frame_event_cb_data,
1418                                        event);
1419                }
1420        } else {
1421                if (dpu_enc->crtc_frame_event_cb)
1422                        dpu_enc->crtc_frame_event_cb(
1423                                dpu_enc->crtc_frame_event_cb_data, event);
1424        }
1425}
1426
1427static void dpu_encoder_off_work(struct work_struct *work)
1428{
1429        struct dpu_encoder_virt *dpu_enc = container_of(work,
1430                        struct dpu_encoder_virt, delayed_off_work.work);
1431
1432        dpu_encoder_resource_control(&dpu_enc->base,
1433                                                DPU_ENC_RC_EVENT_ENTER_IDLE);
1434
1435        dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1436                                DPU_ENCODER_FRAME_EVENT_IDLE);
1437}
1438
1439/**
1440 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1441 * @drm_enc: Pointer to drm encoder structure
1442 * @phys: Pointer to physical encoder structure
1443 * @extra_flush_bits: Additional bit mask to include in flush trigger
1444 */
1445static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1446                struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1447{
1448        struct dpu_hw_ctl *ctl;
1449        int pending_kickoff_cnt;
1450        u32 ret = UINT_MAX;
1451
1452        if (!phys->hw_pp) {
1453                DPU_ERROR("invalid pingpong hw\n");
1454                return;
1455        }
1456
1457        ctl = phys->hw_ctl;
1458        if (!ctl->ops.trigger_flush) {
1459                DPU_ERROR("missing trigger cb\n");
1460                return;
1461        }
1462
1463        pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1464
1465        if (extra_flush_bits && ctl->ops.update_pending_flush)
1466                ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1467
1468        ctl->ops.trigger_flush(ctl);
1469
1470        if (ctl->ops.get_pending_flush)
1471                ret = ctl->ops.get_pending_flush(ctl);
1472
1473        trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
1474                                    pending_kickoff_cnt, ctl->idx,
1475                                    extra_flush_bits, ret);
1476}
1477
1478/**
1479 * _dpu_encoder_trigger_start - trigger start for a physical encoder
1480 * @phys: Pointer to physical encoder structure
1481 */
1482static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1483{
1484        if (!phys) {
1485                DPU_ERROR("invalid argument(s)\n");
1486                return;
1487        }
1488
1489        if (!phys->hw_pp) {
1490                DPU_ERROR("invalid pingpong hw\n");
1491                return;
1492        }
1493
1494        if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1495                phys->ops.trigger_start(phys);
1496}
1497
1498void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1499{
1500        struct dpu_hw_ctl *ctl;
1501
1502        ctl = phys_enc->hw_ctl;
1503        if (ctl->ops.trigger_start) {
1504                ctl->ops.trigger_start(ctl);
1505                trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1506        }
1507}
1508
1509static int dpu_encoder_helper_wait_event_timeout(
1510                int32_t drm_id,
1511                u32 irq_idx,
1512                struct dpu_encoder_wait_info *info)
1513{
1514        int rc = 0;
1515        s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1516        s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1517        s64 time;
1518
1519        do {
1520                rc = wait_event_timeout(*(info->wq),
1521                                atomic_read(info->atomic_cnt) == 0, jiffies);
1522                time = ktime_to_ms(ktime_get());
1523
1524                trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time,
1525                                                 expected_time,
1526                                                 atomic_read(info->atomic_cnt));
1527        /* If we timed out, counter is valid and time is less, wait again */
1528        } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1529                        (time < expected_time));
1530
1531        return rc;
1532}
1533
1534static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1535{
1536        struct dpu_encoder_virt *dpu_enc;
1537        struct dpu_hw_ctl *ctl;
1538        int rc;
1539        struct drm_encoder *drm_enc;
1540
1541        dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1542        ctl = phys_enc->hw_ctl;
1543        drm_enc = phys_enc->parent;
1544
1545        if (!ctl->ops.reset)
1546                return;
1547
1548        DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1549                      ctl->idx);
1550
1551        rc = ctl->ops.reset(ctl);
1552        if (rc) {
1553                DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n",  ctl->idx);
1554                msm_disp_snapshot_state(drm_enc->dev);
1555        }
1556
1557        phys_enc->enable_state = DPU_ENC_ENABLED;
1558}
1559
1560/**
1561 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1562 *      Iterate through the physical encoders and perform consolidated flush
1563 *      and/or control start triggering as needed. This is done in the virtual
1564 *      encoder rather than the individual physical ones in order to handle
1565 *      use cases that require visibility into multiple physical encoders at
1566 *      a time.
1567 * @dpu_enc: Pointer to virtual encoder structure
1568 */
1569static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1570{
1571        struct dpu_hw_ctl *ctl;
1572        uint32_t i, pending_flush;
1573        unsigned long lock_flags;
1574
1575        pending_flush = 0x0;
1576
1577        /* update pending counts and trigger kickoff ctl flush atomically */
1578        spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1579
1580        /* don't perform flush/start operations for slave encoders */
1581        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1582                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1583
1584                if (phys->enable_state == DPU_ENC_DISABLED)
1585                        continue;
1586
1587                ctl = phys->hw_ctl;
1588
1589                /*
1590                 * This is cleared in frame_done worker, which isn't invoked
1591                 * for async commits. So don't set this for async, since it'll
1592                 * roll over to the next commit.
1593                 */
1594                if (phys->split_role != ENC_ROLE_SLAVE)
1595                        set_bit(i, dpu_enc->frame_busy_mask);
1596
1597                if (!phys->ops.needs_single_flush ||
1598                                !phys->ops.needs_single_flush(phys))
1599                        _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1600                else if (ctl->ops.get_pending_flush)
1601                        pending_flush |= ctl->ops.get_pending_flush(ctl);
1602        }
1603
1604        /* for split flush, combine pending flush masks and send to master */
1605        if (pending_flush && dpu_enc->cur_master) {
1606                _dpu_encoder_trigger_flush(
1607                                &dpu_enc->base,
1608                                dpu_enc->cur_master,
1609                                pending_flush);
1610        }
1611
1612        _dpu_encoder_trigger_start(dpu_enc->cur_master);
1613
1614        spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1615}
1616
1617void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1618{
1619        struct dpu_encoder_virt *dpu_enc;
1620        struct dpu_encoder_phys *phys;
1621        unsigned int i;
1622        struct dpu_hw_ctl *ctl;
1623        struct msm_display_info *disp_info;
1624
1625        if (!drm_enc) {
1626                DPU_ERROR("invalid encoder\n");
1627                return;
1628        }
1629        dpu_enc = to_dpu_encoder_virt(drm_enc);
1630        disp_info = &dpu_enc->disp_info;
1631
1632        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1633                phys = dpu_enc->phys_encs[i];
1634
1635                ctl = phys->hw_ctl;
1636                if (ctl->ops.clear_pending_flush)
1637                        ctl->ops.clear_pending_flush(ctl);
1638
1639                /* update only for command mode primary ctl */
1640                if ((phys == dpu_enc->cur_master) &&
1641                   (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE)
1642                    && ctl->ops.trigger_pending)
1643                        ctl->ops.trigger_pending(ctl);
1644        }
1645}
1646
1647static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1648                struct drm_display_mode *mode)
1649{
1650        u64 pclk_rate;
1651        u32 pclk_period;
1652        u32 line_time;
1653
1654        /*
1655         * For linetime calculation, only operate on master encoder.
1656         */
1657        if (!dpu_enc->cur_master)
1658                return 0;
1659
1660        if (!dpu_enc->cur_master->ops.get_line_count) {
1661                DPU_ERROR("get_line_count function not defined\n");
1662                return 0;
1663        }
1664
1665        pclk_rate = mode->clock; /* pixel clock in kHz */
1666        if (pclk_rate == 0) {
1667                DPU_ERROR("pclk is 0, cannot calculate line time\n");
1668                return 0;
1669        }
1670
1671        pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1672        if (pclk_period == 0) {
1673                DPU_ERROR("pclk period is 0\n");
1674                return 0;
1675        }
1676
1677        /*
1678         * Line time calculation based on Pixel clock and HTOTAL.
1679         * Final unit is in ns.
1680         */
1681        line_time = (pclk_period * mode->htotal) / 1000;
1682        if (line_time == 0) {
1683                DPU_ERROR("line time calculation is 0\n");
1684                return 0;
1685        }
1686
1687        DPU_DEBUG_ENC(dpu_enc,
1688                        "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1689                        pclk_rate, pclk_period, line_time);
1690
1691        return line_time;
1692}
1693
1694int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1695{
1696        struct drm_display_mode *mode;
1697        struct dpu_encoder_virt *dpu_enc;
1698        u32 cur_line;
1699        u32 line_time;
1700        u32 vtotal, time_to_vsync;
1701        ktime_t cur_time;
1702
1703        dpu_enc = to_dpu_encoder_virt(drm_enc);
1704
1705        if (!drm_enc->crtc || !drm_enc->crtc->state) {
1706                DPU_ERROR("crtc/crtc state object is NULL\n");
1707                return -EINVAL;
1708        }
1709        mode = &drm_enc->crtc->state->adjusted_mode;
1710
1711        line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1712        if (!line_time)
1713                return -EINVAL;
1714
1715        cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1716
1717        vtotal = mode->vtotal;
1718        if (cur_line >= vtotal)
1719                time_to_vsync = line_time * vtotal;
1720        else
1721                time_to_vsync = line_time * (vtotal - cur_line);
1722
1723        if (time_to_vsync == 0) {
1724                DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1725                                vtotal);
1726                return -EINVAL;
1727        }
1728
1729        cur_time = ktime_get();
1730        *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1731
1732        DPU_DEBUG_ENC(dpu_enc,
1733                        "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1734                        cur_line, vtotal, time_to_vsync,
1735                        ktime_to_ms(cur_time),
1736                        ktime_to_ms(*wakeup_time));
1737        return 0;
1738}
1739
1740static void dpu_encoder_vsync_event_handler(struct timer_list *t)
1741{
1742        struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
1743                        vsync_event_timer);
1744        struct drm_encoder *drm_enc = &dpu_enc->base;
1745        struct msm_drm_private *priv;
1746        struct msm_drm_thread *event_thread;
1747
1748        if (!drm_enc->dev || !drm_enc->crtc) {
1749                DPU_ERROR("invalid parameters\n");
1750                return;
1751        }
1752
1753        priv = drm_enc->dev->dev_private;
1754
1755        if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
1756                DPU_ERROR("invalid crtc index\n");
1757                return;
1758        }
1759        event_thread = &priv->event_thread[drm_enc->crtc->index];
1760        if (!event_thread) {
1761                DPU_ERROR("event_thread not found for crtc:%d\n",
1762                                drm_enc->crtc->index);
1763                return;
1764        }
1765
1766        del_timer(&dpu_enc->vsync_event_timer);
1767}
1768
1769static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
1770{
1771        struct dpu_encoder_virt *dpu_enc = container_of(work,
1772                        struct dpu_encoder_virt, vsync_event_work);
1773        ktime_t wakeup_time;
1774
1775        if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time))
1776                return;
1777
1778        trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time);
1779        mod_timer(&dpu_enc->vsync_event_timer,
1780                        nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1781}
1782
1783void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1784{
1785        struct dpu_encoder_virt *dpu_enc;
1786        struct dpu_encoder_phys *phys;
1787        bool needs_hw_reset = false;
1788        unsigned int i;
1789
1790        dpu_enc = to_dpu_encoder_virt(drm_enc);
1791
1792        trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1793
1794        /* prepare for next kickoff, may include waiting on previous kickoff */
1795        DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1796        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1797                phys = dpu_enc->phys_encs[i];
1798                if (phys->ops.prepare_for_kickoff)
1799                        phys->ops.prepare_for_kickoff(phys);
1800                if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1801                        needs_hw_reset = true;
1802        }
1803        DPU_ATRACE_END("enc_prepare_for_kickoff");
1804
1805        dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1806
1807        /* if any phys needs reset, reset all phys, in-order */
1808        if (needs_hw_reset) {
1809                trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1810                for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1811                        dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1812                }
1813        }
1814}
1815
1816void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
1817{
1818        struct dpu_encoder_virt *dpu_enc;
1819        struct dpu_encoder_phys *phys;
1820        ktime_t wakeup_time;
1821        unsigned long timeout_ms;
1822        unsigned int i;
1823
1824        DPU_ATRACE_BEGIN("encoder_kickoff");
1825        dpu_enc = to_dpu_encoder_virt(drm_enc);
1826
1827        trace_dpu_enc_kickoff(DRMID(drm_enc));
1828
1829        timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
1830                        drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
1831
1832        atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
1833        mod_timer(&dpu_enc->frame_done_timer,
1834                        jiffies + msecs_to_jiffies(timeout_ms));
1835
1836        /* All phys encs are ready to go, trigger the kickoff */
1837        _dpu_encoder_kickoff_phys(dpu_enc);
1838
1839        /* allow phys encs to handle any post-kickoff business */
1840        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1841                phys = dpu_enc->phys_encs[i];
1842                if (phys->ops.handle_post_kickoff)
1843                        phys->ops.handle_post_kickoff(phys);
1844        }
1845
1846        if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
1847                        !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) {
1848                trace_dpu_enc_early_kickoff(DRMID(drm_enc),
1849                                            ktime_to_ms(wakeup_time));
1850                mod_timer(&dpu_enc->vsync_event_timer,
1851                                nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
1852        }
1853
1854        DPU_ATRACE_END("encoder_kickoff");
1855}
1856
1857void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
1858{
1859        struct dpu_encoder_virt *dpu_enc;
1860        struct dpu_encoder_phys *phys;
1861        int i;
1862
1863        if (!drm_enc) {
1864                DPU_ERROR("invalid encoder\n");
1865                return;
1866        }
1867        dpu_enc = to_dpu_encoder_virt(drm_enc);
1868
1869        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1870                phys = dpu_enc->phys_encs[i];
1871                if (phys->ops.prepare_commit)
1872                        phys->ops.prepare_commit(phys);
1873        }
1874}
1875
1876#ifdef CONFIG_DEBUG_FS
1877static int _dpu_encoder_status_show(struct seq_file *s, void *data)
1878{
1879        struct dpu_encoder_virt *dpu_enc = s->private;
1880        int i;
1881
1882        mutex_lock(&dpu_enc->enc_lock);
1883        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1884                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1885
1886                seq_printf(s, "intf:%d    vsync:%8d     underrun:%8d    ",
1887                                phys->intf_idx - INTF_0,
1888                                atomic_read(&phys->vsync_cnt),
1889                                atomic_read(&phys->underrun_cnt));
1890
1891                switch (phys->intf_mode) {
1892                case INTF_MODE_VIDEO:
1893                        seq_puts(s, "mode: video\n");
1894                        break;
1895                case INTF_MODE_CMD:
1896                        seq_puts(s, "mode: command\n");
1897                        break;
1898                default:
1899                        seq_puts(s, "mode: ???\n");
1900                        break;
1901                }
1902        }
1903        mutex_unlock(&dpu_enc->enc_lock);
1904
1905        return 0;
1906}
1907
1908DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
1909
1910static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1911{
1912        struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1913        int i;
1914
1915        char name[DPU_NAME_SIZE];
1916
1917        if (!drm_enc->dev) {
1918                DPU_ERROR("invalid encoder or kms\n");
1919                return -EINVAL;
1920        }
1921
1922        snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id);
1923
1924        /* create overall sub-directory for the encoder */
1925        dpu_enc->debugfs_root = debugfs_create_dir(name,
1926                        drm_enc->dev->primary->debugfs_root);
1927
1928        /* don't error check these */
1929        debugfs_create_file("status", 0600,
1930                dpu_enc->debugfs_root, dpu_enc, &_dpu_encoder_status_fops);
1931
1932        for (i = 0; i < dpu_enc->num_phys_encs; i++)
1933                if (dpu_enc->phys_encs[i]->ops.late_register)
1934                        dpu_enc->phys_encs[i]->ops.late_register(
1935                                        dpu_enc->phys_encs[i],
1936                                        dpu_enc->debugfs_root);
1937
1938        return 0;
1939}
1940#else
1941static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
1942{
1943        return 0;
1944}
1945#endif
1946
1947static int dpu_encoder_late_register(struct drm_encoder *encoder)
1948{
1949        return _dpu_encoder_init_debugfs(encoder);
1950}
1951
1952static void dpu_encoder_early_unregister(struct drm_encoder *encoder)
1953{
1954        struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
1955
1956        debugfs_remove_recursive(dpu_enc->debugfs_root);
1957}
1958
1959static int dpu_encoder_virt_add_phys_encs(
1960                u32 display_caps,
1961                struct dpu_encoder_virt *dpu_enc,
1962                struct dpu_enc_phys_init_params *params)
1963{
1964        struct dpu_encoder_phys *enc = NULL;
1965
1966        DPU_DEBUG_ENC(dpu_enc, "\n");
1967
1968        /*
1969         * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
1970         * in this function, check up-front.
1971         */
1972        if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
1973                        ARRAY_SIZE(dpu_enc->phys_encs)) {
1974                DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
1975                          dpu_enc->num_phys_encs);
1976                return -EINVAL;
1977        }
1978
1979        if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
1980                enc = dpu_encoder_phys_vid_init(params);
1981
1982                if (IS_ERR_OR_NULL(enc)) {
1983                        DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
1984                                PTR_ERR(enc));
1985                        return enc == NULL ? -EINVAL : PTR_ERR(enc);
1986                }
1987
1988                dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
1989                ++dpu_enc->num_phys_encs;
1990        }
1991
1992        if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
1993                enc = dpu_encoder_phys_cmd_init(params);
1994
1995                if (IS_ERR_OR_NULL(enc)) {
1996                        DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
1997                                PTR_ERR(enc));
1998                        return enc == NULL ? -EINVAL : PTR_ERR(enc);
1999                }
2000
2001                dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2002                ++dpu_enc->num_phys_encs;
2003        }
2004
2005        if (params->split_role == ENC_ROLE_SLAVE)
2006                dpu_enc->cur_slave = enc;
2007        else
2008                dpu_enc->cur_master = enc;
2009
2010        return 0;
2011}
2012
2013static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = {
2014        .handle_vblank_virt = dpu_encoder_vblank_callback,
2015        .handle_underrun_virt = dpu_encoder_underrun_callback,
2016        .handle_frame_done = dpu_encoder_frame_done_callback,
2017};
2018
2019static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2020                                 struct dpu_kms *dpu_kms,
2021                                 struct msm_display_info *disp_info)
2022{
2023        int ret = 0;
2024        int i = 0;
2025        enum dpu_intf_type intf_type = INTF_NONE;
2026        struct dpu_enc_phys_init_params phys_params;
2027
2028        if (!dpu_enc) {
2029                DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2030                return -EINVAL;
2031        }
2032
2033        dpu_enc->cur_master = NULL;
2034
2035        memset(&phys_params, 0, sizeof(phys_params));
2036        phys_params.dpu_kms = dpu_kms;
2037        phys_params.parent = &dpu_enc->base;
2038        phys_params.parent_ops = &dpu_encoder_parent_ops;
2039        phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2040
2041        switch (disp_info->intf_type) {
2042        case DRM_MODE_ENCODER_DSI:
2043                intf_type = INTF_DSI;
2044                break;
2045        case DRM_MODE_ENCODER_TMDS:
2046                intf_type = INTF_DP;
2047                break;
2048        }
2049
2050        WARN_ON(disp_info->num_of_h_tiles < 1);
2051
2052        DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2053
2054        if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
2055            (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
2056                dpu_enc->idle_pc_supported =
2057                                dpu_kms->catalog->caps->has_idle_pc;
2058
2059        mutex_lock(&dpu_enc->enc_lock);
2060        for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2061                /*
2062                 * Left-most tile is at index 0, content is controller id
2063                 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2064                 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2065                 */
2066                u32 controller_id = disp_info->h_tile_instance[i];
2067
2068                if (disp_info->num_of_h_tiles > 1) {
2069                        if (i == 0)
2070                                phys_params.split_role = ENC_ROLE_MASTER;
2071                        else
2072                                phys_params.split_role = ENC_ROLE_SLAVE;
2073                } else {
2074                        phys_params.split_role = ENC_ROLE_SOLO;
2075                }
2076
2077                DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2078                                i, controller_id, phys_params.split_role);
2079
2080                phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
2081                                                                                                        intf_type,
2082                                                                                                        controller_id);
2083                if (phys_params.intf_idx == INTF_MAX) {
2084                        DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n",
2085                                                  intf_type, controller_id);
2086                        ret = -EINVAL;
2087                }
2088
2089                if (!ret) {
2090                        ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities,
2091                                                                                                 dpu_enc,
2092                                                                                                 &phys_params);
2093                        if (ret)
2094                                DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2095                }
2096        }
2097
2098        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2099                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2100                atomic_set(&phys->vsync_cnt, 0);
2101                atomic_set(&phys->underrun_cnt, 0);
2102        }
2103        mutex_unlock(&dpu_enc->enc_lock);
2104
2105        return ret;
2106}
2107
2108static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2109{
2110        struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2111                        frame_done_timer);
2112        struct drm_encoder *drm_enc = &dpu_enc->base;
2113        u32 event;
2114
2115        if (!drm_enc->dev) {
2116                DPU_ERROR("invalid parameters\n");
2117                return;
2118        }
2119
2120        if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) {
2121                DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2122                              DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2123                return;
2124        } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2125                DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2126                return;
2127        }
2128
2129        DPU_ERROR_ENC(dpu_enc, "frame done timeout\n");
2130
2131        event = DPU_ENCODER_FRAME_EVENT_ERROR;
2132        trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2133        dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event);
2134}
2135
2136static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2137        .mode_set = dpu_encoder_virt_mode_set,
2138        .disable = dpu_encoder_virt_disable,
2139        .enable = dpu_kms_encoder_enable,
2140        .atomic_check = dpu_encoder_virt_atomic_check,
2141
2142        /* This is called by dpu_kms_encoder_enable */
2143        .commit = dpu_encoder_virt_enable,
2144};
2145
2146static const struct drm_encoder_funcs dpu_encoder_funcs = {
2147                .destroy = dpu_encoder_destroy,
2148                .late_register = dpu_encoder_late_register,
2149                .early_unregister = dpu_encoder_early_unregister,
2150};
2151
2152int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
2153                struct msm_display_info *disp_info)
2154{
2155        struct msm_drm_private *priv = dev->dev_private;
2156        struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2157        struct drm_encoder *drm_enc = NULL;
2158        struct dpu_encoder_virt *dpu_enc = NULL;
2159        int ret = 0;
2160
2161        dpu_enc = to_dpu_encoder_virt(enc);
2162
2163        ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2164        if (ret)
2165                goto fail;
2166
2167        atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2168        timer_setup(&dpu_enc->frame_done_timer,
2169                        dpu_encoder_frame_done_timeout, 0);
2170
2171        if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
2172                timer_setup(&dpu_enc->vsync_event_timer,
2173                                dpu_encoder_vsync_event_handler,
2174                                0);
2175
2176
2177        INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2178                        dpu_encoder_off_work);
2179        dpu_enc->idle_timeout = IDLE_TIMEOUT;
2180
2181        kthread_init_work(&dpu_enc->vsync_event_work,
2182                        dpu_encoder_vsync_event_work_handler);
2183
2184        memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2185
2186        DPU_DEBUG_ENC(dpu_enc, "created\n");
2187
2188        return ret;
2189
2190fail:
2191        DPU_ERROR("failed to create encoder\n");
2192        if (drm_enc)
2193                dpu_encoder_destroy(drm_enc);
2194
2195        return ret;
2196
2197
2198}
2199
2200struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2201                int drm_enc_mode)
2202{
2203        struct dpu_encoder_virt *dpu_enc = NULL;
2204        int rc = 0;
2205
2206        dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL);
2207        if (!dpu_enc)
2208                return ERR_PTR(-ENOMEM);
2209
2210        rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs,
2211                        drm_enc_mode, NULL);
2212        if (rc) {
2213                devm_kfree(dev->dev, dpu_enc);
2214                return ERR_PTR(rc);
2215        }
2216
2217        drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2218
2219        spin_lock_init(&dpu_enc->enc_spinlock);
2220        dpu_enc->enabled = false;
2221        mutex_init(&dpu_enc->enc_lock);
2222        mutex_init(&dpu_enc->rc_lock);
2223
2224        return &dpu_enc->base;
2225}
2226
2227int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc,
2228        enum msm_event_wait event)
2229{
2230        int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL;
2231        struct dpu_encoder_virt *dpu_enc = NULL;
2232        int i, ret = 0;
2233
2234        if (!drm_enc) {
2235                DPU_ERROR("invalid encoder\n");
2236                return -EINVAL;
2237        }
2238        dpu_enc = to_dpu_encoder_virt(drm_enc);
2239        DPU_DEBUG_ENC(dpu_enc, "\n");
2240
2241        for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2242                struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2243
2244                switch (event) {
2245                case MSM_ENC_COMMIT_DONE:
2246                        fn_wait = phys->ops.wait_for_commit_done;
2247                        break;
2248                case MSM_ENC_TX_COMPLETE:
2249                        fn_wait = phys->ops.wait_for_tx_complete;
2250                        break;
2251                case MSM_ENC_VBLANK:
2252                        fn_wait = phys->ops.wait_for_vblank;
2253                        break;
2254                default:
2255                        DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
2256                                        event);
2257                        return -EINVAL;
2258                }
2259
2260                if (fn_wait) {
2261                        DPU_ATRACE_BEGIN("wait_for_completion_event");
2262                        ret = fn_wait(phys);
2263                        DPU_ATRACE_END("wait_for_completion_event");
2264                        if (ret)
2265                                return ret;
2266                }
2267        }
2268
2269        return ret;
2270}
2271
2272enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2273{
2274        struct dpu_encoder_virt *dpu_enc = NULL;
2275
2276        if (!encoder) {
2277                DPU_ERROR("invalid encoder\n");
2278                return INTF_MODE_NONE;
2279        }
2280        dpu_enc = to_dpu_encoder_virt(encoder);
2281
2282        if (dpu_enc->cur_master)
2283                return dpu_enc->cur_master->intf_mode;
2284
2285        if (dpu_enc->num_phys_encs)
2286                return dpu_enc->phys_encs[0]->intf_mode;
2287
2288        return INTF_MODE_NONE;
2289}
2290
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