linux/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
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   1/*
   2 * Copyright 2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#define SWSMU_CODE_LAYER_L2
  25
  26#include <linux/firmware.h>
  27#include <linux/pci.h>
  28#include <linux/i2c.h>
  29#include "amdgpu.h"
  30#include "amdgpu_smu.h"
  31#include "atomfirmware.h"
  32#include "amdgpu_atomfirmware.h"
  33#include "amdgpu_atombios.h"
  34#include "smu_v11_0.h"
  35#include "smu11_driver_if_sienna_cichlid.h"
  36#include "soc15_common.h"
  37#include "atom.h"
  38#include "sienna_cichlid_ppt.h"
  39#include "smu_v11_0_7_pptable.h"
  40#include "smu_v11_0_7_ppsmc.h"
  41#include "nbio/nbio_2_3_offset.h"
  42#include "nbio/nbio_2_3_sh_mask.h"
  43#include "thm/thm_11_0_2_offset.h"
  44#include "thm/thm_11_0_2_sh_mask.h"
  45#include "mp/mp_11_0_offset.h"
  46#include "mp/mp_11_0_sh_mask.h"
  47
  48#include "asic_reg/mp/mp_11_0_sh_mask.h"
  49#include "smu_cmn.h"
  50
  51/*
  52 * DO NOT use these for err/warn/info/debug messages.
  53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54 * They are more MGPU friendly.
  55 */
  56#undef pr_err
  57#undef pr_warn
  58#undef pr_info
  59#undef pr_debug
  60
  61#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  62
  63#define FEATURE_MASK(feature) (1ULL << feature)
  64#define SMC_DPM_FEATURE ( \
  65        FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66        FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67        FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68        FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69        FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70        FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71        FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72        FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76#define GET_PPTABLE_MEMBER(field, member) do {\
  77        if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
  78                (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
  79        else\
  80                (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
  81} while(0)
  82
  83static int get_table_size(struct smu_context *smu)
  84{
  85        if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
  86                return sizeof(PPTable_beige_goby_t);
  87        else
  88                return sizeof(PPTable_t);
  89}
  90
  91static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  92        MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  93        MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  94        MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  95        MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  96        MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  97        MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  98        MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  99        MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
 100        MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
 101        MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
 102        MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
 103        MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
 104        MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
 105        MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
 106        MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
 107        MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
 108        MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
 109        MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
 110        MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
 111        MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
 112        MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
 113        MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
 114        MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 115        MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 116        MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 117        MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 118        MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 119        MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 120        MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 121        MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 122        MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 123        MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 124        MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 125        MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 126        MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 127        MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 128        MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 129        MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 130        MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 131        MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 132        MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 133        MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 134        MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 135        MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 136        MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 137        MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 138        MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 139        MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 140        MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 141        MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 142        MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 143        MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 144        MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 145        MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 146        MSG_MAP(DisallowGpo,                    PPSMC_MSG_DisallowGpo,                 0),
 147        MSG_MAP(Enable2ndUSB20Port,             PPSMC_MSG_Enable2ndUSB20Port,          0),
 148};
 149
 150static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 151        CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 152        CLK_MAP(SCLK,           PPCLK_GFXCLK),
 153        CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 154        CLK_MAP(FCLK,           PPCLK_FCLK),
 155        CLK_MAP(UCLK,           PPCLK_UCLK),
 156        CLK_MAP(MCLK,           PPCLK_UCLK),
 157        CLK_MAP(DCLK,           PPCLK_DCLK_0),
 158        CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 159        CLK_MAP(VCLK,           PPCLK_VCLK_0),
 160        CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 161        CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 162        CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 163        CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 164        CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 165};
 166
 167static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 168        FEA_MAP(DPM_PREFETCHER),
 169        FEA_MAP(DPM_GFXCLK),
 170        FEA_MAP(DPM_GFX_GPO),
 171        FEA_MAP(DPM_UCLK),
 172        FEA_MAP(DPM_FCLK),
 173        FEA_MAP(DPM_SOCCLK),
 174        FEA_MAP(DPM_MP0CLK),
 175        FEA_MAP(DPM_LINK),
 176        FEA_MAP(DPM_DCEFCLK),
 177        FEA_MAP(DPM_XGMI),
 178        FEA_MAP(MEM_VDDCI_SCALING),
 179        FEA_MAP(MEM_MVDD_SCALING),
 180        FEA_MAP(DS_GFXCLK),
 181        FEA_MAP(DS_SOCCLK),
 182        FEA_MAP(DS_FCLK),
 183        FEA_MAP(DS_LCLK),
 184        FEA_MAP(DS_DCEFCLK),
 185        FEA_MAP(DS_UCLK),
 186        FEA_MAP(GFX_ULV),
 187        FEA_MAP(FW_DSTATE),
 188        FEA_MAP(GFXOFF),
 189        FEA_MAP(BACO),
 190        FEA_MAP(MM_DPM_PG),
 191        FEA_MAP(RSMU_SMN_CG),
 192        FEA_MAP(PPT),
 193        FEA_MAP(TDC),
 194        FEA_MAP(APCC_PLUS),
 195        FEA_MAP(GTHR),
 196        FEA_MAP(ACDC),
 197        FEA_MAP(VR0HOT),
 198        FEA_MAP(VR1HOT),
 199        FEA_MAP(FW_CTF),
 200        FEA_MAP(FAN_CONTROL),
 201        FEA_MAP(THERMAL),
 202        FEA_MAP(GFX_DCS),
 203        FEA_MAP(RM),
 204        FEA_MAP(LED_DISPLAY),
 205        FEA_MAP(GFX_SS),
 206        FEA_MAP(OUT_OF_BAND_MONITOR),
 207        FEA_MAP(TEMP_DEPENDENT_VMIN),
 208        FEA_MAP(MMHUB_PG),
 209        FEA_MAP(ATHUB_PG),
 210        FEA_MAP(APCC_DFLL),
 211};
 212
 213static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 214        TAB_MAP(PPTABLE),
 215        TAB_MAP(WATERMARKS),
 216        TAB_MAP(AVFS_PSM_DEBUG),
 217        TAB_MAP(AVFS_FUSE_OVERRIDE),
 218        TAB_MAP(PMSTATUSLOG),
 219        TAB_MAP(SMU_METRICS),
 220        TAB_MAP(DRIVER_SMU_CONFIG),
 221        TAB_MAP(ACTIVITY_MONITOR_COEFF),
 222        TAB_MAP(OVERDRIVE),
 223        TAB_MAP(I2C_COMMANDS),
 224        TAB_MAP(PACE),
 225};
 226
 227static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 228        PWR_MAP(AC),
 229        PWR_MAP(DC),
 230};
 231
 232static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 233        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 234        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 235        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 236        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 237        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 238        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 239        WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 240};
 241
 242static const uint8_t sienna_cichlid_throttler_map[] = {
 243        [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 244        [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 245        [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 246        [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 247        [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 248        [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 249        [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 250        [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 251        [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 252        [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 253        [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 254        [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 255        [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 256        [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 257        [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 258        [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 259        [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 260        [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 261};
 262
 263static int
 264sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 265                                  uint32_t *feature_mask, uint32_t num)
 266{
 267        struct amdgpu_device *adev = smu->adev;
 268
 269        if (num > 2)
 270                return -EINVAL;
 271
 272        memset(feature_mask, 0, sizeof(uint32_t) * num);
 273
 274        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 275                                | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 276                                | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 277                                | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 278                                | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 279                                | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 280                                | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 281                                | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 282                                | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 283                                | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 284                                | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 285                                | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 286                                | FEATURE_MASK(FEATURE_PPT_BIT)
 287                                | FEATURE_MASK(FEATURE_TDC_BIT)
 288                                | FEATURE_MASK(FEATURE_BACO_BIT)
 289                                | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 290                                | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 291                                | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 292                                | FEATURE_MASK(FEATURE_THERMAL_BIT)
 293                                | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 294
 295        if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 296                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 297                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 298        }
 299
 300        if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
 301            (adev->asic_type > CHIP_SIENNA_CICHLID) &&
 302            !(adev->flags & AMD_IS_APU))
 303                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
 304
 305        if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 306                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 307                                        | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 308                                        | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 309
 310        if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 311                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 312
 313        if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 314                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 315
 316        if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 317                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 318
 319        if (adev->pm.pp_feature & PP_ULV_MASK)
 320                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 321
 322        if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 323                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 324
 325        if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 326                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 327
 328        if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 329                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 330
 331        if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 332                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 333
 334        if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 335            smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 336                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 337
 338        if (smu->dc_controlled_by_gpio)
 339       *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 340
 341        if (amdgpu_aspm)
 342                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 343
 344        return 0;
 345}
 346
 347static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
 348{
 349        struct smu_table_context *table_context = &smu->smu_table;
 350        struct smu_11_0_7_powerplay_table *powerplay_table =
 351                table_context->power_play_table;
 352        struct smu_baco_context *smu_baco = &smu->smu_baco;
 353        struct amdgpu_device *adev = smu->adev;
 354        uint32_t val;
 355
 356        if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
 357                val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 358                smu_baco->platform_support =
 359                        (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 360                                                                        false;
 361        }
 362}
 363
 364static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 365{
 366        struct smu_table_context *table_context = &smu->smu_table;
 367        struct smu_11_0_7_powerplay_table *powerplay_table =
 368                table_context->power_play_table;
 369
 370        if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 371                smu->dc_controlled_by_gpio = true;
 372
 373        sienna_cichlid_check_bxco_support(smu);
 374
 375        table_context->thermal_controller_type =
 376                powerplay_table->thermal_controller_type;
 377
 378        /*
 379         * Instead of having its own buffer space and get overdrive_table copied,
 380         * smu->od_settings just points to the actual overdrive_table
 381         */
 382        smu->od_settings = &powerplay_table->overdrive_table;
 383
 384        return 0;
 385}
 386
 387static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 388{
 389        struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 390        int index, ret;
 391        I2cControllerConfig_t *table_member;
 392
 393        index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 394                                            smc_dpm_info);
 395
 396        ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 397                                      (uint8_t **)&smc_dpm_table);
 398        if (ret)
 399                return ret;
 400        GET_PPTABLE_MEMBER(I2cControllers, &table_member);
 401        memcpy(table_member, smc_dpm_table->I2cControllers,
 402                        sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 403        
 404        return 0;
 405}
 406
 407static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 408{
 409        struct smu_table_context *table_context = &smu->smu_table;
 410        struct smu_11_0_7_powerplay_table *powerplay_table =
 411                table_context->power_play_table;
 412        int table_size;
 413
 414        table_size = get_table_size(smu);
 415        memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 416               table_size);
 417
 418        return 0;
 419}
 420
 421static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 422{
 423        int ret = 0;
 424
 425        ret = smu_v11_0_setup_pptable(smu);
 426        if (ret)
 427                return ret;
 428
 429        ret = sienna_cichlid_store_powerplay_table(smu);
 430        if (ret)
 431                return ret;
 432
 433        ret = sienna_cichlid_append_powerplay_table(smu);
 434        if (ret)
 435                return ret;
 436
 437        ret = sienna_cichlid_check_powerplay_table(smu);
 438        if (ret)
 439                return ret;
 440
 441        return ret;
 442}
 443
 444static int sienna_cichlid_tables_init(struct smu_context *smu)
 445{
 446        struct smu_table_context *smu_table = &smu->smu_table;
 447        struct smu_table *tables = smu_table->tables;
 448        int table_size;
 449
 450        table_size = get_table_size(smu);
 451        SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
 452                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 453        SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 454                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 455        SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 456                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 457        SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 458                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 459        SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 460                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 461        SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 462                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 463        SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 464                       sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 465                       AMDGPU_GEM_DOMAIN_VRAM);
 466
 467        smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 468        if (!smu_table->metrics_table)
 469                goto err0_out;
 470        smu_table->metrics_time = 0;
 471
 472        smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 473        smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 474        if (!smu_table->gpu_metrics_table)
 475                goto err1_out;
 476
 477        smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 478        if (!smu_table->watermarks_table)
 479                goto err2_out;
 480
 481        return 0;
 482
 483err2_out:
 484        kfree(smu_table->gpu_metrics_table);
 485err1_out:
 486        kfree(smu_table->metrics_table);
 487err0_out:
 488        return -ENOMEM;
 489}
 490
 491static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 492                                               MetricsMember_t member,
 493                                               uint32_t *value)
 494{
 495        struct smu_table_context *smu_table= &smu->smu_table;
 496        SmuMetrics_t *metrics =
 497                &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 498        int ret = 0;
 499
 500        mutex_lock(&smu->metrics_lock);
 501
 502        ret = smu_cmn_get_metrics_table_locked(smu,
 503                                               NULL,
 504                                               false);
 505        if (ret) {
 506                mutex_unlock(&smu->metrics_lock);
 507                return ret;
 508        }
 509
 510        switch (member) {
 511        case METRICS_CURR_GFXCLK:
 512                *value = metrics->CurrClock[PPCLK_GFXCLK];
 513                break;
 514        case METRICS_CURR_SOCCLK:
 515                *value = metrics->CurrClock[PPCLK_SOCCLK];
 516                break;
 517        case METRICS_CURR_UCLK:
 518                *value = metrics->CurrClock[PPCLK_UCLK];
 519                break;
 520        case METRICS_CURR_VCLK:
 521                *value = metrics->CurrClock[PPCLK_VCLK_0];
 522                break;
 523        case METRICS_CURR_VCLK1:
 524                *value = metrics->CurrClock[PPCLK_VCLK_1];
 525                break;
 526        case METRICS_CURR_DCLK:
 527                *value = metrics->CurrClock[PPCLK_DCLK_0];
 528                break;
 529        case METRICS_CURR_DCLK1:
 530                *value = metrics->CurrClock[PPCLK_DCLK_1];
 531                break;
 532        case METRICS_CURR_DCEFCLK:
 533                *value = metrics->CurrClock[PPCLK_DCEFCLK];
 534                break;
 535        case METRICS_CURR_FCLK:
 536                *value = metrics->CurrClock[PPCLK_FCLK];
 537                break;
 538        case METRICS_AVERAGE_GFXCLK:
 539                if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 540                        *value = metrics->AverageGfxclkFrequencyPostDs;
 541                else
 542                        *value = metrics->AverageGfxclkFrequencyPreDs;
 543                break;
 544        case METRICS_AVERAGE_FCLK:
 545                *value = metrics->AverageFclkFrequencyPostDs;
 546                break;
 547        case METRICS_AVERAGE_UCLK:
 548                *value = metrics->AverageUclkFrequencyPostDs;
 549                break;
 550        case METRICS_AVERAGE_GFXACTIVITY:
 551                *value = metrics->AverageGfxActivity;
 552                break;
 553        case METRICS_AVERAGE_MEMACTIVITY:
 554                *value = metrics->AverageUclkActivity;
 555                break;
 556        case METRICS_AVERAGE_SOCKETPOWER:
 557                *value = metrics->AverageSocketPower << 8;
 558                break;
 559        case METRICS_TEMPERATURE_EDGE:
 560                *value = metrics->TemperatureEdge *
 561                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 562                break;
 563        case METRICS_TEMPERATURE_HOTSPOT:
 564                *value = metrics->TemperatureHotspot *
 565                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 566                break;
 567        case METRICS_TEMPERATURE_MEM:
 568                *value = metrics->TemperatureMem *
 569                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 570                break;
 571        case METRICS_TEMPERATURE_VRGFX:
 572                *value = metrics->TemperatureVrGfx *
 573                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 574                break;
 575        case METRICS_TEMPERATURE_VRSOC:
 576                *value = metrics->TemperatureVrSoc *
 577                        SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 578                break;
 579        case METRICS_THROTTLER_STATUS:
 580                *value = metrics->ThrottlerStatus;
 581                break;
 582        case METRICS_CURR_FANSPEED:
 583                *value = metrics->CurrFanSpeed;
 584                break;
 585        default:
 586                *value = UINT_MAX;
 587                break;
 588        }
 589
 590        mutex_unlock(&smu->metrics_lock);
 591
 592        return ret;
 593
 594}
 595
 596static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 597{
 598        struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 599
 600        smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 601                                       GFP_KERNEL);
 602        if (!smu_dpm->dpm_context)
 603                return -ENOMEM;
 604
 605        smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 606
 607        return 0;
 608}
 609
 610static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 611{
 612        int ret = 0;
 613
 614        ret = sienna_cichlid_tables_init(smu);
 615        if (ret)
 616                return ret;
 617
 618        ret = sienna_cichlid_allocate_dpm_context(smu);
 619        if (ret)
 620                return ret;
 621
 622        return smu_v11_0_init_smc_tables(smu);
 623}
 624
 625static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 626{
 627        struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 628        struct smu_11_0_dpm_table *dpm_table;
 629        struct amdgpu_device *adev = smu->adev;
 630        int ret = 0;
 631        DpmDescriptor_t *table_member;
 632
 633        /* socclk dpm table setup */
 634        dpm_table = &dpm_context->dpm_tables.soc_table;
 635        GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 636        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 637                ret = smu_v11_0_set_single_dpm_table(smu,
 638                                                     SMU_SOCCLK,
 639                                                     dpm_table);
 640                if (ret)
 641                        return ret;
 642                dpm_table->is_fine_grained =
 643                        !table_member[PPCLK_SOCCLK].SnapToDiscrete;
 644        } else {
 645                dpm_table->count = 1;
 646                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 647                dpm_table->dpm_levels[0].enabled = true;
 648                dpm_table->min = dpm_table->dpm_levels[0].value;
 649                dpm_table->max = dpm_table->dpm_levels[0].value;
 650        }
 651
 652        /* gfxclk dpm table setup */
 653        dpm_table = &dpm_context->dpm_tables.gfx_table;
 654        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 655                ret = smu_v11_0_set_single_dpm_table(smu,
 656                                                     SMU_GFXCLK,
 657                                                     dpm_table);
 658                if (ret)
 659                        return ret;
 660                dpm_table->is_fine_grained =
 661                        !table_member[PPCLK_GFXCLK].SnapToDiscrete;
 662        } else {
 663                dpm_table->count = 1;
 664                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 665                dpm_table->dpm_levels[0].enabled = true;
 666                dpm_table->min = dpm_table->dpm_levels[0].value;
 667                dpm_table->max = dpm_table->dpm_levels[0].value;
 668        }
 669
 670        /* uclk dpm table setup */
 671        dpm_table = &dpm_context->dpm_tables.uclk_table;
 672        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 673                ret = smu_v11_0_set_single_dpm_table(smu,
 674                                                     SMU_UCLK,
 675                                                     dpm_table);
 676                if (ret)
 677                        return ret;
 678                dpm_table->is_fine_grained =
 679                        !table_member[PPCLK_UCLK].SnapToDiscrete;
 680        } else {
 681                dpm_table->count = 1;
 682                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 683                dpm_table->dpm_levels[0].enabled = true;
 684                dpm_table->min = dpm_table->dpm_levels[0].value;
 685                dpm_table->max = dpm_table->dpm_levels[0].value;
 686        }
 687
 688        /* fclk dpm table setup */
 689        dpm_table = &dpm_context->dpm_tables.fclk_table;
 690        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 691                ret = smu_v11_0_set_single_dpm_table(smu,
 692                                                     SMU_FCLK,
 693                                                     dpm_table);
 694                if (ret)
 695                        return ret;
 696                dpm_table->is_fine_grained =
 697                        !table_member[PPCLK_FCLK].SnapToDiscrete;
 698        } else {
 699                dpm_table->count = 1;
 700                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 701                dpm_table->dpm_levels[0].enabled = true;
 702                dpm_table->min = dpm_table->dpm_levels[0].value;
 703                dpm_table->max = dpm_table->dpm_levels[0].value;
 704        }
 705
 706        /* vclk0 dpm table setup */
 707        dpm_table = &dpm_context->dpm_tables.vclk_table;
 708        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 709                ret = smu_v11_0_set_single_dpm_table(smu,
 710                                                     SMU_VCLK,
 711                                                     dpm_table);
 712                if (ret)
 713                        return ret;
 714                dpm_table->is_fine_grained =
 715                        !table_member[PPCLK_VCLK_0].SnapToDiscrete;
 716        } else {
 717                dpm_table->count = 1;
 718                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 719                dpm_table->dpm_levels[0].enabled = true;
 720                dpm_table->min = dpm_table->dpm_levels[0].value;
 721                dpm_table->max = dpm_table->dpm_levels[0].value;
 722        }
 723
 724        /* vclk1 dpm table setup */
 725        if (adev->vcn.num_vcn_inst > 1) {
 726                dpm_table = &dpm_context->dpm_tables.vclk1_table;
 727                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 728                        ret = smu_v11_0_set_single_dpm_table(smu,
 729                                                             SMU_VCLK1,
 730                                                             dpm_table);
 731                        if (ret)
 732                                return ret;
 733                        dpm_table->is_fine_grained =
 734                                !table_member[PPCLK_VCLK_1].SnapToDiscrete;
 735                } else {
 736                        dpm_table->count = 1;
 737                        dpm_table->dpm_levels[0].value =
 738                                smu->smu_table.boot_values.vclk / 100;
 739                        dpm_table->dpm_levels[0].enabled = true;
 740                        dpm_table->min = dpm_table->dpm_levels[0].value;
 741                        dpm_table->max = dpm_table->dpm_levels[0].value;
 742                }
 743        }
 744
 745        /* dclk0 dpm table setup */
 746        dpm_table = &dpm_context->dpm_tables.dclk_table;
 747        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 748                ret = smu_v11_0_set_single_dpm_table(smu,
 749                                                     SMU_DCLK,
 750                                                     dpm_table);
 751                if (ret)
 752                        return ret;
 753                dpm_table->is_fine_grained =
 754                        !table_member[PPCLK_DCLK_0].SnapToDiscrete;
 755        } else {
 756                dpm_table->count = 1;
 757                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 758                dpm_table->dpm_levels[0].enabled = true;
 759                dpm_table->min = dpm_table->dpm_levels[0].value;
 760                dpm_table->max = dpm_table->dpm_levels[0].value;
 761        }
 762
 763        /* dclk1 dpm table setup */
 764        if (adev->vcn.num_vcn_inst > 1) {
 765                dpm_table = &dpm_context->dpm_tables.dclk1_table;
 766                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 767                        ret = smu_v11_0_set_single_dpm_table(smu,
 768                                                             SMU_DCLK1,
 769                                                             dpm_table);
 770                        if (ret)
 771                                return ret;
 772                        dpm_table->is_fine_grained =
 773                                !table_member[PPCLK_DCLK_1].SnapToDiscrete;
 774                } else {
 775                        dpm_table->count = 1;
 776                        dpm_table->dpm_levels[0].value =
 777                                smu->smu_table.boot_values.dclk / 100;
 778                        dpm_table->dpm_levels[0].enabled = true;
 779                        dpm_table->min = dpm_table->dpm_levels[0].value;
 780                        dpm_table->max = dpm_table->dpm_levels[0].value;
 781                }
 782        }
 783
 784        /* dcefclk dpm table setup */
 785        dpm_table = &dpm_context->dpm_tables.dcef_table;
 786        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 787                ret = smu_v11_0_set_single_dpm_table(smu,
 788                                                     SMU_DCEFCLK,
 789                                                     dpm_table);
 790                if (ret)
 791                        return ret;
 792                dpm_table->is_fine_grained =
 793                        !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
 794        } else {
 795                dpm_table->count = 1;
 796                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 797                dpm_table->dpm_levels[0].enabled = true;
 798                dpm_table->min = dpm_table->dpm_levels[0].value;
 799                dpm_table->max = dpm_table->dpm_levels[0].value;
 800        }
 801
 802        /* pixelclk dpm table setup */
 803        dpm_table = &dpm_context->dpm_tables.pixel_table;
 804        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 805                ret = smu_v11_0_set_single_dpm_table(smu,
 806                                                     SMU_PIXCLK,
 807                                                     dpm_table);
 808                if (ret)
 809                        return ret;
 810                dpm_table->is_fine_grained =
 811                        !table_member[PPCLK_PIXCLK].SnapToDiscrete;
 812        } else {
 813                dpm_table->count = 1;
 814                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 815                dpm_table->dpm_levels[0].enabled = true;
 816                dpm_table->min = dpm_table->dpm_levels[0].value;
 817                dpm_table->max = dpm_table->dpm_levels[0].value;
 818        }
 819
 820        /* displayclk dpm table setup */
 821        dpm_table = &dpm_context->dpm_tables.display_table;
 822        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 823                ret = smu_v11_0_set_single_dpm_table(smu,
 824                                                     SMU_DISPCLK,
 825                                                     dpm_table);
 826                if (ret)
 827                        return ret;
 828                dpm_table->is_fine_grained =
 829                        !table_member[PPCLK_DISPCLK].SnapToDiscrete;
 830        } else {
 831                dpm_table->count = 1;
 832                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 833                dpm_table->dpm_levels[0].enabled = true;
 834                dpm_table->min = dpm_table->dpm_levels[0].value;
 835                dpm_table->max = dpm_table->dpm_levels[0].value;
 836        }
 837
 838        /* phyclk dpm table setup */
 839        dpm_table = &dpm_context->dpm_tables.phy_table;
 840        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 841                ret = smu_v11_0_set_single_dpm_table(smu,
 842                                                     SMU_PHYCLK,
 843                                                     dpm_table);
 844                if (ret)
 845                        return ret;
 846                dpm_table->is_fine_grained =
 847                        !table_member[PPCLK_PHYCLK].SnapToDiscrete;
 848        } else {
 849                dpm_table->count = 1;
 850                dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 851                dpm_table->dpm_levels[0].enabled = true;
 852                dpm_table->min = dpm_table->dpm_levels[0].value;
 853                dpm_table->max = dpm_table->dpm_levels[0].value;
 854        }
 855
 856        return 0;
 857}
 858
 859static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 860{
 861        struct amdgpu_device *adev = smu->adev;
 862        int ret = 0;
 863
 864        if (enable) {
 865                /* vcn dpm on is a prerequisite for vcn power gate messages */
 866                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 867                        ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 868                        if (ret)
 869                                return ret;
 870                        if (adev->vcn.num_vcn_inst > 1) {
 871                                ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 872                                                                  0x10000, NULL);
 873                                if (ret)
 874                                        return ret;
 875                        }
 876                }
 877        } else {
 878                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 879                        ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 880                        if (ret)
 881                                return ret;
 882                        if (adev->vcn.num_vcn_inst > 1) {
 883                                ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 884                                                                  0x10000, NULL);
 885                                if (ret)
 886                                        return ret;
 887                        }
 888                }
 889        }
 890
 891        return ret;
 892}
 893
 894static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 895{
 896        int ret = 0;
 897
 898        if (enable) {
 899                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 900                        ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 901                        if (ret)
 902                                return ret;
 903                }
 904        } else {
 905                if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 906                        ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 907                        if (ret)
 908                                return ret;
 909                }
 910        }
 911
 912        return ret;
 913}
 914
 915static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 916                                       enum smu_clk_type clk_type,
 917                                       uint32_t *value)
 918{
 919        MetricsMember_t member_type;
 920        int clk_id = 0;
 921
 922        clk_id = smu_cmn_to_asic_specific_index(smu,
 923                                                CMN2ASIC_MAPPING_CLK,
 924                                                clk_type);
 925        if (clk_id < 0)
 926                return clk_id;
 927
 928        switch (clk_id) {
 929        case PPCLK_GFXCLK:
 930                member_type = METRICS_CURR_GFXCLK;
 931                break;
 932        case PPCLK_UCLK:
 933                member_type = METRICS_CURR_UCLK;
 934                break;
 935        case PPCLK_SOCCLK:
 936                member_type = METRICS_CURR_SOCCLK;
 937                break;
 938        case PPCLK_FCLK:
 939                member_type = METRICS_CURR_FCLK;
 940                break;
 941        case PPCLK_VCLK_0:
 942                member_type = METRICS_CURR_VCLK;
 943                break;
 944        case PPCLK_VCLK_1:
 945                member_type = METRICS_CURR_VCLK1;
 946                break;
 947        case PPCLK_DCLK_0:
 948                member_type = METRICS_CURR_DCLK;
 949                break;
 950        case PPCLK_DCLK_1:
 951                member_type = METRICS_CURR_DCLK1;
 952                break;
 953        case PPCLK_DCEFCLK:
 954                member_type = METRICS_CURR_DCEFCLK;
 955                break;
 956        default:
 957                return -EINVAL;
 958        }
 959
 960        return sienna_cichlid_get_smu_metrics_data(smu,
 961                                                   member_type,
 962                                                   value);
 963
 964}
 965
 966static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 967{
 968        DpmDescriptor_t *dpm_desc = NULL;
 969        DpmDescriptor_t *table_member;
 970        uint32_t clk_index = 0;
 971
 972        GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 973        clk_index = smu_cmn_to_asic_specific_index(smu,
 974                                                   CMN2ASIC_MAPPING_CLK,
 975                                                   clk_type);
 976        dpm_desc = &table_member[clk_index];
 977
 978        /* 0 - Fine grained DPM, 1 - Discrete DPM */
 979        return dpm_desc->SnapToDiscrete == 0;
 980}
 981
 982static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
 983                                                   enum SMU_11_0_7_ODFEATURE_CAP cap)
 984{
 985        return od_table->cap[cap];
 986}
 987
 988static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
 989                                                enum SMU_11_0_7_ODSETTING_ID setting,
 990                                                uint32_t *min, uint32_t *max)
 991{
 992        if (min)
 993                *min = od_table->min[setting];
 994        if (max)
 995                *max = od_table->max[setting];
 996}
 997
 998static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 999                        enum smu_clk_type clk_type, char *buf)
1000{
1001        struct amdgpu_device *adev = smu->adev;
1002        struct smu_table_context *table_context = &smu->smu_table;
1003        struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1004        struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1005        uint16_t *table_member;
1006
1007        struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1008        OverDriveTable_t *od_table =
1009                (OverDriveTable_t *)table_context->overdrive_table;
1010        int i, size = 0, ret = 0;
1011        uint32_t cur_value = 0, value = 0, count = 0;
1012        uint32_t freq_values[3] = {0};
1013        uint32_t mark_index = 0;
1014        uint32_t gen_speed, lane_width;
1015        uint32_t min_value, max_value;
1016        uint32_t smu_version;
1017
1018        switch (clk_type) {
1019        case SMU_GFXCLK:
1020        case SMU_SCLK:
1021        case SMU_SOCCLK:
1022        case SMU_MCLK:
1023        case SMU_UCLK:
1024        case SMU_FCLK:
1025        case SMU_VCLK:
1026        case SMU_VCLK1:
1027        case SMU_DCLK:
1028        case SMU_DCLK1:
1029        case SMU_DCEFCLK:
1030                ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1031                if (ret)
1032                        goto print_clk_out;
1033
1034                /* no need to disable gfxoff when retrieving the current gfxclk */
1035                if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1036                        amdgpu_gfx_off_ctrl(adev, false);
1037
1038                ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1039                if (ret)
1040                        goto print_clk_out;
1041
1042                if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1043                        for (i = 0; i < count; i++) {
1044                                ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1045                                if (ret)
1046                                        goto print_clk_out;
1047
1048                                size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
1049                                                cur_value == value ? "*" : "");
1050                        }
1051                } else {
1052                        ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1053                        if (ret)
1054                                goto print_clk_out;
1055                        ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1056                        if (ret)
1057                                goto print_clk_out;
1058
1059                        freq_values[1] = cur_value;
1060                        mark_index = cur_value == freq_values[0] ? 0 :
1061                                     cur_value == freq_values[2] ? 2 : 1;
1062
1063                        count = 3;
1064                        if (mark_index != 1) {
1065                                count = 2;
1066                                freq_values[1] = freq_values[2];
1067                        }
1068
1069                        for (i = 0; i < count; i++) {
1070                                size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
1071                                                cur_value  == freq_values[i] ? "*" : "");
1072                        }
1073
1074                }
1075                break;
1076        case SMU_PCIE:
1077                gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1078                lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1079                GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1080                for (i = 0; i < NUM_LINK_LEVELS; i++)
1081                        size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1082                                        (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1083                                        (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1084                                        (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1085                                        (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1086                                        (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1087                                        (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1088                                        (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1089                                        (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1090                                        (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1091                                        (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1092                                        table_member[i],
1093                                        (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1094                                        (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1095                                        "*" : "");
1096                break;
1097        case SMU_OD_SCLK:
1098                if (!smu->od_enabled || !od_table || !od_settings)
1099                        break;
1100
1101                if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1102                        break;
1103
1104                size += sprintf(buf + size, "OD_SCLK:\n");
1105                size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1106                break;
1107
1108        case SMU_OD_MCLK:
1109                if (!smu->od_enabled || !od_table || !od_settings)
1110                        break;
1111
1112                if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1113                        break;
1114
1115                size += sprintf(buf + size, "OD_MCLK:\n");
1116                size += sprintf(buf + size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1117                break;
1118
1119        case SMU_OD_VDDGFX_OFFSET:
1120                if (!smu->od_enabled || !od_table || !od_settings)
1121                        break;
1122
1123                /*
1124                 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1125                 * and onwards SMU firmwares.
1126                 */
1127                smu_cmn_get_smc_version(smu, NULL, &smu_version);
1128                if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1129                     (smu_version < 0x003a2900))
1130                        break;
1131
1132                size += sprintf(buf + size, "OD_VDDGFX_OFFSET:\n");
1133                size += sprintf(buf + size, "%dmV\n", od_table->VddGfxOffset);
1134                break;
1135
1136        case SMU_OD_RANGE:
1137                if (!smu->od_enabled || !od_table || !od_settings)
1138                        break;
1139
1140                size = sprintf(buf, "%s:\n", "OD_RANGE");
1141
1142                if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1143                        sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1144                                                            &min_value, NULL);
1145                        sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1146                                                            NULL, &max_value);
1147                        size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1148                                        min_value, max_value);
1149                }
1150
1151                if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1152                        sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1153                                                            &min_value, NULL);
1154                        sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1155                                                            NULL, &max_value);
1156                        size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1157                                        min_value, max_value);
1158                }
1159                break;
1160
1161        default:
1162                break;
1163        }
1164
1165print_clk_out:
1166        if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1167                amdgpu_gfx_off_ctrl(adev, true);
1168
1169        return size;
1170}
1171
1172static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1173                                   enum smu_clk_type clk_type, uint32_t mask)
1174{
1175        struct amdgpu_device *adev = smu->adev;
1176        int ret = 0, size = 0;
1177        uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1178
1179        soft_min_level = mask ? (ffs(mask) - 1) : 0;
1180        soft_max_level = mask ? (fls(mask) - 1) : 0;
1181
1182        if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1183                amdgpu_gfx_off_ctrl(adev, false);
1184
1185        switch (clk_type) {
1186        case SMU_GFXCLK:
1187        case SMU_SCLK:
1188        case SMU_SOCCLK:
1189        case SMU_MCLK:
1190        case SMU_UCLK:
1191        case SMU_FCLK:
1192                /* There is only 2 levels for fine grained DPM */
1193                if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1194                        soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1195                        soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1196                }
1197
1198                ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1199                if (ret)
1200                        goto forec_level_out;
1201
1202                ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1203                if (ret)
1204                        goto forec_level_out;
1205
1206                ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1207                if (ret)
1208                        goto forec_level_out;
1209                break;
1210        case SMU_DCEFCLK:
1211                dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1212                break;
1213        default:
1214                break;
1215        }
1216
1217forec_level_out:
1218        if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1219                amdgpu_gfx_off_ctrl(adev, true);
1220
1221        return size;
1222}
1223
1224static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1225{
1226        struct smu_11_0_dpm_context *dpm_context =
1227                                smu->smu_dpm.dpm_context;
1228        struct smu_11_0_dpm_table *gfx_table =
1229                                &dpm_context->dpm_tables.gfx_table;
1230        struct smu_11_0_dpm_table *mem_table =
1231                                &dpm_context->dpm_tables.uclk_table;
1232        struct smu_11_0_dpm_table *soc_table =
1233                                &dpm_context->dpm_tables.soc_table;
1234        struct smu_umd_pstate_table *pstate_table =
1235                                &smu->pstate_table;
1236
1237        pstate_table->gfxclk_pstate.min = gfx_table->min;
1238        pstate_table->gfxclk_pstate.peak = gfx_table->max;
1239        if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1240                pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1241
1242        pstate_table->uclk_pstate.min = mem_table->min;
1243        pstate_table->uclk_pstate.peak = mem_table->max;
1244        if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1245                pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1246
1247        pstate_table->socclk_pstate.min = soc_table->min;
1248        pstate_table->socclk_pstate.peak = soc_table->max;
1249        if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1250                pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1251
1252        return 0;
1253}
1254
1255static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1256{
1257        int ret = 0;
1258        uint32_t max_freq = 0;
1259
1260        /* Sienna_Cichlid do not support to change display num currently */
1261        return 0;
1262#if 0
1263        ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1264        if (ret)
1265                return ret;
1266#endif
1267
1268        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1269                ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1270                if (ret)
1271                        return ret;
1272                ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1273                if (ret)
1274                        return ret;
1275        }
1276
1277        return ret;
1278}
1279
1280static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1281{
1282        int ret = 0;
1283
1284        if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1285            smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1286            smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1287#if 0
1288                ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1289                                                  smu->display_config->num_display,
1290                                                  NULL);
1291#endif
1292                if (ret)
1293                        return ret;
1294        }
1295
1296        return ret;
1297}
1298
1299static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1300{
1301        int ret = 0;
1302        uint32_t feature_mask[2];
1303        uint64_t feature_enabled;
1304
1305        ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1306        if (ret)
1307                return false;
1308
1309        feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1310
1311        return !!(feature_enabled & SMC_DPM_FEATURE);
1312}
1313
1314static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
1315                                                uint32_t *speed)
1316{
1317        int ret;
1318        u32 rpm;
1319
1320        if (!speed)
1321                return -EINVAL;
1322
1323        switch (smu_v11_0_get_fan_control_mode(smu)) {
1324        case AMD_FAN_CTRL_AUTO:
1325                ret = sienna_cichlid_get_smu_metrics_data(smu,
1326                                                          METRICS_CURR_FANSPEED,
1327                                                          &rpm);
1328                if (!ret && smu->fan_max_rpm)
1329                        *speed = rpm * 100 / smu->fan_max_rpm;
1330                return ret;
1331        default:
1332                *speed = smu->user_dpm_profile.fan_speed_percent;
1333                return 0;
1334        }
1335}
1336
1337static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1338{
1339        uint16_t *table_member;
1340
1341        GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1342        smu->fan_max_rpm = *table_member;
1343
1344        return 0;
1345}
1346
1347static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1348{
1349        DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1350        DpmActivityMonitorCoeffInt_t *activity_monitor =
1351                &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1352        uint32_t i, size = 0;
1353        int16_t workload_type = 0;
1354        static const char *profile_name[] = {
1355                                        "BOOTUP_DEFAULT",
1356                                        "3D_FULL_SCREEN",
1357                                        "POWER_SAVING",
1358                                        "VIDEO",
1359                                        "VR",
1360                                        "COMPUTE",
1361                                        "CUSTOM"};
1362        static const char *title[] = {
1363                        "PROFILE_INDEX(NAME)",
1364                        "CLOCK_TYPE(NAME)",
1365                        "FPS",
1366                        "MinFreqType",
1367                        "MinActiveFreqType",
1368                        "MinActiveFreq",
1369                        "BoosterFreqType",
1370                        "BoosterFreq",
1371                        "PD_Data_limit_c",
1372                        "PD_Data_error_coeff",
1373                        "PD_Data_error_rate_coeff"};
1374        int result = 0;
1375
1376        if (!buf)
1377                return -EINVAL;
1378
1379        size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1380                        title[0], title[1], title[2], title[3], title[4], title[5],
1381                        title[6], title[7], title[8], title[9], title[10]);
1382
1383        for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1384                /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1385                workload_type = smu_cmn_to_asic_specific_index(smu,
1386                                                               CMN2ASIC_MAPPING_WORKLOAD,
1387                                                               i);
1388                if (workload_type < 0)
1389                        return -EINVAL;
1390
1391                result = smu_cmn_update_table(smu,
1392                                          SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1393                                          (void *)(&activity_monitor_external), false);
1394                if (result) {
1395                        dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1396                        return result;
1397                }
1398
1399                size += sprintf(buf + size, "%2d %14s%s:\n",
1400                        i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1401
1402                size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1403                        " ",
1404                        0,
1405                        "GFXCLK",
1406                        activity_monitor->Gfx_FPS,
1407                        activity_monitor->Gfx_MinFreqStep,
1408                        activity_monitor->Gfx_MinActiveFreqType,
1409                        activity_monitor->Gfx_MinActiveFreq,
1410                        activity_monitor->Gfx_BoosterFreqType,
1411                        activity_monitor->Gfx_BoosterFreq,
1412                        activity_monitor->Gfx_PD_Data_limit_c,
1413                        activity_monitor->Gfx_PD_Data_error_coeff,
1414                        activity_monitor->Gfx_PD_Data_error_rate_coeff);
1415
1416                size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1417                        " ",
1418                        1,
1419                        "SOCCLK",
1420                        activity_monitor->Fclk_FPS,
1421                        activity_monitor->Fclk_MinFreqStep,
1422                        activity_monitor->Fclk_MinActiveFreqType,
1423                        activity_monitor->Fclk_MinActiveFreq,
1424                        activity_monitor->Fclk_BoosterFreqType,
1425                        activity_monitor->Fclk_BoosterFreq,
1426                        activity_monitor->Fclk_PD_Data_limit_c,
1427                        activity_monitor->Fclk_PD_Data_error_coeff,
1428                        activity_monitor->Fclk_PD_Data_error_rate_coeff);
1429
1430                size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1431                        " ",
1432                        2,
1433                        "MEMLK",
1434                        activity_monitor->Mem_FPS,
1435                        activity_monitor->Mem_MinFreqStep,
1436                        activity_monitor->Mem_MinActiveFreqType,
1437                        activity_monitor->Mem_MinActiveFreq,
1438                        activity_monitor->Mem_BoosterFreqType,
1439                        activity_monitor->Mem_BoosterFreq,
1440                        activity_monitor->Mem_PD_Data_limit_c,
1441                        activity_monitor->Mem_PD_Data_error_coeff,
1442                        activity_monitor->Mem_PD_Data_error_rate_coeff);
1443        }
1444
1445        return size;
1446}
1447
1448static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1449{
1450
1451        DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1452        DpmActivityMonitorCoeffInt_t *activity_monitor =
1453                &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1454        int workload_type, ret = 0;
1455
1456        smu->power_profile_mode = input[size];
1457
1458        if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1459                dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1460                return -EINVAL;
1461        }
1462
1463        if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1464
1465                ret = smu_cmn_update_table(smu,
1466                                       SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1467                                       (void *)(&activity_monitor_external), false);
1468                if (ret) {
1469                        dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1470                        return ret;
1471                }
1472
1473                switch (input[0]) {
1474                case 0: /* Gfxclk */
1475                        activity_monitor->Gfx_FPS = input[1];
1476                        activity_monitor->Gfx_MinFreqStep = input[2];
1477                        activity_monitor->Gfx_MinActiveFreqType = input[3];
1478                        activity_monitor->Gfx_MinActiveFreq = input[4];
1479                        activity_monitor->Gfx_BoosterFreqType = input[5];
1480                        activity_monitor->Gfx_BoosterFreq = input[6];
1481                        activity_monitor->Gfx_PD_Data_limit_c = input[7];
1482                        activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1483                        activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1484                        break;
1485                case 1: /* Socclk */
1486                        activity_monitor->Fclk_FPS = input[1];
1487                        activity_monitor->Fclk_MinFreqStep = input[2];
1488                        activity_monitor->Fclk_MinActiveFreqType = input[3];
1489                        activity_monitor->Fclk_MinActiveFreq = input[4];
1490                        activity_monitor->Fclk_BoosterFreqType = input[5];
1491                        activity_monitor->Fclk_BoosterFreq = input[6];
1492                        activity_monitor->Fclk_PD_Data_limit_c = input[7];
1493                        activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1494                        activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1495                        break;
1496                case 2: /* Memlk */
1497                        activity_monitor->Mem_FPS = input[1];
1498                        activity_monitor->Mem_MinFreqStep = input[2];
1499                        activity_monitor->Mem_MinActiveFreqType = input[3];
1500                        activity_monitor->Mem_MinActiveFreq = input[4];
1501                        activity_monitor->Mem_BoosterFreqType = input[5];
1502                        activity_monitor->Mem_BoosterFreq = input[6];
1503                        activity_monitor->Mem_PD_Data_limit_c = input[7];
1504                        activity_monitor->Mem_PD_Data_error_coeff = input[8];
1505                        activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1506                        break;
1507                }
1508
1509                ret = smu_cmn_update_table(smu,
1510                                       SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1511                                       (void *)(&activity_monitor_external), true);
1512                if (ret) {
1513                        dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1514                        return ret;
1515                }
1516        }
1517
1518        /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1519        workload_type = smu_cmn_to_asic_specific_index(smu,
1520                                                       CMN2ASIC_MAPPING_WORKLOAD,
1521                                                       smu->power_profile_mode);
1522        if (workload_type < 0)
1523                return -EINVAL;
1524        smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1525                                    1 << workload_type, NULL);
1526
1527        return ret;
1528}
1529
1530static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1531{
1532        struct smu_clocks min_clocks = {0};
1533        struct pp_display_clock_request clock_req;
1534        int ret = 0;
1535
1536        min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1537        min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1538        min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1539
1540        if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1541                clock_req.clock_type = amd_pp_dcef_clock;
1542                clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1543
1544                ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1545                if (!ret) {
1546                        if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1547                                ret = smu_cmn_send_smc_msg_with_param(smu,
1548                                                                  SMU_MSG_SetMinDeepSleepDcefclk,
1549                                                                  min_clocks.dcef_clock_in_sr/100,
1550                                                                  NULL);
1551                                if (ret) {
1552                                        dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1553                                        return ret;
1554                                }
1555                        }
1556                } else {
1557                        dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1558                }
1559        }
1560
1561        if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1562                ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1563                if (ret) {
1564                        dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1565                        return ret;
1566                }
1567        }
1568
1569        return 0;
1570}
1571
1572static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1573                                               struct pp_smu_wm_range_sets *clock_ranges)
1574{
1575        Watermarks_t *table = smu->smu_table.watermarks_table;
1576        int ret = 0;
1577        int i;
1578
1579        if (clock_ranges) {
1580                if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1581                    clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1582                        return -EINVAL;
1583
1584                for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1585                        table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1586                                clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1587                        table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1588                                clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1589                        table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1590                                clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1591                        table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1592                                clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1593
1594                        table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1595                                clock_ranges->reader_wm_sets[i].wm_inst;
1596                }
1597
1598                for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1599                        table->WatermarkRow[WM_SOCCLK][i].MinClock =
1600                                clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1601                        table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1602                                clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1603                        table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1604                                clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1605                        table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1606                                clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1607
1608                        table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1609                                clock_ranges->writer_wm_sets[i].wm_inst;
1610                }
1611
1612                smu->watermarks_bitmap |= WATERMARKS_EXIST;
1613        }
1614
1615        if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1616             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1617                ret = smu_cmn_write_watermarks_table(smu);
1618                if (ret) {
1619                        dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1620                        return ret;
1621                }
1622                smu->watermarks_bitmap |= WATERMARKS_LOADED;
1623        }
1624
1625        return 0;
1626}
1627
1628static int sienna_cichlid_read_sensor(struct smu_context *smu,
1629                                 enum amd_pp_sensors sensor,
1630                                 void *data, uint32_t *size)
1631{
1632        int ret = 0;
1633        uint16_t *temp;
1634
1635        if(!data || !size)
1636                return -EINVAL;
1637
1638        mutex_lock(&smu->sensor_lock);
1639        switch (sensor) {
1640        case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1641                GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1642                *(uint16_t *)data = *temp;
1643                *size = 4;
1644                break;
1645        case AMDGPU_PP_SENSOR_MEM_LOAD:
1646                ret = sienna_cichlid_get_smu_metrics_data(smu,
1647                                                          METRICS_AVERAGE_MEMACTIVITY,
1648                                                          (uint32_t *)data);
1649                *size = 4;
1650                break;
1651        case AMDGPU_PP_SENSOR_GPU_LOAD:
1652                ret = sienna_cichlid_get_smu_metrics_data(smu,
1653                                                          METRICS_AVERAGE_GFXACTIVITY,
1654                                                          (uint32_t *)data);
1655                *size = 4;
1656                break;
1657        case AMDGPU_PP_SENSOR_GPU_POWER:
1658                ret = sienna_cichlid_get_smu_metrics_data(smu,
1659                                                          METRICS_AVERAGE_SOCKETPOWER,
1660                                                          (uint32_t *)data);
1661                *size = 4;
1662                break;
1663        case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1664                ret = sienna_cichlid_get_smu_metrics_data(smu,
1665                                                          METRICS_TEMPERATURE_HOTSPOT,
1666                                                          (uint32_t *)data);
1667                *size = 4;
1668                break;
1669        case AMDGPU_PP_SENSOR_EDGE_TEMP:
1670                ret = sienna_cichlid_get_smu_metrics_data(smu,
1671                                                          METRICS_TEMPERATURE_EDGE,
1672                                                          (uint32_t *)data);
1673                *size = 4;
1674                break;
1675        case AMDGPU_PP_SENSOR_MEM_TEMP:
1676                ret = sienna_cichlid_get_smu_metrics_data(smu,
1677                                                          METRICS_TEMPERATURE_MEM,
1678                                                          (uint32_t *)data);
1679                *size = 4;
1680                break;
1681        case AMDGPU_PP_SENSOR_GFX_MCLK:
1682                ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1683                *(uint32_t *)data *= 100;
1684                *size = 4;
1685                break;
1686        case AMDGPU_PP_SENSOR_GFX_SCLK:
1687                ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1688                *(uint32_t *)data *= 100;
1689                *size = 4;
1690                break;
1691        case AMDGPU_PP_SENSOR_VDDGFX:
1692                ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1693                *size = 4;
1694                break;
1695        default:
1696                ret = -EOPNOTSUPP;
1697                break;
1698        }
1699        mutex_unlock(&smu->sensor_lock);
1700
1701        return ret;
1702}
1703
1704static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1705{
1706        uint32_t num_discrete_levels = 0;
1707        uint16_t *dpm_levels = NULL;
1708        uint16_t i = 0;
1709        struct smu_table_context *table_context = &smu->smu_table;
1710        DpmDescriptor_t *table_member1;
1711        uint16_t *table_member2;
1712
1713        if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1714                return -EINVAL;
1715
1716        GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1717        num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1718        GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1719        dpm_levels = table_member2;
1720
1721        if (num_discrete_levels == 0 || dpm_levels == NULL)
1722                return -EINVAL;
1723
1724        *num_states = num_discrete_levels;
1725        for (i = 0; i < num_discrete_levels; i++) {
1726                /* convert to khz */
1727                *clocks_in_khz = (*dpm_levels) * 1000;
1728                clocks_in_khz++;
1729                dpm_levels++;
1730        }
1731
1732        return 0;
1733}
1734
1735static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1736                                                struct smu_temperature_range *range)
1737{
1738        struct smu_table_context *table_context = &smu->smu_table;
1739        struct smu_11_0_7_powerplay_table *powerplay_table =
1740                                table_context->power_play_table;
1741        uint16_t *table_member;
1742        uint16_t temp_edge, temp_hotspot, temp_mem;
1743
1744        if (!range)
1745                return -EINVAL;
1746
1747        memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1748
1749        GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
1750        temp_edge = table_member[TEMP_EDGE];
1751        temp_hotspot = table_member[TEMP_HOTSPOT];
1752        temp_mem = table_member[TEMP_MEM];
1753
1754        range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1755        range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
1756                SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1757        range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1758        range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
1759                SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1760        range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1761        range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
1762                SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1763
1764        range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1765
1766        return 0;
1767}
1768
1769static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1770                                                bool disable_memory_clock_switch)
1771{
1772        int ret = 0;
1773        struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1774                (struct smu_11_0_max_sustainable_clocks *)
1775                        smu->smu_table.max_sustainable_clocks;
1776        uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1777        uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1778
1779        if(smu->disable_uclk_switch == disable_memory_clock_switch)
1780                return 0;
1781
1782        if(disable_memory_clock_switch)
1783                ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1784        else
1785                ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1786
1787        if(!ret)
1788                smu->disable_uclk_switch = disable_memory_clock_switch;
1789
1790        return ret;
1791}
1792
1793static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1794                                          uint32_t *current_power_limit,
1795                                          uint32_t *default_power_limit,
1796                                          uint32_t *max_power_limit)
1797{
1798        struct smu_11_0_7_powerplay_table *powerplay_table =
1799                (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1800        uint32_t power_limit, od_percent;
1801        uint16_t *table_member;
1802
1803        GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
1804
1805        if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1806                power_limit =
1807                        table_member[PPT_THROTTLER_PPT0];
1808        }
1809
1810        if (current_power_limit)
1811                *current_power_limit = power_limit;
1812        if (default_power_limit)
1813                *default_power_limit = power_limit;
1814
1815        if (max_power_limit) {
1816                if (smu->od_enabled) {
1817                        od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1818
1819                        dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1820
1821                        power_limit *= (100 + od_percent);
1822                        power_limit /= 100;
1823                }
1824                *max_power_limit = power_limit;
1825        }
1826
1827        return 0;
1828}
1829
1830static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1831                                         uint32_t pcie_gen_cap,
1832                                         uint32_t pcie_width_cap)
1833{
1834        struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1835
1836        uint32_t smu_pcie_arg;
1837        uint8_t *table_member1, *table_member2;
1838        int ret, i;
1839
1840        GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
1841        GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
1842
1843        /* lclk dpm table setup */
1844        for (i = 0; i < MAX_PCIE_CONF; i++) {
1845                dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
1846                dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
1847        }
1848
1849        for (i = 0; i < NUM_LINK_LEVELS; i++) {
1850                smu_pcie_arg = (i << 16) |
1851                        ((table_member1[i] <= pcie_gen_cap) ?
1852                         (table_member1[i] << 8) :
1853                         (pcie_gen_cap << 8)) |
1854                        ((table_member2[i] <= pcie_width_cap) ?
1855                         table_member2[i] :
1856                         pcie_width_cap);
1857
1858                ret = smu_cmn_send_smc_msg_with_param(smu,
1859                                SMU_MSG_OverridePcieParameters,
1860                                smu_pcie_arg,
1861                                NULL);
1862                if (ret)
1863                        return ret;
1864
1865                if (table_member1[i] > pcie_gen_cap)
1866                        dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1867                if (table_member2[i] > pcie_width_cap)
1868                        dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1869        }
1870
1871        return 0;
1872}
1873
1874static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1875                                enum smu_clk_type clk_type,
1876                                uint32_t *min, uint32_t *max)
1877{
1878        struct amdgpu_device *adev = smu->adev;
1879        int ret;
1880
1881        if (clk_type == SMU_GFXCLK)
1882                amdgpu_gfx_off_ctrl(adev, false);
1883        ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1884        if (clk_type == SMU_GFXCLK)
1885                amdgpu_gfx_off_ctrl(adev, true);
1886
1887        return ret;
1888}
1889
1890static void sienna_cichlid_dump_od_table(struct smu_context *smu,
1891                                         OverDriveTable_t *od_table)
1892{
1893        struct amdgpu_device *adev = smu->adev;
1894        uint32_t smu_version;
1895
1896        dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
1897                                                          od_table->GfxclkFmax);
1898        dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
1899                                                        od_table->UclkFmax);
1900
1901        smu_cmn_get_smc_version(smu, NULL, &smu_version);
1902        if (!((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1903               (smu_version < 0x003a2900)))
1904                dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
1905}
1906
1907static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
1908{
1909        OverDriveTable_t *od_table =
1910                (OverDriveTable_t *)smu->smu_table.overdrive_table;
1911        OverDriveTable_t *boot_od_table =
1912                (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1913        int ret = 0;
1914
1915        ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
1916                                   0, (void *)od_table, false);
1917        if (ret) {
1918                dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1919                return ret;
1920        }
1921
1922        memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
1923
1924        sienna_cichlid_dump_od_table(smu, od_table);
1925
1926        return 0;
1927}
1928
1929static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
1930                                                 struct smu_11_0_7_overdrive_table *od_table,
1931                                                 enum SMU_11_0_7_ODSETTING_ID setting,
1932                                                 uint32_t value)
1933{
1934        if (value < od_table->min[setting]) {
1935                dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
1936                                          setting, value, od_table->min[setting]);
1937                return -EINVAL;
1938        }
1939        if (value > od_table->max[setting]) {
1940                dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
1941                                          setting, value, od_table->max[setting]);
1942                return -EINVAL;
1943        }
1944
1945        return 0;
1946}
1947
1948static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
1949                                            enum PP_OD_DPM_TABLE_COMMAND type,
1950                                            long input[], uint32_t size)
1951{
1952        struct smu_table_context *table_context = &smu->smu_table;
1953        OverDriveTable_t *od_table =
1954                (OverDriveTable_t *)table_context->overdrive_table;
1955        struct smu_11_0_7_overdrive_table *od_settings =
1956                (struct smu_11_0_7_overdrive_table *)smu->od_settings;
1957        struct amdgpu_device *adev = smu->adev;
1958        enum SMU_11_0_7_ODSETTING_ID freq_setting;
1959        uint16_t *freq_ptr;
1960        int i, ret = 0;
1961        uint32_t smu_version;
1962
1963        if (!smu->od_enabled) {
1964                dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
1965                return -EINVAL;
1966        }
1967
1968        if (!smu->od_settings) {
1969                dev_err(smu->adev->dev, "OD board limits are not set!\n");
1970                return -ENOENT;
1971        }
1972
1973        if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
1974                dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
1975                return -EINVAL;
1976        }
1977
1978        switch (type) {
1979        case PP_OD_EDIT_SCLK_VDDC_TABLE:
1980                if (!sienna_cichlid_is_od_feature_supported(od_settings,
1981                                                            SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1982                        dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
1983                        return -ENOTSUPP;
1984                }
1985
1986                for (i = 0; i < size; i += 2) {
1987                        if (i + 2 > size) {
1988                                dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
1989                                return -EINVAL;
1990                        }
1991
1992                        switch (input[i]) {
1993                        case 0:
1994                                if (input[i + 1] > od_table->GfxclkFmax) {
1995                                        dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
1996                                                input[i + 1], od_table->GfxclkFmax);
1997                                        return -EINVAL;
1998                                }
1999
2000                                freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2001                                freq_ptr = &od_table->GfxclkFmin;
2002                                break;
2003
2004                        case 1:
2005                                if (input[i + 1] < od_table->GfxclkFmin) {
2006                                        dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2007                                                input[i + 1], od_table->GfxclkFmin);
2008                                        return -EINVAL;
2009                                }
2010
2011                                freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2012                                freq_ptr = &od_table->GfxclkFmax;
2013                                break;
2014
2015                        default:
2016                                dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2017                                dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2018                                return -EINVAL;
2019                        }
2020
2021                        ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2022                                                                    freq_setting, input[i + 1]);
2023                        if (ret)
2024                                return ret;
2025
2026                        *freq_ptr = (uint16_t)input[i + 1];
2027                }
2028                break;
2029
2030        case PP_OD_EDIT_MCLK_VDDC_TABLE:
2031                if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2032                        dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2033                        return -ENOTSUPP;
2034                }
2035
2036                for (i = 0; i < size; i += 2) {
2037                        if (i + 2 > size) {
2038                                dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2039                                return -EINVAL;
2040                        }
2041
2042                        switch (input[i]) {
2043                        case 0:
2044                                if (input[i + 1] > od_table->UclkFmax) {
2045                                        dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2046                                                input[i + 1], od_table->UclkFmax);
2047                                        return -EINVAL;
2048                                }
2049
2050                                freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2051                                freq_ptr = &od_table->UclkFmin;
2052                                break;
2053
2054                        case 1:
2055                                if (input[i + 1] < od_table->UclkFmin) {
2056                                        dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2057                                                input[i + 1], od_table->UclkFmin);
2058                                        return -EINVAL;
2059                                }
2060
2061                                freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2062                                freq_ptr = &od_table->UclkFmax;
2063                                break;
2064
2065                        default:
2066                                dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2067                                dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2068                                return -EINVAL;
2069                        }
2070
2071                        ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2072                                                                    freq_setting, input[i + 1]);
2073                        if (ret)
2074                                return ret;
2075
2076                        *freq_ptr = (uint16_t)input[i + 1];
2077                }
2078                break;
2079
2080        case PP_OD_RESTORE_DEFAULT_TABLE:
2081                memcpy(table_context->overdrive_table,
2082                                table_context->boot_overdrive_table,
2083                                sizeof(OverDriveTable_t));
2084                fallthrough;
2085
2086        case PP_OD_COMMIT_DPM_TABLE:
2087                sienna_cichlid_dump_od_table(smu, od_table);
2088
2089                ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2090                                           0, (void *)od_table, true);
2091                if (ret) {
2092                        dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2093                        return ret;
2094                }
2095                break;
2096
2097        case PP_OD_EDIT_VDDGFX_OFFSET:
2098                if (size != 1) {
2099                        dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2100                        return -EINVAL;
2101                }
2102
2103                /*
2104                 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2105                 * and onwards SMU firmwares.
2106                 */
2107                smu_cmn_get_smc_version(smu, NULL, &smu_version);
2108                if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
2109                     (smu_version < 0x003a2900)) {
2110                        dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2111                                                "only by 58.41.0 and onwards SMU firmwares!\n");
2112                        return -EOPNOTSUPP;
2113                }
2114
2115                od_table->VddGfxOffset = (int16_t)input[0];
2116
2117                sienna_cichlid_dump_od_table(smu, od_table);
2118                break;
2119
2120        default:
2121                return -ENOSYS;
2122        }
2123
2124        return ret;
2125}
2126
2127static int sienna_cichlid_run_btc(struct smu_context *smu)
2128{
2129        return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2130}
2131
2132static int sienna_cichlid_baco_enter(struct smu_context *smu)
2133{
2134        struct amdgpu_device *adev = smu->adev;
2135
2136        if (adev->in_runpm)
2137                return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2138        else
2139                return smu_v11_0_baco_enter(smu);
2140}
2141
2142static int sienna_cichlid_baco_exit(struct smu_context *smu)
2143{
2144        struct amdgpu_device *adev = smu->adev;
2145
2146        if (adev->in_runpm) {
2147                /* Wait for PMFW handling for the Dstate change */
2148                msleep(10);
2149                return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2150        } else {
2151                return smu_v11_0_baco_exit(smu);
2152        }
2153}
2154
2155static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2156{
2157        struct amdgpu_device *adev = smu->adev;
2158        uint32_t val;
2159        u32 smu_version;
2160
2161        /**
2162         * SRIOV env will not support SMU mode1 reset
2163         * PM FW support mode1 reset from 58.26
2164         */
2165        smu_cmn_get_smc_version(smu, NULL, &smu_version);
2166        if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2167                return false;
2168
2169        /**
2170         * mode1 reset relies on PSP, so we should check if
2171         * PSP is alive.
2172         */
2173        val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2174        return val != 0x0;
2175}
2176
2177static void beige_goby_dump_pptable(struct smu_context *smu)
2178{
2179        struct smu_table_context *table_context = &smu->smu_table;
2180        PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2181        int i;
2182
2183        dev_info(smu->adev->dev, "Dumped PPTable:\n");
2184
2185        dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2186        dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2187        dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2188
2189        for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2190                dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2191                dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2192                dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2193                dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2194        }
2195
2196        for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2197                dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2198                dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2199        }
2200
2201        for (i = 0; i < TEMP_COUNT; i++) {
2202                dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2203        }
2204
2205        dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2206        dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2207        dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2208        dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2209        dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2210
2211        dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2212        for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2213                dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2214                dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2215        }
2216        dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2217
2218        dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2219
2220        dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2221        dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2222        dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2223        dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2224
2225        dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2226
2227        dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2228
2229        dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2230        dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2231        dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2232        dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2233
2234        dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2235        dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2236
2237        dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2238        dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2239        dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2240        dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2241        dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2242        dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2243        dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2244        dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2245
2246        dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2247                        "  .VoltageMode          = 0x%02x\n"
2248                        "  .SnapToDiscrete       = 0x%02x\n"
2249                        "  .NumDiscreteLevels    = 0x%02x\n"
2250                        "  .padding              = 0x%02x\n"
2251                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2252                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2253                        "  .SsFmin               = 0x%04x\n"
2254                        "  .Padding_16           = 0x%04x\n",
2255                        pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2256                        pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2257                        pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2258                        pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2259                        pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2260                        pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2261                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2262                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2263                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2264                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2265                        pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2266
2267        dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2268                        "  .VoltageMode          = 0x%02x\n"
2269                        "  .SnapToDiscrete       = 0x%02x\n"
2270                        "  .NumDiscreteLevels    = 0x%02x\n"
2271                        "  .padding              = 0x%02x\n"
2272                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2273                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2274                        "  .SsFmin               = 0x%04x\n"
2275                        "  .Padding_16           = 0x%04x\n",
2276                        pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2277                        pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2278                        pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2279                        pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2280                        pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2281                        pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2282                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2283                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2284                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2285                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2286                        pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2287
2288        dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2289                        "  .VoltageMode          = 0x%02x\n"
2290                        "  .SnapToDiscrete       = 0x%02x\n"
2291                        "  .NumDiscreteLevels    = 0x%02x\n"
2292                        "  .padding              = 0x%02x\n"
2293                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2294                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2295                        "  .SsFmin               = 0x%04x\n"
2296                        "  .Padding_16           = 0x%04x\n",
2297                        pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2298                        pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2299                        pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2300                        pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2301                        pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2302                        pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2303                        pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2304                        pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2305                        pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2306                        pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2307                        pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2308
2309        dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2310                        "  .VoltageMode          = 0x%02x\n"
2311                        "  .SnapToDiscrete       = 0x%02x\n"
2312                        "  .NumDiscreteLevels    = 0x%02x\n"
2313                        "  .padding              = 0x%02x\n"
2314                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2315                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2316                        "  .SsFmin               = 0x%04x\n"
2317                        "  .Padding_16           = 0x%04x\n",
2318                        pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2319                        pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2320                        pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2321                        pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2322                        pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2323                        pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2324                        pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2325                        pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2326                        pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2327                        pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2328                        pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2329
2330        dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2331                        "  .VoltageMode          = 0x%02x\n"
2332                        "  .SnapToDiscrete       = 0x%02x\n"
2333                        "  .NumDiscreteLevels    = 0x%02x\n"
2334                        "  .padding              = 0x%02x\n"
2335                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2336                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2337                        "  .SsFmin               = 0x%04x\n"
2338                        "  .Padding_16           = 0x%04x\n",
2339                        pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2340                        pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2341                        pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2342                        pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2343                        pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2344                        pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2345                        pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2346                        pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2347                        pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2348                        pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2349                        pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2350
2351        dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2352                        "  .VoltageMode          = 0x%02x\n"
2353                        "  .SnapToDiscrete       = 0x%02x\n"
2354                        "  .NumDiscreteLevels    = 0x%02x\n"
2355                        "  .padding              = 0x%02x\n"
2356                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2357                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2358                        "  .SsFmin               = 0x%04x\n"
2359                        "  .Padding_16           = 0x%04x\n",
2360                        pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2361                        pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2362                        pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2363                        pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2364                        pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2365                        pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2366                        pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2367                        pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2368                        pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2369                        pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2370                        pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2371
2372        dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2373                        "  .VoltageMode          = 0x%02x\n"
2374                        "  .SnapToDiscrete       = 0x%02x\n"
2375                        "  .NumDiscreteLevels    = 0x%02x\n"
2376                        "  .padding              = 0x%02x\n"
2377                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2378                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2379                        "  .SsFmin               = 0x%04x\n"
2380                        "  .Padding_16           = 0x%04x\n",
2381                        pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2382                        pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2383                        pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2384                        pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2385                        pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2386                        pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2387                        pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2388                        pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2389                        pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2390                        pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2391                        pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2392
2393        dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2394                        "  .VoltageMode          = 0x%02x\n"
2395                        "  .SnapToDiscrete       = 0x%02x\n"
2396                        "  .NumDiscreteLevels    = 0x%02x\n"
2397                        "  .padding              = 0x%02x\n"
2398                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2399                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2400                        "  .SsFmin               = 0x%04x\n"
2401                        "  .Padding_16           = 0x%04x\n",
2402                        pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2403                        pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2404                        pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2405                        pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2406                        pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2407                        pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2408                        pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2409                        pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2410                        pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2411                        pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2412                        pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2413
2414        dev_info(smu->adev->dev, "FreqTableGfx\n");
2415        for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2416                dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2417
2418        dev_info(smu->adev->dev, "FreqTableVclk\n");
2419        for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2420                dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2421
2422        dev_info(smu->adev->dev, "FreqTableDclk\n");
2423        for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2424                dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2425
2426        dev_info(smu->adev->dev, "FreqTableSocclk\n");
2427        for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2428                dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2429
2430        dev_info(smu->adev->dev, "FreqTableUclk\n");
2431        for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2432                dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2433
2434        dev_info(smu->adev->dev, "FreqTableFclk\n");
2435        for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2436                dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2437
2438        dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2439        dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2440        dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2441        dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2442        dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2443        dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2444        dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2445        dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2446        dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2447
2448        dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2449        for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2450                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2451
2452        dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2453        dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2454
2455        dev_info(smu->adev->dev, "Mp0clkFreq\n");
2456        for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2457                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2458
2459        dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2460        for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2461                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2462
2463        dev_info(smu->adev->dev, "MemVddciVoltage\n");
2464        for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2465                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2466
2467        dev_info(smu->adev->dev, "MemMvddVoltage\n");
2468        for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2469                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2470
2471        dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2472        dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2473        dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2474        dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2475        dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2476
2477        dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2478
2479        dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2480        dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2481        dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2482        dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2483        dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2484        dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2485        dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2486        dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2487        dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2488        dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2489        dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2490
2491        dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2492        dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2493        dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2494        dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2495        dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2496        dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2497
2498        dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2499        dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2500        dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2501        dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2502        dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2503
2504        dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2505        for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2506                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2507
2508        dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2509        dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2510        dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2511        dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2512
2513        dev_info(smu->adev->dev, "UclkDpmPstates\n");
2514        for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2515                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2516
2517        dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2518        dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2519                pptable->UclkDpmSrcFreqRange.Fmin);
2520        dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2521                pptable->UclkDpmSrcFreqRange.Fmax);
2522        dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2523        dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2524                pptable->UclkDpmTargFreqRange.Fmin);
2525        dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2526                pptable->UclkDpmTargFreqRange.Fmax);
2527        dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2528        dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2529
2530        dev_info(smu->adev->dev, "PcieGenSpeed\n");
2531        for (i = 0; i < NUM_LINK_LEVELS; i++)
2532                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2533
2534        dev_info(smu->adev->dev, "PcieLaneCount\n");
2535        for (i = 0; i < NUM_LINK_LEVELS; i++)
2536                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2537
2538        dev_info(smu->adev->dev, "LclkFreq\n");
2539        for (i = 0; i < NUM_LINK_LEVELS; i++)
2540                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2541
2542        dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2543        dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2544
2545        dev_info(smu->adev->dev, "FanGain\n");
2546        for (i = 0; i < TEMP_COUNT; i++)
2547                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2548
2549        dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2550        dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2551        dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2552        dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2553        dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2554        dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2555        dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2556        dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2557        dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2558        dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2559        dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2560        dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2561
2562        dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2563        dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2564        dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2565        dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2566
2567        dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2568        dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2569        dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2570        dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2571
2572        dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2573                        pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2574                        pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2575                        pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2576        dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2577                        pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2578                        pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2579                        pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2580        dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2581                        pptable->dBtcGbGfxPll.a,
2582                        pptable->dBtcGbGfxPll.b,
2583                        pptable->dBtcGbGfxPll.c);
2584        dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2585                        pptable->dBtcGbGfxDfll.a,
2586                        pptable->dBtcGbGfxDfll.b,
2587                        pptable->dBtcGbGfxDfll.c);
2588        dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2589                        pptable->dBtcGbSoc.a,
2590                        pptable->dBtcGbSoc.b,
2591                        pptable->dBtcGbSoc.c);
2592        dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2593                        pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2594                        pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2595        dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2596                        pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2597                        pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2598
2599        dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2600        for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2601                dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2602                        i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2603                dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2604                        i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2605        }
2606
2607        dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2608                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2609                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2610                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2611        dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2612                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2613                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2614                        pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2615
2616        dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2617        dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2618
2619        dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2620        dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2621        dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2622        dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2623
2624        dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2625        dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2626        dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2627        dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2628
2629        dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2630        dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2631
2632        dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2633        for (i = 0; i < NUM_XGMI_LEVELS; i++)
2634                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2635        dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2636        dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2637
2638        dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2639        dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2640                        pptable->ReservedEquation0.a,
2641                        pptable->ReservedEquation0.b,
2642                        pptable->ReservedEquation0.c);
2643        dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2644                        pptable->ReservedEquation1.a,
2645                        pptable->ReservedEquation1.b,
2646                        pptable->ReservedEquation1.c);
2647        dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2648                        pptable->ReservedEquation2.a,
2649                        pptable->ReservedEquation2.b,
2650                        pptable->ReservedEquation2.c);
2651        dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2652                        pptable->ReservedEquation3.a,
2653                        pptable->ReservedEquation3.b,
2654                        pptable->ReservedEquation3.c);
2655
2656        dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2657        dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2658        dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2659        dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2660        dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2661        dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2662        dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2663        dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2664
2665        dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2666        dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2667        dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2668        dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2669        dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2670        dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2671
2672        for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2673                dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2674                dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2675                                pptable->I2cControllers[i].Enabled);
2676                dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2677                                pptable->I2cControllers[i].Speed);
2678                dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2679                                pptable->I2cControllers[i].SlaveAddress);
2680                dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2681                                pptable->I2cControllers[i].ControllerPort);
2682                dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2683                                pptable->I2cControllers[i].ControllerName);
2684                dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2685                                pptable->I2cControllers[i].ThermalThrotter);
2686                dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2687                                pptable->I2cControllers[i].I2cProtocol);
2688                dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2689                                pptable->I2cControllers[i].PaddingConfig);
2690        }
2691
2692        dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2693        dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2694        dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2695        dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2696
2697        dev_info(smu->adev->dev, "Board Parameters:\n");
2698        dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2699        dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2700        dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2701        dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2702        dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2703        dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2704        dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2705        dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2706
2707        dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2708        dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2709        dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2710
2711        dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2712        dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2713        dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2714
2715        dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2716        dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2717        dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2718
2719        dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2720        dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2721        dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2722
2723        dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2724
2725        dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2726        dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2727        dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2728        dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2729        dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2730        dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2731        dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2732        dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2733        dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2734        dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2735        dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2736        dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2737        dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2738        dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2739        dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2740        dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2741
2742        dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2743        dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2744        dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2745
2746        dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2747        dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2748        dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2749
2750        dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2751        dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2752
2753        dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2754        dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2755        dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2756
2757        dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2758        dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2759        dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2760        dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2761        dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2762
2763        dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2764        dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2765
2766        dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2767        for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2768                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2769        dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2770        for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2771                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2772        dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2773        for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2774                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2775        dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2776        for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2777                dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2778
2779        dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2780        dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2781        dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2782        dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2783
2784        dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2785        dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2786        dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2787        dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2788        dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2789        dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2790        dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2791        dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2792        dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2793        dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2794        dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2795
2796        dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2797        dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2798        dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2799        dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2800        dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2801        dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2802        dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2803        dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2804}
2805
2806static void sienna_cichlid_dump_pptable(struct smu_context *smu)
2807{
2808        struct smu_table_context *table_context = &smu->smu_table;
2809        PPTable_t *pptable = table_context->driver_pptable;
2810        int i;
2811
2812        if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
2813                beige_goby_dump_pptable(smu);
2814                return;
2815        }
2816
2817        dev_info(smu->adev->dev, "Dumped PPTable:\n");
2818
2819        dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2820        dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2821        dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2822
2823        for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2824                dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2825                dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2826                dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2827                dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2828        }
2829
2830        for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2831                dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2832                dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2833        }
2834
2835        for (i = 0; i < TEMP_COUNT; i++) {
2836                dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2837        }
2838
2839        dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2840        dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2841        dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2842        dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2843        dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2844
2845        dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2846        for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2847                dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2848                dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2849        }
2850        dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2851
2852        dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2853
2854        dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2855        dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2856        dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2857        dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2858
2859        dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2860        dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
2861
2862        dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2863        dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
2864        dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
2865        dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
2866
2867        dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2868        dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2869        dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2870        dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2871
2872        dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2873        dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2874
2875        dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2876        dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2877        dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2878        dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2879        dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2880        dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2881        dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2882        dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2883
2884        dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2885                        "  .VoltageMode          = 0x%02x\n"
2886                        "  .SnapToDiscrete       = 0x%02x\n"
2887                        "  .NumDiscreteLevels    = 0x%02x\n"
2888                        "  .padding              = 0x%02x\n"
2889                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2890                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2891                        "  .SsFmin               = 0x%04x\n"
2892                        "  .Padding_16           = 0x%04x\n",
2893                        pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2894                        pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2895                        pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2896                        pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2897                        pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2898                        pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2899                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2900                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2901                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2902                        pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2903                        pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2904
2905        dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2906                        "  .VoltageMode          = 0x%02x\n"
2907                        "  .SnapToDiscrete       = 0x%02x\n"
2908                        "  .NumDiscreteLevels    = 0x%02x\n"
2909                        "  .padding              = 0x%02x\n"
2910                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2911                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2912                        "  .SsFmin               = 0x%04x\n"
2913                        "  .Padding_16           = 0x%04x\n",
2914                        pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2915                        pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2916                        pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2917                        pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2918                        pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2919                        pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2920                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2921                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2922                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2923                        pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2924                        pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2925
2926        dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2927                        "  .VoltageMode          = 0x%02x\n"
2928                        "  .SnapToDiscrete       = 0x%02x\n"
2929                        "  .NumDiscreteLevels    = 0x%02x\n"
2930                        "  .padding              = 0x%02x\n"
2931                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2932                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2933                        "  .SsFmin               = 0x%04x\n"
2934                        "  .Padding_16           = 0x%04x\n",
2935                        pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2936                        pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2937                        pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2938                        pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2939                        pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2940                        pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2941                        pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2942                        pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2943                        pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2944                        pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2945                        pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2946
2947        dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2948                        "  .VoltageMode          = 0x%02x\n"
2949                        "  .SnapToDiscrete       = 0x%02x\n"
2950                        "  .NumDiscreteLevels    = 0x%02x\n"
2951                        "  .padding              = 0x%02x\n"
2952                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2953                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2954                        "  .SsFmin               = 0x%04x\n"
2955                        "  .Padding_16           = 0x%04x\n",
2956                        pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2957                        pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2958                        pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2959                        pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2960                        pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2961                        pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2962                        pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2963                        pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2964                        pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2965                        pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2966                        pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2967
2968        dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2969                        "  .VoltageMode          = 0x%02x\n"
2970                        "  .SnapToDiscrete       = 0x%02x\n"
2971                        "  .NumDiscreteLevels    = 0x%02x\n"
2972                        "  .padding              = 0x%02x\n"
2973                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2974                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2975                        "  .SsFmin               = 0x%04x\n"
2976                        "  .Padding_16           = 0x%04x\n",
2977                        pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2978                        pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2979                        pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2980                        pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2981                        pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2982                        pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2983                        pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2984                        pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2985                        pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2986                        pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2987                        pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2988
2989        dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2990                        "  .VoltageMode          = 0x%02x\n"
2991                        "  .SnapToDiscrete       = 0x%02x\n"
2992                        "  .NumDiscreteLevels    = 0x%02x\n"
2993                        "  .padding              = 0x%02x\n"
2994                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2995                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2996                        "  .SsFmin               = 0x%04x\n"
2997                        "  .Padding_16           = 0x%04x\n",
2998                        pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2999                        pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3000                        pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3001                        pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3002                        pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3003                        pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3004                        pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3005                        pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3006                        pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3007                        pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3008                        pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3009
3010        dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3011                        "  .VoltageMode          = 0x%02x\n"
3012                        "  .SnapToDiscrete       = 0x%02x\n"
3013                        "  .NumDiscreteLevels    = 0x%02x\n"
3014                        "  .padding              = 0x%02x\n"
3015                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3016                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3017                        "  .SsFmin               = 0x%04x\n"
3018                        "  .Padding_16           = 0x%04x\n",
3019                        pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3020                        pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3021                        pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3022                        pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3023                        pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3024                        pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3025                        pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3026                        pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3027                        pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3028                        pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3029                        pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3030
3031        dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3032                        "  .VoltageMode          = 0x%02x\n"
3033                        "  .SnapToDiscrete       = 0x%02x\n"
3034                        "  .NumDiscreteLevels    = 0x%02x\n"
3035                        "  .padding              = 0x%02x\n"
3036                        "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3037                        "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3038                        "  .SsFmin               = 0x%04x\n"
3039                        "  .Padding_16           = 0x%04x\n",
3040                        pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3041                        pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3042                        pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3043                        pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3044                        pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3045                        pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3046                        pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3047                        pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3048                        pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3049                        pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3050                        pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3051
3052        dev_info(smu->adev->dev, "FreqTableGfx\n");
3053        for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3054                dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3055
3056        dev_info(smu->adev->dev, "FreqTableVclk\n");
3057        for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3058                dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3059
3060        dev_info(smu->adev->dev, "FreqTableDclk\n");
3061        for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3062                dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3063
3064        dev_info(smu->adev->dev, "FreqTableSocclk\n");
3065        for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3066                dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3067
3068        dev_info(smu->adev->dev, "FreqTableUclk\n");
3069        for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3070                dev_info(smu->adev->dev, "  .[%02