linux/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
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   1/*
   2 * Copyright 2020 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "dm_services.h"
  27#include "core_types.h"
  28#include "reg_helper.h"
  29#include "dcn30_dpp.h"
  30#include "basics/conversion.h"
  31#include "dcn30_cm_common.h"
  32
  33#define REG(reg)\
  34        dpp->tf_regs->reg
  35
  36#define CTX \
  37        dpp->base.ctx
  38
  39#undef FN
  40#define FN(reg_name, field_name) \
  41        dpp->tf_shift->field_name, dpp->tf_mask->field_name
  42
  43
  44void dpp30_read_state(struct dpp *dpp_base,
  45                struct dcn_dpp_state *s)
  46{
  47        struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
  48
  49        REG_GET(DPP_CONTROL,
  50                        DPP_CLOCK_ENABLE, &s->is_enabled);
  51
  52        // TODO: Implement for DCN3
  53}
  54/*program post scaler scs block in dpp CM*/
  55void dpp3_program_post_csc(
  56                struct dpp *dpp_base,
  57                enum dc_color_space color_space,
  58                enum dcn10_input_csc_select input_select,
  59                const struct out_csc_color_matrix *tbl_entry)
  60{
  61        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
  62        int i;
  63        int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
  64        const uint16_t *regval = NULL;
  65        uint32_t cur_select = 0;
  66        enum dcn10_input_csc_select select;
  67        struct color_matrices_reg gam_regs;
  68
  69        if (input_select == INPUT_CSC_SELECT_BYPASS) {
  70                REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);
  71                return;
  72        }
  73
  74        if (tbl_entry == NULL) {
  75                for (i = 0; i < arr_size; i++)
  76                        if (dpp_input_csc_matrix[i].color_space == color_space) {
  77                                regval = dpp_input_csc_matrix[i].regval;
  78                                break;
  79                        }
  80
  81                if (regval == NULL) {
  82                        BREAK_TO_DEBUGGER();
  83                        return;
  84                }
  85        } else {
  86                regval = tbl_entry->regval;
  87        }
  88
  89        /* determine which CSC matrix (icsc or coma) we are using
  90         * currently.  select the alternate set to double buffer
  91         * the CSC update so CSC is updated on frame boundary
  92         */
  93        REG_GET(CM_POST_CSC_CONTROL,
  94                        CM_POST_CSC_MODE_CURRENT, &cur_select);
  95
  96        if (cur_select != INPUT_CSC_SELECT_ICSC)
  97                select = INPUT_CSC_SELECT_ICSC;
  98        else
  99                select = INPUT_CSC_SELECT_COMA;
 100
 101        gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
 102        gam_regs.masks.csc_c11  = dpp->tf_mask->CM_POST_CSC_C11;
 103        gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
 104        gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
 105
 106        if (select == INPUT_CSC_SELECT_ICSC) {
 107
 108                gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
 109                gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
 110
 111        } else {
 112
 113                gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
 114                gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
 115
 116        }
 117
 118        cm_helper_program_color_matrices(
 119                        dpp->base.ctx,
 120                        regval,
 121                        &gam_regs);
 122
 123        REG_SET(CM_POST_CSC_CONTROL, 0,
 124                        CM_POST_CSC_MODE, select);
 125}
 126
 127
 128/*CNVC degam unit has read only LUTs*/
 129void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
 130{
 131        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 132        int pre_degam_en = 1;
 133        int degamma_lut_selection = 0;
 134
 135        switch (tr) {
 136        case TRANSFER_FUNCTION_LINEAR:
 137        case TRANSFER_FUNCTION_UNITY:
 138                pre_degam_en = 0; //bypass
 139                break;
 140        case TRANSFER_FUNCTION_SRGB:
 141                degamma_lut_selection = 0;
 142                break;
 143        case TRANSFER_FUNCTION_BT709:
 144                degamma_lut_selection = 4;
 145                break;
 146        case TRANSFER_FUNCTION_PQ:
 147                degamma_lut_selection = 5;
 148                break;
 149        case TRANSFER_FUNCTION_HLG:
 150                degamma_lut_selection = 6;
 151                break;
 152        case TRANSFER_FUNCTION_GAMMA22:
 153                degamma_lut_selection = 1;
 154                break;
 155        case TRANSFER_FUNCTION_GAMMA24:
 156                degamma_lut_selection = 2;
 157                break;
 158        case TRANSFER_FUNCTION_GAMMA26:
 159                degamma_lut_selection = 3;
 160                break;
 161        default:
 162                pre_degam_en = 0;
 163                break;
 164        }
 165
 166        REG_SET_2(PRE_DEGAM, 0,
 167                        PRE_DEGAM_MODE, pre_degam_en,
 168                        PRE_DEGAM_SELECT, degamma_lut_selection);
 169}
 170
 171static void dpp3_cnv_setup (
 172                struct dpp *dpp_base,
 173                enum surface_pixel_format format,
 174                enum expansion_mode mode,
 175                struct dc_csc_transform input_csc_color_matrix,
 176                enum dc_color_space input_color_space,
 177                struct cnv_alpha_2bit_lut *alpha_2bit_lut)
 178{
 179        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 180        uint32_t pixel_format = 0;
 181        uint32_t alpha_en = 1;
 182        enum dc_color_space color_space = COLOR_SPACE_SRGB;
 183        enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
 184        bool force_disable_cursor = false;
 185        uint32_t is_2bit = 0;
 186        uint32_t alpha_plane_enable = 0;
 187        uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
 188        uint32_t realpha_en = 0, realpha_ablnd_en = 0;
 189        uint32_t program_prealpha_dealpha = 0;
 190        struct out_csc_color_matrix tbl_entry;
 191        int i;
 192
 193        REG_SET_2(FORMAT_CONTROL, 0,
 194                CNVC_BYPASS, 0,
 195                FORMAT_EXPANSION_MODE, mode);
 196
 197        REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
 198        REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
 199        REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
 200        REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
 201
 202        REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
 203        REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
 204        REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
 205
 206        switch (format) {
 207        case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 208                pixel_format = 1;
 209                break;
 210        case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 211                pixel_format = 3;
 212                alpha_en = 0;
 213                break;
 214        case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 215        case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 216                pixel_format = 8;
 217                break;
 218        case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 219        case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 220                pixel_format = 10;
 221                is_2bit = 1;
 222                break;
 223        case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 224                force_disable_cursor = false;
 225                pixel_format = 65;
 226                color_space = COLOR_SPACE_YCBCR709;
 227                select = INPUT_CSC_SELECT_ICSC;
 228                break;
 229        case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 230                force_disable_cursor = true;
 231                pixel_format = 64;
 232                color_space = COLOR_SPACE_YCBCR709;
 233                select = INPUT_CSC_SELECT_ICSC;
 234                break;
 235        case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 236                force_disable_cursor = true;
 237                pixel_format = 67;
 238                color_space = COLOR_SPACE_YCBCR709;
 239                select = INPUT_CSC_SELECT_ICSC;
 240                break;
 241        case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 242                force_disable_cursor = true;
 243                pixel_format = 66;
 244                color_space = COLOR_SPACE_YCBCR709;
 245                select = INPUT_CSC_SELECT_ICSC;
 246                break;
 247        case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 248        case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 249                pixel_format = 26; /* ARGB16161616_UNORM */
 250                break;
 251        case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 252                pixel_format = 24;
 253                break;
 254        case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 255                pixel_format = 25;
 256                break;
 257        case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
 258                pixel_format = 12;
 259                color_space = COLOR_SPACE_YCBCR709;
 260                select = INPUT_CSC_SELECT_ICSC;
 261                break;
 262        case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
 263                pixel_format = 112;
 264                break;
 265        case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
 266                pixel_format = 113;
 267                break;
 268        case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
 269                pixel_format = 114;
 270                color_space = COLOR_SPACE_YCBCR709;
 271                select = INPUT_CSC_SELECT_ICSC;
 272                is_2bit = 1;
 273                break;
 274        case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
 275                pixel_format = 115;
 276                color_space = COLOR_SPACE_YCBCR709;
 277                select = INPUT_CSC_SELECT_ICSC;
 278                is_2bit = 1;
 279                break;
 280        case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
 281                pixel_format = 116;
 282                alpha_plane_enable = 0;
 283                break;
 284        case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 285                pixel_format = 116;
 286                alpha_plane_enable = 1;
 287                break;
 288        case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
 289                pixel_format = 118;
 290                break;
 291        case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
 292                pixel_format = 119;
 293                break;
 294        default:
 295                break;
 296        }
 297
 298        if (is_2bit == 1 && alpha_2bit_lut != NULL) {
 299                REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
 300                REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
 301                REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
 302                REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
 303        }
 304
 305        REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
 306                        CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
 307                        CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
 308        REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
 309
 310        if (program_prealpha_dealpha) {
 311                dealpha_en = 1;
 312                realpha_en = 1;
 313        }
 314        REG_SET_2(PRE_DEALPHA, 0,
 315                        PRE_DEALPHA_EN, dealpha_en,
 316                        PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
 317        REG_SET_2(PRE_REALPHA, 0,
 318                        PRE_REALPHA_EN, realpha_en,
 319                        PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
 320
 321        /* If input adjustment exists, program the ICSC with those values. */
 322        if (input_csc_color_matrix.enable_adjustment == true) {
 323                for (i = 0; i < 12; i++)
 324                        tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
 325
 326                tbl_entry.color_space = input_color_space;
 327
 328                if (color_space >= COLOR_SPACE_YCBCR601)
 329                        select = INPUT_CSC_SELECT_ICSC;
 330                else
 331                        select = INPUT_CSC_SELECT_BYPASS;
 332
 333                dpp3_program_post_csc(dpp_base, color_space, select,
 334                                      &tbl_entry);
 335        } else {
 336                dpp3_program_post_csc(dpp_base, color_space, select, NULL);
 337        }
 338
 339        if (force_disable_cursor) {
 340                REG_UPDATE(CURSOR_CONTROL,
 341                                CURSOR_ENABLE, 0);
 342                REG_UPDATE(CURSOR0_CONTROL,
 343                                CUR0_ENABLE, 0);
 344        }
 345}
 346
 347#define IDENTITY_RATIO(ratio) (dc_fixpt_u3d19(ratio) == (1 << 19))
 348
 349void dpp3_set_cursor_attributes(
 350                struct dpp *dpp_base,
 351                struct dc_cursor_attributes *cursor_attributes)
 352{
 353        enum dc_cursor_color_format color_format = cursor_attributes->color_format;
 354        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 355        int cur_rom_en = 0;
 356
 357        if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
 358                color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
 359                cur_rom_en = 1;
 360
 361        REG_UPDATE_3(CURSOR0_CONTROL,
 362                        CUR0_MODE, color_format,
 363                        CUR0_EXPANSION_MODE, 0,
 364                        CUR0_ROM_EN, cur_rom_en);
 365
 366        if (color_format == CURSOR_MODE_MONO) {
 367                /* todo: clarify what to program these to */
 368                REG_UPDATE(CURSOR0_COLOR0,
 369                                CUR0_COLOR0, 0x00000000);
 370                REG_UPDATE(CURSOR0_COLOR1,
 371                                CUR0_COLOR1, 0xFFFFFFFF);
 372        }
 373}
 374
 375
 376bool dpp3_get_optimal_number_of_taps(
 377                struct dpp *dpp,
 378                struct scaler_data *scl_data,
 379                const struct scaling_taps *in_taps)
 380{
 381        int num_part_y, num_part_c;
 382        int max_taps_y, max_taps_c;
 383        int min_taps_y, min_taps_c;
 384        enum lb_memory_config lb_config;
 385
 386        if (scl_data->viewport.width > scl_data->h_active &&
 387                dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
 388                scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
 389                return false;
 390
 391        /*
 392         * Set default taps if none are provided
 393         * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling
 394         * taps = 4 for upscaling
 395         */
 396        if (in_taps->h_taps == 0) {
 397                if (dc_fixpt_ceil(scl_data->ratios.horz) > 1)
 398                        scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8);
 399                else
 400                        scl_data->taps.h_taps = 4;
 401        } else
 402                scl_data->taps.h_taps = in_taps->h_taps;
 403        if (in_taps->v_taps == 0) {
 404                if (dc_fixpt_ceil(scl_data->ratios.vert) > 1)
 405                        scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8);
 406                else
 407                        scl_data->taps.v_taps = 4;
 408        } else
 409                scl_data->taps.v_taps = in_taps->v_taps;
 410        if (in_taps->v_taps_c == 0) {
 411                if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1)
 412                        scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8);
 413                else
 414                        scl_data->taps.v_taps_c = 4;
 415        } else
 416                scl_data->taps.v_taps_c = in_taps->v_taps_c;
 417        if (in_taps->h_taps_c == 0) {
 418                if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1)
 419                        scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8);
 420                else
 421                        scl_data->taps.h_taps_c = 4;
 422        } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
 423                /* Only 1 and even h_taps_c are supported by hw */
 424                scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
 425        else
 426                scl_data->taps.h_taps_c = in_taps->h_taps_c;
 427
 428        /*Ensure we can support the requested number of vtaps*/
 429        min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert);
 430        min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
 431
 432        /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */
 433        if ((scl_data->format == PIXEL_FORMAT_420BPP8) || (scl_data->format == PIXEL_FORMAT_420BPP10))
 434                lb_config = LB_MEMORY_CONFIG_3;
 435        else
 436                lb_config = LB_MEMORY_CONFIG_0;
 437
 438        dpp->caps->dscl_calc_lb_num_partitions(
 439                        scl_data, lb_config, &num_part_y, &num_part_c);
 440
 441        /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */
 442        if (dc_fixpt_ceil(scl_data->ratios.vert) > 2)
 443                max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2);
 444        else
 445                max_taps_y = num_part_y;
 446
 447        if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 2)
 448                max_taps_c = num_part_c - (dc_fixpt_ceil(scl_data->ratios.vert_c) - 2);
 449        else
 450                max_taps_c = num_part_c;
 451
 452        if (max_taps_y < min_taps_y)
 453                return false;
 454        else if (max_taps_c < min_taps_c)
 455                return false;
 456
 457        if (scl_data->taps.v_taps > max_taps_y)
 458                scl_data->taps.v_taps = max_taps_y;
 459
 460        if (scl_data->taps.v_taps_c > max_taps_c)
 461                scl_data->taps.v_taps_c = max_taps_c;
 462
 463        if (!dpp->ctx->dc->debug.always_scale) {
 464                if (IDENTITY_RATIO(scl_data->ratios.horz))
 465                        scl_data->taps.h_taps = 1;
 466                if (IDENTITY_RATIO(scl_data->ratios.vert))
 467                        scl_data->taps.v_taps = 1;
 468                if (IDENTITY_RATIO(scl_data->ratios.horz_c))
 469                        scl_data->taps.h_taps_c = 1;
 470                if (IDENTITY_RATIO(scl_data->ratios.vert_c))
 471                        scl_data->taps.v_taps_c = 1;
 472        }
 473
 474        return true;
 475}
 476
 477void dpp3_cnv_set_bias_scale(
 478                struct dpp *dpp_base,
 479                struct  dc_bias_and_scale *bias_and_scale)
 480{
 481        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 482
 483        REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red);
 484        REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green);
 485        REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue);
 486        REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red);
 487        REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green);
 488        REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
 489}
 490
 491static void dpp3_power_on_blnd_lut(
 492        struct dpp *dpp_base,
 493        bool power_on)
 494{
 495        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 496
 497        if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
 498                REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, power_on ? 0 : 3);
 499                if (power_on)
 500                        REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5);
 501        } else {
 502                REG_SET(CM_MEM_PWR_CTRL, 0,
 503                                BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
 504        }
 505}
 506
 507static void dpp3_power_on_hdr3dlut(
 508        struct dpp *dpp_base,
 509        bool power_on)
 510{
 511        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 512
 513        if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
 514                REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, power_on ? 0 : 3);
 515                if (power_on)
 516                        REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
 517        }
 518}
 519
 520static void dpp3_power_on_shaper(
 521        struct dpp *dpp_base,
 522        bool power_on)
 523{
 524        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 525
 526        if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
 527                REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, power_on ? 0 : 3);
 528                if (power_on)
 529                        REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
 530        }
 531}
 532
 533static void dpp3_configure_blnd_lut(
 534                struct dpp *dpp_base,
 535                bool is_ram_a)
 536{
 537        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 538
 539        REG_UPDATE_2(CM_BLNDGAM_LUT_CONTROL,
 540                        CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 7,
 541                        CM_BLNDGAM_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
 542
 543        REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
 544}
 545
 546static void dpp3_program_blnd_pwl(
 547                struct dpp *dpp_base,
 548                const struct pwl_result_data *rgb,
 549                uint32_t num)
 550{
 551        uint32_t i;
 552        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 553        uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
 554        uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
 555        uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
 556
 557        if (is_rgb_equal(rgb, num)) {
 558                for (i = 0 ; i < num; i++)
 559                        REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
 560                REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
 561        } else {
 562                REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
 563                for (i = 0 ; i < num; i++)
 564                        REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
 565                REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
 566
 567                REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
 568                for (i = 0 ; i < num; i++)
 569                        REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
 570                REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
 571
 572                REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
 573                for (i = 0 ; i < num; i++)
 574                        REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
 575                REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);
 576        }
 577}
 578
 579static void dcn3_dpp_cm_get_reg_field(
 580                struct dcn3_dpp *dpp,
 581                struct dcn3_xfer_func_reg *reg)
 582{
 583        reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
 584        reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
 585        reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
 586        reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
 587        reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
 588        reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
 589        reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
 590        reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
 591
 592        reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
 593        reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;
 594        reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
 595        reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;
 596        reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
 597        reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;
 598        reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
 599        reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;
 600        reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
 601        reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;
 602        reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
 603        reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
 604}
 605
 606/*program blnd lut RAM A*/
 607static void dpp3_program_blnd_luta_settings(
 608                struct dpp *dpp_base,
 609                const struct pwl_params *params)
 610{
 611        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 612        struct dcn3_xfer_func_reg gam_regs;
 613
 614        dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
 615
 616        gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B);
 617        gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G);
 618        gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R);
 619        gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B);
 620        gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G);
 621        gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R);
 622        gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B);
 623        gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B);
 624        gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G);
 625        gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G);
 626        gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R);
 627        gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R);
 628        gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1);
 629        gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33);
 630
 631        cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
 632}
 633
 634/*program blnd lut RAM B*/
 635static void dpp3_program_blnd_lutb_settings(
 636                struct dpp *dpp_base,
 637                const struct pwl_params *params)
 638{
 639        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 640        struct dcn3_xfer_func_reg gam_regs;
 641
 642        dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);
 643
 644        gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B);
 645        gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G);
 646        gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R);
 647        gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B);
 648        gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G);
 649        gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R);
 650        gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B);
 651        gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B);
 652        gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G);
 653        gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G);
 654        gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R);
 655        gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R);
 656        gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1);
 657        gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33);
 658
 659        cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);
 660}
 661
 662static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
 663{
 664        enum dc_lut_mode mode;
 665        uint32_t mode_current = 0;
 666        uint32_t in_use = 0;
 667
 668        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 669
 670        REG_GET(CM_BLNDGAM_CONTROL,
 671                        CM_BLNDGAM_MODE_CURRENT, &mode_current);
 672        REG_GET(CM_BLNDGAM_CONTROL,
 673                        CM_BLNDGAM_SELECT_CURRENT, &in_use);
 674
 675                switch (mode_current) {
 676                case 0:
 677                case 1:
 678                        mode = LUT_BYPASS;
 679                        break;
 680
 681                case 2:
 682                        if (in_use == 0)
 683                                mode = LUT_RAM_A;
 684                        else
 685                                mode = LUT_RAM_B;
 686                        break;
 687                default:
 688                        mode = LUT_BYPASS;
 689                        break;
 690                }
 691                return mode;
 692}
 693
 694bool dpp3_program_blnd_lut(
 695        struct dpp *dpp_base, const struct pwl_params *params)
 696{
 697        enum dc_lut_mode current_mode;
 698        enum dc_lut_mode next_mode;
 699        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 700
 701        if (params == NULL) {
 702                REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);
 703                if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
 704                        dpp3_power_on_blnd_lut(dpp_base, false);
 705                return false;
 706        }
 707
 708        current_mode = dpp3_get_blndgam_current(dpp_base);
 709        if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
 710                next_mode = LUT_RAM_A;
 711        else
 712                next_mode = LUT_RAM_B;
 713
 714        dpp3_power_on_blnd_lut(dpp_base, true);
 715        dpp3_configure_blnd_lut(dpp_base, next_mode == LUT_RAM_A);
 716
 717        if (next_mode == LUT_RAM_A)
 718                dpp3_program_blnd_luta_settings(dpp_base, params);
 719        else
 720                dpp3_program_blnd_lutb_settings(dpp_base, params);
 721
 722        dpp3_program_blnd_pwl(
 723                        dpp_base, params->rgb_resulted, params->hw_points_num);
 724
 725        REG_UPDATE_2(CM_BLNDGAM_CONTROL,
 726                        CM_BLNDGAM_MODE, 2,
 727                        CM_BLNDGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
 728
 729        return true;
 730}
 731
 732
 733static void dpp3_program_shaper_lut(
 734                struct dpp *dpp_base,
 735                const struct pwl_result_data *rgb,
 736                uint32_t num)
 737{
 738        uint32_t i, red, green, blue;
 739        uint32_t  red_delta, green_delta, blue_delta;
 740        uint32_t  red_value, green_value, blue_value;
 741
 742        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 743
 744        for (i = 0 ; i < num; i++) {
 745
 746                red   = rgb[i].red_reg;
 747                green = rgb[i].green_reg;
 748                blue  = rgb[i].blue_reg;
 749
 750                red_delta   = rgb[i].delta_red_reg;
 751                green_delta = rgb[i].delta_green_reg;
 752                blue_delta  = rgb[i].delta_blue_reg;
 753
 754                red_value   = ((red_delta   & 0x3ff) << 14) | (red   & 0x3fff);
 755                green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
 756                blue_value  = ((blue_delta  & 0x3ff) << 14) | (blue  & 0x3fff);
 757
 758                REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);
 759                REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);
 760                REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);
 761        }
 762
 763}
 764
 765static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
 766{
 767        enum dc_lut_mode mode;
 768        uint32_t state_mode;
 769        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 770
 771        REG_GET(CM_SHAPER_CONTROL,
 772                        CM_SHAPER_MODE_CURRENT, &state_mode);
 773
 774                switch (state_mode) {
 775                case 0:
 776                        mode = LUT_BYPASS;
 777                        break;
 778                case 1:
 779                        mode = LUT_RAM_A;
 780                        break;
 781                case 2:
 782                        mode = LUT_RAM_B;
 783                        break;
 784                default:
 785                        mode = LUT_BYPASS;
 786                        break;
 787                }
 788                return mode;
 789}
 790
 791static void dpp3_configure_shaper_lut(
 792                struct dpp *dpp_base,
 793                bool is_ram_a)
 794{
 795        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 796
 797        REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
 798                        CM_SHAPER_LUT_WRITE_EN_MASK, 7);
 799        REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,
 800                        CM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
 801        REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);
 802}
 803
 804/*program shaper RAM A*/
 805
 806static void dpp3_program_shaper_luta_settings(
 807                struct dpp *dpp_base,
 808                const struct pwl_params *params)
 809{
 810        const struct gamma_curve *curve;
 811        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 812
 813        REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0,
 814                CM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
 815                CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 816        REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0,
 817                CM_SHAPER_RAMA_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
 818                CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, 0);
 819        REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0,
 820                CM_SHAPER_RAMA_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
 821                CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, 0);
 822
 823        REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0,
 824                CM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
 825                CM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
 826
 827        REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0,
 828                CM_SHAPER_RAMA_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
 829                CM_SHAPER_RAMA_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
 830
 831        REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0,
 832                CM_SHAPER_RAMA_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
 833                CM_SHAPER_RAMA_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
 834
 835        curve = params->arr_curve_points;
 836        REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0,
 837                CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 838                CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 839                CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 840                CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 841
 842        curve += 2;
 843        REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0,
 844                CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
 845                CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
 846                CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
 847                CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
 848
 849        curve += 2;
 850        REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0,
 851                CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
 852                CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
 853                CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
 854                CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
 855
 856        curve += 2;
 857        REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0,
 858                CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
 859                CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
 860                CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
 861                CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
 862
 863        curve += 2;
 864        REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0,
 865                CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
 866                CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
 867                CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
 868                CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
 869
 870        curve += 2;
 871        REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0,
 872                CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
 873                CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
 874                CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
 875                CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
 876
 877        curve += 2;
 878        REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0,
 879                CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
 880                CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
 881                CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
 882                CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
 883
 884        curve += 2;
 885        REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0,
 886                CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
 887                CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
 888                CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
 889                CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
 890
 891        curve += 2;
 892        REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0,
 893                CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
 894                CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
 895                CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
 896                CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
 897
 898        curve += 2;
 899        REG_SET_4(CM_SHAPER_RAMA_REGION_18_19, 0,
 900                CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
 901                CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
 902                CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
 903                CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
 904
 905        curve += 2;
 906        REG_SET_4(CM_SHAPER_RAMA_REGION_20_21, 0,
 907                CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
 908                CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
 909                CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
 910                CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
 911
 912        curve += 2;
 913        REG_SET_4(CM_SHAPER_RAMA_REGION_22_23, 0,
 914                CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
 915                CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
 916                CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
 917                CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
 918
 919        curve += 2;
 920        REG_SET_4(CM_SHAPER_RAMA_REGION_24_25, 0,
 921                CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
 922                CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
 923                CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
 924                CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
 925
 926        curve += 2;
 927        REG_SET_4(CM_SHAPER_RAMA_REGION_26_27, 0,
 928                CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
 929                CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
 930                CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
 931                CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
 932
 933        curve += 2;
 934        REG_SET_4(CM_SHAPER_RAMA_REGION_28_29, 0,
 935                CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
 936                CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
 937                CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
 938                CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
 939
 940        curve += 2;
 941        REG_SET_4(CM_SHAPER_RAMA_REGION_30_31, 0,
 942                CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
 943                CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
 944                CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
 945                CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
 946
 947        curve += 2;
 948        REG_SET_4(CM_SHAPER_RAMA_REGION_32_33, 0,
 949                CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
 950                CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
 951                CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
 952                CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
 953}
 954
 955/*program shaper RAM B*/
 956static void dpp3_program_shaper_lutb_settings(
 957                struct dpp *dpp_base,
 958                const struct pwl_params *params)
 959{
 960        const struct gamma_curve *curve;
 961        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
 962
 963        REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0,
 964                CM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
 965                CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0);
 966        REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0,
 967                CM_SHAPER_RAMB_EXP_REGION_START_G, params->corner_points[0].green.custom_float_x,
 968                CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, 0);
 969        REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0,
 970                CM_SHAPER_RAMB_EXP_REGION_START_R, params->corner_points[0].red.custom_float_x,
 971                CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, 0);
 972
 973        REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0,
 974                CM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
 975                CM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
 976
 977        REG_SET_2(CM_SHAPER_RAMB_END_CNTL_G, 0,
 978                CM_SHAPER_RAMB_EXP_REGION_END_G, params->corner_points[1].green.custom_float_x,
 979                CM_SHAPER_RAMB_EXP_REGION_END_BASE_G, params->corner_points[1].green.custom_float_y);
 980
 981        REG_SET_2(CM_SHAPER_RAMB_END_CNTL_R, 0,
 982                CM_SHAPER_RAMB_EXP_REGION_END_R, params->corner_points[1].red.custom_float_x,
 983                CM_SHAPER_RAMB_EXP_REGION_END_BASE_R, params->corner_points[1].red.custom_float_y);
 984
 985        curve = params->arr_curve_points;
 986        REG_SET_4(CM_SHAPER_RAMB_REGION_0_1, 0,
 987                CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 988                CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 989                CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 990                CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 991
 992        curve += 2;
 993        REG_SET_4(CM_SHAPER_RAMB_REGION_2_3, 0,
 994                CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
 995                CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
 996                CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
 997                CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
 998
 999        curve += 2;
1000        REG_SET_4(CM_SHAPER_RAMB_REGION_4_5, 0,
1001                CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
1002                CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
1003                CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
1004                CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
1005
1006        curve += 2;
1007        REG_SET_4(CM_SHAPER_RAMB_REGION_6_7, 0,
1008                CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
1009                CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
1010                CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
1011                CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
1012
1013        curve += 2;
1014        REG_SET_4(CM_SHAPER_RAMB_REGION_8_9, 0,
1015                CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
1016                CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
1017                CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
1018                CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
1019
1020        curve += 2;
1021        REG_SET_4(CM_SHAPER_RAMB_REGION_10_11, 0,
1022                CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
1023                CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
1024                CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
1025                CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
1026
1027        curve += 2;
1028        REG_SET_4(CM_SHAPER_RAMB_REGION_12_13, 0,
1029                CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
1030                CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
1031                CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
1032                CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
1033
1034        curve += 2;
1035        REG_SET_4(CM_SHAPER_RAMB_REGION_14_15, 0,
1036                CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
1037                CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
1038                CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
1039                CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
1040
1041        curve += 2;
1042        REG_SET_4(CM_SHAPER_RAMB_REGION_16_17, 0,
1043                CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
1044                CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
1045                CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
1046                CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
1047
1048        curve += 2;
1049        REG_SET_4(CM_SHAPER_RAMB_REGION_18_19, 0,
1050                CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
1051                CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
1052                CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
1053                CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
1054
1055        curve += 2;
1056        REG_SET_4(CM_SHAPER_RAMB_REGION_20_21, 0,
1057                CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
1058                CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
1059                CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
1060                CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
1061
1062        curve += 2;
1063        REG_SET_4(CM_SHAPER_RAMB_REGION_22_23, 0,
1064                CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
1065                CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
1066                CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
1067                CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
1068
1069        curve += 2;
1070        REG_SET_4(CM_SHAPER_RAMB_REGION_24_25, 0,
1071                CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
1072                CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
1073                CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
1074                CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
1075
1076        curve += 2;
1077        REG_SET_4(CM_SHAPER_RAMB_REGION_26_27, 0,
1078                CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
1079                CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
1080                CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
1081                CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
1082
1083        curve += 2;
1084        REG_SET_4(CM_SHAPER_RAMB_REGION_28_29, 0,
1085                CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
1086                CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
1087                CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
1088                CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
1089
1090        curve += 2;
1091        REG_SET_4(CM_SHAPER_RAMB_REGION_30_31, 0,
1092                CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
1093                CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
1094                CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
1095                CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
1096
1097        curve += 2;
1098        REG_SET_4(CM_SHAPER_RAMB_REGION_32_33, 0,
1099                CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
1100                CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
1101                CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
1102                CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
1103
1104}
1105
1106
1107bool dpp3_program_shaper(
1108                struct dpp *dpp_base,
1109                const struct pwl_params *params)
1110{
1111        enum dc_lut_mode current_mode;
1112        enum dc_lut_mode next_mode;
1113
1114        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1115
1116        if (params == NULL) {
1117                REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
1118                if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1119                        dpp3_power_on_shaper(dpp_base, false);
1120                return false;
1121        }
1122
1123        if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1124                dpp3_power_on_shaper(dpp_base, true);
1125
1126        current_mode = dpp3_get_shaper_current(dpp_base);
1127
1128        if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
1129                next_mode = LUT_RAM_B;
1130        else
1131                next_mode = LUT_RAM_A;
1132
1133        dpp3_configure_shaper_lut(dpp_base, next_mode == LUT_RAM_A);
1134
1135        if (next_mode == LUT_RAM_A)
1136                dpp3_program_shaper_luta_settings(dpp_base, params);
1137        else
1138                dpp3_program_shaper_lutb_settings(dpp_base, params);
1139
1140        dpp3_program_shaper_lut(
1141                        dpp_base, params->rgb_resulted, params->hw_points_num);
1142
1143        REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
1144
1145        return true;
1146
1147}
1148
1149static enum dc_lut_mode get3dlut_config(
1150                        struct dpp *dpp_base,
1151                        bool *is_17x17x17,
1152                        bool *is_12bits_color_channel)
1153{
1154        uint32_t i_mode, i_enable_10bits, lut_size;
1155        enum dc_lut_mode mode;
1156        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1157
1158        REG_GET(CM_3DLUT_READ_WRITE_CONTROL,
1159                        CM_3DLUT_30BIT_EN, &i_enable_10bits);
1160        REG_GET(CM_3DLUT_MODE,
1161                        CM_3DLUT_MODE_CURRENT, &i_mode);
1162
1163        switch (i_mode) {
1164        case 0:
1165                mode = LUT_BYPASS;
1166                break;
1167        case 1:
1168                mode = LUT_RAM_A;
1169                break;
1170        case 2:
1171                mode = LUT_RAM_B;
1172                break;
1173        default:
1174                mode = LUT_BYPASS;
1175                break;
1176        }
1177        if (i_enable_10bits > 0)
1178                *is_12bits_color_channel = false;
1179        else
1180                *is_12bits_color_channel = true;
1181
1182        REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size);
1183
1184        if (lut_size == 0)
1185                *is_17x17x17 = true;
1186        else
1187                *is_17x17x17 = false;
1188
1189        return mode;
1190}
1191/*
1192 * select ramA or ramB, or bypass
1193 * select color channel size 10 or 12 bits
1194 * select 3dlut size 17x17x17 or 9x9x9
1195 */
1196static void dpp3_set_3dlut_mode(
1197                struct dpp *dpp_base,
1198                enum dc_lut_mode mode,
1199                bool is_color_channel_12bits,
1200                bool is_lut_size17x17x17)
1201{
1202        uint32_t lut_mode;
1203        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1204
1205        if (mode == LUT_BYPASS)
1206                lut_mode = 0;
1207        else if (mode == LUT_RAM_A)
1208                lut_mode = 1;
1209        else
1210                lut_mode = 2;
1211
1212        REG_UPDATE_2(CM_3DLUT_MODE,
1213                        CM_3DLUT_MODE, lut_mode,
1214                        CM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
1215}
1216
1217static void dpp3_select_3dlut_ram(
1218                struct dpp *dpp_base,
1219                enum dc_lut_mode mode,
1220                bool is_color_channel_12bits)
1221{
1222        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1223
1224        REG_UPDATE_2(CM_3DLUT_READ_WRITE_CONTROL,
1225                        CM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
1226                        CM_3DLUT_30BIT_EN,
1227                        is_color_channel_12bits == true ? 0:1);
1228}
1229
1230
1231
1232static void dpp3_set3dlut_ram12(
1233                struct dpp *dpp_base,
1234                const struct dc_rgb *lut,
1235                uint32_t entries)
1236{
1237        uint32_t i, red, green, blue, red1, green1, blue1;
1238        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1239
1240        for (i = 0 ; i < entries; i += 2) {
1241                red   = lut[i].red<<4;
1242                green = lut[i].green<<4;
1243                blue  = lut[i].blue<<4;
1244                red1   = lut[i+1].red<<4;
1245                green1 = lut[i+1].green<<4;
1246                blue1  = lut[i+1].blue<<4;
1247
1248                REG_SET_2(CM_3DLUT_DATA, 0,
1249                                CM_3DLUT_DATA0, red,
1250                                CM_3DLUT_DATA1, red1);
1251
1252                REG_SET_2(CM_3DLUT_DATA, 0,
1253                                CM_3DLUT_DATA0, green,
1254                                CM_3DLUT_DATA1, green1);
1255
1256                REG_SET_2(CM_3DLUT_DATA, 0,
1257                                CM_3DLUT_DATA0, blue,
1258                                CM_3DLUT_DATA1, blue1);
1259
1260        }
1261}
1262
1263/*
1264 * load selected lut with 10 bits color channels
1265 */
1266static void dpp3_set3dlut_ram10(
1267                struct dpp *dpp_base,
1268                const struct dc_rgb *lut,
1269                uint32_t entries)
1270{
1271        uint32_t i, red, green, blue, value;
1272        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1273
1274        for (i = 0; i < entries; i++) {
1275                red   = lut[i].red;
1276                green = lut[i].green;
1277                blue  = lut[i].blue;
1278
1279                value = (red<<20) | (green<<10) | blue;
1280
1281                REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);
1282        }
1283
1284}
1285
1286
1287static void dpp3_select_3dlut_ram_mask(
1288                struct dpp *dpp_base,
1289                uint32_t ram_selection_mask)
1290{
1291        struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
1292
1293        REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,
1294                        ram_selection_mask);
1295        REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1296}
1297
1298bool dpp3_program_3dlut(
1299                struct dpp *dpp_base,
1300                struct tetrahedral_params *params)
1301{
1302        enum dc_lut_mode mode;
1303        bool is_17x17x17;
1304        bool is_12bits_color_channel;
1305        struct dc_rgb *lut0;
1306        struct dc_rgb *lut1;
1307        struct dc_rgb *lut2;
1308        struct dc_rgb *lut3;
1309        int lut_size0;
1310        int lut_size;
1311
1312        if (params == NULL) {
1313                dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
1314                if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1315                        dpp3_power_on_hdr3dlut(dpp_base, false);
1316                return false;
1317        }
1318
1319        if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
1320                dpp3_power_on_hdr3dlut(dpp_base, true);
1321
1322        mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
1323
1324        if (mode == LUT_BYPASS || mode == LUT_RAM_B)
1325                mode = LUT_RAM_A;
1326        else
1327                mode = LUT_RAM_B;
1328
1329        is_17x17x17 = !params->use_tetrahedral_9;
1330        is_12bits_color_channel = params->use_12bits;
1331        if (is_17x17x17) {
1332                lut0 = params->tetrahedral_17.lut0;
1333                lut1 = params->tetrahedral_17.lut1;
1334                lut2 = params->tetrahedral_17.lut2;
1335                lut3 = params->tetrahedral_17.lut3;
1336                lut_size0 = sizeof(params->tetrahedral_17.lut0)/
1337                                        sizeof(params->tetrahedral_17.lut0[0]);
1338                lut_size  = sizeof(params->tetrahedral_17.lut1)/
1339                                        sizeof(params->tetrahedral_17.lut1[0]);
1340        } else {
1341                lut0 = params->tetrahedral_9.lut0;
1342                lut1 = params->tetrahedral_9.lut1;
1343                lut2 = params->tetrahedral_9.lut2;
1344                lut3 = params->tetrahedral_9.lut3;
1345                lut_size0 = sizeof(params->tetrahedral_9.lut0)/
1346                                sizeof(params->tetrahedral_9.lut0[0]);
1347                lut_size  = sizeof(params->tetrahedral_9.lut1)/
1348                                sizeof(params->tetrahedral_9.lut1[0]);
1349                }
1350
1351        dpp3_select_3dlut_ram(dpp_base, mode,
1352                                is_12bits_color_channel);
1353        dpp3_select_3dlut_ram_mask(dpp_base, 0x1);
1354        if (is_12bits_color_channel)
1355                dpp3_set3dlut_ram12(dpp_base, lut0, lut_size0);
1356        else
1357                dpp3_set3dlut_ram10(dpp_base, lut0, lut_size0);
1358
1359        dpp3_select_3dlut_ram_mask(dpp_base, 0x2);
1360        if (is_12bits_color_channel)
1361                dpp3_set3dlut_ram12(dpp_base, lut1, lut_size);
1362        else
1363                dpp3_set3dlut_ram10(dpp_base, lut1, lut_size);
1364
1365        dpp3_select_3dlut_ram_mask(dpp_base, 0x4);
1366        if (is_12bits_color_channel)
1367                dpp3_set3dlut_ram12(dpp_base, lut2, lut_size);
1368        else
1369                dpp3_set3dlut_ram10(dpp_base, lut2, lut_size);
1370
1371        dpp3_select_3dlut_ram_mask(dpp_base, 0x8);
1372        if (is_12bits_color_channel)
1373                dpp3_set3dlut_ram12(dpp_base, lut3, lut_size);
1374        else
1375                dpp3_set3dlut_ram10(dpp_base, lut3, lut_size);
1376
1377
1378        dpp3_set_3dlut_mode(dpp_base, mode, is_12bits_color_channel,
1379                                        is_17x17x17);
1380
1381        return true;
1382}
1383static struct dpp_funcs dcn30_dpp_funcs = {
1384        .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
1385        .dpp_read_state                 = dpp30_read_state,
1386        .dpp_reset                      = dpp_reset,
1387        .dpp_set_scaler                 = dpp1_dscl_set_scaler_manual_scale,
1388        .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
1389        .dpp_set_gamut_remap            = dpp3_cm_set_gamut_remap,
1390        .dpp_set_csc_adjustment         = NULL,
1391        .dpp_set_csc_default            = NULL,
1392        .dpp_program_regamma_pwl        = NULL,
1393        .dpp_set_pre_degam              = dpp3_set_pre_degam,
1394        .dpp_program_input_lut          = NULL,
1395        .dpp_full_bypass                = dpp1_full_bypass,
1396        .dpp_setup                      = dpp3_cnv_setup,
1397        .dpp_program_degamma_pwl        = NULL,
1398        .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
1399        .dpp_program_cm_bias = dpp3_program_cm_bias,
1400        .dpp_program_blnd_lut = dpp3_program_blnd_lut,
1401        .dpp_program_shaper_lut = dpp3_program_shaper,
1402        .dpp_program_3dlut = dpp3_program_3dlut,
1403        .dpp_program_bias_and_scale     = NULL,
1404        .dpp_cnv_set_alpha_keyer        = dpp2_cnv_set_alpha_keyer,
1405        .set_cursor_attributes          = dpp3_set_cursor_attributes,
1406        .set_cursor_position            = dpp1_set_cursor_position,
1407        .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
1408        .dpp_dppclk_control             = dpp1_dppclk_control,
1409        .dpp_set_hdr_multiplier         = dpp3_set_hdr_multiplier,
1410};
1411
1412
1413static struct dpp_caps dcn30_dpp_cap = {
1414        .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
1415        .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
1416};
1417
1418bool dpp3_construct(
1419        struct dcn3_dpp *dpp,
1420        struct dc_context *ctx,
1421        uint32_t inst,
1422        const struct dcn3_dpp_registers *tf_regs,
1423        const struct dcn3_dpp_shift *tf_shift,
1424        const struct dcn3_dpp_mask *tf_mask)
1425{
1426        dpp->base.ctx = ctx;
1427
1428        dpp->base.inst = inst;
1429        dpp->base.funcs = &dcn30_dpp_funcs;
1430        dpp->base.caps = &dcn30_dpp_cap;
1431
1432        dpp->tf_regs = tf_regs;
1433        dpp->tf_shift = tf_shift;
1434        dpp->tf_mask = tf_mask;
1435
1436        return true;
1437}
1438
1439
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