linux/arch/x86/include/asm/processor.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef _ASM_X86_PROCESSOR_H
   3#define _ASM_X86_PROCESSOR_H
   4
   5#include <asm/processor-flags.h>
   6
   7/* Forward declaration, a strange C thing */
   8struct task_struct;
   9struct mm_struct;
  10struct io_bitmap;
  11struct vm86;
  12
  13#include <asm/math_emu.h>
  14#include <asm/segment.h>
  15#include <asm/types.h>
  16#include <uapi/asm/sigcontext.h>
  17#include <asm/current.h>
  18#include <asm/cpufeatures.h>
  19#include <asm/page.h>
  20#include <asm/pgtable_types.h>
  21#include <asm/percpu.h>
  22#include <asm/msr.h>
  23#include <asm/desc_defs.h>
  24#include <asm/nops.h>
  25#include <asm/special_insns.h>
  26#include <asm/fpu/types.h>
  27#include <asm/unwind_hints.h>
  28#include <asm/vmxfeatures.h>
  29#include <asm/vdso/processor.h>
  30
  31#include <linux/personality.h>
  32#include <linux/cache.h>
  33#include <linux/threads.h>
  34#include <linux/math64.h>
  35#include <linux/err.h>
  36#include <linux/irqflags.h>
  37#include <linux/mem_encrypt.h>
  38
  39/*
  40 * We handle most unaligned accesses in hardware.  On the other hand
  41 * unaligned DMA can be quite expensive on some Nehalem processors.
  42 *
  43 * Based on this we disable the IP header alignment in network drivers.
  44 */
  45#define NET_IP_ALIGN    0
  46
  47#define HBP_NUM 4
  48
  49/*
  50 * These alignment constraints are for performance in the vSMP case,
  51 * but in the task_struct case we must also meet hardware imposed
  52 * alignment requirements of the FPU state:
  53 */
  54#ifdef CONFIG_X86_VSMP
  55# define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  56# define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  57#else
  58# define ARCH_MIN_TASKALIGN             __alignof__(union fpregs_state)
  59# define ARCH_MIN_MMSTRUCT_ALIGN        0
  60#endif
  61
  62enum tlb_infos {
  63        ENTRIES,
  64        NR_INFO
  65};
  66
  67extern u16 __read_mostly tlb_lli_4k[NR_INFO];
  68extern u16 __read_mostly tlb_lli_2m[NR_INFO];
  69extern u16 __read_mostly tlb_lli_4m[NR_INFO];
  70extern u16 __read_mostly tlb_lld_4k[NR_INFO];
  71extern u16 __read_mostly tlb_lld_2m[NR_INFO];
  72extern u16 __read_mostly tlb_lld_4m[NR_INFO];
  73extern u16 __read_mostly tlb_lld_1g[NR_INFO];
  74
  75/*
  76 *  CPU type and hardware bug flags. Kept separately for each CPU.
  77 *  Members of this structure are referenced in head_32.S, so think twice
  78 *  before touching them. [mj]
  79 */
  80
  81struct cpuinfo_x86 {
  82        __u8                    x86;            /* CPU family */
  83        __u8                    x86_vendor;     /* CPU vendor */
  84        __u8                    x86_model;
  85        __u8                    x86_stepping;
  86#ifdef CONFIG_X86_64
  87        /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  88        int                     x86_tlbsize;
  89#endif
  90#ifdef CONFIG_X86_VMX_FEATURE_NAMES
  91        __u32                   vmx_capability[NVMXINTS];
  92#endif
  93        __u8                    x86_virt_bits;
  94        __u8                    x86_phys_bits;
  95        /* CPUID returned core id bits: */
  96        __u8                    x86_coreid_bits;
  97        __u8                    cu_id;
  98        /* Max extended CPUID function supported: */
  99        __u32                   extended_cpuid_level;
 100        /* Maximum supported CPUID level, -1=no CPUID: */
 101        int                     cpuid_level;
 102        /*
 103         * Align to size of unsigned long because the x86_capability array
 104         * is passed to bitops which require the alignment. Use unnamed
 105         * union to enforce the array is aligned to size of unsigned long.
 106         */
 107        union {
 108                __u32           x86_capability[NCAPINTS + NBUGINTS];
 109                unsigned long   x86_capability_alignment;
 110        };
 111        char                    x86_vendor_id[16];
 112        char                    x86_model_id[64];
 113        /* in KB - valid for CPUS which support this call: */
 114        unsigned int            x86_cache_size;
 115        int                     x86_cache_alignment;    /* In bytes */
 116        /* Cache QoS architectural values, valid only on the BSP: */
 117        int                     x86_cache_max_rmid;     /* max index */
 118        int                     x86_cache_occ_scale;    /* scale to bytes */
 119        int                     x86_cache_mbm_width_offset;
 120        int                     x86_power;
 121        unsigned long           loops_per_jiffy;
 122        /* cpuid returned max cores value: */
 123        u16                     x86_max_cores;
 124        u16                     apicid;
 125        u16                     initial_apicid;
 126        u16                     x86_clflush_size;
 127        /* number of cores as seen by the OS: */
 128        u16                     booted_cores;
 129        /* Physical processor id: */
 130        u16                     phys_proc_id;
 131        /* Logical processor id: */
 132        u16                     logical_proc_id;
 133        /* Core id: */
 134        u16                     cpu_core_id;
 135        u16                     cpu_die_id;
 136        u16                     logical_die_id;
 137        /* Index into per_cpu list: */
 138        u16                     cpu_index;
 139        u32                     microcode;
 140        /* Address space bits used by the cache internally */
 141        u8                      x86_cache_bits;
 142        unsigned                initialized : 1;
 143} __randomize_layout;
 144
 145struct cpuid_regs {
 146        u32 eax, ebx, ecx, edx;
 147};
 148
 149enum cpuid_regs_idx {
 150        CPUID_EAX = 0,
 151        CPUID_EBX,
 152        CPUID_ECX,
 153        CPUID_EDX,
 154};
 155
 156#define X86_VENDOR_INTEL        0
 157#define X86_VENDOR_CYRIX        1
 158#define X86_VENDOR_AMD          2
 159#define X86_VENDOR_UMC          3
 160#define X86_VENDOR_CENTAUR      5
 161#define X86_VENDOR_TRANSMETA    7
 162#define X86_VENDOR_NSC          8
 163#define X86_VENDOR_HYGON        9
 164#define X86_VENDOR_ZHAOXIN      10
 165#define X86_VENDOR_NUM          11
 166
 167#define X86_VENDOR_UNKNOWN      0xff
 168
 169/*
 170 * capabilities of CPUs
 171 */
 172extern struct cpuinfo_x86       boot_cpu_data;
 173extern struct cpuinfo_x86       new_cpu_data;
 174
 175extern __u32                    cpu_caps_cleared[NCAPINTS + NBUGINTS];
 176extern __u32                    cpu_caps_set[NCAPINTS + NBUGINTS];
 177
 178#ifdef CONFIG_SMP
 179DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
 180#define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 181#else
 182#define cpu_info                boot_cpu_data
 183#define cpu_data(cpu)           boot_cpu_data
 184#endif
 185
 186extern const struct seq_operations cpuinfo_op;
 187
 188#define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 189
 190extern void cpu_detect(struct cpuinfo_x86 *c);
 191
 192static inline unsigned long long l1tf_pfn_limit(void)
 193{
 194        return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
 195}
 196
 197extern void early_cpu_init(void);
 198extern void identify_boot_cpu(void);
 199extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 200extern void print_cpu_info(struct cpuinfo_x86 *);
 201void print_cpu_msr(struct cpuinfo_x86 *);
 202
 203#ifdef CONFIG_X86_32
 204extern int have_cpuid_p(void);
 205#else
 206static inline int have_cpuid_p(void)
 207{
 208        return 1;
 209}
 210#endif
 211static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 212                                unsigned int *ecx, unsigned int *edx)
 213{
 214        /* ecx is often an input as well as an output. */
 215        asm volatile("cpuid"
 216            : "=a" (*eax),
 217              "=b" (*ebx),
 218              "=c" (*ecx),
 219              "=d" (*edx)
 220            : "0" (*eax), "2" (*ecx)
 221            : "memory");
 222}
 223
 224#define native_cpuid_reg(reg)                                   \
 225static inline unsigned int native_cpuid_##reg(unsigned int op)  \
 226{                                                               \
 227        unsigned int eax = op, ebx, ecx = 0, edx;               \
 228                                                                \
 229        native_cpuid(&eax, &ebx, &ecx, &edx);                   \
 230                                                                \
 231        return reg;                                             \
 232}
 233
 234/*
 235 * Native CPUID functions returning a single datum.
 236 */
 237native_cpuid_reg(eax)
 238native_cpuid_reg(ebx)
 239native_cpuid_reg(ecx)
 240native_cpuid_reg(edx)
 241
 242/*
 243 * Friendlier CR3 helpers.
 244 */
 245static inline unsigned long read_cr3_pa(void)
 246{
 247        return __read_cr3() & CR3_ADDR_MASK;
 248}
 249
 250static inline unsigned long native_read_cr3_pa(void)
 251{
 252        return __native_read_cr3() & CR3_ADDR_MASK;
 253}
 254
 255static inline void load_cr3(pgd_t *pgdir)
 256{
 257        write_cr3(__sme_pa(pgdir));
 258}
 259
 260/*
 261 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
 262 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
 263 * unrelated to the task-switch mechanism:
 264 */
 265#ifdef CONFIG_X86_32
 266/* This is the TSS defined by the hardware. */
 267struct x86_hw_tss {
 268        unsigned short          back_link, __blh;
 269        unsigned long           sp0;
 270        unsigned short          ss0, __ss0h;
 271        unsigned long           sp1;
 272
 273        /*
 274         * We don't use ring 1, so ss1 is a convenient scratch space in
 275         * the same cacheline as sp0.  We use ss1 to cache the value in
 276         * MSR_IA32_SYSENTER_CS.  When we context switch
 277         * MSR_IA32_SYSENTER_CS, we first check if the new value being
 278         * written matches ss1, and, if it's not, then we wrmsr the new
 279         * value and update ss1.
 280         *
 281         * The only reason we context switch MSR_IA32_SYSENTER_CS is
 282         * that we set it to zero in vm86 tasks to avoid corrupting the
 283         * stack if we were to go through the sysenter path from vm86
 284         * mode.
 285         */
 286        unsigned short          ss1;    /* MSR_IA32_SYSENTER_CS */
 287
 288        unsigned short          __ss1h;
 289        unsigned long           sp2;
 290        unsigned short          ss2, __ss2h;
 291        unsigned long           __cr3;
 292        unsigned long           ip;
 293        unsigned long           flags;
 294        unsigned long           ax;
 295        unsigned long           cx;
 296        unsigned long           dx;
 297        unsigned long           bx;
 298        unsigned long           sp;
 299        unsigned long           bp;
 300        unsigned long           si;
 301        unsigned long           di;
 302        unsigned short          es, __esh;
 303        unsigned short          cs, __csh;
 304        unsigned short          ss, __ssh;
 305        unsigned short          ds, __dsh;
 306        unsigned short          fs, __fsh;
 307        unsigned short          gs, __gsh;
 308        unsigned short          ldt, __ldth;
 309        unsigned short          trace;
 310        unsigned short          io_bitmap_base;
 311
 312} __attribute__((packed));
 313#else
 314struct x86_hw_tss {
 315        u32                     reserved1;
 316        u64                     sp0;
 317        u64                     sp1;
 318
 319        /*
 320         * Since Linux does not use ring 2, the 'sp2' slot is unused by
 321         * hardware.  entry_SYSCALL_64 uses it as scratch space to stash
 322         * the user RSP value.
 323         */
 324        u64                     sp2;
 325
 326        u64                     reserved2;
 327        u64                     ist[7];
 328        u32                     reserved3;
 329        u32                     reserved4;
 330        u16                     reserved5;
 331        u16                     io_bitmap_base;
 332
 333} __attribute__((packed));
 334#endif
 335
 336/*
 337 * IO-bitmap sizes:
 338 */
 339#define IO_BITMAP_BITS                  65536
 340#define IO_BITMAP_BYTES                 (IO_BITMAP_BITS / BITS_PER_BYTE)
 341#define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES / sizeof(long))
 342
 343#define IO_BITMAP_OFFSET_VALID_MAP                              \
 344        (offsetof(struct tss_struct, io_bitmap.bitmap) -        \
 345         offsetof(struct tss_struct, x86_tss))
 346
 347#define IO_BITMAP_OFFSET_VALID_ALL                              \
 348        (offsetof(struct tss_struct, io_bitmap.mapall) -        \
 349         offsetof(struct tss_struct, x86_tss))
 350
 351#ifdef CONFIG_X86_IOPL_IOPERM
 352/*
 353 * sizeof(unsigned long) coming from an extra "long" at the end of the
 354 * iobitmap. The limit is inclusive, i.e. the last valid byte.
 355 */
 356# define __KERNEL_TSS_LIMIT     \
 357        (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \
 358         sizeof(unsigned long) - 1)
 359#else
 360# define __KERNEL_TSS_LIMIT     \
 361        (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1)
 362#endif
 363
 364/* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */
 365#define IO_BITMAP_OFFSET_INVALID        (__KERNEL_TSS_LIMIT + 1)
 366
 367struct entry_stack {
 368        char    stack[PAGE_SIZE];
 369};
 370
 371struct entry_stack_page {
 372        struct entry_stack stack;
 373} __aligned(PAGE_SIZE);
 374
 375/*
 376 * All IO bitmap related data stored in the TSS:
 377 */
 378struct x86_io_bitmap {
 379        /* The sequence number of the last active bitmap. */
 380        u64                     prev_sequence;
 381
 382        /*
 383         * Store the dirty size of the last io bitmap offender. The next
 384         * one will have to do the cleanup as the switch out to a non io
 385         * bitmap user will just set x86_tss.io_bitmap_base to a value
 386         * outside of the TSS limit. So for sane tasks there is no need to
 387         * actually touch the io_bitmap at all.
 388         */
 389        unsigned int            prev_max;
 390
 391        /*
 392         * The extra 1 is there because the CPU will access an
 393         * additional byte beyond the end of the IO permission
 394         * bitmap. The extra byte must be all 1 bits, and must
 395         * be within the limit.
 396         */
 397        unsigned long           bitmap[IO_BITMAP_LONGS + 1];
 398
 399        /*
 400         * Special I/O bitmap to emulate IOPL(3). All bytes zero,
 401         * except the additional byte at the end.
 402         */
 403        unsigned long           mapall[IO_BITMAP_LONGS + 1];
 404};
 405
 406struct tss_struct {
 407        /*
 408         * The fixed hardware portion.  This must not cross a page boundary
 409         * at risk of violating the SDM's advice and potentially triggering
 410         * errata.
 411         */
 412        struct x86_hw_tss       x86_tss;
 413
 414        struct x86_io_bitmap    io_bitmap;
 415} __aligned(PAGE_SIZE);
 416
 417DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
 418
 419/* Per CPU interrupt stacks */
 420struct irq_stack {
 421        char            stack[IRQ_STACK_SIZE];
 422} __aligned(IRQ_STACK_SIZE);
 423
 424DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
 425
 426#ifdef CONFIG_X86_64
 427struct fixed_percpu_data {
 428        /*
 429         * GCC hardcodes the stack canary as %gs:40.  Since the
 430         * irq_stack is the object at %gs:0, we reserve the bottom
 431         * 48 bytes of the irq stack for the canary.
 432         *
 433         * Once we are willing to require -mstack-protector-guard-symbol=
 434         * support for x86_64 stackprotector, we can get rid of this.
 435         */
 436        char            gs_base[40];
 437        unsigned long   stack_canary;
 438};
 439
 440DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
 441DECLARE_INIT_PER_CPU(fixed_percpu_data);
 442
 443static inline unsigned long cpu_kernelmode_gs_base(int cpu)
 444{
 445        return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
 446}
 447
 448DECLARE_PER_CPU(void *, hardirq_stack_ptr);
 449DECLARE_PER_CPU(bool, hardirq_stack_inuse);
 450extern asmlinkage void ignore_sysret(void);
 451
 452/* Save actual FS/GS selectors and bases to current->thread */
 453void current_save_fsgs(void);
 454#else   /* X86_64 */
 455#ifdef CONFIG_STACKPROTECTOR
 456DECLARE_PER_CPU(unsigned long, __stack_chk_guard);
 457#endif
 458DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
 459DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr);
 460#endif  /* !X86_64 */
 461
 462extern unsigned int fpu_kernel_xstate_size;
 463extern unsigned int fpu_user_xstate_size;
 464
 465struct perf_event;
 466
 467struct thread_struct {
 468        /* Cached TLS descriptors: */
 469        struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 470#ifdef CONFIG_X86_32
 471        unsigned long           sp0;
 472#endif
 473        unsigned long           sp;
 474#ifdef CONFIG_X86_32
 475        unsigned long           sysenter_cs;
 476#else
 477        unsigned short          es;
 478        unsigned short          ds;
 479        unsigned short          fsindex;
 480        unsigned short          gsindex;
 481#endif
 482
 483#ifdef CONFIG_X86_64
 484        unsigned long           fsbase;
 485        unsigned long           gsbase;
 486#else
 487        /*
 488         * XXX: this could presumably be unsigned short.  Alternatively,
 489         * 32-bit kernels could be taught to use fsindex instead.
 490         */
 491        unsigned long fs;
 492        unsigned long gs;
 493#endif
 494
 495        /* Save middle states of ptrace breakpoints */
 496        struct perf_event       *ptrace_bps[HBP_NUM];
 497        /* Debug status used for traps, single steps, etc... */
 498        unsigned long           virtual_dr6;
 499        /* Keep track of the exact dr7 value set by the user */
 500        unsigned long           ptrace_dr7;
 501        /* Fault info: */
 502        unsigned long           cr2;
 503        unsigned long           trap_nr;
 504        unsigned long           error_code;
 505#ifdef CONFIG_VM86
 506        /* Virtual 86 mode info */
 507        struct vm86             *vm86;
 508#endif
 509        /* IO permissions: */
 510        struct io_bitmap        *io_bitmap;
 511
 512        /*
 513         * IOPL. Privilege level dependent I/O permission which is
 514         * emulated via the I/O bitmap to prevent user space from disabling
 515         * interrupts.
 516         */
 517        unsigned long           iopl_emul;
 518
 519        unsigned int            sig_on_uaccess_err:1;
 520
 521        /*
 522         * Protection Keys Register for Userspace.  Loaded immediately on
 523         * context switch. Store it in thread_struct to avoid a lookup in
 524         * the tasks's FPU xstate buffer. This value is only valid when a
 525         * task is scheduled out. For 'current' the authoritative source of
 526         * PKRU is the hardware itself.
 527         */
 528        u32                     pkru;
 529
 530        /* Floating point and extended processor state */
 531        struct fpu              fpu;
 532        /*
 533         * WARNING: 'fpu' is dynamically-sized.  It *MUST* be at
 534         * the end.
 535         */
 536};
 537
 538/* Whitelist the FPU state from the task_struct for hardened usercopy. */
 539static inline void arch_thread_struct_whitelist(unsigned long *offset,
 540                                                unsigned long *size)
 541{
 542        *offset = offsetof(struct thread_struct, fpu.state);
 543        *size = fpu_kernel_xstate_size;
 544}
 545
 546static inline void
 547native_load_sp0(unsigned long sp0)
 548{
 549        this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
 550}
 551
 552static __always_inline void native_swapgs(void)
 553{
 554#ifdef CONFIG_X86_64
 555        asm volatile("swapgs" ::: "memory");
 556#endif
 557}
 558
 559static inline unsigned long current_top_of_stack(void)
 560{
 561        /*
 562         *  We can't read directly from tss.sp0: sp0 on x86_32 is special in
 563         *  and around vm86 mode and sp0 on x86_64 is special because of the
 564         *  entry trampoline.
 565         */
 566        return this_cpu_read_stable(cpu_current_top_of_stack);
 567}
 568
 569static inline bool on_thread_stack(void)
 570{
 571        return (unsigned long)(current_top_of_stack() -
 572                               current_stack_pointer) < THREAD_SIZE;
 573}
 574
 575#ifdef CONFIG_PARAVIRT_XXL
 576#include <asm/paravirt.h>
 577#else
 578#define __cpuid                 native_cpuid
 579
 580static inline void load_sp0(unsigned long sp0)
 581{
 582        native_load_sp0(sp0);
 583}
 584
 585#endif /* CONFIG_PARAVIRT_XXL */
 586
 587/* Free all resources held by a thread. */
 588extern void release_thread(struct task_struct *);
 589
 590unsigned long get_wchan(struct task_struct *p);
 591
 592/*
 593 * Generic CPUID function
 594 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 595 * resulting in stale register contents being returned.
 596 */
 597static inline void cpuid(unsigned int op,
 598                         unsigned int *eax, unsigned int *ebx,
 599                         unsigned int *ecx, unsigned int *edx)
 600{
 601        *eax = op;
 602        *ecx = 0;
 603        __cpuid(eax, ebx, ecx, edx);
 604}
 605
 606/* Some CPUID calls want 'count' to be placed in ecx */
 607static inline void cpuid_count(unsigned int op, int count,
 608                               unsigned int *eax, unsigned int *ebx,
 609                               unsigned int *ecx, unsigned int *edx)
 610{
 611        *eax = op;
 612        *ecx = count;
 613        __cpuid(eax, ebx, ecx, edx);
 614}
 615
 616/*
 617 * CPUID functions returning a single datum
 618 */
 619static inline unsigned int cpuid_eax(unsigned int op)
 620{
 621        unsigned int eax, ebx, ecx, edx;
 622
 623        cpuid(op, &eax, &ebx, &ecx, &edx);
 624
 625        return eax;
 626}
 627
 628static inline unsigned int cpuid_ebx(unsigned int op)
 629{
 630        unsigned int eax, ebx, ecx, edx;
 631
 632        cpuid(op, &eax, &ebx, &ecx, &edx);
 633
 634        return ebx;
 635}
 636
 637static inline unsigned int cpuid_ecx(unsigned int op)
 638{
 639        unsigned int eax, ebx, ecx, edx;
 640
 641        cpuid(op, &eax, &ebx, &ecx, &edx);
 642
 643        return ecx;
 644}
 645
 646static inline unsigned int cpuid_edx(unsigned int op)
 647{
 648        unsigned int eax, ebx, ecx, edx;
 649
 650        cpuid(op, &eax, &ebx, &ecx, &edx);
 651
 652        return edx;
 653}
 654
 655extern void select_idle_routine(const struct cpuinfo_x86 *c);
 656extern void amd_e400_c1e_apic_setup(void);
 657
 658extern unsigned long            boot_option_idle_override;
 659
 660enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 661                         IDLE_POLL};
 662
 663extern void enable_sep_cpu(void);
 664extern int sysenter_setup(void);
 665
 666
 667/* Defined in head.S */
 668extern struct desc_ptr          early_gdt_descr;
 669
 670extern void switch_to_new_gdt(int);
 671extern void load_direct_gdt(int);
 672extern void load_fixmap_gdt(int);
 673extern void load_percpu_segment(int);
 674extern void cpu_init(void);
 675extern void cpu_init_secondary(void);
 676extern void cpu_init_exception_handling(void);
 677extern void cr4_init(void);
 678
 679static inline unsigned long get_debugctlmsr(void)
 680{
 681        unsigned long debugctlmsr = 0;
 682
 683#ifndef CONFIG_X86_DEBUGCTLMSR
 684        if (boot_cpu_data.x86 < 6)
 685                return 0;
 686#endif
 687        rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 688
 689        return debugctlmsr;
 690}
 691
 692static inline void update_debugctlmsr(unsigned long debugctlmsr)
 693{
 694#ifndef CONFIG_X86_DEBUGCTLMSR
 695        if (boot_cpu_data.x86 < 6)
 696                return;
 697#endif
 698        wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 699}
 700
 701extern void set_task_blockstep(struct task_struct *task, bool on);
 702
 703/* Boot loader type from the setup header: */
 704extern int                      bootloader_type;
 705extern int                      bootloader_version;
 706
 707extern char                     ignore_fpu_irq;
 708
 709#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 710#define ARCH_HAS_PREFETCHW
 711#define ARCH_HAS_SPINLOCK_PREFETCH
 712
 713#ifdef CONFIG_X86_32
 714# define BASE_PREFETCH          ""
 715# define ARCH_HAS_PREFETCH
 716#else
 717# define BASE_PREFETCH          "prefetcht0 %P1"
 718#endif
 719
 720/*
 721 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 722 *
 723 * It's not worth to care about 3dnow prefetches for the K6
 724 * because they are microcoded there and very slow.
 725 */
 726static inline void prefetch(const void *x)
 727{
 728        alternative_input(BASE_PREFETCH, "prefetchnta %P1",
 729                          X86_FEATURE_XMM,
 730                          "m" (*(const char *)x));
 731}
 732
 733/*
 734 * 3dnow prefetch to get an exclusive cache line.
 735 * Useful for spinlocks to avoid one state transition in the
 736 * cache coherency protocol:
 737 */
 738static __always_inline void prefetchw(const void *x)
 739{
 740        alternative_input(BASE_PREFETCH, "prefetchw %P1",
 741                          X86_FEATURE_3DNOWPREFETCH,
 742                          "m" (*(const char *)x));
 743}
 744
 745static inline void spin_lock_prefetch(const void *x)
 746{
 747        prefetchw(x);
 748}
 749
 750#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
 751                           TOP_OF_KERNEL_STACK_PADDING)
 752
 753#define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
 754
 755#define task_pt_regs(task) \
 756({                                                                      \
 757        unsigned long __ptr = (unsigned long)task_stack_page(task);     \
 758        __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;             \
 759        ((struct pt_regs *)__ptr) - 1;                                  \
 760})
 761
 762#ifdef CONFIG_X86_32
 763#define INIT_THREAD  {                                                    \
 764        .sp0                    = TOP_OF_INIT_STACK,                      \
 765        .sysenter_cs            = __KERNEL_CS,                            \
 766}
 767
 768#define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 769
 770#else
 771#define INIT_THREAD { }
 772
 773extern unsigned long KSTK_ESP(struct task_struct *task);
 774
 775#endif /* CONFIG_X86_64 */
 776
 777extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 778                                               unsigned long new_sp);
 779
 780/*
 781 * This decides where the kernel will search for a free chunk of vm
 782 * space during mmap's.
 783 */
 784#define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
 785#define TASK_UNMAPPED_BASE              __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
 786
 787#define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 788
 789/* Get/set a process' ability to use the timestamp counter instruction */
 790#define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 791#define SET_TSC_CTL(val)        set_tsc_mode((val))
 792
 793extern int get_tsc_mode(unsigned long adr);
 794extern int set_tsc_mode(unsigned int val);
 795
 796DECLARE_PER_CPU(u64, msr_misc_features_shadow);
 797
 798#ifdef CONFIG_CPU_SUP_AMD
 799extern u32 amd_get_nodes_per_socket(void);
 800extern u32 amd_get_highest_perf(void);
 801#else
 802static inline u32 amd_get_nodes_per_socket(void)        { return 0; }
 803static inline u32 amd_get_highest_perf(void)            { return 0; }
 804#endif
 805
 806static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
 807{
 808        uint32_t base, eax, signature[3];
 809
 810        for (base = 0x40000000; base < 0x40010000; base += 0x100) {
 811                cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
 812
 813                if (!memcmp(sig, signature, 12) &&
 814                    (leaves == 0 || ((eax - base) >= leaves)))
 815                        return base;
 816        }
 817
 818        return 0;
 819}
 820
 821extern unsigned long arch_align_stack(unsigned long sp);
 822void free_init_pages(const char *what, unsigned long begin, unsigned long end);
 823extern void free_kernel_image_pages(const char *what, void *begin, void *end);
 824
 825void default_idle(void);
 826#ifdef  CONFIG_XEN
 827bool xen_set_default_idle(void);
 828#else
 829#define xen_set_default_idle 0
 830#endif
 831
 832void stop_this_cpu(void *dummy);
 833void microcode_check(void);
 834
 835enum l1tf_mitigations {
 836        L1TF_MITIGATION_OFF,
 837        L1TF_MITIGATION_FLUSH_NOWARN,
 838        L1TF_MITIGATION_FLUSH,
 839        L1TF_MITIGATION_FLUSH_NOSMT,
 840        L1TF_MITIGATION_FULL,
 841        L1TF_MITIGATION_FULL_FORCE
 842};
 843
 844extern enum l1tf_mitigations l1tf_mitigation;
 845
 846enum mds_mitigations {
 847        MDS_MITIGATION_OFF,
 848        MDS_MITIGATION_FULL,
 849        MDS_MITIGATION_VMWERV,
 850};
 851
 852#endif /* _ASM_X86_PROCESSOR_H */
 853
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