linux/arch/arc/include/asm/pgtable.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   4 *
   5 * vineetg: May 2011
   6 *  -Folded PAGE_PRESENT (used by VM) and PAGE_VALID (used by MMU) into 1.
   7 *     They are semantically the same although in different contexts
   8 *     VALID marks a TLB entry exists and it will only happen if PRESENT
   9 *  - Utilise some unused free bits to confine PTE flags to 12 bits
  10 *     This is a must for 4k pg-sz
  11 *
  12 * vineetg: Mar 2011 - changes to accommodate MMU TLB Page Descriptor mods
  13 *  -TLB Locking never really existed, except for initial specs
  14 *  -SILENT_xxx not needed for our port
  15 *  -Per my request, MMU V3 changes the layout of some of the bits
  16 *     to avoid a few shifts in TLB Miss handlers.
  17 *
  18 * vineetg: April 2010
  19 *  -PGD entry no longer contains any flags. If empty it is 0, otherwise has
  20 *   Pg-Tbl ptr. Thus pmd_present(), pmd_valid(), pmd_set( ) become simpler
  21 *
  22 * vineetg: April 2010
  23 *  -Switched form 8:11:13 split for page table lookup to 11:8:13
  24 *  -this speeds up page table allocation itself as we now have to memset 1K
  25 *    instead of 8k per page table.
  26 * -TODO: Right now page table alloc is 8K and rest 7K is unused
  27 *    need to optimise it
  28 *
  29 * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
  30 */
  31
  32#ifndef _ASM_ARC_PGTABLE_H
  33#define _ASM_ARC_PGTABLE_H
  34
  35#include <linux/bits.h>
  36#include <asm-generic/pgtable-nopmd.h>
  37#include <asm/page.h>
  38#include <asm/mmu.h>    /* to propagate CONFIG_ARC_MMU_VER <n> */
  39
  40/**************************************************************************
  41 * Page Table Flags
  42 *
  43 * ARC700 MMU only deals with softare managed TLB entries.
  44 * Page Tables are purely for Linux VM's consumption and the bits below are
  45 * suited to that (uniqueness). Hence some are not implemented in the TLB and
  46 * some have different value in TLB.
  47 * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible because they live in
  48 *      seperate PD0 and PD1, which combined forms a translation entry)
  49 *      while for PTE perspective, they are 8 and 9 respectively
  50 * with MMU v3: Most bits (except SHARED) represent the exact hardware pos
  51 *      (saves some bit shift ops in TLB Miss hdlrs)
  52 */
  53
  54#if (CONFIG_ARC_MMU_VER <= 2)
  55
  56#define _PAGE_ACCESSED      (1<<1)      /* Page is accessed (S) */
  57#define _PAGE_CACHEABLE     (1<<2)      /* Page is cached (H) */
  58#define _PAGE_EXECUTE       (1<<3)      /* Page has user execute perm (H) */
  59#define _PAGE_WRITE         (1<<4)      /* Page has user write perm (H) */
  60#define _PAGE_READ          (1<<5)      /* Page has user read perm (H) */
  61#define _PAGE_DIRTY         (1<<6)      /* Page modified (dirty) (S) */
  62#define _PAGE_SPECIAL       (1<<7)
  63#define _PAGE_GLOBAL        (1<<8)      /* Page is global (H) */
  64#define _PAGE_PRESENT       (1<<10)     /* TLB entry is valid (H) */
  65
  66#else   /* MMU v3 onwards */
  67
  68#define _PAGE_CACHEABLE     (1<<0)      /* Page is cached (H) */
  69#define _PAGE_EXECUTE       (1<<1)      /* Page has user execute perm (H) */
  70#define _PAGE_WRITE         (1<<2)      /* Page has user write perm (H) */
  71#define _PAGE_READ          (1<<3)      /* Page has user read perm (H) */
  72#define _PAGE_ACCESSED      (1<<4)      /* Page is accessed (S) */
  73#define _PAGE_DIRTY         (1<<5)      /* Page modified (dirty) (S) */
  74#define _PAGE_SPECIAL       (1<<6)
  75
  76#if (CONFIG_ARC_MMU_VER >= 4)
  77#define _PAGE_WTHRU         (1<<7)      /* Page cache mode write-thru (H) */
  78#endif
  79
  80#define _PAGE_GLOBAL        (1<<8)      /* Page is global (H) */
  81#define _PAGE_PRESENT       (1<<9)      /* TLB entry is valid (H) */
  82
  83#if (CONFIG_ARC_MMU_VER >= 4)
  84#define _PAGE_HW_SZ         (1<<10)     /* Page Size indicator (H): 0 normal, 1 super */
  85#endif
  86
  87#define _PAGE_SHARED_CODE   (1<<11)     /* Shared Code page with cmn vaddr
  88                                           usable for shared TLB entries (H) */
  89
  90#define _PAGE_UNUSED_BIT    (1<<12)
  91#endif
  92
  93/* vmalloc permissions */
  94#define _K_PAGE_PERMS  (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ | \
  95                        _PAGE_GLOBAL | _PAGE_PRESENT)
  96
  97#ifndef CONFIG_ARC_CACHE_PAGES
  98#undef _PAGE_CACHEABLE
  99#define _PAGE_CACHEABLE 0
 100#endif
 101
 102#ifndef _PAGE_HW_SZ
 103#define _PAGE_HW_SZ     0
 104#endif
 105
 106/* Defaults for every user page */
 107#define ___DEF (_PAGE_PRESENT | _PAGE_CACHEABLE)
 108
 109/* Set of bits not changed in pte_modify */
 110#define _PAGE_CHG_MASK  (PAGE_MASK_PHYS | _PAGE_ACCESSED | _PAGE_DIRTY | \
 111                                                           _PAGE_SPECIAL)
 112/* More Abbrevaited helpers */
 113#define PAGE_U_NONE     __pgprot(___DEF)
 114#define PAGE_U_R        __pgprot(___DEF | _PAGE_READ)
 115#define PAGE_U_W_R      __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE)
 116#define PAGE_U_X_R      __pgprot(___DEF | _PAGE_READ | _PAGE_EXECUTE)
 117#define PAGE_U_X_W_R    __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE | \
 118                                                       _PAGE_EXECUTE)
 119
 120#define PAGE_SHARED     PAGE_U_W_R
 121
 122/* While kernel runs out of unstranslated space, vmalloc/modules use a chunk of
 123 * user vaddr space - visible in all addr spaces, but kernel mode only
 124 * Thus Global, all-kernel-access, no-user-access, cached
 125 */
 126#define PAGE_KERNEL          __pgprot(_K_PAGE_PERMS | _PAGE_CACHEABLE)
 127
 128/* ioremap */
 129#define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)
 130
 131/* Masks for actual TLB "PD"s */
 132#define PTE_BITS_IN_PD0         (_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ)
 133#define PTE_BITS_RWX            (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
 134
 135#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK_PHYS | _PAGE_CACHEABLE)
 136
 137/**************************************************************************
 138 * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
 139 *
 140 * Certain cases have 1:1 mapping
 141 *  e.g. __P101 means VM_READ, VM_EXEC and !VM_SHARED
 142 *       which directly corresponds to  PAGE_U_X_R
 143 *
 144 * Other rules which cause the divergence from 1:1 mapping
 145 *
 146 *  1. Although ARC700 can do exclusive execute/write protection (meaning R
 147 *     can be tracked independet of X/W unlike some other CPUs), still to
 148 *     keep things consistent with other archs:
 149 *      -Write implies Read:   W => R
 150 *      -Execute implies Read: X => R
 151 *
 152 *  2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W
 153 *     This is to enable COW mechanism
 154 */
 155        /* xwr */
 156#define __P000  PAGE_U_NONE
 157#define __P001  PAGE_U_R
 158#define __P010  PAGE_U_R        /* Pvt-W => !W */
 159#define __P011  PAGE_U_R        /* Pvt-W => !W */
 160#define __P100  PAGE_U_X_R      /* X => R */
 161#define __P101  PAGE_U_X_R
 162#define __P110  PAGE_U_X_R      /* Pvt-W => !W and X => R */
 163#define __P111  PAGE_U_X_R      /* Pvt-W => !W */
 164
 165#define __S000  PAGE_U_NONE
 166#define __S001  PAGE_U_R
 167#define __S010  PAGE_U_W_R      /* W => R */
 168#define __S011  PAGE_U_W_R
 169#define __S100  PAGE_U_X_R      /* X => R */
 170#define __S101  PAGE_U_X_R
 171#define __S110  PAGE_U_X_W_R    /* X => R */
 172#define __S111  PAGE_U_X_W_R
 173
 174/****************************************************************
 175 * 2 tier (PGD:PTE) software page walker
 176 *
 177 * [31]             32 bit virtual address              [0]
 178 * -------------------------------------------------------
 179 * |               | <------------ PGDIR_SHIFT ----------> |
 180 * |               |                                     |
 181 * | BITS_FOR_PGD  |  BITS_FOR_PTE  | <-- PAGE_SHIFT --> |
 182 * -------------------------------------------------------
 183 *       |                  |                |
 184 *       |                  |                --> off in page frame
 185 *       |                  ---> index into Page Table
 186 *       ----> index into Page Directory
 187 *
 188 * In a single page size configuration, only PAGE_SHIFT is fixed
 189 * So both PGD and PTE sizing can be tweaked
 190 *  e.g. 8K page (PAGE_SHIFT 13) can have
 191 *  - PGDIR_SHIFT 21  -> 11:8:13 address split
 192 *  - PGDIR_SHIFT 24  -> 8:11:13 address split
 193 *
 194 * If Super Page is configured, PGDIR_SHIFT becomes fixed too,
 195 * so the sizing flexibility is gone.
 196 */
 197
 198#if defined(CONFIG_ARC_HUGEPAGE_16M)
 199#define PGDIR_SHIFT     24
 200#elif defined(CONFIG_ARC_HUGEPAGE_2M)
 201#define PGDIR_SHIFT     21
 202#else
 203/*
 204 * Only Normal page support so "hackable" (see comment above)
 205 * Default value provides 11:8:13 (8K), 11:9:12 (4K)
 206 */
 207#define PGDIR_SHIFT     21
 208#endif
 209
 210#define BITS_FOR_PTE    (PGDIR_SHIFT - PAGE_SHIFT)
 211#define BITS_FOR_PGD    (32 - PGDIR_SHIFT)
 212
 213#define PGDIR_SIZE      BIT(PGDIR_SHIFT)        /* vaddr span, not PDG sz */
 214#define PGDIR_MASK      (~(PGDIR_SIZE-1))
 215
 216#define PTRS_PER_PTE    BIT(BITS_FOR_PTE)
 217#define PTRS_PER_PGD    BIT(BITS_FOR_PGD)
 218
 219/*
 220 * Number of entries a user land program use.
 221 * TASK_SIZE is the maximum vaddr that can be used by a userland program.
 222 */
 223#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
 224
 225
 226/****************************************************************
 227 * Bucket load of VM Helpers
 228 */
 229
 230#ifndef __ASSEMBLY__
 231
 232#define pte_ERROR(e) \
 233        pr_crit("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 234#define pgd_ERROR(e) \
 235        pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 236
 237/* the zero page used for uninitialized and anonymous pages */
 238extern char empty_zero_page[PAGE_SIZE];
 239#define ZERO_PAGE(vaddr)        (virt_to_page(empty_zero_page))
 240
 241#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
 242#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
 243
 244/* find the page descriptor of the Page Tbl ref by PMD entry */
 245#define pmd_page(pmd)           virt_to_page(pmd_val(pmd) & PAGE_MASK)
 246
 247/* find the logical addr (phy for ARC) of the Page Tbl ref by PMD entry */
 248#define pmd_page_vaddr(pmd)     (pmd_val(pmd) & PAGE_MASK)
 249
 250/* In a 2 level sys, setup the PGD entry with PTE value */
 251static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
 252{
 253        pmd_val(*pmdp) = (unsigned long)ptep;
 254}
 255
 256#define pte_none(x)                     (!pte_val(x))
 257#define pte_present(x)                  (pte_val(x) & _PAGE_PRESENT)
 258#define pte_clear(mm, addr, ptep)       set_pte_at(mm, addr, ptep, __pte(0))
 259
 260#define pmd_none(x)                     (!pmd_val(x))
 261#define pmd_bad(x)                      ((pmd_val(x) & ~PAGE_MASK))
 262#define pmd_present(x)                  (pmd_val(x))
 263#define pmd_leaf(x)                     (pmd_val(x) & _PAGE_HW_SZ)
 264#define pmd_clear(xp)                   do { pmd_val(*(xp)) = 0; } while (0)
 265
 266#define pte_page(pte)           pfn_to_page(pte_pfn(pte))
 267#define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 268#define pfn_pte(pfn, prot)      __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
 269
 270/* Don't use virt_to_pfn for macros below: could cause truncations for PAE40*/
 271#define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
 272
 273/* Zoo of pte_xxx function */
 274#define pte_read(pte)           (pte_val(pte) & _PAGE_READ)
 275#define pte_write(pte)          (pte_val(pte) & _PAGE_WRITE)
 276#define pte_dirty(pte)          (pte_val(pte) & _PAGE_DIRTY)
 277#define pte_young(pte)          (pte_val(pte) & _PAGE_ACCESSED)
 278#define pte_special(pte)        (pte_val(pte) & _PAGE_SPECIAL)
 279
 280#define PTE_BIT_FUNC(fn, op) \
 281        static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
 282
 283PTE_BIT_FUNC(mknotpresent,      &= ~(_PAGE_PRESENT));
 284PTE_BIT_FUNC(wrprotect, &= ~(_PAGE_WRITE));
 285PTE_BIT_FUNC(mkwrite,   |= (_PAGE_WRITE));
 286PTE_BIT_FUNC(mkclean,   &= ~(_PAGE_DIRTY));
 287PTE_BIT_FUNC(mkdirty,   |= (_PAGE_DIRTY));
 288PTE_BIT_FUNC(mkold,     &= ~(_PAGE_ACCESSED));
 289PTE_BIT_FUNC(mkyoung,   |= (_PAGE_ACCESSED));
 290PTE_BIT_FUNC(exprotect, &= ~(_PAGE_EXECUTE));
 291PTE_BIT_FUNC(mkexec,    |= (_PAGE_EXECUTE));
 292PTE_BIT_FUNC(mkspecial, |= (_PAGE_SPECIAL));
 293PTE_BIT_FUNC(mkhuge,    |= (_PAGE_HW_SZ));
 294
 295static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 296{
 297        return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 298}
 299
 300/* Macro to mark a page protection as uncacheable */
 301#define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE))
 302
 303static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 304                              pte_t *ptep, pte_t pteval)
 305{
 306        set_pte(ptep, pteval);
 307}
 308
 309/*
 310 * Macro to quickly access the PGD entry, utlising the fact that some
 311 * arch may cache the pointer to Page Directory of "current" task
 312 * in a MMU register
 313 *
 314 * Thus task->mm->pgd (3 pointer dereferences, cache misses etc simply
 315 * becomes read a register
 316 *
 317 * ********CAUTION*******:
 318 * Kernel code might be dealing with some mm_struct of NON "current"
 319 * Thus use this macro only when you are certain that "current" is current
 320 * e.g. when dealing with signal frame setup code etc
 321 */
 322#ifdef ARC_USE_SCRATCH_REG
 323#define pgd_offset_fast(mm, addr)       \
 324({                                      \
 325        pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0);  \
 326        pgd_base + pgd_index(addr);     \
 327})
 328#else
 329#define pgd_offset_fast(mm, addr)       pgd_offset(mm, addr)
 330#endif
 331
 332extern pgd_t swapper_pg_dir[] __aligned(PAGE_SIZE);
 333void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
 334                      pte_t *ptep);
 335
 336/* Encode swap {type,off} tuple into PTE
 337 * We reserve 13 bits for 5-bit @type, keeping bits 12-5 zero, ensuring that
 338 * PAGE_PRESENT is zero in a PTE holding swap "identifier"
 339 */
 340#define __swp_entry(type, off)  ((swp_entry_t) { \
 341                                        ((type) & 0x1f) | ((off) << 13) })
 342
 343/* Decode a PTE containing swap "identifier "into constituents */
 344#define __swp_type(pte_lookalike)       (((pte_lookalike).val) & 0x1f)
 345#define __swp_offset(pte_lookalike)     ((pte_lookalike).val >> 13)
 346
 347/* NOPs, to keep generic kernel happy */
 348#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 349#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 350
 351#define kern_addr_valid(addr)   (1)
 352
 353#define pmd_pgtable(pmd)       ((pgtable_t) pmd_page_vaddr(pmd))
 354
 355/*
 356 * remap a physical page `pfn' of size `size' with page protection `prot'
 357 * into virtual address `from'
 358 */
 359#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 360#include <asm/hugepage.h>
 361#endif
 362
 363/* to cope with aliasing VIPT cache */
 364#define HAVE_ARCH_UNMAPPED_AREA
 365
 366#endif /* __ASSEMBLY__ */
 367
 368#endif
 369
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