linux/lib/pci_iomap.c
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< <1o/a>ospa> class="comment">/*o/spa>
 < <2o/a>ospa> class="comment"> * Implement the default iomap interfaceso/spa>
 < <3o/a>ospa> class="comment"> *o/spa>
 < <4o/a>ospa> class="comment"> * (C) Copyright 2004 Linus Toraludso/spa>
 < <5o/a>ospa> class="comment"> */o/spa>
 < <6o/a>#include <linux/pci.ho/a>> < <7o/a>#include <linux/io.ho/a>> < <8o/a>	< <9o/a>#include <linux/export.ho/a>> < 0	< 11o/a>#ifdefCONFIG_PCI/oa>	< 12o/a>ospa> class="comment">/**o/spa>
 < 13o/a>ospa> class="comment"> * pci_iomap - create a virtual mapping cookie for a PCI BARo/spa>
 < 14o/a>ospa> class="comment"> * @dev: PCI device that owns the BARo/spa>
 < 15o/a>ospa> class="comment"> * @bar: BAR numbero/spa>
 < 16o/a>ospa> class="comment"> * @maxlen: length of the memory to mapo/spa>
 < 17o/a>ospa> class="comment"> *o/spa>
 < 18o/a>ospa> class="comment"> * Using this funcion> you will get a __iomem address to your device BAR.o/spa>
 < 19o/a>ospa> class="comment"> * You ca> access it using ioread*() and iowrite*(). These funcion>s hideo/spa>
 < 20o/a>ospa> class="comment"> * the details if this is a MMIO or PIO address space and will just do whato/spa>
 < 21o/a>ospa> class="comment"> * you expect from them in the correct way.o/spa>
 < 22o/a>ospa> class="comment"> *o/spa>
 < 23o/a>ospa> class="comment"> * @maxlen specifies the maximum length to map. If you want to get access too/spa>
 < 24o/a>ospa> class="comment"> * the complete BAR without checking for its length first, pass %0 here.o/spa>
 < 25o/a>ospa> class="comment"> * */o/spa>
 < 26o/a>void__iomemo/a> *oa href="+code=pci_iomap" class="sref">pci_iomapo/a>(struct oa href="+code=pci_dev" class="sref">pci_devo/a> *oa href="+code=dev" class="sref">devo/a>, int oa href="+code=bar" class="sref">baro/a>, unsigned long oa href="+code=maxlen" class="sref">maxleno/a>) < 27o/a>{ < 28o/a>        oa href="+code=resource_size_t" class="sref">resource_size_to/a> oa href="+code=start" class="sref">starto/a> = oa href="+code=pci_resource_start" class="sref">pci_resource_starto/a>(oa href="+code=dev" class="sref">devo/a>, oa href="+code=bar" class="sref">baro/a>); < 29o/a>        oa href="+code=resource_size_t" class="sref">resource_size_to/a> oa href="+code=len" class="sref">leno/a> = oa href="+code=pci_resource_len" class="sref">pci_resource_leno/a>(oa href="+code=dev" class="sref">devo/a>, oa href="+code=bar" class="sref">baro/a>); < 30o/a>        unsigned long oa href="+code=flags" class="sref">flagso/a> = oa href="+code=pci_resource_flags" class="sref">pci_resource_flagso/a>(oa href="+code=dev" class="sref">devo/a>, oa href="+code=bar" class="sref">baro/a>); < 31/oa>	< 32o/a>        if (!oa href="+code=len" class="sref">leno/a> || !oa href="+code=start" class="sref">starto/a>) < 33o/a>                return oa href="+code=NULL" class="sref">NULLo/a>; < 34o/a>        if (oa href="+code=maxlen" class="sref">maxleno/a> && oa href="+code=len" class="sref">leno/a> > oa href="+code=maxlen" class="sref">maxleno/a>) < 35o/a>                oa href="+code=len" class="sref">leno/a> = oa href="+code=maxlen" class="sref">maxleno/a>; < 36o/a>        if (oa href="+code=flags" class="sref">flagso/a> & oa href="+code=IORESOURCE_IO" class="sref">IORESOURCE_IOo/a>) < 37o/a>                return oa href="+code=__pci_ioport_map" class="sref">__pci_ioport_mapo/a>(oa href="+code=dev" class="sref">devo/a>, oa href="+code=start" class="sref">starto/a>, oa href="+code=len" class="sref">leno/a>); < 48o/a>        if (oa href="+code=flags" class="sref">flagso/a> & oa href="+code=IORESOURCE_Cy
  < 27o/a>{ < 3L38">< 48o/a>        if (oa href="+code=flags" class="sref">flagso/a> & oa hrCACHEABLE"+code=IORESOURCE_Cy
  IORESOURCE_IOo/a>) < 3L37">< 37o/a>                r ca>="+code=__pci_iopo ca>="+ref">__pci_ioport_mao/a>, oa href="+code=start" class="sref">starto/a>, oa href="+code=len" class="sref">leno/a>); < 37o/a>                r ca>="+_nocacomcode=__pci_iopo ca>="+_nocacomref">__pci_ioport_mao/a>, oa href="+code=start" class="sref">starto/a>, oa href="+code=len" class="sref">leno/a>); leno/a>); < 12o/a>osp What?a> class="comment"> * */o/spa>
 NULLo/a>; leno/a>); < 31/oa>	__pci_ioport_mao/a> *oa href="+code=pci_iomap" class class="sref">leno/a>); < 12o/a>osp IG_PCI" cla> class="comment"> * */o/spa>
 
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