linux/include/linux/clk-provider.h
<<
>>
Prefs
   1/*
   2 *  linux/include/linux/clk-provider.h
   3 *
   4 *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
   5 *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 */
  11#ifndef __LINUX_CLK_PROVIDER_H
  12#define __LINUX_CLK_PROVIDER_H
  13
  14#include <linux/clk.h>
  15
  16#ifdef CONFIG_COMMON_CLK
  17
  18/*
  19 * flags used across common struct clk.  these flags should only affect the
  20 * top-level framework.  custom flags for dealing with hardware specifics
  21 * belong in struct clk_foo
  22 */
  23#define CLK_SET_RATE_GATE       BIT(0) /* must be gated across rate change */
  24#define CLK_SET_PARENT_GATE     BIT(1) /* must be gated across re-parent */
  25#define CLK_SET_RATE_PARENT     BIT(2) /* propagate rate change up one level */
  26#define CLK_IGNORE_UNUSED       BIT(3) /* do not gate even if unused */
  27#define CLK_IS_ROOT             BIT(4) /* root clk, has no parent */
  28#define CLK_IS_BASIC            BIT(5) /* Basic clk, can't do a to_clk_foo() */
  29#define CLK_GET_RATE_NOCACHE    BIT(6) /* do not use the cached clk rate */
  30
  31struct clk_hw;
  32
  33/**
  34 * struct clk_ops -  Callback operations for hardware clocks; these are to
  35 * be provided by the clock implementation, and will be called by drivers
  36 * through the clk_* api.
  37 *
  38 * @prepare:    Prepare the clock for enabling. This must not return until
  39 *              the clock is fully prepared, and it's safe to call clk_enable.
  40 *              This callback is intended to allow clock implementations to
  41 *              do any initialisation that may sleep. Called with
  42 *              prepare_lock held.
  43 *
  44 * @unprepare:  Release the clock from its prepared state. This will typically
  45 *              undo any work done in the @prepare callback. Called with
  46 *              prepare_lock held.
  47 *
  48 * @enable:     Enable the clock atomically. This must not return until the
  49 *              clock is generating a valid clock signal, usable by consumer
  50 *              devices. Called with enable_lock held. This function must not
  51 *              sleep.
  52 *
  53 * @disable:    Disable the clock atomically. Called with enable_lock held.
  54 *              This function must not sleep.
  55 *
  56 * @is_enabled: Queries the hardware to determine if the clock is enabled.
  57 *              This function must not sleep. Optional, if this op is not
  58 *              set then the enable count will be used.
  59 *
  60 * @disable_unused: Disable the clock atomically.  Only called from
  61 *              clk_disable_unused for gate clocks with special needs.
  62 *              Called with enable_lock held.  This function must not
  63 *              sleep.
  64 *
  65 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
  66 *              parent rate is an input parameter.  It is up to the caller to
  67 *              ensure that the prepare_mutex is held across this call.
  68 *              Returns the calculated rate.  Optional, but recommended - if
  69 *              this op is not set then clock rate will be initialized to 0.
  70 *
  71 * @round_rate: Given a target rate as input, returns the closest rate actually
  72 *              supported by the clock.
  73 *
  74 * @get_parent: Queries the hardware to determine the parent of a clock.  The
  75 *              return value is a u8 which specifies the index corresponding to
  76 *              the parent clock.  This index can be applied to either the
  77 *              .parent_names or .parents arrays.  In short, this function
  78 *              translates the parent value read from hardware into an array
  79 *              index.  Currently only called when the clock is initialized by
  80 *              __clk_init.  This callback is mandatory for clocks with
  81 *              multiple parents.  It is optional (and unnecessary) for clocks
  82 *              with 0 or 1 parents.
  83 *
  84 * @set_parent: Change the input source of this clock; for clocks with multiple
  85 *              possible parents specify a new parent by passing in the index
  86 *              as a u8 corresponding to the parent in either the .parent_names
  87 *              or .parents arrays.  This function in affect translates an
  88 *              array index into the value programmed into the hardware.
  89 *              Returns 0 on success, -EERROR otherwise.
  90 *
  91 * @set_rate:   Change the rate of this clock. The requested rate is specified
  92 *              by the second argument, which should typically be the return
  93 *              of .round_rate call.  The third argument gives the parent rate
  94 *              which is likely helpful for most .set_rate implementation.
  95 *              Returns 0 on success, -EERROR otherwise.
  96 *
  97 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
  98 * implementations to split any work between atomic (enable) and sleepable
  99 * (prepare) contexts.  If enabling a clock requires code that might sleep,
 100 * this must be done in clk_prepare.  Clock enable code that will never be
 101 * called in a sleepable context may be implemented in clk_enable.
 102 *
 103 * Typically, drivers will call clk_prepare when a clock may be needed later
 104 * (eg. when a device is opened), and clk_enable when the clock is actually
 105 * required (eg. from an interrupt). Note that clk_prepare MUST have been
 106 * called before clk_enable.
 107 */
 108struct clk_ops {
 109        int             (*prepare)(struct clk_hw *hw);
 110        void            (*unprepare)(struct clk_hw *hw);
 111        int             (*enable)(struct clk_hw *hw);
 112        void            (*disable)(struct clk_hw *hw);
 113        int             (*is_enabled)(struct clk_hw *hw);
 114        void            (*disable_unused)(struct clk_hw *hw);
 115        unsigned long   (*recalc_rate)(struct clk_hw *hw,
 116                                        unsigned long parent_rate);
 117        long            (*round_rate)(struct clk_hw *hw, unsigned long,
 118                                        unsigned long *);
 119        int             (*set_parent)(struct clk_hw *hw, u8 index);
 120        u8              (*get_parent)(struct clk_hw *hw);
 121        int             (*set_rate)(struct clk_hw *hw, unsigned long,
 122                                    unsigned long);
 123        void            (*init)(struct clk_hw *hw);
 124};
 125
 126/**
 127 * struct clk_init_data - holds init data that's common to all clocks and is
 128 * shared between the clock provider and the common clock framework.
 129 *
 130 * @name: clock name
 131 * @ops: operations this clock supports
 132 * @parent_names: array of string names for all possible parents
 133 * @num_parents: number of possible parents
 134 * @flags: framework-level hints and quirks
 135 */
 136struct clk_init_data {
 137        const char              *name;
 138        const struct clk_ops    *ops;
 139        const char              **parent_names;
 140        u8                      num_parents;
 141        unsigned long           flags;
 142};
 143
 144/**
 145 * struct clk_hw - handle for traversing from a struct clk to its corresponding
 146 * hardware-specific structure.  struct clk_hw should be declared within struct
 147 * clk_foo and then referenced by the struct clk instance that uses struct
 148 * clk_foo's clk_ops
 149 *
 150 * @clk: pointer to the struct clk instance that points back to this struct
 151 * clk_hw instance
 152 *
 153 * @init: pointer to struct clk_init_data that contains the init data shared
 154 * with the common clock framework.
 155 */
 156struct clk_hw {
 157        struct clk *clk;
 158        const struct clk_init_data *init;
 159};
 160
 161/*
 162 * DOC: Basic clock implementations common to many platforms
 163 *
 164 * Each basic clock hardware type is comprised of a structure describing the
 165 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
 166 * unique flags for that hardware type, a registration function and an
 167 * alternative macro for static initialization
 168 */
 169
 170/**
 171 * struct clk_fixed_rate - fixed-rate clock
 172 * @hw:         handle between common and hardware-specific interfaces
 173 * @fixed_rate: constant frequency of clock
 174 */
 175struct clk_fixed_rate {
 176        struct          clk_hw hw;
 177        unsigned long   fixed_rate;
 178        u8              flags;
 179};
 180
 181extern const struct clk_ops clk_fixed_rate_ops;
 182struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 183                const char *parent_name, unsigned long flags,
 184                unsigned long fixed_rate);
 185
 186void of_fixed_clk_setup(struct device_node *np);
 187
 188/**
 189 * struct clk_gate - gating clock
 190 *
 191 * @hw:         handle between common and hardware-specific interfaces
 192 * @reg:        register controlling gate
 193 * @bit_idx:    single bit controlling gate
 194 * @flags:      hardware-specific flags
 195 * @lock:       register lock
 196 *
 197 * Clock which can gate its output.  Implements .enable & .disable
 198 *
 199 * Flags:
 200 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
 201 *      enable the clock.  Setting this flag does the opposite: setting the bit
 202 *      disable the clock and clearing it enables the clock
 203 */
 204struct clk_gate {
 205        struct clk_hw hw;
 206        void __iomem    *reg;
 207        u8              bit_idx;
 208        u8              flags;
 209        spinlock_t      *lock;
 210};
 211
 212#define CLK_GATE_SET_TO_DISABLE         BIT(0)
 213
 214extern const struct clk_ops clk_gate_ops;
 215struct clk *clk_register_gate(struct device *dev, const char *name,
 216                const char *parent_name, unsigned long flags,
 217                void __iomem *reg, u8 bit_idx,
 218                u8 clk_gate_flags, spinlock_t *lock);
 219
 220struct clk_div_table {
 221        unsigned int    val;
 222        unsigned int    div;
 223};
 224
 225/**
 226 * struct clk_divider - adjustable divider clock
 227 *
 228 * @hw:         handle between common and hardware-specific interfaces
 229 * @reg:        register containing the divider
 230 * @shift:      shift to the divider bit field
 231 * @width:      width of the divider bit field
 232 * @table:      array of value/divider pairs, last entry should have div = 0
 233 * @lock:       register lock
 234 *
 235 * Clock with an adjustable divider affecting its output frequency.  Implements
 236 * .recalc_rate, .set_rate and .round_rate
 237 *
 238 * Flags:
 239 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
 240 *      register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
 241 *      the raw value read from the register, with the value of zero considered
 242 *      invalid
 243 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
 244 *      the hardware register
 245 */
 246struct clk_divider {
 247        struct clk_hw   hw;
 248        void __iomem    *reg;
 249        u8              shift;
 250        u8              width;
 251        u8              flags;
 252        const struct clk_div_table      *table;
 253        spinlock_t      *lock;
 254};
 255
 256#define CLK_DIVIDER_ONE_BASED           BIT(0)
 257#define CLK_DIVIDER_POWER_OF_TWO        BIT(1)
 258
 259extern const struct clk_ops clk_divider_ops;
 260struct clk *clk_register_divider(struct device *dev, const char *name,
 261                const char *parent_name, unsigned long flags,
 262                void __iomem *reg, u8 shift, u8 width,
 263                u8 clk_divider_flags, spinlock_t *lock);
 264struct clk *clk_register_divider_table(struct device *dev, const char *name,
 265                const char *parent_name, unsigned long flags,
 266                void __iomem *reg, u8 shift, u8 width,
 267                u8 clk_divider_flags, const struct clk_div_table *table,
 268                spinlock_t *lock);
 269
 270/**
 271 * struct clk_mux - multiplexer clock
 272 *
 273 * @hw:         handle between common and hardware-specific interfaces
 274 * @reg:        register controlling multiplexer
 275 * @shift:      shift to multiplexer bit field
 276 * @width:      width of mutliplexer bit field
 277 * @num_clks:   number of parent clocks
 278 * @lock:       register lock
 279 *
 280 * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
 281 * and .recalc_rate
 282 *
 283 * Flags:
 284 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
 285 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
 286 */
 287struct clk_mux {
 288        struct clk_hw   hw;
 289        void __iomem    *reg;
 290        u8              shift;
 291        u8              width;
 292        u8              flags;
 293        spinlock_t      *lock;
 294};
 295
 296#define CLK_MUX_INDEX_ONE               BIT(0)
 297#define CLK_MUX_INDEX_BIT               BIT(1)
 298
 299extern const struct clk_ops clk_mux_ops;
 300struct clk *clk_register_mux(struct device *dev, const char *name,
 301                const char **parent_names, u8 num_parents, unsigned long flags,
 302                void __iomem *reg, u8 shift, u8 width,
 303                u8 clk_mux_flags, spinlock_t *lock);
 304
 305/**
 306 * struct clk_fixed_factor - fixed multiplier and divider clock
 307 *
 308 * @hw:         handle between common and hardware-specific interfaces
 309 * @mult:       multiplier
 310 * @div:        divider
 311 *
 312 * Clock with a fixed multiplier and divider. The output frequency is the
 313 * parent clock rate divided by div and multiplied by mult.
 314 * Implements .recalc_rate, .set_rate and .round_rate
 315 */
 316
 317struct clk_fixed_factor {
 318        struct clk_hw   hw;
 319        unsigned int    mult;
 320        unsigned int    div;
 321};
 322
 323extern struct clk_ops clk_fixed_factor_ops;
 324struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
 325                const char *parent_name, unsigned long flags,
 326                unsigned int mult, unsigned int div);
 327
 328/**
 329 * clk_register - allocate a new clock, register it and return an opaque cookie
 330 * @dev: device that is registering this clock
 331 * @hw: link to hardware-specific clock data
 332 *
 333 * clk_register is the primary interface for populating the clock tree with new
 334 * clock nodes.  It returns a pointer to the newly allocated struct clk which
 335 * cannot be dereferenced by driver code but may be used in conjuction with the
 336 * rest of the clock API.  In the event of an error clk_register will return an
 337 * error code; drivers must test for an error code after calling clk_register.
 338 */
 339struct clk *clk_register(struct device *dev, struct clk_hw *hw);
 340struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
 341
 342void clk_unregister(struct clk *clk);
 343void devm_clk_unregister(struct device *dev, struct clk *clk);
 344
 345/* helper functions */
 346const char *__clk_get_name(struct clk *clk);
 347struct clk_hw *__clk_get_hw(struct clk *clk);
 348u8 __clk_get_num_parents(struct clk *clk);
 349struct clk *__clk_get_parent(struct clk *clk);
 350unsigned int __clk_get_enable_count(struct clk *clk);
 351unsigned int __clk_get_prepare_count(struct clk *clk);
 352unsigned long __clk_get_rate(struct clk *clk);
 353unsigned long __clk_get_flags(struct clk *clk);
 354bool __clk_is_enabled(struct clk *clk);
 355struct clk *__clk_lookup(const char *name);
 356
 357/*
 358 * FIXME clock api without lock protection
 359 */
 360int __clk_prepare(struct clk *clk);
 361void __clk_unprepare(struct clk *clk);
 362void __clk_reparent(struct clk *clk, struct clk *new_parent);
 363unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
 364
 365struct of_device_id;
 366
 367typedef void (*of_clk_init_cb_t)(struct device_node *);
 368
 369int of_clk_add_provider(struct device_node *np,
 370                        struct clk *(*clk_src_get)(struct of_phandle_args *args,
 371                                                   void *data),
 372                        void *data);
 373void of_clk_del_provider(struct device_node *np);
 374struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
 375                                  void *data);
 376struct clk_onecell_data {
 377        struct clk **clks;
 378        unsigned int clk_num;
 379};
 380struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
 381const char *of_clk_get_parent_name(struct device_node *np, int index);
 382
 383void of_clk_init(const struct of_device_id *matches);
 384
 385#define CLK_OF_DECLARE(name, compat, fn)                        \
 386        static const struct of_device_id __clk_of_table_##name  \
 387                __used __section(__clk_of_table)                \
 388                = { .compatible = compat, .data = fn };
 389
 390#endif /* CONFIG_COMMON_CLK */
 391#endif /* CLK_PROVIDER_H */
 392
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.