linux/include/linux/atmel-ssc.h
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   1#ifndef __INCLUDE_ATMEL_SSC_H
   2#define __INCLUDE_ATMEL_SSC_H
   3
   4#include <linux/platform_device.h>
   5#include <linux/list.h>
   6#include <linux/io.h>
   7
   8struct atmel_ssc_platform_data {
   9        int                     use_dma;
  10};
  11
  12struct ssc_device {
  13        struct list_head        list;
  14        resource_size_t         phybase;
  15        void __iomem            *regs;
  16        struct platform_device  *pdev;
  17        struct atmel_ssc_platform_data *pdata;
  18        struct clk              *clk;
  19        int                     user;
  20        int                     irq;
  21};
  22
  23struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
  24void ssc_free(struct ssc_device *ssc);
  25
  26/* SSC register offsets */
  27
  28/* SSC Control Register */
  29#define SSC_CR                          0x00000000
  30#define SSC_CR_RXDIS_SIZE                        1
  31#define SSC_CR_RXDIS_OFFSET                      1
  32#define SSC_CR_RXEN_SIZE                         1
  33#define SSC_CR_RXEN_OFFSET                       0
  34#define SSC_CR_SWRST_SIZE                        1
  35#define SSC_CR_SWRST_OFFSET                     15
  36#define SSC_CR_TXDIS_SIZE                        1
  37#define SSC_CR_TXDIS_OFFSET                      9
  38#define SSC_CR_TXEN_SIZE                         1
  39#define SSC_CR_TXEN_OFFSET                       8
  40
  41/* SSC Clock Mode Register */
  42#define SSC_CMR                         0x00000004
  43#define SSC_CMR_DIV_SIZE                        12
  44#define SSC_CMR_DIV_OFFSET                       0
  45
  46/* SSC Receive Clock Mode Register */
  47#define SSC_RCMR                        0x00000010
  48#define SSC_RCMR_CKG_SIZE                        2
  49#define SSC_RCMR_CKG_OFFSET                      6
  50#define SSC_RCMR_CKI_SIZE                        1
  51#define SSC_RCMR_CKI_OFFSET                      5
  52#define SSC_RCMR_CKO_SIZE                        3
  53#define SSC_RCMR_CKO_OFFSET                      2
  54#define SSC_RCMR_CKS_SIZE                        2
  55#define SSC_RCMR_CKS_OFFSET                      0
  56#define SSC_RCMR_PERIOD_SIZE                     8
  57#define SSC_RCMR_PERIOD_OFFSET                  24
  58#define SSC_RCMR_START_SIZE                      4
  59#define SSC_RCMR_START_OFFSET                    8
  60#define SSC_RCMR_STOP_SIZE                       1
  61#define SSC_RCMR_STOP_OFFSET                    12
  62#define SSC_RCMR_STTDLY_SIZE                     8
  63#define SSC_RCMR_STTDLY_OFFSET                  16
  64
  65/* SSC Receive Frame Mode Register */
  66#define SSC_RFMR                        0x00000014
  67#define SSC_RFMR_DATLEN_SIZE                     5
  68#define SSC_RFMR_DATLEN_OFFSET                   0
  69#define SSC_RFMR_DATNB_SIZE                      4
  70#define SSC_RFMR_DATNB_OFFSET                    8
  71#define SSC_RFMR_FSEDGE_SIZE                     1
  72#define SSC_RFMR_FSEDGE_OFFSET                  24
  73#define SSC_RFMR_FSLEN_SIZE                      4
  74#define SSC_RFMR_FSLEN_OFFSET                   16
  75#define SSC_RFMR_FSOS_SIZE                       4
  76#define SSC_RFMR_FSOS_OFFSET                    20
  77#define SSC_RFMR_LOOP_SIZE                       1
  78#define SSC_RFMR_LOOP_OFFSET                     5
  79#define SSC_RFMR_MSBF_SIZE                       1
  80#define SSC_RFMR_MSBF_OFFSET                     7
  81
  82/* SSC Transmit Clock Mode Register */
  83#define SSC_TCMR                        0x00000018
  84#define SSC_TCMR_CKG_SIZE                        2
  85#define SSC_TCMR_CKG_OFFSET                      6
  86#define SSC_TCMR_CKI_SIZE                        1
  87#define SSC_TCMR_CKI_OFFSET                      5
  88#define SSC_TCMR_CKO_SIZE                        3
  89#define SSC_TCMR_CKO_OFFSET                      2
  90#define SSC_TCMR_CKS_SIZE                        2
  91#define SSC_TCMR_CKS_OFFSET                      0
  92#define SSC_TCMR_PERIOD_SIZE                     8
  93#define SSC_TCMR_PERIOD_OFFSET                  24
  94#define SSC_TCMR_START_SIZE                      4
  95#define SSC_TCMR_START_OFFSET                    8
  96#define SSC_TCMR_STTDLY_SIZE                     8
  97#define SSC_TCMR_STTDLY_OFFSET                  16
  98
  99/* SSC Transmit Frame Mode Register */
 100#define SSC_TFMR                        0x0000001c
 101#define SSC_TFMR_DATDEF_SIZE                     1
 102#define SSC_TFMR_DATDEF_OFFSET                   5
 103#define SSC_TFMR_DATLEN_SIZE                     5
 104#define SSC_TFMR_DATLEN_OFFSET                   0
 105#define SSC_TFMR_DATNB_SIZE                      4
 106#define SSC_TFMR_DATNB_OFFSET                    8
 107#define SSC_TFMR_FSDEN_SIZE                      1
 108#define SSC_TFMR_FSDEN_OFFSET                   23
 109#define SSC_TFMR_FSEDGE_SIZE                     1
 110#define SSC_TFMR_FSEDGE_OFFSET                  24
 111#define SSC_TFMR_FSLEN_SIZE                      4
 112#define SSC_TFMR_FSLEN_OFFSET                   16
 113#define SSC_TFMR_FSOS_SIZE                       3
 114#define SSC_TFMR_FSOS_OFFSET                    20
 115#define SSC_TFMR_MSBF_SIZE                       1
 116#define SSC_TFMR_MSBF_OFFSET                     7
 117
 118/* SSC Receive Hold Register */
 119#define SSC_RHR                         0x00000020
 120#define SSC_RHR_RDAT_SIZE                       32
 121#define SSC_RHR_RDAT_OFFSET                      0
 122
 123/* SSC Transmit Hold Register */
 124#define SSC_THR                         0x00000024
 125#define SSC_THR_TDAT_SIZE                       32
 126#define SSC_THR_TDAT_OFFSET                      0
 127
 128/* SSC Receive Sync. Holding Register */
 129#define SSC_RSHR                        0x00000030
 130#define SSC_RSHR_RSDAT_SIZE                     16
 131#define SSC_RSHR_RSDAT_OFFSET                    0
 132
 133/* SSC Transmit Sync. Holding Register */
 134#define SSC_TSHR                        0x00000034
 135#define SSC_TSHR_TSDAT_SIZE                     16
 136#define SSC_TSHR_RSDAT_OFFSET                    0
 137
 138/* SSC Receive Compare 0 Register */
 139#define SSC_RC0R                        0x00000038
 140#define SSC_RC0R_CP0_SIZE                       16
 141#define SSC_RC0R_CP0_OFFSET                      0
 142
 143/* SSC Receive Compare 1 Register */
 144#define SSC_RC1R                        0x0000003c
 145#define SSC_RC1R_CP1_SIZE                       16
 146#define SSC_RC1R_CP1_OFFSET                      0
 147
 148/* SSC Status Register */
 149#define SSC_SR                          0x00000040
 150#define SSC_SR_CP0_SIZE                          1
 151#define SSC_SR_CP0_OFFSET                        8
 152#define SSC_SR_CP1_SIZE                          1
 153#define SSC_SR_CP1_OFFSET                        9
 154#define SSC_SR_ENDRX_SIZE                        1
 155#define SSC_SR_ENDRX_OFFSET                      6
 156#define SSC_SR_ENDTX_SIZE                        1
 157#define SSC_SR_ENDTX_OFFSET                      2
 158#define SSC_SR_OVRUN_SIZE                        1
 159#define SSC_SR_OVRUN_OFFSET                      5
 160#define SSC_SR_RXBUFF_SIZE                       1
 161#define SSC_SR_RXBUFF_OFFSET                     7
 162#define SSC_SR_RXEN_SIZE                         1
 163#define SSC_SR_RXEN_OFFSET                      17
 164#define SSC_SR_RXRDY_SIZE                        1
 165#define SSC_SR_RXRDY_OFFSET                      4
 166#define SSC_SR_RXSYN_SIZE                        1
 167#define SSC_SR_RXSYN_OFFSET                     11
 168#define SSC_SR_TXBUFE_SIZE                       1
 169#define SSC_SR_TXBUFE_OFFSET                     3
 170#define SSC_SR_TXEMPTY_SIZE                      1
 171#define SSC_SR_TXEMPTY_OFFSET                    1
 172#define SSC_SR_TXEN_SIZE                         1
 173#define SSC_SR_TXEN_OFFSET                      16
 174#define SSC_SR_TXRDY_SIZE                        1
 175#define SSC_SR_TXRDY_OFFSET                      0
 176#define SSC_SR_TXSYN_SIZE                        1
 177#define SSC_SR_TXSYN_OFFSET                     10
 178
 179/* SSC Interrupt Enable Register */
 180#define SSC_IER                         0x00000044
 181#define SSC_IER_CP0_SIZE                         1
 182#define SSC_IER_CP0_OFFSET                       8
 183#define SSC_IER_CP1_SIZE                         1
 184#define SSC_IER_CP1_OFFSET                       9
 185#define SSC_IER_ENDRX_SIZE                       1
 186#define SSC_IER_ENDRX_OFFSET                     6
 187#define SSC_IER_ENDTX_SIZE                       1
 188#define SSC_IER_ENDTX_OFFSET                     2
 189#define SSC_IER_OVRUN_SIZE                       1
 190#define SSC_IER_OVRUN_OFFSET                     5
 191#define SSC_IER_RXBUFF_SIZE                      1
 192#define SSC_IER_RXBUFF_OFFSET                    7
 193#define SSC_IER_RXRDY_SIZE                       1
 194#define SSC_IER_RXRDY_OFFSET                     4
 195#define SSC_IER_RXSYN_SIZE                       1
 196#define SSC_IER_RXSYN_OFFSET                    11
 197#define SSC_IER_TXBUFE_SIZE                      1
 198#define SSC_IER_TXBUFE_OFFSET                    3
 199#define SSC_IER_TXEMPTY_SIZE                     1
 200#define SSC_IER_TXEMPTY_OFFSET                   1
 201#define SSC_IER_TXRDY_SIZE                       1
 202#define SSC_IER_TXRDY_OFFSET                     0
 203#define SSC_IER_TXSYN_SIZE                       1
 204#define SSC_IER_TXSYN_OFFSET                    10
 205
 206/* SSC Interrupt Disable Register */
 207#define SSC_IDR                         0x00000048
 208#define SSC_IDR_CP0_SIZE                         1
 209#define SSC_IDR_CP0_OFFSET                       8
 210#define SSC_IDR_CP1_SIZE                         1
 211#define SSC_IDR_CP1_OFFSET                       9
 212#define SSC_IDR_ENDRX_SIZE                       1
 213#define SSC_IDR_ENDRX_OFFSET                     6
 214#define SSC_IDR_ENDTX_SIZE                       1
 215#define SSC_IDR_ENDTX_OFFSET                     2
 216#define SSC_IDR_OVRUN_SIZE                       1
 217#define SSC_IDR_OVRUN_OFFSET                     5
 218#define SSC_IDR_RXBUFF_SIZE                      1
 219#define SSC_IDR_RXBUFF_OFFSET                    7
 220#define SSC_IDR_RXRDY_SIZE                       1
 221#define SSC_IDR_RXRDY_OFFSET                     4
 222#define SSC_IDR_RXSYN_SIZE                       1
 223#define SSC_IDR_RXSYN_OFFSET                    11
 224#define SSC_IDR_TXBUFE_SIZE                      1
 225#define SSC_IDR_TXBUFE_OFFSET                    3
 226#define SSC_IDR_TXEMPTY_SIZE                     1
 227#define SSC_IDR_TXEMPTY_OFFSET                   1
 228#define SSC_IDR_TXRDY_SIZE                       1
 229#define SSC_IDR_TXRDY_OFFSET                     0
 230#define SSC_IDR_TXSYN_SIZE                       1
 231#define SSC_IDR_TXSYN_OFFSET                    10
 232
 233/* SSC Interrupt Mask Register */
 234#define SSC_IMR                         0x0000004c
 235#define SSC_IMR_CP0_SIZE                         1
 236#define SSC_IMR_CP0_OFFSET                       8
 237#define SSC_IMR_CP1_SIZE                         1
 238#define SSC_IMR_CP1_OFFSET                       9
 239#define SSC_IMR_ENDRX_SIZE                       1
 240#define SSC_IMR_ENDRX_OFFSET                     6
 241#define SSC_IMR_ENDTX_SIZE                       1
 242#define SSC_IMR_ENDTX_OFFSET                     2
 243#define SSC_IMR_OVRUN_SIZE                       1
 244#define SSC_IMR_OVRUN_OFFSET                     5
 245#define SSC_IMR_RXBUFF_SIZE                      1
 246#define SSC_IMR_RXBUFF_OFFSET                    7
 247#define SSC_IMR_RXRDY_SIZE                       1
 248#define SSC_IMR_RXRDY_OFFSET                     4
 249#define SSC_IMR_RXSYN_SIZE                       1
 250#define SSC_IMR_RXSYN_OFFSET                    11
 251#define SSC_IMR_TXBUFE_SIZE                      1
 252#define SSC_IMR_TXBUFE_OFFSET                    3
 253#define SSC_IMR_TXEMPTY_SIZE                     1
 254#define SSC_IMR_TXEMPTY_OFFSET                   1
 255#define SSC_IMR_TXRDY_SIZE                       1
 256#define SSC_IMR_TXRDY_OFFSET                     0
 257#define SSC_IMR_TXSYN_SIZE                       1
 258#define SSC_IMR_TXSYN_OFFSET                    10
 259
 260/* SSC PDC Receive Pointer Register */
 261#define SSC_PDC_RPR                     0x00000100
 262
 263/* SSC PDC Receive Counter Register */
 264#define SSC_PDC_RCR                     0x00000104
 265
 266/* SSC PDC Transmit Pointer Register */
 267#define SSC_PDC_TPR                     0x00000108
 268
 269/* SSC PDC Receive Next Pointer Register */
 270#define SSC_PDC_RNPR                    0x00000110
 271
 272/* SSC PDC Receive Next Counter Register */
 273#define SSC_PDC_RNCR                    0x00000114
 274
 275/* SSC PDC Transmit Counter Register */
 276#define SSC_PDC_TCR                     0x0000010c
 277
 278/* SSC PDC Transmit Next Pointer Register */
 279#define SSC_PDC_TNPR                    0x00000118
 280
 281/* SSC PDC Transmit Next Counter Register */
 282#define SSC_PDC_TNCR                    0x0000011c
 283
 284/* SSC PDC Transfer Control Register */
 285#define SSC_PDC_PTCR                    0x00000120
 286#define SSC_PDC_PTCR_RXTDIS_SIZE                 1
 287#define SSC_PDC_PTCR_RXTDIS_OFFSET               1
 288#define SSC_PDC_PTCR_RXTEN_SIZE                  1
 289#define SSC_PDC_PTCR_RXTEN_OFFSET                0
 290#define SSC_PDC_PTCR_TXTDIS_SIZE                 1
 291#define SSC_PDC_PTCR_TXTDIS_OFFSET               9
 292#define SSC_PDC_PTCR_TXTEN_SIZE                  1
 293#define SSC_PDC_PTCR_TXTEN_OFFSET                8
 294
 295/* SSC PDC Transfer Status Register */
 296#define SSC_PDC_PTSR                    0x00000124
 297#define SSC_PDC_PTSR_RXTEN_SIZE                  1
 298#define SSC_PDC_PTSR_RXTEN_OFFSET                0
 299#define SSC_PDC_PTSR_TXTEN_SIZE                  1
 300#define SSC_PDC_PTSR_TXTEN_OFFSET                8
 301
 302/* Bit manipulation macros */
 303#define SSC_BIT(name)                                   \
 304        (1 << SSC_##name##_OFFSET)
 305#define SSC_BF(name, value)                             \
 306        (((value) & ((1 << SSC_##name##_SIZE) - 1))     \
 307         << SSC_##name##_OFFSET)
 308#define SSC_BFEXT(name, value)                          \
 309        (((value) >> SSC_##name##_OFFSET)               \
 310         & ((1 << SSC_##name##_SIZE) - 1))
 311#define SSC_BFINS(name, value, old)                     \
 312        (((old) & ~(((1 << SSC_##name##_SIZE) - 1)      \
 313        << SSC_##name##_OFFSET)) | SSC_BF(name, value))
 314
 315/* Register access macros */
 316#define ssc_readl(base, reg)            __raw_readl(base + SSC_##reg)
 317#define ssc_writel(base, reg, value)    __raw_writel((value), base + SSC_##reg)
 318
 319#endif /* __INCLUDE_ATMEL_SSC_H */
 320
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