linux/drivers/watchdog/davinci_wdt.c
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   1/*
   2 * drivers/char/watchdog/davinci_wdt.c
   3 *
   4 * Watchdog driver for DaVinci DM644x/DM646x processors
   5 *
   6 * Copyright (C) 2006 Texas Instruments.
   7 *
   8 * 2007 (c) MontaVista Software, Inc. This file is licensed under
   9 * the terms of the GNU General Public License version 2. This program
  10 * is licensed "as is" without any warranty of any kind, whether express
  11 * or implied.
  12 */
  13
  14#include <linux/module.h>
  15#include <linux/moduleparam.h>
  16#include <linux/types.h>
  17#include <linux/kernel.h>
  18#include <linux/fs.h>
  19#include <linux/miscdevice.h>
  20#include <linux/watchdog.h>
  21#include <linux/init.h>
  22#include <linux/bitops.h>
  23#include <linux/platform_device.h>
  24#include <linux/spinlock.h>
  25#include <linux/uaccess.h>
  26#include <linux/io.h>
  27#include <linux/device.h>
  28#include <linux/clk.h>
  29#include <linux/slab.h>
  30
  31#define MODULE_NAME "DAVINCI-WDT: "
  32
  33#define DEFAULT_HEARTBEAT 60
  34#define MAX_HEARTBEAT     600   /* really the max margin is 264/27MHz*/
  35
  36/* Timer register set definition */
  37#define PID12   (0x0)
  38#define EMUMGT  (0x4)
  39#define TIM12   (0x10)
  40#define TIM34   (0x14)
  41#define PRD12   (0x18)
  42#define PRD34   (0x1C)
  43#define TCR     (0x20)
  44#define TGCR    (0x24)
  45#define WDTCR   (0x28)
  46
  47/* TCR bit definitions */
  48#define ENAMODE12_DISABLED      (0 << 6)
  49#define ENAMODE12_ONESHOT       (1 << 6)
  50#define ENAMODE12_PERIODIC      (2 << 6)
  51
  52/* TGCR bit definitions */
  53#define TIM12RS_UNRESET         (1 << 0)
  54#define TIM34RS_UNRESET         (1 << 1)
  55#define TIMMODE_64BIT_WDOG      (2 << 2)
  56
  57/* WDTCR bit definitions */
  58#define WDEN                    (1 << 14)
  59#define WDFLAG                  (1 << 15)
  60#define WDKEY_SEQ0              (0xa5c6 << 16)
  61#define WDKEY_SEQ1              (0xda7e << 16)
  62
  63static int heartbeat = DEFAULT_HEARTBEAT;
  64
  65static DEFINE_SPINLOCK(io_lock);
  66static unsigned long wdt_status;
  67#define WDT_IN_USE        0
  68#define WDT_OK_TO_CLOSE   1
  69#define WDT_REGION_INITED 2
  70#define WDT_DEVICE_INITED 3
  71
  72static void __iomem     *wdt_base;
  73struct clk              *wdt_clk;
  74
  75static void wdt_service(void)
  76{
  77        spin_lock(&io_lock);
  78
  79        /* put watchdog in service state */
  80        iowrite32(WDKEY_SEQ0, wdt_base + WDTCR);
  81        /* put watchdog in active state */
  82        iowrite32(WDKEY_SEQ1, wdt_base + WDTCR);
  83
  84        spin_unlock(&io_lock);
  85}
  86
  87static void wdt_enable(void)
  88{
  89        u32 tgcr;
  90        u32 timer_margin;
  91        unsigned long wdt_freq;
  92
  93        wdt_freq = clk_get_rate(wdt_clk);
  94
  95        spin_lock(&io_lock);
  96
  97        /* disable, internal clock source */
  98        iowrite32(0, wdt_base + TCR);
  99        /* reset timer, set mode to 64-bit watchdog, and unreset */
 100        iowrite32(0, wdt_base + TGCR);
 101        tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
 102        iowrite32(tgcr, wdt_base + TGCR);
 103        /* clear counter regs */
 104        iowrite32(0, wdt_base + TIM12);
 105        iowrite32(0, wdt_base + TIM34);
 106        /* set timeout period */
 107        timer_margin = (((u64)heartbeat * wdt_freq) & 0xffffffff);
 108        iowrite32(timer_margin, wdt_base + PRD12);
 109        timer_margin = (((u64)heartbeat * wdt_freq) >> 32);
 110        iowrite32(timer_margin, wdt_base + PRD34);
 111        /* enable run continuously */
 112        iowrite32(ENAMODE12_PERIODIC, wdt_base + TCR);
 113        /* Once the WDT is in pre-active state write to
 114         * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
 115         * write protected (except for the WDKEY field)
 116         */
 117        /* put watchdog in pre-active state */
 118        iowrite32(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
 119        /* put watchdog in active state */
 120        iowrite32(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
 121
 122        spin_unlock(&io_lock);
 123}
 124
 125static int davinci_wdt_open(struct inode *inode, struct file *file)
 126{
 127        if (test_and_set_bit(WDT_IN_USE, &wdt_status))
 128                return -EBUSY;
 129
 130        wdt_enable();
 131
 132        return nonseekable_open(inode, file);
 133}
 134
 135static ssize_t
 136davinci_wdt_write(struct file *file, const char *data, size_t len,
 137                  loff_t *ppos)
 138{
 139        if (len)
 140                wdt_service();
 141
 142        return len;
 143}
 144
 145static const struct watchdog_info ident = {
 146        .options = WDIOF_KEEPALIVEPING,
 147        .identity = "DaVinci Watchdog",
 148};
 149
 150static long davinci_wdt_ioctl(struct file *file,
 151                                        unsigned int cmd, unsigned long arg)
 152{
 153        int ret = -ENOTTY;
 154
 155        switch (cmd) {
 156        case WDIOC_GETSUPPORT:
 157                ret = copy_to_user((struct watchdog_info *)arg, &ident,
 158                                   sizeof(ident)) ? -EFAULT : 0;
 159                break;
 160
 161        case WDIOC_GETSTATUS:
 162        case WDIOC_GETBOOTSTATUS:
 163                ret = put_user(0, (int *)arg);
 164                break;
 165
 166        case WDIOC_KEEPALIVE:
 167                wdt_service();
 168                ret = 0;
 169                break;
 170
 171        case WDIOC_GETTIMEOUT:
 172                ret = put_user(heartbeat, (int *)arg);
 173                break;
 174        }
 175        return ret;
 176}
 177
 178static int davinci_wdt_release(struct inode *inode, struct file *file)
 179{
 180        wdt_service();
 181        clear_bit(WDT_IN_USE, &wdt_status);
 182
 183        return 0;
 184}
 185
 186static const struct file_operations davinci_wdt_fops = {
 187        .owner = THIS_MODULE,
 188        .llseek = no_llseek,
 189        .write = davinci_wdt_write,
 190        .unlocked_ioctl = davinci_wdt_ioctl,
 191        .open = davinci_wdt_open,
 192        .release = davinci_wdt_release,
 193};
 194
 195static struct miscdevice davinci_wdt_miscdev = {
 196        .minor = WATCHDOG_MINOR,
 197        .name = "watchdog",
 198        .fops = &davinci_wdt_fops,
 199};
 200
 201static int davinci_wdt_probe(struct platform_device *pdev)
 202{
 203        int ret = 0;
 204        struct device *dev = &pdev->dev;
 205        struct resource  *wdt_mem;
 206
 207        wdt_clk = devm_clk_get(dev, NULL);
 208        if (WARN_ON(IS_ERR(wdt_clk)))
 209                return PTR_ERR(wdt_clk);
 210
 211        clk_prepare_enable(wdt_clk);
 212
 213        if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
 214                heartbeat = DEFAULT_HEARTBEAT;
 215
 216        dev_info(dev, "heartbeat %d sec\n", heartbeat);
 217
 218        wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 219        if (wdt_mem == NULL) {
 220                dev_err(dev, "failed to get memory region resource\n");
 221                return -ENOENT;
 222        }
 223
 224        wdt_base = devm_request_and_ioremap(dev, wdt_mem);
 225        if (!wdt_base) {
 226                dev_err(dev, "ioremap failed\n");
 227                return -EADDRNOTAVAIL;
 228        }
 229
 230        ret = misc_register(&davinci_wdt_miscdev);
 231        if (ret < 0) {
 232                dev_err(dev, "cannot register misc device\n");
 233        } else {
 234                set_bit(WDT_DEVICE_INITED, &wdt_status);
 235        }
 236
 237        return ret;
 238}
 239
 240static int davinci_wdt_remove(struct platform_device *pdev)
 241{
 242        misc_deregister(&davinci_wdt_miscdev);
 243        clk_disable_unprepare(wdt_clk);
 244
 245        return 0;
 246}
 247
 248static const struct of_device_id davinci_wdt_of_match[] = {
 249        { .compatible = "ti,davinci-wdt", },
 250        {},
 251};
 252MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
 253
 254static struct platform_driver platform_wdt_driver = {
 255        .driver = {
 256                .name = "watchdog",
 257                .owner  = THIS_MODULE,
 258                .of_match_table = davinci_wdt_of_match,
 259        },
 260        .probe = davinci_wdt_probe,
 261        .remove = davinci_wdt_remove,
 262};
 263
 264module_platform_driver(platform_wdt_driver);
 265
 266MODULE_AUTHOR("Texas Instruments");
 267MODULE_DESCRIPTION("DaVinci Watchdog Driver");
 268
 269module_param(heartbeat, int, 0);
 270MODULE_PARM_DESC(heartbeat,
 271                 "Watchdog heartbeat period in seconds from 1 to "
 272                 __MODULE_STRING(MAX_HEARTBEAT) ", default "
 273                 __MODULE_STRING(DEFAULT_HEARTBEAT));
 274
 275MODULE_LICENSE("GPL");
 276MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 277MODULE_ALIAS("platform:watchdog");
 278
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