linux/drivers/video/s3c-fb.c
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   1/* linux/drivers/video/s3c-fb.c
   2 *
   3 * Copyright 2008 Openmoko Inc.
   4 * Copyright 2008-2010 Simtec Electronics
   5 *      Ben Dooks <ben@simtec.co.uk>
   6 *      http://armlinux.simtec.co.uk/
   7 *
   8 * Samsung SoC Framebuffer driver
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as
  12 * published by the Free Software FoundatIon.
  13*/
  14
  15#include <linux/kernel.h>
  16#include <linux/module.h>
  17#include <linux/platform_device.h>
  18#include <linux/dma-mapping.h>
  19#include <linux/slab.h>
  20#include <linux/init.h>
  21#include <linux/clk.h>
  22#include <linux/fb.h>
  23#include <linux/io.h>
  24#include <linux/uaccess.h>
  25#include <linux/interrupt.h>
  26#include <linux/pm_runtime.h>
  27
  28#include <video/samsung_fimd.h>
  29#include <mach/map.h>
  30#include <plat/fb.h>
  31
  32/* This driver will export a number of framebuffer interfaces depending
  33 * on the configuration passed in via the platform data. Each fb instance
  34 * maps to a hardware window. Currently there is no support for runtime
  35 * setting of the alpha-blending functions that each window has, so only
  36 * window 0 is actually useful.
  37 *
  38 * Window 0 is treated specially, it is used for the basis of the LCD
  39 * output timings and as the control for the output power-down state.
  40*/
  41
  42/* note, the previous use of <mach/regs-fb.h> to get platform specific data
  43 * has been replaced by using the platform device name to pick the correct
  44 * configuration data for the system.
  45*/
  46
  47#ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
  48#undef writel
  49#define writel(v, r) do { \
  50        pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \
  51        __raw_writel(v, r); \
  52} while (0)
  53#endif /* FB_S3C_DEBUG_REGWRITE */
  54
  55/* irq_flags bits */
  56#define S3C_FB_VSYNC_IRQ_EN     0
  57
  58#define VSYNC_TIMEOUT_MSEC 50
  59
  60struct s3c_fb;
  61
  62#define VALID_BPP(x) (1 << ((x) - 1))
  63
  64#define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
  65#define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
  66#define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
  67#define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
  68#define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
  69
  70/**
  71 * struct s3c_fb_variant - fb variant information
  72 * @is_2443: Set if S3C2443/S3C2416 style hardware.
  73 * @nr_windows: The number of windows.
  74 * @vidtcon: The base for the VIDTCONx registers
  75 * @wincon: The base for the WINxCON registers.
  76 * @winmap: The base for the WINxMAP registers.
  77 * @keycon: The abse for the WxKEYCON registers.
  78 * @buf_start: Offset of buffer start registers.
  79 * @buf_size: Offset of buffer size registers.
  80 * @buf_end: Offset of buffer end registers.
  81 * @osd: The base for the OSD registers.
  82 * @palette: Address of palette memory, or 0 if none.
  83 * @has_prtcon: Set if has PRTCON register.
  84 * @has_shadowcon: Set if has SHADOWCON register.
  85 * @has_blendcon: Set if has BLENDCON register.
  86 * @has_clksel: Set if VIDCON0 register has CLKSEL bit.
  87 * @has_fixvclk: Set if VIDCON1 register has FIXVCLK bits.
  88 */
  89struct s3c_fb_variant {
  90        unsigned int    is_2443:1;
  91        unsigned short  nr_windows;
  92        unsigned int    vidtcon;
  93        unsigned short  wincon;
  94        unsigned short  winmap;
  95        unsigned short  keycon;
  96        unsigned short  buf_start;
  97        unsigned short  buf_end;
  98        unsigned short  buf_size;
  99        unsigned short  osd;
 100        unsigned short  osd_stride;
 101        unsigned short  palette[S3C_FB_MAX_WIN];
 102
 103        unsigned int    has_prtcon:1;
 104        unsigned int    has_shadowcon:1;
 105        unsigned int    has_blendcon:1;
 106        unsigned int    has_clksel:1;
 107        unsigned int    has_fixvclk:1;
 108};
 109
 110/**
 111 * struct s3c_fb_win_variant
 112 * @has_osd_c: Set if has OSD C register.
 113 * @has_osd_d: Set if has OSD D register.
 114 * @has_osd_alpha: Set if can change alpha transparency for a window.
 115 * @palette_sz: Size of palette in entries.
 116 * @palette_16bpp: Set if palette is 16bits wide.
 117 * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
 118 *                register is located at the given offset from OSD_BASE.
 119 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
 120 *
 121 * valid_bpp bit x is set if (x+1)BPP is supported.
 122 */
 123struct s3c_fb_win_variant {
 124        unsigned int    has_osd_c:1;
 125        unsigned int    has_osd_d:1;
 126        unsigned int    has_osd_alpha:1;
 127        unsigned int    palette_16bpp:1;
 128        unsigned short  osd_size_off;
 129        unsigned short  palette_sz;
 130        u32             valid_bpp;
 131};
 132
 133/**
 134 * struct s3c_fb_driverdata - per-device type driver data for init time.
 135 * @variant: The variant information for this driver.
 136 * @win: The window information for each window.
 137 */
 138struct s3c_fb_driverdata {
 139        struct s3c_fb_variant   variant;
 140        struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];
 141};
 142
 143/**
 144 * struct s3c_fb_palette - palette information
 145 * @r: Red bitfield.
 146 * @g: Green bitfield.
 147 * @b: Blue bitfield.
 148 * @a: Alpha bitfield.
 149 */
 150struct s3c_fb_palette {
 151        struct fb_bitfield      r;
 152        struct fb_bitfield      g;
 153        struct fb_bitfield      b;
 154        struct fb_bitfield      a;
 155};
 156
 157/**
 158 * struct s3c_fb_win - per window private data for each framebuffer.
 159 * @windata: The platform data supplied for the window configuration.
 160 * @parent: The hardware that this window is part of.
 161 * @fbinfo: Pointer pack to the framebuffer info for this window.
 162 * @varint: The variant information for this window.
 163 * @palette_buffer: Buffer/cache to hold palette entries.
 164 * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
 165 * @index: The window number of this window.
 166 * @palette: The bitfields for changing r/g/b into a hardware palette entry.
 167 */
 168struct s3c_fb_win {
 169        struct s3c_fb_pd_win    *windata;
 170        struct s3c_fb           *parent;
 171        struct fb_info          *fbinfo;
 172        struct s3c_fb_palette    palette;
 173        struct s3c_fb_win_variant variant;
 174
 175        u32                     *palette_buffer;
 176        u32                      pseudo_palette[16];
 177        unsigned int             index;
 178};
 179
 180/**
 181 * struct s3c_fb_vsync - vsync information
 182 * @wait:       a queue for processes waiting for vsync
 183 * @count:      vsync interrupt count
 184 */
 185struct s3c_fb_vsync {
 186        wait_queue_head_t       wait;
 187        unsigned int            count;
 188};
 189
 190/**
 191 * struct s3c_fb - overall hardware state of the hardware
 192 * @slock: The spinlock protection for this data structure.
 193 * @dev: The device that we bound to, for printing, etc.
 194 * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
 195 * @lcd_clk: The clk (sclk) feeding pixclk.
 196 * @regs: The mapped hardware registers.
 197 * @variant: Variant information for this hardware.
 198 * @enabled: A bitmask of enabled hardware windows.
 199 * @output_on: Flag if the physical output is enabled.
 200 * @pdata: The platform configuration data passed with the device.
 201 * @windows: The hardware windows that have been claimed.
 202 * @irq_no: IRQ line number
 203 * @irq_flags: irq flags
 204 * @vsync_info: VSYNC-related information (count, queues...)
 205 */
 206struct s3c_fb {
 207        spinlock_t              slock;
 208        struct device           *dev;
 209        struct clk              *bus_clk;
 210        struct clk              *lcd_clk;
 211        void __iomem            *regs;
 212        struct s3c_fb_variant    variant;
 213
 214        unsigned char            enabled;
 215        bool                     output_on;
 216
 217        struct s3c_fb_platdata  *pdata;
 218        struct s3c_fb_win       *windows[S3C_FB_MAX_WIN];
 219
 220        int                      irq_no;
 221        unsigned long            irq_flags;
 222        struct s3c_fb_vsync      vsync_info;
 223};
 224
 225/**
 226 * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
 227 * @win: The device window.
 228 * @bpp: The bit depth.
 229 */
 230static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
 231{
 232        return win->variant.valid_bpp & VALID_BPP(bpp);
 233}
 234
 235/**
 236 * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
 237 * @var: The screen information to verify.
 238 * @info: The framebuffer device.
 239 *
 240 * Framebuffer layer call to verify the given information and allow us to
 241 * update various information depending on the hardware capabilities.
 242 */
 243static int s3c_fb_check_var(struct fb_var_screeninfo *var,
 244                            struct fb_info *info)
 245{
 246        struct s3c_fb_win *win = info->par;
 247        struct s3c_fb *sfb = win->parent;
 248
 249        dev_dbg(sfb->dev, "checking parameters\n");
 250
 251        var->xres_virtual = max(var->xres_virtual, var->xres);
 252        var->yres_virtual = max(var->yres_virtual, var->yres);
 253
 254        if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
 255                dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
 256                        win->index, var->bits_per_pixel);
 257                return -EINVAL;
 258        }
 259
 260        /* always ensure these are zero, for drop through cases below */
 261        var->transp.offset = 0;
 262        var->transp.length = 0;
 263
 264        switch (var->bits_per_pixel) {
 265        case 1:
 266        case 2:
 267        case 4:
 268        case 8:
 269                if (sfb->variant.palette[win->index] != 0) {
 270                        /* non palletised, A:1,R:2,G:3,B:2 mode */
 271                        var->red.offset         = 5;
 272                        var->green.offset       = 2;
 273                        var->blue.offset        = 0;
 274                        var->red.length         = 2;
 275                        var->green.length       = 3;
 276                        var->blue.length        = 2;
 277                        var->transp.offset      = 7;
 278                        var->transp.length      = 1;
 279                } else {
 280                        var->red.offset = 0;
 281                        var->red.length = var->bits_per_pixel;
 282                        var->green      = var->red;
 283                        var->blue       = var->red;
 284                }
 285                break;
 286
 287        case 19:
 288                /* 666 with one bit alpha/transparency */
 289                var->transp.offset      = 18;
 290                var->transp.length      = 1;
 291                /* drop through */
 292        case 18:
 293                var->bits_per_pixel     = 32;
 294
 295                /* 666 format */
 296                var->red.offset         = 12;
 297                var->green.offset       = 6;
 298                var->blue.offset        = 0;
 299                var->red.length         = 6;
 300                var->green.length       = 6;
 301                var->blue.length        = 6;
 302                break;
 303
 304        case 16:
 305                /* 16 bpp, 565 format */
 306                var->red.offset         = 11;
 307                var->green.offset       = 5;
 308                var->blue.offset        = 0;
 309                var->red.length         = 5;
 310                var->green.length       = 6;
 311                var->blue.length        = 5;
 312                break;
 313
 314        case 32:
 315        case 28:
 316        case 25:
 317                var->transp.length      = var->bits_per_pixel - 24;
 318                var->transp.offset      = 24;
 319                /* drop through */
 320        case 24:
 321                /* our 24bpp is unpacked, so 32bpp */
 322                var->bits_per_pixel     = 32;
 323                var->red.offset         = 16;
 324                var->red.length         = 8;
 325                var->green.offset       = 8;
 326                var->green.length       = 8;
 327                var->blue.offset        = 0;
 328                var->blue.length        = 8;
 329                break;
 330
 331        default:
 332                dev_err(sfb->dev, "invalid bpp\n");
 333                return -EINVAL;
 334        }
 335
 336        dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
 337        return 0;
 338}
 339
 340/**
 341 * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
 342 * @sfb: The hardware state.
 343 * @pixclock: The pixel clock wanted, in picoseconds.
 344 *
 345 * Given the specified pixel clock, work out the necessary divider to get
 346 * close to the output frequency.
 347 */
 348static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
 349{
 350        unsigned long clk;
 351        unsigned long long tmp;
 352        unsigned int result;
 353
 354        if (sfb->variant.has_clksel)
 355                clk = clk_get_rate(sfb->bus_clk);
 356        else
 357                clk = clk_get_rate(sfb->lcd_clk);
 358
 359        tmp = (unsigned long long)clk;
 360        tmp *= pixclk;
 361
 362        do_div(tmp, 1000000000UL);
 363        result = (unsigned int)tmp / 1000;
 364
 365        dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
 366                pixclk, clk, result, result ? clk / result : clk);
 367
 368        return result;
 369}
 370
 371/**
 372 * s3c_fb_align_word() - align pixel count to word boundary
 373 * @bpp: The number of bits per pixel
 374 * @pix: The value to be aligned.
 375 *
 376 * Align the given pixel count so that it will start on an 32bit word
 377 * boundary.
 378 */
 379static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
 380{
 381        int pix_per_word;
 382
 383        if (bpp > 16)
 384                return pix;
 385
 386        pix_per_word = (8 * 32) / bpp;
 387        return ALIGN(pix, pix_per_word);
 388}
 389
 390/**
 391 * vidosd_set_size() - set OSD size for a window
 392 *
 393 * @win: the window to set OSD size for
 394 * @size: OSD size register value
 395 */
 396static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
 397{
 398        struct s3c_fb *sfb = win->parent;
 399
 400        /* OSD can be set up if osd_size_off != 0 for this window */
 401        if (win->variant.osd_size_off)
 402                writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
 403                                + win->variant.osd_size_off);
 404}
 405
 406/**
 407 * vidosd_set_alpha() - set alpha transparency for a window
 408 *
 409 * @win: the window to set OSD size for
 410 * @alpha: alpha register value
 411 */
 412static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
 413{
 414        struct s3c_fb *sfb = win->parent;
 415
 416        if (win->variant.has_osd_alpha)
 417                writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
 418}
 419
 420/**
 421 * shadow_protect_win() - disable updating values from shadow registers at vsync
 422 *
 423 * @win: window to protect registers for
 424 * @protect: 1 to protect (disable updates)
 425 */
 426static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
 427{
 428        struct s3c_fb *sfb = win->parent;
 429        u32 reg;
 430
 431        if (protect) {
 432                if (sfb->variant.has_prtcon) {
 433                        writel(PRTCON_PROTECT, sfb->regs + PRTCON);
 434                } else if (sfb->variant.has_shadowcon) {
 435                        reg = readl(sfb->regs + SHADOWCON);
 436                        writel(reg | SHADOWCON_WINx_PROTECT(win->index),
 437                                sfb->regs + SHADOWCON);
 438                }
 439        } else {
 440                if (sfb->variant.has_prtcon) {
 441                        writel(0, sfb->regs + PRTCON);
 442                } else if (sfb->variant.has_shadowcon) {
 443                        reg = readl(sfb->regs + SHADOWCON);
 444                        writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
 445                                sfb->regs + SHADOWCON);
 446                }
 447        }
 448}
 449
 450/**
 451 * s3c_fb_enable() - Set the state of the main LCD output
 452 * @sfb: The main framebuffer state.
 453 * @enable: The state to set.
 454 */
 455static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
 456{
 457        u32 vidcon0 = readl(sfb->regs + VIDCON0);
 458
 459        if (enable && !sfb->output_on)
 460                pm_runtime_get_sync(sfb->dev);
 461
 462        if (enable) {
 463                vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 464        } else {
 465                /* see the note in the framebuffer datasheet about
 466                 * why you cannot take both of these bits down at the
 467                 * same time. */
 468
 469                if (vidcon0 & VIDCON0_ENVID) {
 470                        vidcon0 |= VIDCON0_ENVID;
 471                        vidcon0 &= ~VIDCON0_ENVID_F;
 472                }
 473        }
 474
 475        writel(vidcon0, sfb->regs + VIDCON0);
 476
 477        if (!enable && sfb->output_on)
 478                pm_runtime_put_sync(sfb->dev);
 479
 480        sfb->output_on = enable;
 481}
 482
 483/**
 484 * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
 485 * @info: The framebuffer to change.
 486 *
 487 * Framebuffer layer request to set a new mode for the specified framebuffer
 488 */
 489static int s3c_fb_set_par(struct fb_info *info)
 490{
 491        struct fb_var_screeninfo *var = &info->var;
 492        struct s3c_fb_win *win = info->par;
 493        struct s3c_fb *sfb = win->parent;
 494        void __iomem *regs = sfb->regs;
 495        void __iomem *buf = regs;
 496        int win_no = win->index;
 497        u32 alpha = 0;
 498        u32 data;
 499        u32 pagewidth;
 500
 501        dev_dbg(sfb->dev, "setting framebuffer parameters\n");
 502
 503        pm_runtime_get_sync(sfb->dev);
 504
 505        shadow_protect_win(win, 1);
 506
 507        switch (var->bits_per_pixel) {
 508        case 32:
 509        case 24:
 510        case 16:
 511        case 12:
 512                info->fix.visual = FB_VISUAL_TRUECOLOR;
 513                break;
 514        case 8:
 515                if (win->variant.palette_sz >= 256)
 516                        info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 517                else
 518                        info->fix.visual = FB_VISUAL_TRUECOLOR;
 519                break;
 520        case 1:
 521                info->fix.visual = FB_VISUAL_MONO01;
 522                break;
 523        default:
 524                info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 525                break;
 526        }
 527
 528        info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
 529
 530        info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
 531        info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
 532
 533        /* disable the window whilst we update it */
 534        writel(0, regs + WINCON(win_no));
 535
 536        if (!sfb->output_on)
 537                s3c_fb_enable(sfb, 1);
 538
 539        /* write the buffer address */
 540
 541        /* start and end registers stride is 8 */
 542        buf = regs + win_no * 8;
 543
 544        writel(info->fix.smem_start, buf + sfb->variant.buf_start);
 545
 546        data = info->fix.smem_start + info->fix.line_length * var->yres;
 547        writel(data, buf + sfb->variant.buf_end);
 548
 549        pagewidth = (var->xres * var->bits_per_pixel) >> 3;
 550        data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
 551               VIDW_BUF_SIZE_PAGEWIDTH(pagewidth) |
 552               VIDW_BUF_SIZE_OFFSET_E(info->fix.line_length - pagewidth) |
 553               VIDW_BUF_SIZE_PAGEWIDTH_E(pagewidth);
 554        writel(data, regs + sfb->variant.buf_size + (win_no * 4));
 555
 556        /* write 'OSD' registers to control position of framebuffer */
 557
 558        data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0) |
 559               VIDOSDxA_TOPLEFT_X_E(0) | VIDOSDxA_TOPLEFT_Y_E(0);
 560        writel(data, regs + VIDOSD_A(win_no, sfb->variant));
 561
 562        data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
 563                                                     var->xres - 1)) |
 564               VIDOSDxB_BOTRIGHT_Y(var->yres - 1) |
 565               VIDOSDxB_BOTRIGHT_X_E(s3c_fb_align_word(var->bits_per_pixel,
 566                                                     var->xres - 1)) |
 567               VIDOSDxB_BOTRIGHT_Y_E(var->yres - 1);
 568
 569        writel(data, regs + VIDOSD_B(win_no, sfb->variant));
 570
 571        data = var->xres * var->yres;
 572
 573        alpha = VIDISD14C_ALPHA1_R(0xf) |
 574                VIDISD14C_ALPHA1_G(0xf) |
 575                VIDISD14C_ALPHA1_B(0xf);
 576
 577        vidosd_set_alpha(win, alpha);
 578        vidosd_set_size(win, data);
 579
 580        /* Enable DMA channel for this window */
 581        if (sfb->variant.has_shadowcon) {
 582                data = readl(sfb->regs + SHADOWCON);
 583                data |= SHADOWCON_CHx_ENABLE(win_no);
 584                writel(data, sfb->regs + SHADOWCON);
 585        }
 586
 587        data = WINCONx_ENWIN;
 588        sfb->enabled |= (1 << win->index);
 589
 590        /* note, since we have to round up the bits-per-pixel, we end up
 591         * relying on the bitfield information for r/g/b/a to work out
 592         * exactly which mode of operation is intended. */
 593
 594        switch (var->bits_per_pixel) {
 595        case 1:
 596                data |= WINCON0_BPPMODE_1BPP;
 597                data |= WINCONx_BITSWP;
 598                data |= WINCONx_BURSTLEN_4WORD;
 599                break;
 600        case 2:
 601                data |= WINCON0_BPPMODE_2BPP;
 602                data |= WINCONx_BITSWP;
 603                data |= WINCONx_BURSTLEN_8WORD;
 604                break;
 605        case 4:
 606                data |= WINCON0_BPPMODE_4BPP;
 607                data |= WINCONx_BITSWP;
 608                data |= WINCONx_BURSTLEN_8WORD;
 609                break;
 610        case 8:
 611                if (var->transp.length != 0)
 612                        data |= WINCON1_BPPMODE_8BPP_1232;
 613                else
 614                        data |= WINCON0_BPPMODE_8BPP_PALETTE;
 615                data |= WINCONx_BURSTLEN_8WORD;
 616                data |= WINCONx_BYTSWP;
 617                break;
 618        case 16:
 619                if (var->transp.length != 0)
 620                        data |= WINCON1_BPPMODE_16BPP_A1555;
 621                else
 622                        data |= WINCON0_BPPMODE_16BPP_565;
 623                data |= WINCONx_HAWSWP;
 624                data |= WINCONx_BURSTLEN_16WORD;
 625                break;
 626        case 24:
 627        case 32:
 628                if (var->red.length == 6) {
 629                        if (var->transp.length != 0)
 630                                data |= WINCON1_BPPMODE_19BPP_A1666;
 631                        else
 632                                data |= WINCON1_BPPMODE_18BPP_666;
 633                } else if (var->transp.length == 1)
 634                        data |= WINCON1_BPPMODE_25BPP_A1888
 635                                | WINCON1_BLD_PIX;
 636                else if ((var->transp.length == 4) ||
 637                        (var->transp.length == 8))
 638                        data |= WINCON1_BPPMODE_28BPP_A4888
 639                                | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 640                else
 641                        data |= WINCON0_BPPMODE_24BPP_888;
 642
 643                data |= WINCONx_WSWP;
 644                data |= WINCONx_BURSTLEN_16WORD;
 645                break;
 646        }
 647
 648        /* Enable the colour keying for the window below this one */
 649        if (win_no > 0) {
 650                u32 keycon0_data = 0, keycon1_data = 0;
 651                void __iomem *keycon = regs + sfb->variant.keycon;
 652
 653                keycon0_data = ~(WxKEYCON0_KEYBL_EN |
 654                                WxKEYCON0_KEYEN_F |
 655                                WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 656
 657                keycon1_data = WxKEYCON1_COLVAL(0xffffff);
 658
 659                keycon += (win_no - 1) * 8;
 660
 661                writel(keycon0_data, keycon + WKEYCON0);
 662                writel(keycon1_data, keycon + WKEYCON1);
 663        }
 664
 665        writel(data, regs + sfb->variant.wincon + (win_no * 4));
 666        writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
 667
 668        /* Set alpha value width */
 669        if (sfb->variant.has_blendcon) {
 670                data = readl(sfb->regs + BLENDCON);
 671                data &= ~BLENDCON_NEW_MASK;
 672                if (var->transp.length > 4)
 673                        data |= BLENDCON_NEW_8BIT_ALPHA_VALUE;
 674                else
 675                        data |= BLENDCON_NEW_4BIT_ALPHA_VALUE;
 676                writel(data, sfb->regs + BLENDCON);
 677        }
 678
 679        shadow_protect_win(win, 0);
 680
 681        pm_runtime_put_sync(sfb->dev);
 682
 683        return 0;
 684}
 685
 686/**
 687 * s3c_fb_update_palette() - set or schedule a palette update.
 688 * @sfb: The hardware information.
 689 * @win: The window being updated.
 690 * @reg: The palette index being changed.
 691 * @value: The computed palette value.
 692 *
 693 * Change the value of a palette register, either by directly writing to
 694 * the palette (this requires the palette RAM to be disconnected from the
 695 * hardware whilst this is in progress) or schedule the update for later.
 696 *
 697 * At the moment, since we have no VSYNC interrupt support, we simply set
 698 * the palette entry directly.
 699 */
 700static void s3c_fb_update_palette(struct s3c_fb *sfb,
 701                                  struct s3c_fb_win *win,
 702                                  unsigned int reg,
 703                                  u32 value)
 704{
 705        void __iomem *palreg;
 706        u32 palcon;
 707
 708        palreg = sfb->regs + sfb->variant.palette[win->index];
 709
 710        dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
 711                __func__, win->index, reg, palreg, value);
 712
 713        win->palette_buffer[reg] = value;
 714
 715        palcon = readl(sfb->regs + WPALCON);
 716        writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
 717
 718        if (win->variant.palette_16bpp)
 719                writew(value, palreg + (reg * 2));
 720        else
 721                writel(value, palreg + (reg * 4));
 722
 723        writel(palcon, sfb->regs + WPALCON);
 724}
 725
 726static inline unsigned int chan_to_field(unsigned int chan,
 727                                         struct fb_bitfield *bf)
 728{
 729        chan &= 0xffff;
 730        chan >>= 16 - bf->length;
 731        return chan << bf->offset;
 732}
 733
 734/**
 735 * s3c_fb_setcolreg() - framebuffer layer request to change palette.
 736 * @regno: The palette index to change.
 737 * @red: The red field for the palette data.
 738 * @green: The green field for the palette data.
 739 * @blue: The blue field for the palette data.
 740 * @trans: The transparency (alpha) field for the palette data.
 741 * @info: The framebuffer being changed.
 742 */
 743static int s3c_fb_setcolreg(unsigned regno,
 744                            unsigned red, unsigned green, unsigned blue,
 745                            unsigned transp, struct fb_info *info)
 746{
 747        struct s3c_fb_win *win = info->par;
 748        struct s3c_fb *sfb = win->parent;
 749        unsigned int val;
 750
 751        dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
 752                __func__, win->index, regno, red, green, blue);
 753
 754        pm_runtime_get_sync(sfb->dev);
 755
 756        switch (info->fix.visual) {
 757        case FB_VISUAL_TRUECOLOR:
 758                /* true-colour, use pseudo-palette */
 759
 760                if (regno < 16) {
 761                        u32 *pal = info->pseudo_palette;
 762
 763                        val  = chan_to_field(red,   &info->var.red);
 764                        val |= chan_to_field(green, &info->var.green);
 765                        val |= chan_to_field(blue,  &info->var.blue);
 766
 767                        pal[regno] = val;
 768                }
 769                break;
 770
 771        case FB_VISUAL_PSEUDOCOLOR:
 772                if (regno < win->variant.palette_sz) {
 773                        val  = chan_to_field(red, &win->palette.r);
 774                        val |= chan_to_field(green, &win->palette.g);
 775                        val |= chan_to_field(blue, &win->palette.b);
 776
 777                        s3c_fb_update_palette(sfb, win, regno, val);
 778                }
 779
 780                break;
 781
 782        default:
 783                pm_runtime_put_sync(sfb->dev);
 784                return 1;       /* unknown type */
 785        }
 786
 787        pm_runtime_put_sync(sfb->dev);
 788        return 0;
 789}
 790
 791/**
 792 * s3c_fb_blank() - blank or unblank the given window
 793 * @blank_mode: The blank state from FB_BLANK_*
 794 * @info: The framebuffer to blank.
 795 *
 796 * Framebuffer layer request to change the power state.
 797 */
 798static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 799{
 800        struct s3c_fb_win *win = info->par;
 801        struct s3c_fb *sfb = win->parent;
 802        unsigned int index = win->index;
 803        u32 wincon;
 804        u32 output_on = sfb->output_on;
 805
 806        dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
 807
 808        pm_runtime_get_sync(sfb->dev);
 809
 810        wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
 811
 812        switch (blank_mode) {
 813        case FB_BLANK_POWERDOWN:
 814                wincon &= ~WINCONx_ENWIN;
 815                sfb->enabled &= ~(1 << index);
 816                /* fall through to FB_BLANK_NORMAL */
 817
 818        case FB_BLANK_NORMAL:
 819                /* disable the DMA and display 0x0 (black) */
 820                shadow_protect_win(win, 1);
 821                writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
 822                       sfb->regs + sfb->variant.winmap + (index * 4));
 823                shadow_protect_win(win, 0);
 824                break;
 825
 826        case FB_BLANK_UNBLANK:
 827                shadow_protect_win(win, 1);
 828                writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
 829                shadow_protect_win(win, 0);
 830                wincon |= WINCONx_ENWIN;
 831                sfb->enabled |= (1 << index);
 832                break;
 833
 834        case FB_BLANK_VSYNC_SUSPEND:
 835        case FB_BLANK_HSYNC_SUSPEND:
 836        default:
 837                pm_runtime_put_sync(sfb->dev);
 838                return 1;
 839        }
 840
 841        shadow_protect_win(win, 1);
 842        writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
 843
 844        /* Check the enabled state to see if we need to be running the
 845         * main LCD interface, as if there are no active windows then
 846         * it is highly likely that we also do not need to output
 847         * anything.
 848         */
 849        s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
 850        shadow_protect_win(win, 0);
 851
 852        pm_runtime_put_sync(sfb->dev);
 853
 854        return output_on == sfb->output_on;
 855}
 856
 857/**
 858 * s3c_fb_pan_display() - Pan the display.
 859 *
 860 * Note that the offsets can be written to the device at any time, as their
 861 * values are latched at each vsync automatically. This also means that only
 862 * the last call to this function will have any effect on next vsync, but
 863 * there is no need to sleep waiting for it to prevent tearing.
 864 *
 865 * @var: The screen information to verify.
 866 * @info: The framebuffer device.
 867 */
 868static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
 869                              struct fb_info *info)
 870{
 871        struct s3c_fb_win *win  = info->par;
 872        struct s3c_fb *sfb      = win->parent;
 873        void __iomem *buf       = sfb->regs + win->index * 8;
 874        unsigned int start_boff, end_boff;
 875
 876        pm_runtime_get_sync(sfb->dev);
 877
 878        /* Offset in bytes to the start of the displayed area */
 879        start_boff = var->yoffset * info->fix.line_length;
 880        /* X offset depends on the current bpp */
 881        if (info->var.bits_per_pixel >= 8) {
 882                start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
 883        } else {
 884                switch (info->var.bits_per_pixel) {
 885                case 4:
 886                        start_boff += var->xoffset >> 1;
 887                        break;
 888                case 2:
 889                        start_boff += var->xoffset >> 2;
 890                        break;
 891                case 1:
 892                        start_boff += var->xoffset >> 3;
 893                        break;
 894                default:
 895                        dev_err(sfb->dev, "invalid bpp\n");
 896                        pm_runtime_put_sync(sfb->dev);
 897                        return -EINVAL;
 898                }
 899        }
 900        /* Offset in bytes to the end of the displayed area */
 901        end_boff = start_boff + info->var.yres * info->fix.line_length;
 902
 903        /* Temporarily turn off per-vsync update from shadow registers until
 904         * both start and end addresses are updated to prevent corruption */
 905        shadow_protect_win(win, 1);
 906
 907        writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
 908        writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
 909
 910        shadow_protect_win(win, 0);
 911
 912        pm_runtime_put_sync(sfb->dev);
 913        return 0;
 914}
 915
 916/**
 917 * s3c_fb_enable_irq() - enable framebuffer interrupts
 918 * @sfb: main hardware state
 919 */
 920static void s3c_fb_enable_irq(struct s3c_fb *sfb)
 921{
 922        void __iomem *regs = sfb->regs;
 923        u32 irq_ctrl_reg;
 924
 925        if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
 926                /* IRQ disabled, enable it */
 927                irq_ctrl_reg = readl(regs + VIDINTCON0);
 928
 929                irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
 930                irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
 931
 932                irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
 933                irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
 934                irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
 935                irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
 936
 937                writel(irq_ctrl_reg, regs + VIDINTCON0);
 938        }
 939}
 940
 941/**
 942 * s3c_fb_disable_irq() - disable framebuffer interrupts
 943 * @sfb: main hardware state
 944 */
 945static void s3c_fb_disable_irq(struct s3c_fb *sfb)
 946{
 947        void __iomem *regs = sfb->regs;
 948        u32 irq_ctrl_reg;
 949
 950        if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
 951                /* IRQ enabled, disable it */
 952                irq_ctrl_reg = readl(regs + VIDINTCON0);
 953
 954                irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
 955                irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
 956
 957                writel(irq_ctrl_reg, regs + VIDINTCON0);
 958        }
 959}
 960
 961static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
 962{
 963        struct s3c_fb *sfb = dev_id;
 964        void __iomem  *regs = sfb->regs;
 965        u32 irq_sts_reg;
 966
 967        spin_lock(&sfb->slock);
 968
 969        irq_sts_reg = readl(regs + VIDINTCON1);
 970
 971        if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
 972
 973                /* VSYNC interrupt, accept it */
 974                writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
 975
 976                sfb->vsync_info.count++;
 977                wake_up_interruptible(&sfb->vsync_info.wait);
 978        }
 979
 980        /* We only support waiting for VSYNC for now, so it's safe
 981         * to always disable irqs here.
 982         */
 983        s3c_fb_disable_irq(sfb);
 984
 985        spin_unlock(&sfb->slock);
 986        return IRQ_HANDLED;
 987}
 988
 989/**
 990 * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
 991 * @sfb: main hardware state
 992 * @crtc: head index.
 993 */
 994static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
 995{
 996        unsigned long count;
 997        int ret;
 998
 999        if (crtc != 0)
1000                return -ENODEV;
1001
1002        pm_runtime_get_sync(sfb->dev);
1003
1004        count = sfb->vsync_info.count;
1005        s3c_fb_enable_irq(sfb);
1006        ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
1007                                       count != sfb->vsync_info.count,
1008                                       msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
1009
1010        pm_runtime_put_sync(sfb->dev);
1011
1012        if (ret == 0)
1013                return -ETIMEDOUT;
1014
1015        return 0;
1016}
1017
1018static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
1019                        unsigned long arg)
1020{
1021        struct s3c_fb_win *win = info->par;
1022        struct s3c_fb *sfb = win->parent;
1023        int ret;
1024        u32 crtc;
1025
1026        switch (cmd) {
1027        case FBIO_WAITFORVSYNC:
1028                if (get_user(crtc, (u32 __user *)arg)) {
1029                        ret = -EFAULT;
1030                        break;
1031                }
1032
1033                ret = s3c_fb_wait_for_vsync(sfb, crtc);
1034                break;
1035        default:
1036                ret = -ENOTTY;
1037        }
1038
1039        return ret;
1040}
1041
1042static struct fb_ops s3c_fb_ops = {
1043        .owner          = THIS_MODULE,
1044        .fb_check_var   = s3c_fb_check_var,
1045        .fb_set_par     = s3c_fb_set_par,
1046        .fb_blank       = s3c_fb_blank,
1047        .fb_setcolreg   = s3c_fb_setcolreg,
1048        .fb_fillrect    = cfb_fillrect,
1049        .fb_copyarea    = cfb_copyarea,
1050        .fb_imageblit   = cfb_imageblit,
1051        .fb_pan_display = s3c_fb_pan_display,
1052        .fb_ioctl       = s3c_fb_ioctl,
1053};
1054
1055/**
1056 * s3c_fb_missing_pixclock() - calculates pixel clock
1057 * @mode: The video mode to change.
1058 *
1059 * Calculate the pixel clock when none has been given through platform data.
1060 */
1061static void s3c_fb_missing_pixclock(struct fb_videomode *mode)
1062{
1063        u64 pixclk = 1000000000000ULL;
1064        u32 div;
1065
1066        div  = mode->left_margin + mode->hsync_len + mode->right_margin +
1067               mode->xres;
1068        div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
1069               mode->yres;
1070        div *= mode->refresh ? : 60;
1071
1072        do_div(pixclk, div);
1073
1074        mode->pixclock = pixclk;
1075}
1076
1077/**
1078 * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
1079 * @sfb: The base resources for the hardware.
1080 * @win: The window to initialise memory for.
1081 *
1082 * Allocate memory for the given framebuffer.
1083 */
1084static int s3c_fb_alloc_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1085{
1086        struct s3c_fb_pd_win *windata = win->windata;
1087        unsigned int real_size, virt_size, size;
1088        struct fb_info *fbi = win->fbinfo;
1089        dma_addr_t map_dma;
1090
1091        dev_dbg(sfb->dev, "allocating memory for display\n");
1092
1093        real_size = windata->xres * windata->yres;
1094        virt_size = windata->virtual_x * windata->virtual_y;
1095
1096        dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1097                real_size, windata->xres, windata->yres,
1098                virt_size, windata->virtual_x, windata->virtual_y);
1099
1100        size = (real_size > virt_size) ? real_size : virt_size;
1101        size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
1102        size /= 8;
1103
1104        fbi->fix.smem_len = size;
1105        size = PAGE_ALIGN(size);
1106
1107        dev_dbg(sfb->dev, "want %u bytes for window\n", size);
1108
1109        fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
1110                                                  &map_dma, GFP_KERNEL);
1111        if (!fbi->screen_base)
1112                return -ENOMEM;
1113
1114        dev_dbg(sfb->dev, "mapped %x to %p\n",
1115                (unsigned int)map_dma, fbi->screen_base);
1116
1117        memset(fbi->screen_base, 0x0, size);
1118        fbi->fix.smem_start = map_dma;
1119
1120        return 0;
1121}
1122
1123/**
1124 * s3c_fb_free_memory() - free the display memory for the given window
1125 * @sfb: The base resources for the hardware.
1126 * @win: The window to free the display memory for.
1127 *
1128 * Free the display memory allocated by s3c_fb_alloc_memory().
1129 */
1130static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1131{
1132        struct fb_info *fbi = win->fbinfo;
1133
1134        if (fbi->screen_base)
1135                dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
1136                              fbi->screen_base, fbi->fix.smem_start);
1137}
1138
1139/**
1140 * s3c_fb_release_win() - release resources for a framebuffer window.
1141 * @win: The window to cleanup the resources for.
1142 *
1143 * Release the resources that where claimed for the hardware window,
1144 * such as the framebuffer instance and any memory claimed for it.
1145 */
1146static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
1147{
1148        u32 data;
1149
1150        if (win->fbinfo) {
1151                if (sfb->variant.has_shadowcon) {
1152                        data = readl(sfb->regs + SHADOWCON);
1153                        data &= ~SHADOWCON_CHx_ENABLE(win->index);
1154                        data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
1155                        writel(data, sfb->regs + SHADOWCON);
1156                }
1157                unregister_framebuffer(win->fbinfo);
1158                if (win->fbinfo->cmap.len)
1159                        fb_dealloc_cmap(&win->fbinfo->cmap);
1160                s3c_fb_free_memory(sfb, win);
1161                framebuffer_release(win->fbinfo);
1162        }
1163}
1164
1165/**
1166 * s3c_fb_probe_win() - register an hardware window
1167 * @sfb: The base resources for the hardware
1168 * @variant: The variant information for this window.
1169 * @res: Pointer to where to place the resultant window.
1170 *
1171 * Allocate and do the basic initialisation for one of the hardware's graphics
1172 * windows.
1173 */
1174static int s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
1175                            struct s3c_fb_win_variant *variant,
1176                            struct s3c_fb_win **res)
1177{
1178        struct fb_var_screeninfo *var;
1179        struct fb_videomode initmode;
1180        struct s3c_fb_pd_win *windata;
1181        struct s3c_fb_win *win;
1182        struct fb_info *fbinfo;
1183        int palette_size;
1184        int ret;
1185
1186        dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
1187
1188        init_waitqueue_head(&sfb->vsync_info.wait);
1189
1190        palette_size = variant->palette_sz * 4;
1191
1192        fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
1193                                   palette_size * sizeof(u32), sfb->dev);
1194        if (!fbinfo) {
1195                dev_err(sfb->dev, "failed to allocate framebuffer\n");
1196                return -ENOENT;
1197        }
1198
1199        windata = sfb->pdata->win[win_no];
1200        initmode = *sfb->pdata->vtiming;
1201
1202        WARN_ON(windata->max_bpp == 0);
1203        WARN_ON(windata->xres == 0);
1204        WARN_ON(windata->yres == 0);
1205
1206        win = fbinfo->par;
1207        *res = win;
1208        var = &fbinfo->var;
1209        win->variant = *variant;
1210        win->fbinfo = fbinfo;
1211        win->parent = sfb;
1212        win->windata = windata;
1213        win->index = win_no;
1214        win->palette_buffer = (u32 *)(win + 1);
1215
1216        ret = s3c_fb_alloc_memory(sfb, win);
1217        if (ret) {
1218                dev_err(sfb->dev, "failed to allocate display memory\n");
1219                return ret;
1220        }
1221
1222        /* setup the r/b/g positions for the window's palette */
1223        if (win->variant.palette_16bpp) {
1224                /* Set RGB 5:6:5 as default */
1225                win->palette.r.offset = 11;
1226                win->palette.r.length = 5;
1227                win->palette.g.offset = 5;
1228                win->palette.g.length = 6;
1229                win->palette.b.offset = 0;
1230                win->palette.b.length = 5;
1231
1232        } else {
1233                /* Set 8bpp or 8bpp and 1bit alpha */
1234                win->palette.r.offset = 16;
1235                win->palette.r.length = 8;
1236                win->palette.g.offset = 8;
1237                win->palette.g.length = 8;
1238                win->palette.b.offset = 0;
1239                win->palette.b.length = 8;
1240        }
1241
1242        /* setup the initial video mode from the window */
1243        initmode.xres = windata->xres;
1244        initmode.yres = windata->yres;
1245        fb_videomode_to_var(&fbinfo->var, &initmode);
1246
1247        fbinfo->fix.type        = FB_TYPE_PACKED_PIXELS;
1248        fbinfo->fix.accel       = FB_ACCEL_NONE;
1249        fbinfo->var.activate    = FB_ACTIVATE_NOW;
1250        fbinfo->var.vmode       = FB_VMODE_NONINTERLACED;
1251        fbinfo->var.bits_per_pixel = windata->default_bpp;
1252        fbinfo->fbops           = &s3c_fb_ops;
1253        fbinfo->flags           = FBINFO_FLAG_DEFAULT;
1254        fbinfo->pseudo_palette  = &win->pseudo_palette;
1255
1256        /* prepare to actually start the framebuffer */
1257
1258        ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
1259        if (ret < 0) {
1260                dev_err(sfb->dev, "check_var failed on initial video params\n");
1261                return ret;
1262        }
1263
1264        /* create initial colour map */
1265
1266        ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
1267        if (ret == 0)
1268                fb_set_cmap(&fbinfo->cmap, fbinfo);
1269        else
1270                dev_err(sfb->dev, "failed to allocate fb cmap\n");
1271
1272        s3c_fb_set_par(fbinfo);
1273
1274        dev_dbg(sfb->dev, "about to register framebuffer\n");
1275
1276        /* run the check_var and set_par on our configuration. */
1277
1278        ret = register_framebuffer(fbinfo);
1279        if (ret < 0) {
1280                dev_err(sfb->dev, "failed to register framebuffer\n");
1281                return ret;
1282        }
1283
1284        dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
1285
1286        return 0;
1287}
1288
1289/**
1290 * s3c_fb_set_rgb_timing() - set video timing for rgb interface.
1291 * @sfb: The base resources for the hardware.
1292 *
1293 * Set horizontal and vertical lcd rgb interface timing.
1294 */
1295static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb)
1296{
1297        struct fb_videomode *vmode = sfb->pdata->vtiming;
1298        void __iomem *regs = sfb->regs;
1299        int clkdiv;
1300        u32 data;
1301
1302        if (!vmode->pixclock)
1303                s3c_fb_missing_pixclock(vmode);
1304
1305        clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);
1306
1307        data = sfb->pdata->vidcon0;
1308        data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
1309
1310        if (clkdiv > 1)
1311                data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
1312        else
1313                data &= ~VIDCON0_CLKDIR;        /* 1:1 clock */
1314
1315        if (sfb->variant.is_2443)
1316                data |= (1 << 5);
1317        writel(data, regs + VIDCON0);
1318
1319        data = VIDTCON0_VBPD(vmode->upper_margin - 1) |
1320               VIDTCON0_VFPD(vmode->lower_margin - 1) |
1321               VIDTCON0_VSPW(vmode->vsync_len - 1);
1322        writel(data, regs + sfb->variant.vidtcon);
1323
1324        data = VIDTCON1_HBPD(vmode->left_margin - 1) |
1325               VIDTCON1_HFPD(vmode->right_margin - 1) |
1326               VIDTCON1_HSPW(vmode->hsync_len - 1);
1327        writel(data, regs + sfb->variant.vidtcon + 4);
1328
1329        data = VIDTCON2_LINEVAL(vmode->yres - 1) |
1330               VIDTCON2_HOZVAL(vmode->xres - 1) |
1331               VIDTCON2_LINEVAL_E(vmode->yres - 1) |
1332               VIDTCON2_HOZVAL_E(vmode->xres - 1);
1333        writel(data, regs + sfb->variant.vidtcon + 8);
1334}
1335
1336/**
1337 * s3c_fb_clear_win() - clear hardware window registers.
1338 * @sfb: The base resources for the hardware.
1339 * @win: The window to process.
1340 *
1341 * Reset the specific window registers to a known state.
1342 */
1343static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
1344{
1345        void __iomem *regs = sfb->regs;
1346        u32 reg;
1347
1348        writel(0, regs + sfb->variant.wincon + (win * 4));
1349        writel(0, regs + VIDOSD_A(win, sfb->variant));
1350        writel(0, regs + VIDOSD_B(win, sfb->variant));
1351        writel(0, regs + VIDOSD_C(win, sfb->variant));
1352
1353        if (sfb->variant.has_shadowcon) {
1354                reg = readl(sfb->regs + SHADOWCON);
1355                reg &= ~(SHADOWCON_WINx_PROTECT(win) |
1356                        SHADOWCON_CHx_ENABLE(win) |
1357                        SHADOWCON_CHx_LOCAL_ENABLE(win));
1358                writel(reg, sfb->regs + SHADOWCON);
1359        }
1360}
1361
1362static int s3c_fb_probe(struct platform_device *pdev)
1363{
1364        const struct platform_device_id *platid;
1365        struct s3c_fb_driverdata *fbdrv;
1366        struct device *dev = &pdev->dev;
1367        struct s3c_fb_platdata *pd;
1368        struct s3c_fb *sfb;
1369        struct resource *res;
1370        int win;
1371        int ret = 0;
1372        u32 reg;
1373
1374        platid = platform_get_device_id(pdev);
1375        fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;
1376
1377        if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
1378                dev_err(dev, "too many windows, cannot attach\n");
1379                return -EINVAL;
1380        }
1381
1382        pd = pdev->dev.platform_data;
1383        if (!pd) {
1384                dev_err(dev, "no platform data specified\n");
1385                return -EINVAL;
1386        }
1387
1388        sfb = devm_kzalloc(dev, sizeof(struct s3c_fb), GFP_KERNEL);
1389        if (!sfb) {
1390                dev_err(dev, "no memory for framebuffers\n");
1391                return -ENOMEM;
1392        }
1393
1394        dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
1395
1396        sfb->dev = dev;
1397        sfb->pdata = pd;
1398        sfb->variant = fbdrv->variant;
1399
1400        spin_lock_init(&sfb->slock);
1401
1402        sfb->bus_clk = devm_clk_get(dev, "lcd");
1403        if (IS_ERR(sfb->bus_clk)) {
1404                dev_err(dev, "failed to get bus clock\n");
1405                return PTR_ERR(sfb->bus_clk);
1406        }
1407
1408        clk_prepare_enable(sfb->bus_clk);
1409
1410        if (!sfb->variant.has_clksel) {
1411                sfb->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1412                if (IS_ERR(sfb->lcd_clk)) {
1413                        dev_err(dev, "failed to get lcd clock\n");
1414                        ret = PTR_ERR(sfb->lcd_clk);
1415                        goto err_bus_clk;
1416                }
1417
1418                clk_prepare_enable(sfb->lcd_clk);
1419        }
1420
1421        pm_runtime_enable(sfb->dev);
1422
1423        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1424        sfb->regs = devm_ioremap_resource(dev, res);
1425        if (IS_ERR(sfb->regs)) {
1426                ret = PTR_ERR(sfb->regs);
1427                goto err_lcd_clk;
1428        }
1429
1430        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1431        if (!res) {
1432                dev_err(dev, "failed to acquire irq resource\n");
1433                ret = -ENOENT;
1434                goto err_lcd_clk;
1435        }
1436        sfb->irq_no = res->start;
1437        ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq,
1438                          0, "s3c_fb", sfb);
1439        if (ret) {
1440                dev_err(dev, "irq request failed\n");
1441                goto err_lcd_clk;
1442        }
1443
1444        dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
1445
1446        platform_set_drvdata(pdev, sfb);
1447        pm_runtime_get_sync(sfb->dev);
1448
1449        /* setup gpio and output polarity controls */
1450
1451        pd->setup_gpio();
1452
1453        writel(pd->vidcon1, sfb->regs + VIDCON1);
1454
1455        /* set video clock running at under-run */
1456        if (sfb->variant.has_fixvclk) {
1457                reg = readl(sfb->regs + VIDCON1);
1458                reg &= ~VIDCON1_VCLK_MASK;
1459                reg |= VIDCON1_VCLK_RUN;
1460                writel(reg, sfb->regs + VIDCON1);
1461        }
1462
1463        /* zero all windows before we do anything */
1464
1465        for (win = 0; win < fbdrv->variant.nr_windows; win++)
1466                s3c_fb_clear_win(sfb, win);
1467
1468        /* initialise colour key controls */
1469        for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
1470                void __iomem *regs = sfb->regs + sfb->variant.keycon;
1471
1472                regs += (win * 8);
1473                writel(0xffffff, regs + WKEYCON0);
1474                writel(0xffffff, regs + WKEYCON1);
1475        }
1476
1477        s3c_fb_set_rgb_timing(sfb);
1478
1479        /* we have the register setup, start allocating framebuffers */
1480
1481        for (win = 0; win < fbdrv->variant.nr_windows; win++) {
1482                if (!pd->win[win])
1483                        continue;
1484
1485                ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
1486                                       &sfb->windows[win]);
1487                if (ret < 0) {
1488                        dev_err(dev, "failed to create window %d\n", win);
1489                        for (; win >= 0; win--)
1490                                s3c_fb_release_win(sfb, sfb->windows[win]);
1491                        goto err_pm_runtime;
1492                }
1493        }
1494
1495        platform_set_drvdata(pdev, sfb);
1496        pm_runtime_put_sync(sfb->dev);
1497
1498        return 0;
1499
1500err_pm_runtime:
1501        pm_runtime_put_sync(sfb->dev);
1502
1503err_lcd_clk:
1504        pm_runtime_disable(sfb->dev);
1505
1506        if (!sfb->variant.has_clksel)
1507                clk_disable_unprepare(sfb->lcd_clk);
1508
1509err_bus_clk:
1510        clk_disable_unprepare(sfb->bus_clk);
1511
1512        return ret;
1513}
1514
1515/**
1516 * s3c_fb_remove() - Cleanup on module finalisation
1517 * @pdev: The platform device we are bound to.
1518 *
1519 * Shutdown and then release all the resources that the driver allocated
1520 * on initialisation.
1521 */
1522static int s3c_fb_remove(struct platform_device *pdev)
1523{
1524        struct s3c_fb *sfb = platform_get_drvdata(pdev);
1525        int win;
1526
1527        pm_runtime_get_sync(sfb->dev);
1528
1529        for (win = 0; win < S3C_FB_MAX_WIN; win++)
1530                if (sfb->windows[win])
1531                        s3c_fb_release_win(sfb, sfb->windows[win]);
1532
1533        if (!sfb->variant.has_clksel)
1534                clk_disable_unprepare(sfb->lcd_clk);
1535
1536        clk_disable_unprepare(sfb->bus_clk);
1537
1538        pm_runtime_put_sync(sfb->dev);
1539        pm_runtime_disable(sfb->dev);
1540
1541        return 0;
1542}
1543
1544#ifdef CONFIG_PM_SLEEP
1545static int s3c_fb_suspend(struct device *dev)
1546{
1547        struct s3c_fb *sfb = dev_get_drvdata(dev);
1548        struct s3c_fb_win *win;
1549        int win_no;
1550
1551        pm_runtime_get_sync(sfb->dev);
1552
1553        for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
1554                win = sfb->windows[win_no];
1555                if (!win)
1556                        continue;
1557
1558                /* use the blank function to push into power-down */
1559                s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
1560        }
1561
1562        if (!sfb->variant.has_clksel)
1563                clk_disable_unprepare(sfb->lcd_clk);
1564
1565        clk_disable_unprepare(sfb->bus_clk);
1566
1567        pm_runtime_put_sync(sfb->dev);
1568
1569        return 0;
1570}
1571
1572static int s3c_fb_resume(struct device *dev)
1573{
1574        struct s3c_fb *sfb = dev_get_drvdata(dev);
1575        struct s3c_fb_platdata *pd = sfb->pdata;
1576        struct s3c_fb_win *win;
1577        int win_no;
1578        u32 reg;
1579
1580        pm_runtime_get_sync(sfb->dev);
1581
1582        clk_prepare_enable(sfb->bus_clk);
1583
1584        if (!sfb->variant.has_clksel)
1585                clk_prepare_enable(sfb->lcd_clk);
1586
1587        /* setup gpio and output polarity controls */
1588        pd->setup_gpio();
1589        writel(pd->vidcon1, sfb->regs + VIDCON1);
1590
1591        /* set video clock running at under-run */
1592        if (sfb->variant.has_fixvclk) {
1593                reg = readl(sfb->regs + VIDCON1);
1594                reg &= ~VIDCON1_VCLK_MASK;
1595                reg |= VIDCON1_VCLK_RUN;
1596                writel(reg, sfb->regs + VIDCON1);
1597        }
1598
1599        /* zero all windows before we do anything */
1600        for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1601                s3c_fb_clear_win(sfb, win_no);
1602
1603        for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1604                void __iomem *regs = sfb->regs + sfb->variant.keycon;
1605                win = sfb->windows[win_no];
1606                if (!win)
1607                        continue;
1608
1609                shadow_protect_win(win, 1);
1610                regs += (win_no * 8);
1611                writel(0xffffff, regs + WKEYCON0);
1612                writel(0xffffff, regs + WKEYCON1);
1613                shadow_protect_win(win, 0);
1614        }
1615
1616        s3c_fb_set_rgb_timing(sfb);
1617
1618        /* restore framebuffers */
1619        for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
1620                win = sfb->windows[win_no];
1621                if (!win)
1622                        continue;
1623
1624                dev_dbg(dev, "resuming window %d\n", win_no);
1625                s3c_fb_set_par(win->fbinfo);
1626        }
1627
1628        pm_runtime_put_sync(sfb->dev);
1629
1630        return 0;
1631}
1632#endif
1633
1634#ifdef CONFIG_PM_RUNTIME
1635static int s3c_fb_runtime_suspend(struct device *dev)
1636{
1637        struct s3c_fb *sfb = dev_get_drvdata(dev);
1638
1639        if (!sfb->variant.has_clksel)
1640                clk_disable_unprepare(sfb->lcd_clk);
1641
1642        clk_disable_unprepare(sfb->bus_clk);
1643
1644        return 0;
1645}
1646
1647static int s3c_fb_runtime_resume(struct device *dev)
1648{
1649        struct s3c_fb *sfb = dev_get_drvdata(dev);
1650        struct s3c_fb_platdata *pd = sfb->pdata;
1651
1652        clk_prepare_enable(sfb->bus_clk);
1653
1654        if (!sfb->variant.has_clksel)
1655                clk_prepare_enable(sfb->lcd_clk);
1656
1657        /* setup gpio and output polarity controls */
1658        pd->setup_gpio();
1659        writel(pd->vidcon1, sfb->regs + VIDCON1);
1660
1661        return 0;
1662}
1663#endif
1664
1665#define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
1666#define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
1667
1668static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
1669        [0] = {
1670                .has_osd_c      = 1,
1671                .osd_size_off   = 0x8,
1672                .palette_sz     = 256,
1673                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1674                                   VALID_BPP(18) | VALID_BPP(24)),
1675        },
1676        [1] = {
1677                .has_osd_c      = 1,
1678                .has_osd_d      = 1,
1679                .osd_size_off   = 0xc,
1680                .has_osd_alpha  = 1,
1681                .palette_sz     = 256,
1682                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1683                                   VALID_BPP(18) | VALID_BPP(19) |
1684                                   VALID_BPP(24) | VALID_BPP(25) |
1685                                   VALID_BPP(28)),
1686        },
1687        [2] = {
1688                .has_osd_c      = 1,
1689                .has_osd_d      = 1,
1690                .osd_size_off   = 0xc,
1691                .has_osd_alpha  = 1,
1692                .palette_sz     = 16,
1693                .palette_16bpp  = 1,
1694                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1695                                   VALID_BPP(18) | VALID_BPP(19) |
1696                                   VALID_BPP(24) | VALID_BPP(25) |
1697                                   VALID_BPP(28)),
1698        },
1699        [3] = {
1700                .has_osd_c      = 1,
1701                .has_osd_alpha  = 1,
1702                .palette_sz     = 16,
1703                .palette_16bpp  = 1,
1704                .valid_bpp      = (VALID_BPP124  | VALID_BPP(16) |
1705                                   VALID_BPP(18) | VALID_BPP(19) |
1706                                   VALID_BPP(24) | VALID_BPP(25) |
1707                                   VALID_BPP(28)),
1708        },
1709        [4] = {
1710                .has_osd_c      = 1,
1711                .has_osd_alpha  = 1,
1712                .palette_sz     = 4,
1713                .palette_16bpp  = 1,
1714                .valid_bpp      = (VALID_BPP(1) | VALID_BPP(2) |
1715                                   VALID_BPP(16) | VALID_BPP(18) |
1716                                   VALID_BPP(19) | VALID_BPP(24) |
1717                                   VALID_BPP(25) | VALID_BPP(28)),
1718        },
1719};
1720
1721static struct s3c_fb_win_variant s3c_fb_data_s5p_wins[] = {
1722        [0] = {
1723                .has_osd_c      = 1,
1724                .osd_size_off   = 0x8,
1725                .palette_sz     = 256,
1726                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(13) |
1727                                   VALID_BPP(15) | VALID_BPP(16) |
1728                                   VALID_BPP(18) | VALID_BPP(19) |
1729                                   VALID_BPP(24) | VALID_BPP(25) |
1730                                   VALID_BPP(32)),
1731        },
1732        [1] = {
1733                .has_osd_c      = 1,
1734                .has_osd_d      = 1,
1735                .osd_size_off   = 0xc,
1736                .has_osd_alpha  = 1,
1737                .palette_sz     = 256,
1738                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(13) |
1739                                   VALID_BPP(15) | VALID_BPP(16) |
1740                                   VALID_BPP(18) | VALID_BPP(19) |
1741                                   VALID_BPP(24) | VALID_BPP(25) |
1742                                   VALID_BPP(32)),
1743        },
1744        [2] = {
1745                .has_osd_c      = 1,
1746                .has_osd_d      = 1,
1747                .osd_size_off   = 0xc,
1748                .has_osd_alpha  = 1,
1749                .palette_sz     = 256,
1750                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(13) |
1751                                   VALID_BPP(15) | VALID_BPP(16) |
1752                                   VALID_BPP(18) | VALID_BPP(19) |
1753                                   VALID_BPP(24) | VALID_BPP(25) |
1754                                   VALID_BPP(32)),
1755        },
1756        [3] = {
1757                .has_osd_c      = 1,
1758                .has_osd_alpha  = 1,
1759                .palette_sz     = 256,
1760                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(13) |
1761                                   VALID_BPP(15) | VALID_BPP(16) |
1762                                   VALID_BPP(18) | VALID_BPP(19) |
1763                                   VALID_BPP(24) | VALID_BPP(25) |
1764                                   VALID_BPP(32)),
1765        },
1766        [4] = {
1767                .has_osd_c      = 1,
1768                .has_osd_alpha  = 1,
1769                .palette_sz     = 256,
1770                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(13) |
1771                                   VALID_BPP(15) | VALID_BPP(16) |
1772                                   VALID_BPP(18) | VALID_BPP(19) |
1773                                   VALID_BPP(24) | VALID_BPP(25) |
1774                                   VALID_BPP(32)),
1775        },
1776};
1777
1778static struct s3c_fb_driverdata s3c_fb_data_64xx = {
1779        .variant = {
1780                .nr_windows     = 5,
1781                .vidtcon        = VIDTCON0,
1782                .wincon         = WINCON(0),
1783                .winmap         = WINxMAP(0),
1784                .keycon         = WKEYCON,
1785                .osd            = VIDOSD_BASE,
1786                .osd_stride     = 16,
1787                .buf_start      = VIDW_BUF_START(0),
1788                .buf_size       = VIDW_BUF_SIZE(0),
1789                .buf_end        = VIDW_BUF_END(0),
1790
1791                .palette = {
1792                        [0] = 0x400,
1793                        [1] = 0x800,
1794                        [2] = 0x300,
1795                        [3] = 0x320,
1796                        [4] = 0x340,
1797                },
1798
1799                .has_prtcon     = 1,
1800                .has_clksel     = 1,
1801        },
1802        .win[0] = &s3c_fb_data_64xx_wins[0],
1803        .win[1] = &s3c_fb_data_64xx_wins[1],
1804        .win[2] = &s3c_fb_data_64xx_wins[2],
1805        .win[3] = &s3c_fb_data_64xx_wins[3],
1806        .win[4] = &s3c_fb_data_64xx_wins[4],
1807};
1808
1809static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = {
1810        .variant = {
1811                .nr_windows     = 5,
1812                .vidtcon        = VIDTCON0,
1813                .wincon         = WINCON(0),
1814                .winmap         = WINxMAP(0),
1815                .keycon         = WKEYCON,
1816                .osd            = VIDOSD_BASE,
1817                .osd_stride     = 16,
1818                .buf_start      = VIDW_BUF_START(0),
1819                .buf_size       = VIDW_BUF_SIZE(0),
1820                .buf_end        = VIDW_BUF_END(0),
1821
1822                .palette = {
1823                        [0] = 0x2400,
1824                        [1] = 0x2800,
1825                        [2] = 0x2c00,
1826                        [3] = 0x3000,
1827                        [4] = 0x3400,
1828                },
1829
1830                .has_prtcon     = 1,
1831                .has_blendcon   = 1,
1832                .has_clksel     = 1,
1833        },
1834        .win[0] = &s3c_fb_data_s5p_wins[0],
1835        .win[1] = &s3c_fb_data_s5p_wins[1],
1836        .win[2] = &s3c_fb_data_s5p_wins[2],
1837        .win[3] = &s3c_fb_data_s5p_wins[3],
1838        .win[4] = &s3c_fb_data_s5p_wins[4],
1839};
1840
1841static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
1842        .variant = {
1843                .nr_windows     = 5,
1844                .vidtcon        = VIDTCON0,
1845                .wincon         = WINCON(0),
1846                .winmap         = WINxMAP(0),
1847                .keycon         = WKEYCON,
1848                .osd            = VIDOSD_BASE,
1849                .osd_stride     = 16,
1850                .buf_start      = VIDW_BUF_START(0),
1851                .buf_size       = VIDW_BUF_SIZE(0),
1852                .buf_end        = VIDW_BUF_END(0),
1853
1854                .palette = {
1855                        [0] = 0x2400,
1856                        [1] = 0x2800,
1857                        [2] = 0x2c00,
1858                        [3] = 0x3000,
1859                        [4] = 0x3400,
1860                },
1861
1862                .has_shadowcon  = 1,
1863                .has_blendcon   = 1,
1864                .has_clksel     = 1,
1865                .has_fixvclk    = 1,
1866        },
1867        .win[0] = &s3c_fb_data_s5p_wins[0],
1868        .win[1] = &s3c_fb_data_s5p_wins[1],
1869        .win[2] = &s3c_fb_data_s5p_wins[2],
1870        .win[3] = &s3c_fb_data_s5p_wins[3],
1871        .win[4] = &s3c_fb_data_s5p_wins[4],
1872};
1873
1874static struct s3c_fb_driverdata s3c_fb_data_exynos4 = {
1875        .variant = {
1876                .nr_windows     = 5,
1877                .vidtcon        = VIDTCON0,
1878                .wincon         = WINCON(0),
1879                .winmap         = WINxMAP(0),
1880                .keycon         = WKEYCON,
1881                .osd            = VIDOSD_BASE,
1882                .osd_stride     = 16,
1883                .buf_start      = VIDW_BUF_START(0),
1884                .buf_size       = VIDW_BUF_SIZE(0),
1885                .buf_end        = VIDW_BUF_END(0),
1886
1887                .palette = {
1888                        [0] = 0x2400,
1889                        [1] = 0x2800,
1890                        [2] = 0x2c00,
1891                        [3] = 0x3000,
1892                        [4] = 0x3400,
1893                },
1894
1895                .has_shadowcon  = 1,
1896                .has_blendcon   = 1,
1897                .has_fixvclk    = 1,
1898        },
1899        .win[0] = &s3c_fb_data_s5p_wins[0],
1900        .win[1] = &s3c_fb_data_s5p_wins[1],
1901        .win[2] = &s3c_fb_data_s5p_wins[2],
1902        .win[3] = &s3c_fb_data_s5p_wins[3],
1903        .win[4] = &s3c_fb_data_s5p_wins[4],
1904};
1905
1906static struct s3c_fb_driverdata s3c_fb_data_exynos5 = {
1907        .variant = {
1908                .nr_windows     = 5,
1909                .vidtcon        = FIMD_V8_VIDTCON0,
1910                .wincon         = WINCON(0),
1911                .winmap         = WINxMAP(0),
1912                .keycon         = WKEYCON,
1913                .osd            = VIDOSD_BASE,
1914                .osd_stride     = 16,
1915                .buf_start      = VIDW_BUF_START(0),
1916                .buf_size       = VIDW_BUF_SIZE(0),
1917                .buf_end        = VIDW_BUF_END(0),
1918
1919                .palette = {
1920                        [0] = 0x2400,
1921                        [1] = 0x2800,
1922                        [2] = 0x2c00,
1923                        [3] = 0x3000,
1924                        [4] = 0x3400,
1925                },
1926                .has_shadowcon  = 1,
1927                .has_blendcon   = 1,
1928                .has_fixvclk    = 1,
1929        },
1930        .win[0] = &s3c_fb_data_s5p_wins[0],
1931        .win[1] = &s3c_fb_data_s5p_wins[1],
1932        .win[2] = &s3c_fb_data_s5p_wins[2],
1933        .win[3] = &s3c_fb_data_s5p_wins[3],
1934        .win[4] = &s3c_fb_data_s5p_wins[4],
1935};
1936
1937/* S3C2443/S3C2416 style hardware */
1938static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
1939        .variant = {
1940                .nr_windows     = 2,
1941                .is_2443        = 1,
1942
1943                .vidtcon        = 0x08,
1944                .wincon         = 0x14,
1945                .winmap         = 0xd0,
1946                .keycon         = 0xb0,
1947                .osd            = 0x28,
1948                .osd_stride     = 12,
1949                .buf_start      = 0x64,
1950                .buf_size       = 0x94,
1951                .buf_end        = 0x7c,
1952
1953                .palette = {
1954                        [0] = 0x400,
1955                        [1] = 0x800,
1956                },
1957                .has_clksel     = 1,
1958        },
1959        .win[0] = &(struct s3c_fb_win_variant) {
1960                .palette_sz     = 256,
1961                .valid_bpp      = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1962        },
1963        .win[1] = &(struct s3c_fb_win_variant) {
1964                .has_osd_c      = 1,
1965                .has_osd_alpha  = 1,
1966                .palette_sz     = 256,
1967                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1968                                   VALID_BPP(18) | VALID_BPP(19) |
1969                                   VALID_BPP(24) | VALID_BPP(25) |
1970                                   VALID_BPP(28)),
1971        },
1972};
1973
1974static struct s3c_fb_driverdata s3c_fb_data_s5p64x0 = {
1975        .variant = {
1976                .nr_windows     = 3,
1977                .vidtcon        = VIDTCON0,
1978                .wincon         = WINCON(0),
1979                .winmap         = WINxMAP(0),
1980                .keycon         = WKEYCON,
1981                .osd            = VIDOSD_BASE,
1982                .osd_stride     = 16,
1983                .buf_start      = VIDW_BUF_START(0),
1984                .buf_size       = VIDW_BUF_SIZE(0),
1985                .buf_end        = VIDW_BUF_END(0),
1986
1987                .palette = {
1988                        [0] = 0x2400,
1989                        [1] = 0x2800,
1990                        [2] = 0x2c00,
1991                },
1992
1993                .has_blendcon   = 1,
1994                .has_fixvclk    = 1,
1995        },
1996        .win[0] = &s3c_fb_data_s5p_wins[0],
1997        .win[1] = &s3c_fb_data_s5p_wins[1],
1998        .win[2] = &s3c_fb_data_s5p_wins[2],
1999};
2000
2001static struct platform_device_id s3c_fb_driver_ids[] = {
2002        {
2003                .name           = "s3c-fb",
2004                .driver_data    = (unsigned long)&s3c_fb_data_64xx,
2005        }, {
2006                .name           = "s5pc100-fb",
2007                .driver_data    = (unsigned long)&s3c_fb_data_s5pc100,
2008        }, {
2009                .name           = "s5pv210-fb",
2010                .driver_data    = (unsigned long)&s3c_fb_data_s5pv210,
2011        }, {
2012                .name           = "exynos4-fb",
2013                .driver_data    = (unsigned long)&s3c_fb_data_exynos4,
2014        }, {
2015                .name           = "exynos5-fb",
2016                .driver_data    = (unsigned long)&s3c_fb_data_exynos5,
2017        }, {
2018                .name           = "s3c2443-fb",
2019                .driver_data    = (unsigned long)&s3c_fb_data_s3c2443,
2020        }, {
2021                .name           = "s5p64x0-fb",
2022                .driver_data    = (unsigned long)&s3c_fb_data_s5p64x0,
2023        },
2024        {},
2025};
2026MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
2027
2028static const struct dev_pm_ops s3cfb_pm_ops = {
2029        SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)
2030        SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume,
2031                           NULL)
2032};
2033
2034static struct platform_driver s3c_fb_driver = {
2035        .probe          = s3c_fb_probe,
2036        .remove         = s3c_fb_remove,
2037        .id_table       = s3c_fb_driver_ids,
2038        .driver         = {
2039                .name   = "s3c-fb",
2040                .owner  = THIS_MODULE,
2041                .pm     = &s3cfb_pm_ops,
2042        },
2043};
2044
2045module_platform_driver(s3c_fb_driver);
2046
2047MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2048MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
2049MODULE_LICENSE("GPL");
2050MODULE_ALIAS("platform:s3c-fb");
2051
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