linux/drivers/spi/spi-txx9.c
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   1/*
   2 * TXx9 SPI controller driver.
   3 *
   4 * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
   5 * Copyright (C) 2000-2001 Toshiba Corporation
   6 *
   7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   8 * terms of the GNU General Public License version 2. This program is
   9 * licensed "as is" without any warranty of any kind, whether express
  10 * or implied.
  11 *
  12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  13 *
  14 * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
  15 */
  16#include <linux/init.h>
  17#include <linux/delay.h>
  18#include <linux/errno.h>
  19#include <linux/interrupt.h>
  20#include <linux/platform_device.h>
  21#include <linux/sched.h>
  22#include <linux/spinlock.h>
  23#include <linux/workqueue.h>
  24#include <linux/spi/spi.h>
  25#include <linux/err.h>
  26#include <linux/clk.h>
  27#include <linux/io.h>
  28#include <linux/module.h>
  29#include <asm/gpio.h>
  30
  31
  32#define SPI_FIFO_SIZE 4
  33#define SPI_MAX_DIVIDER 0xff    /* Max. value for SPCR1.SER */
  34#define SPI_MIN_DIVIDER 1       /* Min. value for SPCR1.SER */
  35
  36#define TXx9_SPMCR              0x00
  37#define TXx9_SPCR0              0x04
  38#define TXx9_SPCR1              0x08
  39#define TXx9_SPFS               0x0c
  40#define TXx9_SPSR               0x14
  41#define TXx9_SPDR               0x18
  42
  43/* SPMCR : SPI Master Control */
  44#define TXx9_SPMCR_OPMODE       0xc0
  45#define TXx9_SPMCR_CONFIG       0x40
  46#define TXx9_SPMCR_ACTIVE       0x80
  47#define TXx9_SPMCR_SPSTP        0x02
  48#define TXx9_SPMCR_BCLR         0x01
  49
  50/* SPCR0 : SPI Control 0 */
  51#define TXx9_SPCR0_TXIFL_MASK   0xc000
  52#define TXx9_SPCR0_RXIFL_MASK   0x3000
  53#define TXx9_SPCR0_SIDIE        0x0800
  54#define TXx9_SPCR0_SOEIE        0x0400
  55#define TXx9_SPCR0_RBSIE        0x0200
  56#define TXx9_SPCR0_TBSIE        0x0100
  57#define TXx9_SPCR0_IFSPSE       0x0010
  58#define TXx9_SPCR0_SBOS         0x0004
  59#define TXx9_SPCR0_SPHA         0x0002
  60#define TXx9_SPCR0_SPOL         0x0001
  61
  62/* SPSR : SPI Status */
  63#define TXx9_SPSR_TBSI          0x8000
  64#define TXx9_SPSR_RBSI          0x4000
  65#define TXx9_SPSR_TBS_MASK      0x3800
  66#define TXx9_SPSR_RBS_MASK      0x0700
  67#define TXx9_SPSR_SPOE          0x0080
  68#define TXx9_SPSR_IFSD          0x0008
  69#define TXx9_SPSR_SIDLE         0x0004
  70#define TXx9_SPSR_STRDY         0x0002
  71#define TXx9_SPSR_SRRDY         0x0001
  72
  73
  74struct txx9spi {
  75        struct workqueue_struct *workqueue;
  76        struct work_struct work;
  77        spinlock_t lock;        /* protect 'queue' */
  78        struct list_head queue;
  79        wait_queue_head_t waitq;
  80        void __iomem *membase;
  81        int baseclk;
  82        struct clk *clk;
  83        u32 max_speed_hz, min_speed_hz;
  84        int last_chipselect;
  85        int last_chipselect_val;
  86};
  87
  88static u32 txx9spi_rd(struct txx9spi *c, int reg)
  89{
  90        return __raw_readl(c->membase + reg);
  91}
  92static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
  93{
  94        __raw_writel(val, c->membase + reg);
  95}
  96
  97static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
  98                int on, unsigned int cs_delay)
  99{
 100        int val = (spi->mode & SPI_CS_HIGH) ? on : !on;
 101        if (on) {
 102                /* deselect the chip with cs_change hint in last transfer */
 103                if (c->last_chipselect >= 0)
 104                        gpio_set_value(c->last_chipselect,
 105                                        !c->last_chipselect_val);
 106                c->last_chipselect = spi->chip_select;
 107                c->last_chipselect_val = val;
 108        } else {
 109                c->last_chipselect = -1;
 110                ndelay(cs_delay);       /* CS Hold Time */
 111        }
 112        gpio_set_value(spi->chip_select, val);
 113        ndelay(cs_delay);       /* CS Setup Time / CS Recovery Time */
 114}
 115
 116static int txx9spi_setup(struct spi_device *spi)
 117{
 118        struct txx9spi *c = spi_master_get_devdata(spi->master);
 119        u8 bits_per_word;
 120
 121        if (!spi->max_speed_hz
 122                        || spi->max_speed_hz > c->max_speed_hz
 123                        || spi->max_speed_hz < c->min_speed_hz)
 124                return -EINVAL;
 125
 126        bits_per_word = spi->bits_per_word;
 127        if (bits_per_word != 8 && bits_per_word != 16)
 128                return -EINVAL;
 129
 130        if (gpio_direction_output(spi->chip_select,
 131                        !(spi->mode & SPI_CS_HIGH))) {
 132                dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n");
 133                return -EINVAL;
 134        }
 135
 136        /* deselect chip */
 137        spin_lock(&c->lock);
 138        txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
 139        spin_unlock(&c->lock);
 140
 141        return 0;
 142}
 143
 144static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
 145{
 146        struct txx9spi *c = dev_id;
 147
 148        /* disable rx intr */
 149        txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
 150                        TXx9_SPCR0);
 151        wake_up(&c->waitq);
 152        return IRQ_HANDLED;
 153}
 154
 155static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
 156{
 157        struct spi_device *spi = m->spi;
 158        struct spi_transfer *t;
 159        unsigned int cs_delay;
 160        unsigned int cs_change = 1;
 161        int status = 0;
 162        u32 mcr;
 163        u32 prev_speed_hz = 0;
 164        u8 prev_bits_per_word = 0;
 165
 166        /* CS setup/hold/recovery time in nsec */
 167        cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
 168
 169        mcr = txx9spi_rd(c, TXx9_SPMCR);
 170        if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
 171                dev_err(&spi->dev, "Bad mode.\n");
 172                status = -EIO;
 173                goto exit;
 174        }
 175        mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
 176
 177        /* enter config mode */
 178        txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
 179        txx9spi_wr(c, TXx9_SPCR0_SBOS
 180                        | ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
 181                        | ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
 182                        | 0x08,
 183                        TXx9_SPCR0);
 184
 185        list_for_each_entry (t, &m->transfers, transfer_list) {
 186                const void *txbuf = t->tx_buf;
 187                void *rxbuf = t->rx_buf;
 188                u32 data;
 189                unsigned int len = t->len;
 190                unsigned int wsize;
 191                u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
 192                u8 bits_per_word = t->bits_per_word;
 193
 194                wsize = bits_per_word >> 3; /* in bytes */
 195
 196                if (prev_speed_hz != speed_hz
 197                                || prev_bits_per_word != bits_per_word) {
 198                        int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1;
 199                        n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER);
 200                        /* enter config mode */
 201                        txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
 202                                        TXx9_SPMCR);
 203                        txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1);
 204                        /* enter active mode */
 205                        txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
 206
 207                        prev_speed_hz = speed_hz;
 208                        prev_bits_per_word = bits_per_word;
 209                }
 210
 211                if (cs_change)
 212                        txx9spi_cs_func(spi, c, 1, cs_delay);
 213                cs_change = t->cs_change;
 214                while (len) {
 215                        unsigned int count = SPI_FIFO_SIZE;
 216                        int i;
 217                        u32 cr0;
 218
 219                        if (len < count * wsize)
 220                                count = len / wsize;
 221                        /* now tx must be idle... */
 222                        while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
 223                                cpu_relax();
 224                        cr0 = txx9spi_rd(c, TXx9_SPCR0);
 225                        cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
 226                        cr0 |= (count - 1) << 12;
 227                        /* enable rx intr */
 228                        cr0 |= TXx9_SPCR0_RBSIE;
 229                        txx9spi_wr(c, cr0, TXx9_SPCR0);
 230                        /* send */
 231                        for (i = 0; i < count; i++) {
 232                                if (txbuf) {
 233                                        data = (wsize == 1)
 234                                                ? *(const u8 *)txbuf
 235                                                : *(const u16 *)txbuf;
 236                                        txx9spi_wr(c, data, TXx9_SPDR);
 237                                        txbuf += wsize;
 238                                } else
 239                                        txx9spi_wr(c, 0, TXx9_SPDR);
 240                        }
 241                        /* wait all rx data */
 242                        wait_event(c->waitq,
 243                                txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
 244                        /* receive */
 245                        for (i = 0; i < count; i++) {
 246                                data = txx9spi_rd(c, TXx9_SPDR);
 247                                if (rxbuf) {
 248                                        if (wsize == 1)
 249                                                *(u8 *)rxbuf = data;
 250                                        else
 251                                                *(u16 *)rxbuf = data;
 252                                        rxbuf += wsize;
 253                                }
 254                        }
 255                        len -= count * wsize;
 256                }
 257                m->actual_length += t->len;
 258                if (t->delay_usecs)
 259                        udelay(t->delay_usecs);
 260
 261                if (!cs_change)
 262                        continue;
 263                if (t->transfer_list.next == &m->transfers)
 264                        break;
 265                /* sometimes a short mid-message deselect of the chip
 266                 * may be needed to terminate a mode or command
 267                 */
 268                txx9spi_cs_func(spi, c, 0, cs_delay);
 269        }
 270
 271exit:
 272        m->status = status;
 273        m->complete(m->context);
 274
 275        /* normally deactivate chipselect ... unless no error and
 276         * cs_change has hinted that the next message will probably
 277         * be for this chip too.
 278         */
 279        if (!(status == 0 && cs_change))
 280                txx9spi_cs_func(spi, c, 0, cs_delay);
 281
 282        /* enter config mode */
 283        txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
 284}
 285
 286static void txx9spi_work(struct work_struct *work)
 287{
 288        struct txx9spi *c = container_of(work, struct txx9spi, work);
 289        unsigned long flags;
 290
 291        spin_lock_irqsave(&c->lock, flags);
 292        while (!list_empty(&c->queue)) {
 293                struct spi_message *m;
 294
 295                m = container_of(c->queue.next, struct spi_message, queue);
 296                list_del_init(&m->queue);
 297                spin_unlock_irqrestore(&c->lock, flags);
 298
 299                txx9spi_work_one(c, m);
 300
 301                spin_lock_irqsave(&c->lock, flags);
 302        }
 303        spin_unlock_irqrestore(&c->lock, flags);
 304}
 305
 306static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
 307{
 308        struct spi_master *master = spi->master;
 309        struct txx9spi *c = spi_master_get_devdata(master);
 310        struct spi_transfer *t;
 311        unsigned long flags;
 312
 313        m->actual_length = 0;
 314
 315        /* check each transfer's parameters */
 316        list_for_each_entry (t, &m->transfers, transfer_list) {
 317                u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
 318                u8 bits_per_word = t->bits_per_word;
 319
 320                if (!t->tx_buf && !t->rx_buf && t->len)
 321                        return -EINVAL;
 322                if (bits_per_word != 8 && bits_per_word != 16)
 323                        return -EINVAL;
 324                if (t->len & ((bits_per_word >> 3) - 1))
 325                        return -EINVAL;
 326                if (speed_hz < c->min_speed_hz || speed_hz > c->max_speed_hz)
 327                        return -EINVAL;
 328        }
 329
 330        spin_lock_irqsave(&c->lock, flags);
 331        list_add_tail(&m->queue, &c->queue);
 332        queue_work(c->workqueue, &c->work);
 333        spin_unlock_irqrestore(&c->lock, flags);
 334
 335        return 0;
 336}
 337
 338static int txx9spi_probe(struct platform_device *dev)
 339{
 340        struct spi_master *master;
 341        struct txx9spi *c;
 342        struct resource *res;
 343        int ret = -ENODEV;
 344        u32 mcr;
 345        int irq;
 346
 347        master = spi_alloc_master(&dev->dev, sizeof(*c));
 348        if (!master)
 349                return ret;
 350        c = spi_master_get_devdata(master);
 351        platform_set_drvdata(dev, master);
 352
 353        INIT_WORK(&c->work, txx9spi_work);
 354        spin_lock_init(&c->lock);
 355        INIT_LIST_HEAD(&c->queue);
 356        init_waitqueue_head(&c->waitq);
 357
 358        c->clk = clk_get(&dev->dev, "spi-baseclk");
 359        if (IS_ERR(c->clk)) {
 360                ret = PTR_ERR(c->clk);
 361                c->clk = NULL;
 362                goto exit;
 363        }
 364        ret = clk_enable(c->clk);
 365        if (ret) {
 366                clk_put(c->clk);
 367                c->clk = NULL;
 368                goto exit;
 369        }
 370        c->baseclk = clk_get_rate(c->clk);
 371        c->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1);
 372        c->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1);
 373
 374        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 375        if (!res)
 376                goto exit_busy;
 377        if (!devm_request_mem_region(&dev->dev, res->start, resource_size(res),
 378                                     "spi_txx9"))
 379                goto exit_busy;
 380        c->membase = devm_ioremap(&dev->dev, res->start, resource_size(res));
 381        if (!c->membase)
 382                goto exit_busy;
 383
 384        /* enter config mode */
 385        mcr = txx9spi_rd(c, TXx9_SPMCR);
 386        mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
 387        txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
 388
 389        irq = platform_get_irq(dev, 0);
 390        if (irq < 0)
 391                goto exit_busy;
 392        ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0,
 393                               "spi_txx9", c);
 394        if (ret)
 395                goto exit;
 396
 397        c->workqueue = create_singlethread_workqueue(
 398                                dev_name(master->dev.parent));
 399        if (!c->workqueue)
 400                goto exit_busy;
 401        c->last_chipselect = -1;
 402
 403        dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
 404                 (unsigned long long)res->start, irq,
 405                 (c->baseclk + 500000) / 1000000);
 406
 407        /* the spi->mode bits understood by this driver: */
 408        master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
 409
 410        master->bus_num = dev->id;
 411        master->setup = txx9spi_setup;
 412        master->transfer = txx9spi_transfer;
 413        master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
 414
 415        ret = spi_register_master(master);
 416        if (ret)
 417                goto exit;
 418        return 0;
 419exit_busy:
 420        ret = -EBUSY;
 421exit:
 422        if (c->workqueue)
 423                destroy_workqueue(c->workqueue);
 424        if (c->clk) {
 425                clk_disable(c->clk);
 426                clk_put(c->clk);
 427        }
 428        platform_set_drvdata(dev, NULL);
 429        spi_master_put(master);
 430        return ret;
 431}
 432
 433static int txx9spi_remove(struct platform_device *dev)
 434{
 435        struct spi_master *master = spi_master_get(platform_get_drvdata(dev));
 436        struct txx9spi *c = spi_master_get_devdata(master);
 437
 438        spi_unregister_master(master);
 439        platform_set_drvdata(dev, NULL);
 440        destroy_workqueue(c->workqueue);
 441        clk_disable(c->clk);
 442        clk_put(c->clk);
 443        spi_master_put(master);
 444        return 0;
 445}
 446
 447/* work with hotplug and coldplug */
 448MODULE_ALIAS("platform:spi_txx9");
 449
 450static struct platform_driver txx9spi_driver = {
 451        .remove = txx9spi_remove,
 452        .driver = {
 453                .name = "spi_txx9",
 454                .owner = THIS_MODULE,
 455        },
 456};
 457
 458static int __init txx9spi_init(void)
 459{
 460        return platform_driver_probe(&txx9spi_driver, txx9spi_probe);
 461}
 462subsys_initcall(txx9spi_init);
 463
 464static void __exit txx9spi_exit(void)
 465{
 466        platform_driver_unregister(&txx9spi_driver);
 467}
 468module_exit(txx9spi_exit);
 469
 470MODULE_DESCRIPTION("TXx9 SPI Driver");
 471MODULE_LICENSE("GPL");
 472
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