linux/drivers/spi/spi-pxa2xx.c
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   1/*
   2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   3 * Copyright (C) 2013, Intel Corporation
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20#include <linux/init.h>
  21#include <linux/module.h>
  22#include <linux/device.h>
  23#include <linux/ioport.h>
  24#include <linux/errno.h>
  25#include <linux/interrupt.h>
  26#include <linux/platform_device.h>
  27#include <linux/spi/pxa2xx_spi.h>
  28#include <linux/spi/spi.h>
  29#include <linux/workqueue.h>
  30#include <linux/delay.h>
  31#include <linux/gpio.h>
  32#include <linux/slab.h>
  33#include <linux/clk.h>
  34#include <linux/pm_runtime.h>
  35#include <linux/acpi.h>
  36
  37#include <asm/io.h>
  38#include <asm/irq.h>
  39#include <asm/delay.h>
  40
  41#include "spi-pxa2xx.h"
  42
  43MODULE_AUTHOR("Stephen Street");
  44MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  45MODULE_LICENSE("GPL");
  46MODULE_ALIAS("platform:pxa2xx-spi");
  47
  48#define MAX_BUSES 3
  49
  50#define TIMOUT_DFLT             1000
  51
  52/*
  53 * for testing SSCR1 changes that require SSP restart, basically
  54 * everything except the service and interrupt enables, the pxa270 developer
  55 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  56 * list, but the PXA255 dev man says all bits without really meaning the
  57 * service and interrupt enables
  58 */
  59#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  60                                | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  61                                | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  62                                | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  63                                | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  64                                | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  65
  66#define LPSS_RX_THRESH_DFLT     64
  67#define LPSS_TX_LOTHRESH_DFLT   160
  68#define LPSS_TX_HITHRESH_DFLT   224
  69
  70/* Offset from drv_data->lpss_base */
  71#define SPI_CS_CONTROL          0x18
  72#define SPI_CS_CONTROL_SW_MODE  BIT(0)
  73#define SPI_CS_CONTROL_CS_HIGH  BIT(1)
  74
  75static bool is_lpss_ssp(const struct driver_data *drv_data)
  76{
  77        return drv_data->ssp_type == LPSS_SSP;
  78}
  79
  80/*
  81 * Read and write LPSS SSP private registers. Caller must first check that
  82 * is_lpss_ssp() returns true before these can be called.
  83 */
  84static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
  85{
  86        WARN_ON(!drv_data->lpss_base);
  87        return readl(drv_data->lpss_base + offset);
  88}
  89
  90static void __lpss_ssp_write_priv(struct driver_data *drv_data,
  91                                  unsigned offset, u32 value)
  92{
  93        WARN_ON(!drv_data->lpss_base);
  94        writel(value, drv_data->lpss_base + offset);
  95}
  96
  97/*
  98 * lpss_ssp_setup - perform LPSS SSP specific setup
  99 * @drv_data: pointer to the driver private data
 100 *
 101 * Perform LPSS SSP specific setup. This function must be called first if
 102 * one is going to use LPSS SSP private registers.
 103 */
 104static void lpss_ssp_setup(struct driver_data *drv_data)
 105{
 106        unsigned offset = 0x400;
 107        u32 value, orig;
 108
 109        if (!is_lpss_ssp(drv_data))
 110                return;
 111
 112        /*
 113         * Perform auto-detection of the LPSS SSP private registers. They
 114         * can be either at 1k or 2k offset from the base address.
 115         */
 116        orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
 117
 118        value = orig | SPI_CS_CONTROL_SW_MODE;
 119        writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
 120        value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
 121        if (value != (orig | SPI_CS_CONTROL_SW_MODE)) {
 122                offset = 0x800;
 123                goto detection_done;
 124        }
 125
 126        value &= ~SPI_CS_CONTROL_SW_MODE;
 127        writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
 128        value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
 129        if (value != orig) {
 130                offset = 0x800;
 131                goto detection_done;
 132        }
 133
 134detection_done:
 135        /* Now set the LPSS base */
 136        drv_data->lpss_base = drv_data->ioaddr + offset;
 137
 138        /* Enable software chip select control */
 139        value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
 140        __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
 141}
 142
 143static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
 144{
 145        u32 value;
 146
 147        if (!is_lpss_ssp(drv_data))
 148                return;
 149
 150        value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
 151        if (enable)
 152                value &= ~SPI_CS_CONTROL_CS_HIGH;
 153        else
 154                value |= SPI_CS_CONTROL_CS_HIGH;
 155        __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
 156}
 157
 158static void cs_assert(struct driver_data *drv_data)
 159{
 160        struct chip_data *chip = drv_data->cur_chip;
 161
 162        if (drv_data->ssp_type == CE4100_SSP) {
 163                write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
 164                return;
 165        }
 166
 167        if (chip->cs_control) {
 168                chip->cs_control(PXA2XX_CS_ASSERT);
 169                return;
 170        }
 171
 172        if (gpio_is_valid(chip->gpio_cs)) {
 173                gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
 174                return;
 175        }
 176
 177        lpss_ssp_cs_control(drv_data, true);
 178}
 179
 180static void cs_deassert(struct driver_data *drv_data)
 181{
 182        struct chip_data *chip = drv_data->cur_chip;
 183
 184        if (drv_data->ssp_type == CE4100_SSP)
 185                return;
 186
 187        if (chip->cs_control) {
 188                chip->cs_control(PXA2XX_CS_DEASSERT);
 189                return;
 190        }
 191
 192        if (gpio_is_valid(chip->gpio_cs)) {
 193                gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
 194                return;
 195        }
 196
 197        lpss_ssp_cs_control(drv_data, false);
 198}
 199
 200int pxa2xx_spi_flush(struct driver_data *drv_data)
 201{
 202        unsigned long limit = loops_per_jiffy << 1;
 203
 204        void __iomem *reg = drv_data->ioaddr;
 205
 206        do {
 207                while (read_SSSR(reg) & SSSR_RNE) {
 208                        read_SSDR(reg);
 209                }
 210        } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
 211        write_SSSR_CS(drv_data, SSSR_ROR);
 212
 213        return limit;
 214}
 215
 216static int null_writer(struct driver_data *drv_data)
 217{
 218        void __iomem *reg = drv_data->ioaddr;
 219        u8 n_bytes = drv_data->n_bytes;
 220
 221        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 222                || (drv_data->tx == drv_data->tx_end))
 223                return 0;
 224
 225        write_SSDR(0, reg);
 226        drv_data->tx += n_bytes;
 227
 228        return 1;
 229}
 230
 231static int null_reader(struct driver_data *drv_data)
 232{
 233        void __iomem *reg = drv_data->ioaddr;
 234        u8 n_bytes = drv_data->n_bytes;
 235
 236        while ((read_SSSR(reg) & SSSR_RNE)
 237                && (drv_data->rx < drv_data->rx_end)) {
 238                read_SSDR(reg);
 239                drv_data->rx += n_bytes;
 240        }
 241
 242        return drv_data->rx == drv_data->rx_end;
 243}
 244
 245static int u8_writer(struct driver_data *drv_data)
 246{
 247        void __iomem *reg = drv_data->ioaddr;
 248
 249        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 250                || (drv_data->tx == drv_data->tx_end))
 251                return 0;
 252
 253        write_SSDR(*(u8 *)(drv_data->tx), reg);
 254        ++drv_data->tx;
 255
 256        return 1;
 257}
 258
 259static int u8_reader(struct driver_data *drv_data)
 260{
 261        void __iomem *reg = drv_data->ioaddr;
 262
 263        while ((read_SSSR(reg) & SSSR_RNE)
 264                && (drv_data->rx < drv_data->rx_end)) {
 265                *(u8 *)(drv_data->rx) = read_SSDR(reg);
 266                ++drv_data->rx;
 267        }
 268
 269        return drv_data->rx == drv_data->rx_end;
 270}
 271
 272static int u16_writer(struct driver_data *drv_data)
 273{
 274        void __iomem *reg = drv_data->ioaddr;
 275
 276        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 277                || (drv_data->tx == drv_data->tx_end))
 278                return 0;
 279
 280        write_SSDR(*(u16 *)(drv_data->tx), reg);
 281        drv_data->tx += 2;
 282
 283        return 1;
 284}
 285
 286static int u16_reader(struct driver_data *drv_data)
 287{
 288        void __iomem *reg = drv_data->ioaddr;
 289
 290        while ((read_SSSR(reg) & SSSR_RNE)
 291                && (drv_data->rx < drv_data->rx_end)) {
 292                *(u16 *)(drv_data->rx) = read_SSDR(reg);
 293                drv_data->rx += 2;
 294        }
 295
 296        return drv_data->rx == drv_data->rx_end;
 297}
 298
 299static int u32_writer(struct driver_data *drv_data)
 300{
 301        void __iomem *reg = drv_data->ioaddr;
 302
 303        if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
 304                || (drv_data->tx == drv_data->tx_end))
 305                return 0;
 306
 307        write_SSDR(*(u32 *)(drv_data->tx), reg);
 308        drv_data->tx += 4;
 309
 310        return 1;
 311}
 312
 313static int u32_reader(struct driver_data *drv_data)
 314{
 315        void __iomem *reg = drv_data->ioaddr;
 316
 317        while ((read_SSSR(reg) & SSSR_RNE)
 318                && (drv_data->rx < drv_data->rx_end)) {
 319                *(u32 *)(drv_data->rx) = read_SSDR(reg);
 320                drv_data->rx += 4;
 321        }
 322
 323        return drv_data->rx == drv_data->rx_end;
 324}
 325
 326void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
 327{
 328        struct spi_message *msg = drv_data->cur_msg;
 329        struct spi_transfer *trans = drv_data->cur_transfer;
 330
 331        /* Move to next transfer */
 332        if (trans->transfer_list.next != &msg->transfers) {
 333                drv_data->cur_transfer =
 334                        list_entry(trans->transfer_list.next,
 335                                        struct spi_transfer,
 336                                        transfer_list);
 337                return RUNNING_STATE;
 338        } else
 339                return DONE_STATE;
 340}
 341
 342/* caller already set message->status; dma and pio irqs are blocked */
 343static void giveback(struct driver_data *drv_data)
 344{
 345        struct spi_transfer* last_transfer;
 346        struct spi_message *msg;
 347
 348        msg = drv_data->cur_msg;
 349        drv_data->cur_msg = NULL;
 350        drv_data->cur_transfer = NULL;
 351
 352        last_transfer = list_entry(msg->transfers.prev,
 353                                        struct spi_transfer,
 354                                        transfer_list);
 355
 356        /* Delay if requested before any change in chip select */
 357        if (last_transfer->delay_usecs)
 358                udelay(last_transfer->delay_usecs);
 359
 360        /* Drop chip select UNLESS cs_change is true or we are returning
 361         * a message with an error, or next message is for another chip
 362         */
 363        if (!last_transfer->cs_change)
 364                cs_deassert(drv_data);
 365        else {
 366                struct spi_message *next_msg;
 367
 368                /* Holding of cs was hinted, but we need to make sure
 369                 * the next message is for the same chip.  Don't waste
 370                 * time with the following tests unless this was hinted.
 371                 *
 372                 * We cannot postpone this until pump_messages, because
 373                 * after calling msg->complete (below) the driver that
 374                 * sent the current message could be unloaded, which
 375                 * could invalidate the cs_control() callback...
 376                 */
 377
 378                /* get a pointer to the next message, if any */
 379                next_msg = spi_get_next_queued_message(drv_data->master);
 380
 381                /* see if the next and current messages point
 382                 * to the same chip
 383                 */
 384                if (next_msg && next_msg->spi != msg->spi)
 385                        next_msg = NULL;
 386                if (!next_msg || msg->state == ERROR_STATE)
 387                        cs_deassert(drv_data);
 388        }
 389
 390        spi_finalize_current_message(drv_data->master);
 391        drv_data->cur_chip = NULL;
 392}
 393
 394static void reset_sccr1(struct driver_data *drv_data)
 395{
 396        void __iomem *reg = drv_data->ioaddr;
 397        struct chip_data *chip = drv_data->cur_chip;
 398        u32 sccr1_reg;
 399
 400        sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
 401        sccr1_reg &= ~SSCR1_RFT;
 402        sccr1_reg |= chip->threshold;
 403        write_SSCR1(sccr1_reg, reg);
 404}
 405
 406static void int_error_stop(struct driver_data *drv_data, const char* msg)
 407{
 408        void __iomem *reg = drv_data->ioaddr;
 409
 410        /* Stop and reset SSP */
 411        write_SSSR_CS(drv_data, drv_data->clear_sr);
 412        reset_sccr1(drv_data);
 413        if (!pxa25x_ssp_comp(drv_data))
 414                write_SSTO(0, reg);
 415        pxa2xx_spi_flush(drv_data);
 416        write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 417
 418        dev_err(&drv_data->pdev->dev, "%s\n", msg);
 419
 420        drv_data->cur_msg->state = ERROR_STATE;
 421        tasklet_schedule(&drv_data->pump_transfers);
 422}
 423
 424static void int_transfer_complete(struct driver_data *drv_data)
 425{
 426        void __iomem *reg = drv_data->ioaddr;
 427
 428        /* Stop SSP */
 429        write_SSSR_CS(drv_data, drv_data->clear_sr);
 430        reset_sccr1(drv_data);
 431        if (!pxa25x_ssp_comp(drv_data))
 432                write_SSTO(0, reg);
 433
 434        /* Update total byte transferred return count actual bytes read */
 435        drv_data->cur_msg->actual_length += drv_data->len -
 436                                (drv_data->rx_end - drv_data->rx);
 437
 438        /* Transfer delays and chip select release are
 439         * handled in pump_transfers or giveback
 440         */
 441
 442        /* Move to next transfer */
 443        drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
 444
 445        /* Schedule transfer tasklet */
 446        tasklet_schedule(&drv_data->pump_transfers);
 447}
 448
 449static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 450{
 451        void __iomem *reg = drv_data->ioaddr;
 452
 453        u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
 454                        drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 455
 456        u32 irq_status = read_SSSR(reg) & irq_mask;
 457
 458        if (irq_status & SSSR_ROR) {
 459                int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 460                return IRQ_HANDLED;
 461        }
 462
 463        if (irq_status & SSSR_TINT) {
 464                write_SSSR(SSSR_TINT, reg);
 465                if (drv_data->read(drv_data)) {
 466                        int_transfer_complete(drv_data);
 467                        return IRQ_HANDLED;
 468                }
 469        }
 470
 471        /* Drain rx fifo, Fill tx fifo and prevent overruns */
 472        do {
 473                if (drv_data->read(drv_data)) {
 474                        int_transfer_complete(drv_data);
 475                        return IRQ_HANDLED;
 476                }
 477        } while (drv_data->write(drv_data));
 478
 479        if (drv_data->read(drv_data)) {
 480                int_transfer_complete(drv_data);
 481                return IRQ_HANDLED;
 482        }
 483
 484        if (drv_data->tx == drv_data->tx_end) {
 485                u32 bytes_left;
 486                u32 sccr1_reg;
 487
 488                sccr1_reg = read_SSCR1(reg);
 489                sccr1_reg &= ~SSCR1_TIE;
 490
 491                /*
 492                 * PXA25x_SSP has no timeout, set up rx threshould for the
 493                 * remaining RX bytes.
 494                 */
 495                if (pxa25x_ssp_comp(drv_data)) {
 496
 497                        sccr1_reg &= ~SSCR1_RFT;
 498
 499                        bytes_left = drv_data->rx_end - drv_data->rx;
 500                        switch (drv_data->n_bytes) {
 501                        case 4:
 502                                bytes_left >>= 1;
 503                        case 2:
 504                                bytes_left >>= 1;
 505                        }
 506
 507                        if (bytes_left > RX_THRESH_DFLT)
 508                                bytes_left = RX_THRESH_DFLT;
 509
 510                        sccr1_reg |= SSCR1_RxTresh(bytes_left);
 511                }
 512                write_SSCR1(sccr1_reg, reg);
 513        }
 514
 515        /* We did something */
 516        return IRQ_HANDLED;
 517}
 518
 519static irqreturn_t ssp_int(int irq, void *dev_id)
 520{
 521        struct driver_data *drv_data = dev_id;
 522        void __iomem *reg = drv_data->ioaddr;
 523        u32 sccr1_reg;
 524        u32 mask = drv_data->mask_sr;
 525        u32 status;
 526
 527        /*
 528         * The IRQ might be shared with other peripherals so we must first
 529         * check that are we RPM suspended or not. If we are we assume that
 530         * the IRQ was not for us (we shouldn't be RPM suspended when the
 531         * interrupt is enabled).
 532         */
 533        if (pm_runtime_suspended(&drv_data->pdev->dev))
 534                return IRQ_NONE;
 535
 536        sccr1_reg = read_SSCR1(reg);
 537        status = read_SSSR(reg);
 538
 539        /* Ignore possible writes if we don't need to write */
 540        if (!(sccr1_reg & SSCR1_TIE))
 541                mask &= ~SSSR_TFS;
 542
 543        if (!(status & mask))
 544                return IRQ_NONE;
 545
 546        if (!drv_data->cur_msg) {
 547
 548                write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 549                write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 550                if (!pxa25x_ssp_comp(drv_data))
 551                        write_SSTO(0, reg);
 552                write_SSSR_CS(drv_data, drv_data->clear_sr);
 553
 554                dev_err(&drv_data->pdev->dev, "bad message state "
 555                        "in interrupt handler\n");
 556
 557                /* Never fail */
 558                return IRQ_HANDLED;
 559        }
 560
 561        return drv_data->transfer_handler(drv_data);
 562}
 563
 564static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
 565{
 566        unsigned long ssp_clk = drv_data->max_clk_rate;
 567        const struct ssp_device *ssp = drv_data->ssp;
 568
 569        rate = min_t(int, ssp_clk, rate);
 570
 571        if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
 572                return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
 573        else
 574                return ((ssp_clk / rate - 1) & 0xfff) << 8;
 575}
 576
 577static void pump_transfers(unsigned long data)
 578{
 579        struct driver_data *drv_data = (struct driver_data *)data;
 580        struct spi_message *message = NULL;
 581        struct spi_transfer *transfer = NULL;
 582        struct spi_transfer *previous = NULL;
 583        struct chip_data *chip = NULL;
 584        void __iomem *reg = drv_data->ioaddr;
 585        u32 clk_div = 0;
 586        u8 bits = 0;
 587        u32 speed = 0;
 588        u32 cr0;
 589        u32 cr1;
 590        u32 dma_thresh = drv_data->cur_chip->dma_threshold;
 591        u32 dma_burst = drv_data->cur_chip->dma_burst_size;
 592
 593        /* Get current state information */
 594        message = drv_data->cur_msg;
 595        transfer = drv_data->cur_transfer;
 596        chip = drv_data->cur_chip;
 597
 598        /* Handle for abort */
 599        if (message->state == ERROR_STATE) {
 600                message->status = -EIO;
 601                giveback(drv_data);
 602                return;
 603        }
 604
 605        /* Handle end of message */
 606        if (message->state == DONE_STATE) {
 607                message->status = 0;
 608                giveback(drv_data);
 609                return;
 610        }
 611
 612        /* Delay if requested at end of transfer before CS change */
 613        if (message->state == RUNNING_STATE) {
 614                previous = list_entry(transfer->transfer_list.prev,
 615                                        struct spi_transfer,
 616                                        transfer_list);
 617                if (previous->delay_usecs)
 618                        udelay(previous->delay_usecs);
 619
 620                /* Drop chip select only if cs_change is requested */
 621                if (previous->cs_change)
 622                        cs_deassert(drv_data);
 623        }
 624
 625        /* Check if we can DMA this transfer */
 626        if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
 627
 628                /* reject already-mapped transfers; PIO won't always work */
 629                if (message->is_dma_mapped
 630                                || transfer->rx_dma || transfer->tx_dma) {
 631                        dev_err(&drv_data->pdev->dev,
 632                                "pump_transfers: mapped transfer length "
 633                                "of %u is greater than %d\n",
 634                                transfer->len, MAX_DMA_LEN);
 635                        message->status = -EINVAL;
 636                        giveback(drv_data);
 637                        return;
 638                }
 639
 640                /* warn ... we force this to PIO mode */
 641                if (printk_ratelimit())
 642                        dev_warn(&message->spi->dev, "pump_transfers: "
 643                                "DMA disabled for transfer length %ld "
 644                                "greater than %d\n",
 645                                (long)drv_data->len, MAX_DMA_LEN);
 646        }
 647
 648        /* Setup the transfer state based on the type of transfer */
 649        if (pxa2xx_spi_flush(drv_data) == 0) {
 650                dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 651                message->status = -EIO;
 652                giveback(drv_data);
 653                return;
 654        }
 655        drv_data->n_bytes = chip->n_bytes;
 656        drv_data->tx = (void *)transfer->tx_buf;
 657        drv_data->tx_end = drv_data->tx + transfer->len;
 658        drv_data->rx = transfer->rx_buf;
 659        drv_data->rx_end = drv_data->rx + transfer->len;
 660        drv_data->rx_dma = transfer->rx_dma;
 661        drv_data->tx_dma = transfer->tx_dma;
 662        drv_data->len = transfer->len;
 663        drv_data->write = drv_data->tx ? chip->write : null_writer;
 664        drv_data->read = drv_data->rx ? chip->read : null_reader;
 665
 666        /* Change speed and bit per word on a per transfer */
 667        cr0 = chip->cr0;
 668        if (transfer->speed_hz || transfer->bits_per_word) {
 669
 670                bits = chip->bits_per_word;
 671                speed = chip->speed_hz;
 672
 673                if (transfer->speed_hz)
 674                        speed = transfer->speed_hz;
 675
 676                if (transfer->bits_per_word)
 677                        bits = transfer->bits_per_word;
 678
 679                clk_div = ssp_get_clk_div(drv_data, speed);
 680
 681                if (bits <= 8) {
 682                        drv_data->n_bytes = 1;
 683                        drv_data->read = drv_data->read != null_reader ?
 684                                                u8_reader : null_reader;
 685                        drv_data->write = drv_data->write != null_writer ?
 686                                                u8_writer : null_writer;
 687                } else if (bits <= 16) {
 688                        drv_data->n_bytes = 2;
 689                        drv_data->read = drv_data->read != null_reader ?
 690                                                u16_reader : null_reader;
 691                        drv_data->write = drv_data->write != null_writer ?
 692                                                u16_writer : null_writer;
 693                } else if (bits <= 32) {
 694                        drv_data->n_bytes = 4;
 695                        drv_data->read = drv_data->read != null_reader ?
 696                                                u32_reader : null_reader;
 697                        drv_data->write = drv_data->write != null_writer ?
 698                                                u32_writer : null_writer;
 699                }
 700                /* if bits/word is changed in dma mode, then must check the
 701                 * thresholds and burst also */
 702                if (chip->enable_dma) {
 703                        if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
 704                                                        message->spi,
 705                                                        bits, &dma_burst,
 706                                                        &dma_thresh))
 707                                if (printk_ratelimit())
 708                                        dev_warn(&message->spi->dev,
 709                                                "pump_transfers: "
 710                                                "DMA burst size reduced to "
 711                                                "match bits_per_word\n");
 712                }
 713
 714                cr0 = clk_div
 715                        | SSCR0_Motorola
 716                        | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 717                        | SSCR0_SSE
 718                        | (bits > 16 ? SSCR0_EDSS : 0);
 719        }
 720
 721        message->state = RUNNING_STATE;
 722
 723        drv_data->dma_mapped = 0;
 724        if (pxa2xx_spi_dma_is_possible(drv_data->len))
 725                drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
 726        if (drv_data->dma_mapped) {
 727
 728                /* Ensure we have the correct interrupt handler */
 729                drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
 730
 731                pxa2xx_spi_dma_prepare(drv_data, dma_burst);
 732
 733                /* Clear status and start DMA engine */
 734                cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
 735                write_SSSR(drv_data->clear_sr, reg);
 736
 737                pxa2xx_spi_dma_start(drv_data);
 738        } else {
 739                /* Ensure we have the correct interrupt handler */
 740                drv_data->transfer_handler = interrupt_transfer;
 741
 742                /* Clear status  */
 743                cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
 744                write_SSSR_CS(drv_data, drv_data->clear_sr);
 745        }
 746
 747        if (is_lpss_ssp(drv_data)) {
 748                if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
 749                        write_SSIRF(chip->lpss_rx_threshold, reg);
 750                if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
 751                        write_SSITF(chip->lpss_tx_threshold, reg);
 752        }
 753
 754        /* see if we need to reload the config registers */
 755        if ((read_SSCR0(reg) != cr0)
 756                || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
 757                        (cr1 & SSCR1_CHANGE_MASK)) {
 758
 759                /* stop the SSP, and update the other bits */
 760                write_SSCR0(cr0 & ~SSCR0_SSE, reg);
 761                if (!pxa25x_ssp_comp(drv_data))
 762                        write_SSTO(chip->timeout, reg);
 763                /* first set CR1 without interrupt and service enables */
 764                write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
 765                /* restart the SSP */
 766                write_SSCR0(cr0, reg);
 767
 768        } else {
 769                if (!pxa25x_ssp_comp(drv_data))
 770                        write_SSTO(chip->timeout, reg);
 771        }
 772
 773        cs_assert(drv_data);
 774
 775        /* after chip select, release the data by enabling service
 776         * requests and interrupts, without changing any mode bits */
 777        write_SSCR1(cr1, reg);
 778}
 779
 780static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
 781                                           struct spi_message *msg)
 782{
 783        struct driver_data *drv_data = spi_master_get_devdata(master);
 784
 785        drv_data->cur_msg = msg;
 786        /* Initial message state*/
 787        drv_data->cur_msg->state = START_STATE;
 788        drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 789                                                struct spi_transfer,
 790                                                transfer_list);
 791
 792        /* prepare to setup the SSP, in pump_transfers, using the per
 793         * chip configuration */
 794        drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 795
 796        /* Mark as busy and launch transfers */
 797        tasklet_schedule(&drv_data->pump_transfers);
 798        return 0;
 799}
 800
 801static int pxa2xx_spi_prepare_transfer(struct spi_master *master)
 802{
 803        struct driver_data *drv_data = spi_master_get_devdata(master);
 804
 805        pm_runtime_get_sync(&drv_data->pdev->dev);
 806        return 0;
 807}
 808
 809static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
 810{
 811        struct driver_data *drv_data = spi_master_get_devdata(master);
 812
 813        /* Disable the SSP now */
 814        write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
 815                    drv_data->ioaddr);
 816
 817        pm_runtime_mark_last_busy(&drv_data->pdev->dev);
 818        pm_runtime_put_autosuspend(&drv_data->pdev->dev);
 819        return 0;
 820}
 821
 822static int setup_cs(struct spi_device *spi, struct chip_data *chip,
 823                    struct pxa2xx_spi_chip *chip_info)
 824{
 825        int err = 0;
 826
 827        if (chip == NULL || chip_info == NULL)
 828                return 0;
 829
 830        /* NOTE: setup() can be called multiple times, possibly with
 831         * different chip_info, release previously requested GPIO
 832         */
 833        if (gpio_is_valid(chip->gpio_cs))
 834                gpio_free(chip->gpio_cs);
 835
 836        /* If (*cs_control) is provided, ignore GPIO chip select */
 837        if (chip_info->cs_control) {
 838                chip->cs_control = chip_info->cs_control;
 839                return 0;
 840        }
 841
 842        if (gpio_is_valid(chip_info->gpio_cs)) {
 843                err = gpio_request(chip_info->gpio_cs, "SPI_CS");
 844                if (err) {
 845                        dev_err(&spi->dev, "failed to request chip select "
 846                                        "GPIO%d\n", chip_info->gpio_cs);
 847                        return err;
 848                }
 849
 850                chip->gpio_cs = chip_info->gpio_cs;
 851                chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
 852
 853                err = gpio_direction_output(chip->gpio_cs,
 854                                        !chip->gpio_cs_inverted);
 855        }
 856
 857        return err;
 858}
 859
 860static int setup(struct spi_device *spi)
 861{
 862        struct pxa2xx_spi_chip *chip_info = NULL;
 863        struct chip_data *chip;
 864        struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 865        unsigned int clk_div;
 866        uint tx_thres, tx_hi_thres, rx_thres;
 867
 868        if (is_lpss_ssp(drv_data)) {
 869                tx_thres = LPSS_TX_LOTHRESH_DFLT;
 870                tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
 871                rx_thres = LPSS_RX_THRESH_DFLT;
 872        } else {
 873                tx_thres = TX_THRESH_DFLT;
 874                tx_hi_thres = 0;
 875                rx_thres = RX_THRESH_DFLT;
 876        }
 877
 878        if (!pxa25x_ssp_comp(drv_data)
 879                && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
 880                dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
 881                                "b/w not 4-32 for type non-PXA25x_SSP\n",
 882                                drv_data->ssp_type, spi->bits_per_word);
 883                return -EINVAL;
 884        } else if (pxa25x_ssp_comp(drv_data)
 885                        && (spi->bits_per_word < 4
 886                                || spi->bits_per_word > 16)) {
 887                dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
 888                                "b/w not 4-16 for type PXA25x_SSP\n",
 889                                drv_data->ssp_type, spi->bits_per_word);
 890                return -EINVAL;
 891        }
 892
 893        /* Only alloc on first setup */
 894        chip = spi_get_ctldata(spi);
 895        if (!chip) {
 896                chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 897                if (!chip) {
 898                        dev_err(&spi->dev,
 899                                "failed setup: can't allocate chip data\n");
 900                        return -ENOMEM;
 901                }
 902
 903                if (drv_data->ssp_type == CE4100_SSP) {
 904                        if (spi->chip_select > 4) {
 905                                dev_err(&spi->dev, "failed setup: "
 906                                "cs number must not be > 4.\n");
 907                                kfree(chip);
 908                                return -EINVAL;
 909                        }
 910
 911                        chip->frm = spi->chip_select;
 912                } else
 913                        chip->gpio_cs = -1;
 914                chip->enable_dma = 0;
 915                chip->timeout = TIMOUT_DFLT;
 916        }
 917
 918        /* protocol drivers may change the chip settings, so...
 919         * if chip_info exists, use it */
 920        chip_info = spi->controller_data;
 921
 922        /* chip_info isn't always needed */
 923        chip->cr1 = 0;
 924        if (chip_info) {
 925                if (chip_info->timeout)
 926                        chip->timeout = chip_info->timeout;
 927                if (chip_info->tx_threshold)
 928                        tx_thres = chip_info->tx_threshold;
 929                if (chip_info->tx_hi_threshold)
 930                        tx_hi_thres = chip_info->tx_hi_threshold;
 931                if (chip_info->rx_threshold)
 932                        rx_thres = chip_info->rx_threshold;
 933                chip->enable_dma = drv_data->master_info->enable_dma;
 934                chip->dma_threshold = 0;
 935                if (chip_info->enable_loopback)
 936                        chip->cr1 = SSCR1_LBM;
 937        } else if (ACPI_HANDLE(&spi->dev)) {
 938                /*
 939                 * Slave devices enumerated from ACPI namespace don't
 940                 * usually have chip_info but we still might want to use
 941                 * DMA with them.
 942                 */
 943                chip->enable_dma = drv_data->master_info->enable_dma;
 944        }
 945
 946        chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
 947                        (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
 948
 949        chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
 950        chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
 951                                | SSITF_TxHiThresh(tx_hi_thres);
 952
 953        /* set dma burst and threshold outside of chip_info path so that if
 954         * chip_info goes away after setting chip->enable_dma, the
 955         * burst and threshold can still respond to changes in bits_per_word */
 956        if (chip->enable_dma) {
 957                /* set up legal burst and threshold for dma */
 958                if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
 959                                                spi->bits_per_word,
 960                                                &chip->dma_burst_size,
 961                                                &chip->dma_threshold)) {
 962                        dev_warn(&spi->dev, "in setup: DMA burst size reduced "
 963                                        "to match bits_per_word\n");
 964                }
 965        }
 966
 967        clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
 968        chip->speed_hz = spi->max_speed_hz;
 969
 970        chip->cr0 = clk_div
 971                        | SSCR0_Motorola
 972                        | SSCR0_DataSize(spi->bits_per_word > 16 ?
 973                                spi->bits_per_word - 16 : spi->bits_per_word)
 974                        | SSCR0_SSE
 975                        | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
 976        chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
 977        chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
 978                        | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
 979
 980        if (spi->mode & SPI_LOOP)
 981                chip->cr1 |= SSCR1_LBM;
 982
 983        /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
 984        if (!pxa25x_ssp_comp(drv_data))
 985                dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
 986                        drv_data->max_clk_rate
 987                                / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
 988                        chip->enable_dma ? "DMA" : "PIO");
 989        else
 990                dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
 991                        drv_data->max_clk_rate / 2
 992                                / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
 993                        chip->enable_dma ? "DMA" : "PIO");
 994
 995        if (spi->bits_per_word <= 8) {
 996                chip->n_bytes = 1;
 997                chip->read = u8_reader;
 998                chip->write = u8_writer;
 999        } else if (spi->bits_per_word <= 16) {
1000                chip->n_bytes = 2;
1001                chip->read = u16_reader;
1002                chip->write = u16_writer;
1003        } else if (spi->bits_per_word <= 32) {
1004                chip->cr0 |= SSCR0_EDSS;
1005                chip->n_bytes = 4;
1006                chip->read = u32_reader;
1007                chip->write = u32_writer;
1008        } else {
1009                dev_err(&spi->dev, "invalid wordsize\n");
1010                return -ENODEV;
1011        }
1012        chip->bits_per_word = spi->bits_per_word;
1013
1014        spi_set_ctldata(spi, chip);
1015
1016        if (drv_data->ssp_type == CE4100_SSP)
1017                return 0;
1018
1019        return setup_cs(spi, chip, chip_info);
1020}
1021
1022static void cleanup(struct spi_device *spi)
1023{
1024        struct chip_data *chip = spi_get_ctldata(spi);
1025        struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1026
1027        if (!chip)
1028                return;
1029
1030        if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1031                gpio_free(chip->gpio_cs);
1032
1033        kfree(chip);
1034}
1035
1036#ifdef CONFIG_ACPI
1037static int pxa2xx_spi_acpi_add_dma(struct acpi_resource *res, void *data)
1038{
1039        struct pxa2xx_spi_master *pdata = data;
1040
1041        if (res->type == ACPI_RESOURCE_TYPE_FIXED_DMA) {
1042                const struct acpi_resource_fixed_dma *dma;
1043
1044                dma = &res->data.fixed_dma;
1045                if (pdata->tx_slave_id < 0) {
1046                        pdata->tx_slave_id = dma->request_lines;
1047                        pdata->tx_chan_id = dma->channels;
1048                } else if (pdata->rx_slave_id < 0) {
1049                        pdata->rx_slave_id = dma->request_lines;
1050                        pdata->rx_chan_id = dma->channels;
1051                }
1052        }
1053
1054        /* Tell the ACPI core to skip this resource */
1055        return 1;
1056}
1057
1058static struct pxa2xx_spi_master *
1059pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1060{
1061        struct pxa2xx_spi_master *pdata;
1062        struct list_head resource_list;
1063        struct acpi_device *adev;
1064        struct ssp_device *ssp;
1065        struct resource *res;
1066        int devid;
1067
1068        if (!ACPI_HANDLE(&pdev->dev) ||
1069            acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1070                return NULL;
1071
1072        pdata = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);
1073        if (!pdata) {
1074                dev_err(&pdev->dev,
1075                        "failed to allocate memory for platform data\n");
1076                return NULL;
1077        }
1078
1079        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1080        if (!res)
1081                return NULL;
1082
1083        ssp = &pdata->ssp;
1084
1085        ssp->phys_base = res->start;
1086        ssp->mmio_base = devm_request_and_ioremap(&pdev->dev, res);
1087        if (!ssp->mmio_base) {
1088                dev_err(&pdev->dev, "failed to ioremap mmio_base\n");
1089                return NULL;
1090        }
1091
1092        ssp->clk = devm_clk_get(&pdev->dev, NULL);
1093        ssp->irq = platform_get_irq(pdev, 0);
1094        ssp->type = LPSS_SSP;
1095        ssp->pdev = pdev;
1096
1097        ssp->port_id = -1;
1098        if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
1099                ssp->port_id = devid;
1100
1101        pdata->num_chipselect = 1;
1102        pdata->rx_slave_id = -1;
1103        pdata->tx_slave_id = -1;
1104
1105        INIT_LIST_HEAD(&resource_list);
1106        acpi_dev_get_resources(adev, &resource_list, pxa2xx_spi_acpi_add_dma,
1107                               pdata);
1108        acpi_dev_free_resource_list(&resource_list);
1109
1110        pdata->enable_dma = pdata->rx_slave_id >= 0 && pdata->tx_slave_id >= 0;
1111
1112        return pdata;
1113}
1114
1115static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1116        { "INT33C0", 0 },
1117        { "INT33C1", 0 },
1118        { },
1119};
1120MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1121#else
1122static inline struct pxa2xx_spi_master *
1123pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1124{
1125        return NULL;
1126}
1127#endif
1128
1129static int pxa2xx_spi_probe(struct platform_device *pdev)
1130{
1131        struct device *dev = &pdev->dev;
1132        struct pxa2xx_spi_master *platform_info;
1133        struct spi_master *master;
1134        struct driver_data *drv_data;
1135        struct ssp_device *ssp;
1136        int status;
1137
1138        platform_info = dev_get_platdata(dev);
1139        if (!platform_info) {
1140                platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1141                if (!platform_info) {
1142                        dev_err(&pdev->dev, "missing platform data\n");
1143                        return -ENODEV;
1144                }
1145        }
1146
1147        ssp = pxa_ssp_request(pdev->id, pdev->name);
1148        if (!ssp)
1149                ssp = &platform_info->ssp;
1150
1151        if (!ssp->mmio_base) {
1152                dev_err(&pdev->dev, "failed to get ssp\n");
1153                return -ENODEV;
1154        }
1155
1156        /* Allocate master with space for drv_data and null dma buffer */
1157        master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1158        if (!master) {
1159                dev_err(&pdev->dev, "cannot alloc spi_master\n");
1160                pxa_ssp_free(ssp);
1161                return -ENOMEM;
1162        }
1163        drv_data = spi_master_get_devdata(master);
1164        drv_data->master = master;
1165        drv_data->master_info = platform_info;
1166        drv_data->pdev = pdev;
1167        drv_data->ssp = ssp;
1168
1169        master->dev.parent = &pdev->dev;
1170        master->dev.of_node = pdev->dev.of_node;
1171        /* the spi->mode bits understood by this driver: */
1172        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1173
1174        master->bus_num = ssp->port_id;
1175        master->num_chipselect = platform_info->num_chipselect;
1176        master->dma_alignment = DMA_ALIGNMENT;
1177        master->cleanup = cleanup;
1178        master->setup = setup;
1179        master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1180        master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer;
1181        master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1182
1183        drv_data->ssp_type = ssp->type;
1184        drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
1185
1186        drv_data->ioaddr = ssp->mmio_base;
1187        drv_data->ssdr_physical = ssp->phys_base + SSDR;
1188        if (pxa25x_ssp_comp(drv_data)) {
1189                drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1190                drv_data->dma_cr1 = 0;
1191                drv_data->clear_sr = SSSR_ROR;
1192                drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1193        } else {
1194                drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1195                drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1196                drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1197                drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1198        }
1199
1200        status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1201                        drv_data);
1202        if (status < 0) {
1203                dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1204                goto out_error_master_alloc;
1205        }
1206
1207        /* Setup DMA if requested */
1208        drv_data->tx_channel = -1;
1209        drv_data->rx_channel = -1;
1210        if (platform_info->enable_dma) {
1211                status = pxa2xx_spi_dma_setup(drv_data);
1212                if (status) {
1213                        dev_warn(dev, "failed to setup DMA, using PIO\n");
1214                        platform_info->enable_dma = false;
1215                }
1216        }
1217
1218        /* Enable SOC clock */
1219        clk_prepare_enable(ssp->clk);
1220
1221        drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1222
1223        /* Load default SSP configuration */
1224        write_SSCR0(0, drv_data->ioaddr);
1225        write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1226                                SSCR1_TxTresh(TX_THRESH_DFLT),
1227                                drv_data->ioaddr);
1228        write_SSCR0(SSCR0_SCR(2)
1229                        | SSCR0_Motorola
1230                        | SSCR0_DataSize(8),
1231                        drv_data->ioaddr);
1232        if (!pxa25x_ssp_comp(drv_data))
1233                write_SSTO(0, drv_data->ioaddr);
1234        write_SSPSP(0, drv_data->ioaddr);
1235
1236        lpss_ssp_setup(drv_data);
1237
1238        tasklet_init(&drv_data->pump_transfers, pump_transfers,
1239                     (unsigned long)drv_data);
1240
1241        /* Register with the SPI framework */
1242        platform_set_drvdata(pdev, drv_data);
1243        status = spi_register_master(master);
1244        if (status != 0) {
1245                dev_err(&pdev->dev, "problem registering spi master\n");
1246                goto out_error_clock_enabled;
1247        }
1248
1249        pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1250        pm_runtime_use_autosuspend(&pdev->dev);
1251        pm_runtime_set_active(&pdev->dev);
1252        pm_runtime_enable(&pdev->dev);
1253
1254        return status;
1255
1256out_error_clock_enabled:
1257        clk_disable_unprepare(ssp->clk);
1258        pxa2xx_spi_dma_release(drv_data);
1259        free_irq(ssp->irq, drv_data);
1260
1261out_error_master_alloc:
1262        spi_master_put(master);
1263        pxa_ssp_free(ssp);
1264        return status;
1265}
1266
1267static int pxa2xx_spi_remove(struct platform_device *pdev)
1268{
1269        struct driver_data *drv_data = platform_get_drvdata(pdev);
1270        struct ssp_device *ssp;
1271
1272        if (!drv_data)
1273                return 0;
1274        ssp = drv_data->ssp;
1275
1276        pm_runtime_get_sync(&pdev->dev);
1277
1278        /* Disable the SSP at the peripheral and SOC level */
1279        write_SSCR0(0, drv_data->ioaddr);
1280        clk_disable_unprepare(ssp->clk);
1281
1282        /* Release DMA */
1283        if (drv_data->master_info->enable_dma)
1284                pxa2xx_spi_dma_release(drv_data);
1285
1286        pm_runtime_put_noidle(&pdev->dev);
1287        pm_runtime_disable(&pdev->dev);
1288
1289        /* Release IRQ */
1290        free_irq(ssp->irq, drv_data);
1291
1292        /* Release SSP */
1293        pxa_ssp_free(ssp);
1294
1295        /* Disconnect from the SPI framework */
1296        spi_unregister_master(drv_data->master);
1297
1298        /* Prevent double remove */
1299        platform_set_drvdata(pdev, NULL);
1300
1301        return 0;
1302}
1303
1304static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1305{
1306        int status = 0;
1307
1308        if ((status = pxa2xx_spi_remove(pdev)) != 0)
1309                dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1310}
1311
1312#ifdef CONFIG_PM
1313static int pxa2xx_spi_suspend(struct device *dev)
1314{
1315        struct driver_data *drv_data = dev_get_drvdata(dev);
1316        struct ssp_device *ssp = drv_data->ssp;
1317        int status = 0;
1318
1319        status = spi_master_suspend(drv_data->master);
1320        if (status != 0)
1321                return status;
1322        write_SSCR0(0, drv_data->ioaddr);
1323        clk_disable_unprepare(ssp->clk);
1324
1325        return 0;
1326}
1327
1328static int pxa2xx_spi_resume(struct device *dev)
1329{
1330        struct driver_data *drv_data = dev_get_drvdata(dev);
1331        struct ssp_device *ssp = drv_data->ssp;
1332        int status = 0;
1333
1334        pxa2xx_spi_dma_resume(drv_data);
1335
1336        /* Enable the SSP clock */
1337        clk_prepare_enable(ssp->clk);
1338
1339        /* Start the queue running */
1340        status = spi_master_resume(drv_data->master);
1341        if (status != 0) {
1342                dev_err(dev, "problem starting queue (%d)\n", status);
1343                return status;
1344        }
1345
1346        return 0;
1347}
1348#endif
1349
1350#ifdef CONFIG_PM_RUNTIME
1351static int pxa2xx_spi_runtime_suspend(struct device *dev)
1352{
1353        struct driver_data *drv_data = dev_get_drvdata(dev);
1354
1355        clk_disable_unprepare(drv_data->ssp->clk);
1356        return 0;
1357}
1358
1359static int pxa2xx_spi_runtime_resume(struct device *dev)
1360{
1361        struct driver_data *drv_data = dev_get_drvdata(dev);
1362
1363        clk_prepare_enable(drv_data->ssp->clk);
1364        return 0;
1365}
1366#endif
1367
1368static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1369        SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1370        SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1371                           pxa2xx_spi_runtime_resume, NULL)
1372};
1373
1374static struct platform_driver driver = {
1375        .driver = {
1376                .name   = "pxa2xx-spi",
1377                .owner  = THIS_MODULE,
1378                .pm     = &pxa2xx_spi_pm_ops,
1379                .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1380        },
1381        .probe = pxa2xx_spi_probe,
1382        .remove = pxa2xx_spi_remove,
1383        .shutdown = pxa2xx_spi_shutdown,
1384};
1385
1386static int __init pxa2xx_spi_init(void)
1387{
1388        return platform_driver_register(&driver);
1389}
1390subsys_initcall(pxa2xx_spi_init);
1391
1392static void __exit pxa2xx_spi_exit(void)
1393{
1394        platform_driver_unregister(&driver);
1395}
1396module_exit(pxa2xx_spi_exit);
1397
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